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-rw-r--r--Documentation/devicetree/bindings/arm/rockchip.txt6
-rw-r--r--Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt1
-rw-r--r--arch/arm64/boot/dts/rockchip/Makefile1
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3368.dtsi66
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399-evb.dts (renamed from arch/arm64/boot/dts/rockchip/rk3368-thermal.dtsi)124
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3399.dtsi1013
-rw-r--r--include/dt-bindings/clock/rk3399-cru.h755
7 files changed, 1908 insertions, 58 deletions
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
index 25495190db23..6491b560c876 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
@@ -101,4 +101,8 @@ Rockchip platforms device tree bindings
101 101
102- Rockchip RK3228 Evaluation board: 102- Rockchip RK3228 Evaluation board:
103 Required root node properties: 103 Required root node properties:
104 - compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; 104 - compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
105
106- Rockchip RK3399 evb:
107 Required root node properties:
108 - compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
index ea5614b6f613..07184e8f894e 100644
--- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
@@ -15,6 +15,7 @@ Required Properties:
15 - "rockchip,rk3288-dw-mshc": for Rockchip RK3288 15 - "rockchip,rk3288-dw-mshc": for Rockchip RK3288
16 - "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036 16 - "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036
17 - "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368 17 - "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368
18 - "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399
18 19
19Optional Properties: 20Optional Properties:
20* clocks: from common clock binding: if ciu_drive and ciu_sample are 21* clocks: from common clock binding: if ciu_drive and ciu_sample are
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index df37865e8ced..7037a161b6ef 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -1,6 +1,7 @@
1dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb 1dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
2dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb 2dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
3dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb 3dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
4dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
4 5
5always := $(dtb-y) 6always := $(dtb-y)
6subdir-y := $(dts-dirs) 7subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 7056a0fa1921..8b4a7c9154e9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -413,7 +413,71 @@
413 }; 413 };
414 414
415 thermal-zones { 415 thermal-zones {
416 #include "rk3368-thermal.dtsi" 416 cpu {
417 polling-delay-passive = <100>; /* milliseconds */
418 polling-delay = <5000>; /* milliseconds */
419
420 thermal-sensors = <&tsadc 0>;
421
422 trips {
423 cpu_alert0: cpu_alert0 {
424 temperature = <75000>; /* millicelsius */
425 hysteresis = <2000>; /* millicelsius */
426 type = "passive";
427 };
428 cpu_alert1: cpu_alert1 {
429 temperature = <80000>; /* millicelsius */
430 hysteresis = <2000>; /* millicelsius */
431 type = "passive";
432 };
433 cpu_crit: cpu_crit {
434 temperature = <95000>; /* millicelsius */
435 hysteresis = <2000>; /* millicelsius */
436 type = "critical";
437 };
438 };
439
440 cooling-maps {
441 map0 {
442 trip = <&cpu_alert0>;
443 cooling-device =
444 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
445 };
446 map1 {
447 trip = <&cpu_alert1>;
448 cooling-device =
449 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
450 };
451 };
452 };
453
454 gpu {
455 polling-delay-passive = <100>; /* milliseconds */
456 polling-delay = <5000>; /* milliseconds */
457
458 thermal-sensors = <&tsadc 1>;
459
460 trips {
461 gpu_alert0: gpu_alert0 {
462 temperature = <80000>; /* millicelsius */
463 hysteresis = <2000>; /* millicelsius */
464 type = "passive";
465 };
466 gpu_crit: gpu_crit {
467 temperature = <115000>; /* millicelsius */
468 hysteresis = <2000>; /* millicelsius */
469 type = "critical";
470 };
471 };
472
473 cooling-maps {
474 map0 {
475 trip = <&gpu_alert0>;
476 cooling-device =
477 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
478 };
479 };
480 };
417 }; 481 };
418 482
419 tsadc: tsadc@ff280000 { 483 tsadc: tsadc@ff280000 {
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-thermal.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
index a10010f92f96..1a3eb1482050 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-thermal.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
@@ -1,8 +1,5 @@
1/* 1/*
2 * Device Tree Source for RK3368 SoC thermal 2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
5 * Caesar Wang <wxt@rock-chips.com>
6 * 3 *
7 * This file is dual-licensed: you can use it either under the terms 4 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual 5 * of the GPL or the X11 license, at your option. Note that this dual
@@ -43,70 +40,85 @@
43 * OTHER DEALINGS IN THE SOFTWARE. 40 * OTHER DEALINGS IN THE SOFTWARE.
44 */ 41 */
45 42
46#include <dt-bindings/thermal/thermal.h> 43/dts-v1/;
44#include <dt-bindings/pwm/pwm.h>
45#include "rk3399.dtsi"
47 46
48cpu_thermal: cpu_thermal { 47/ {
49 polling-delay-passive = <100>; /* milliseconds */ 48 model = "Rockchip RK3399 Evaluation Board";
50 polling-delay = <5000>; /* milliseconds */ 49 compatible = "rockchip,rk3399-evb", "rockchip,rk3399",
50 "google,rk3399evb-rev2";
51 51
52 thermal-sensors = <&tsadc 0>; 52 vdd_center: vdd-center {
53 compatible = "pwm-regulator";
54 pwms = <&pwm3 0 25000 0>;
55 regulator-name = "vdd_center";
56 regulator-min-microvolt = <800000>;
57 regulator-max-microvolt = <1400000>;
58 regulator-always-on;
59 regulator-boot-on;
60 status = "okay";
61 };
53 62
54 trips { 63 vcc3v3_sys: vcc3v3-sys {
55 cpu_alert0: cpu_alert0 { 64 compatible = "regulator-fixed";
56 temperature = <75000>; /* millicelsius */ 65 regulator-name = "vcc3v3_sys";
57 hysteresis = <2000>; /* millicelsius */ 66 regulator-always-on;
58 type = "passive"; 67 regulator-boot-on;
59 }; 68 regulator-min-microvolt = <3300000>;
60 cpu_alert1: cpu_alert1 { 69 regulator-max-microvolt = <3300000>;
61 temperature = <80000>; /* millicelsius */
62 hysteresis = <2000>; /* millicelsius */
63 type = "passive";
64 };
65 cpu_crit: cpu_crit {
66 temperature = <95000>; /* millicelsius */
67 hysteresis = <2000>; /* millicelsius */
68 type = "critical";
69 };
70 }; 70 };
71 71
72 cooling-maps { 72 vcc_phy: vcc-phy-regulator {
73 map0 { 73 compatible = "regulator-fixed";
74 trip = <&cpu_alert0>; 74 regulator-name = "vcc_phy";
75 cooling-device = 75 regulator-always-on;
76 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 76 regulator-boot-on;
77 };
78 map1 {
79 trip = <&cpu_alert1>;
80 cooling-device =
81 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
82 };
83 }; 77 };
84}; 78};
85 79
86gpu_thermal: gpu_thermal { 80&pwm0 {
87 polling-delay-passive = <100>; /* milliseconds */ 81 status = "okay";
88 polling-delay = <5000>; /* milliseconds */ 82};
83
84&pwm2 {
85 status = "okay";
86};
89 87
90 thermal-sensors = <&tsadc 1>; 88&pwm3 {
89 status = "okay";
90};
91 91
92 trips { 92&uart2 {
93 gpu_alert0: gpu_alert0 { 93 status = "okay";
94 temperature = <80000>; /* millicelsius */ 94};
95 hysteresis = <2000>; /* millicelsius */ 95
96 type = "passive"; 96&usb_host0_ehci {
97 }; 97 status = "okay";
98 gpu_crit: gpu_crit { 98};
99 temperature = <1150000>; /* millicelsius */ 99
100 hysteresis = <2000>; /* millicelsius */ 100&usb_host0_ohci {
101 type = "critical"; 101 status = "okay";
102};
103
104&usb_host1_ehci {
105 status = "okay";
106};
107
108&usb_host1_ohci {
109 status = "okay";
110};
111
112&pinctrl {
113 pmic {
114 pmic_int_l: pmic-int-l {
115 rockchip,pins =
116 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
102 }; 117 };
103 };
104 118
105 cooling-maps { 119 pmic_dvs2: pmic-dvs2 {
106 map0 { 120 rockchip,pins =
107 trip = <&gpu_alert0>; 121 <1 18 RK_FUNC_GPIO &pcfg_pull_down>;
108 cooling-device =
109 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
110 }; 122 };
111 }; 123 };
112}; 124};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
new file mode 100644
index 000000000000..46f325a143b0
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -0,0 +1,1013 @@
1/*
2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include <dt-bindings/clock/rk3399-cru.h>
44#include <dt-bindings/gpio/gpio.h>
45#include <dt-bindings/interrupt-controller/arm-gic.h>
46#include <dt-bindings/interrupt-controller/irq.h>
47#include <dt-bindings/pinctrl/rockchip.h>
48
49/ {
50 compatible = "rockchip,rk3399";
51
52 interrupt-parent = <&gic>;
53 #address-cells = <2>;
54 #size-cells = <2>;
55
56 aliases {
57 serial0 = &uart0;
58 serial1 = &uart1;
59 serial2 = &uart2;
60 serial3 = &uart3;
61 serial4 = &uart4;
62 };
63
64 cpus {
65 #address-cells = <2>;
66 #size-cells = <0>;
67
68 cpu-map {
69 cluster0 {
70 core0 {
71 cpu = <&cpu_l0>;
72 };
73 core1 {
74 cpu = <&cpu_l1>;
75 };
76 core2 {
77 cpu = <&cpu_l2>;
78 };
79 core3 {
80 cpu = <&cpu_l3>;
81 };
82 };
83
84 cluster1 {
85 core0 {
86 cpu = <&cpu_b0>;
87 };
88 core1 {
89 cpu = <&cpu_b1>;
90 };
91 };
92 };
93
94 cpu_l0: cpu@0 {
95 device_type = "cpu";
96 compatible = "arm,cortex-a53", "arm,armv8";
97 reg = <0x0 0x0>;
98 enable-method = "psci";
99 #cooling-cells = <2>; /* min followed by max */
100 clocks = <&cru ARMCLKL>;
101 };
102
103 cpu_l1: cpu@1 {
104 device_type = "cpu";
105 compatible = "arm,cortex-a53", "arm,armv8";
106 reg = <0x0 0x1>;
107 enable-method = "psci";
108 clocks = <&cru ARMCLKL>;
109 };
110
111 cpu_l2: cpu@2 {
112 device_type = "cpu";
113 compatible = "arm,cortex-a53", "arm,armv8";
114 reg = <0x0 0x2>;
115 enable-method = "psci";
116 clocks = <&cru ARMCLKL>;
117 };
118
119 cpu_l3: cpu@3 {
120 device_type = "cpu";
121 compatible = "arm,cortex-a53", "arm,armv8";
122 reg = <0x0 0x3>;
123 enable-method = "psci";
124 clocks = <&cru ARMCLKL>;
125 };
126
127 cpu_b0: cpu@100 {
128 device_type = "cpu";
129 compatible = "arm,cortex-a72", "arm,armv8";
130 reg = <0x0 0x100>;
131 enable-method = "psci";
132 #cooling-cells = <2>; /* min followed by max */
133 clocks = <&cru ARMCLKB>;
134 };
135
136 cpu_b1: cpu@101 {
137 device_type = "cpu";
138 compatible = "arm,cortex-a72", "arm,armv8";
139 reg = <0x0 0x101>;
140 enable-method = "psci";
141 clocks = <&cru ARMCLKB>;
142 };
143 };
144
145 psci {
146 compatible = "arm,psci-1.0";
147 method = "smc";
148 };
149
150 timer {
151 compatible = "arm,armv8-timer";
152 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
153 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
154 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
155 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
156 };
157
158 xin24m: xin24m {
159 compatible = "fixed-clock";
160 clock-frequency = <24000000>;
161 clock-output-names = "xin24m";
162 #clock-cells = <0>;
163 };
164
165 amba {
166 compatible = "arm,amba-bus";
167 #address-cells = <2>;
168 #size-cells = <2>;
169 ranges;
170
171 dmac_bus: dma-controller@ff6d0000 {
172 compatible = "arm,pl330", "arm,primecell";
173 reg = <0x0 0xff6d0000 0x0 0x4000>;
174 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
176 #dma-cells = <1>;
177 clocks = <&cru ACLK_DMAC0_PERILP>;
178 clock-names = "apb_pclk";
179 };
180
181 dmac_peri: dma-controller@ff6e0000 {
182 compatible = "arm,pl330", "arm,primecell";
183 reg = <0x0 0xff6e0000 0x0 0x4000>;
184 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
186 #dma-cells = <1>;
187 clocks = <&cru ACLK_DMAC1_PERILP>;
188 clock-names = "apb_pclk";
189 };
190 };
191
192 sdio0: dwmmc@fe310000 {
193 compatible = "rockchip,rk3399-dw-mshc",
194 "rockchip,rk3288-dw-mshc";
195 reg = <0x0 0xfe310000 0x0 0x4000>;
196 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
197 clock-freq-min-max = <400000 150000000>;
198 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
199 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
200 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
201 fifo-depth = <0x100>;
202 status = "disabled";
203 };
204
205 sdmmc: dwmmc@fe320000 {
206 compatible = "rockchip,rk3399-dw-mshc",
207 "rockchip,rk3288-dw-mshc";
208 reg = <0x0 0xfe320000 0x0 0x4000>;
209 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
210 clock-freq-min-max = <400000 150000000>;
211 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
212 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
213 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
214 fifo-depth = <0x100>;
215 status = "disabled";
216 };
217
218 usb_host0_ehci: usb@fe380000 {
219 compatible = "generic-ehci";
220 reg = <0x0 0xfe380000 0x0 0x20000>;
221 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
223 clock-names = "hclk_host0", "hclk_host0_arb";
224 status = "disabled";
225 };
226
227 usb_host0_ohci: usb@fe3a0000 {
228 compatible = "generic-ohci";
229 reg = <0x0 0xfe3a0000 0x0 0x20000>;
230 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
232 clock-names = "hclk_host0", "hclk_host0_arb";
233 status = "disabled";
234 };
235
236 usb_host1_ehci: usb@fe3c0000 {
237 compatible = "generic-ehci";
238 reg = <0x0 0xfe3c0000 0x0 0x20000>;
239 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
241 clock-names = "hclk_host1", "hclk_host1_arb";
242 status = "disabled";
243 };
244
245 usb_host1_ohci: usb@fe3e0000 {
246 compatible = "generic-ohci";
247 reg = <0x0 0xfe3e0000 0x0 0x20000>;
248 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
249 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
250 clock-names = "hclk_host1", "hclk_host1_arb";
251 status = "disabled";
252 };
253
254 gic: interrupt-controller@fee00000 {
255 compatible = "arm,gic-v3";
256 #interrupt-cells = <3>;
257 #address-cells = <2>;
258 #size-cells = <2>;
259 ranges;
260 interrupt-controller;
261
262 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
263 <0x0 0xfef00000 0 0xc0000>, /* GICR */
264 <0x0 0xfff00000 0 0x10000>, /* GICC */
265 <0x0 0xfff10000 0 0x10000>, /* GICH */
266 <0x0 0xfff20000 0 0x10000>; /* GICV */
267 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
268 its: interrupt-controller@fee20000 {
269 compatible = "arm,gic-v3-its";
270 msi-controller;
271 reg = <0x0 0xfee20000 0x0 0x20000>;
272 };
273 };
274
275 uart0: serial@ff180000 {
276 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
277 reg = <0x0 0xff180000 0x0 0x100>;
278 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
279 clock-names = "baudclk", "apb_pclk";
280 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
281 reg-shift = <2>;
282 reg-io-width = <4>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&uart0_xfer>;
285 status = "disabled";
286 };
287
288 uart1: serial@ff190000 {
289 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
290 reg = <0x0 0xff190000 0x0 0x100>;
291 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
292 clock-names = "baudclk", "apb_pclk";
293 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
294 reg-shift = <2>;
295 reg-io-width = <4>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&uart1_xfer>;
298 status = "disabled";
299 };
300
301 uart2: serial@ff1a0000 {
302 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
303 reg = <0x0 0xff1a0000 0x0 0x100>;
304 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
305 clock-names = "baudclk", "apb_pclk";
306 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
307 reg-shift = <2>;
308 reg-io-width = <4>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&uart2c_xfer>;
311 status = "disabled";
312 };
313
314 uart3: serial@ff1b0000 {
315 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
316 reg = <0x0 0xff1b0000 0x0 0x100>;
317 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
318 clock-names = "baudclk", "apb_pclk";
319 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
320 reg-shift = <2>;
321 reg-io-width = <4>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&uart3_xfer>;
324 status = "disabled";
325 };
326
327 spi0: spi@ff1c0000 {
328 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
329 reg = <0x0 0xff1c0000 0x0 0x1000>;
330 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
331 clock-names = "spiclk", "apb_pclk";
332 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
333 pinctrl-names = "default";
334 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
335 #address-cells = <1>;
336 #size-cells = <0>;
337 status = "disabled";
338 };
339
340 spi1: spi@ff1d0000 {
341 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
342 reg = <0x0 0xff1d0000 0x0 0x1000>;
343 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
344 clock-names = "spiclk", "apb_pclk";
345 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
346 pinctrl-names = "default";
347 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
348 #address-cells = <1>;
349 #size-cells = <0>;
350 status = "disabled";
351 };
352
353 spi2: spi@ff1e0000 {
354 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
355 reg = <0x0 0xff1e0000 0x0 0x1000>;
356 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
357 clock-names = "spiclk", "apb_pclk";
358 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
359 pinctrl-names = "default";
360 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
361 #address-cells = <1>;
362 #size-cells = <0>;
363 status = "disabled";
364 };
365
366 spi4: spi@ff1f0000 {
367 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
368 reg = <0x0 0xff1f0000 0x0 0x1000>;
369 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
370 clock-names = "spiclk", "apb_pclk";
371 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
374 #address-cells = <1>;
375 #size-cells = <0>;
376 status = "disabled";
377 };
378
379 spi5: spi@ff200000 {
380 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
381 reg = <0x0 0xff200000 0x0 0x1000>;
382 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
383 clock-names = "spiclk", "apb_pclk";
384 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
387 #address-cells = <1>;
388 #size-cells = <0>;
389 status = "disabled";
390 };
391
392 pmugrf: syscon@ff320000 {
393 compatible = "rockchip,rk3399-pmugrf", "syscon";
394 reg = <0x0 0xff320000 0x0 0x1000>;
395 };
396
397 spi3: spi@ff350000 {
398 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
399 reg = <0x0 0xff350000 0x0 0x1000>;
400 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
401 clock-names = "spiclk", "apb_pclk";
402 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
405 #address-cells = <1>;
406 #size-cells = <0>;
407 status = "disabled";
408 };
409
410 uart4: serial@ff370000 {
411 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
412 reg = <0x0 0xff370000 0x0 0x100>;
413 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
414 clock-names = "baudclk", "apb_pclk";
415 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
416 reg-shift = <2>;
417 reg-io-width = <4>;
418 pinctrl-names = "default";
419 pinctrl-0 = <&uart4_xfer>;
420 status = "disabled";
421 };
422
423 pwm0: pwm@ff420000 {
424 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
425 reg = <0x0 0xff420000 0x0 0x10>;
426 #pwm-cells = <3>;
427 pinctrl-names = "default";
428 pinctrl-0 = <&pwm0_pin>;
429 clocks = <&pmucru PCLK_RKPWM_PMU>;
430 clock-names = "pwm";
431 status = "disabled";
432 };
433
434 pwm1: pwm@ff420010 {
435 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
436 reg = <0x0 0xff420010 0x0 0x10>;
437 #pwm-cells = <3>;
438 pinctrl-names = "default";
439 pinctrl-0 = <&pwm1_pin>;
440 clocks = <&pmucru PCLK_RKPWM_PMU>;
441 clock-names = "pwm";
442 status = "disabled";
443 };
444
445 pwm2: pwm@ff420020 {
446 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
447 reg = <0x0 0xff420020 0x0 0x10>;
448 #pwm-cells = <3>;
449 pinctrl-names = "default";
450 pinctrl-0 = <&pwm2_pin>;
451 clocks = <&pmucru PCLK_RKPWM_PMU>;
452 clock-names = "pwm";
453 status = "disabled";
454 };
455
456 pwm3: pwm@ff420030 {
457 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
458 reg = <0x0 0xff420030 0x0 0x10>;
459 #pwm-cells = <3>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&pwm3a_pin>;
462 clocks = <&pmucru PCLK_RKPWM_PMU>;
463 clock-names = "pwm";
464 status = "disabled";
465 };
466
467 pmucru: pmu-clock-controller@ff750000 {
468 compatible = "rockchip,rk3399-pmucru";
469 reg = <0x0 0xff750000 0x0 0x1000>;
470 #clock-cells = <1>;
471 #reset-cells = <1>;
472 assigned-clocks = <&pmucru PLL_PPLL>;
473 assigned-clock-rates = <676000000>;
474 };
475
476 cru: clock-controller@ff760000 {
477 compatible = "rockchip,rk3399-cru";
478 reg = <0x0 0xff760000 0x0 0x1000>;
479 #clock-cells = <1>;
480 #reset-cells = <1>;
481 };
482
483 grf: syscon@ff770000 {
484 compatible = "rockchip,rk3399-grf", "syscon";
485 reg = <0x0 0xff770000 0x0 0x10000>;
486 };
487
488 watchdog@ff840000 {
489 compatible = "snps,dw-wdt";
490 reg = <0x0 0xff840000 0x0 0x100>;
491 clocks = <&cru PCLK_WDT>;
492 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
493 };
494
495 spdif: spdif@ff870000 {
496 compatible = "rockchip,rk3399-spdif";
497 reg = <0x0 0xff870000 0x0 0x1000>;
498 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
499 dmas = <&dmac_bus 7>;
500 dma-names = "tx";
501 clock-names = "mclk", "hclk";
502 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
503 pinctrl-names = "default";
504 pinctrl-0 = <&spdif_bus>;
505 status = "disabled";
506 };
507
508 i2s0: i2s@ff880000 {
509 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
510 reg = <0x0 0xff880000 0x0 0x1000>;
511 rockchip,grf = <&grf>;
512 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
513 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
514 dma-names = "tx", "rx";
515 clock-names = "i2s_clk", "i2s_hclk";
516 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
517 pinctrl-names = "default";
518 pinctrl-0 = <&i2s0_8ch_bus>;
519 status = "disabled";
520 };
521
522 i2s1: i2s@ff890000 {
523 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
524 reg = <0x0 0xff890000 0x0 0x1000>;
525 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
526 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
527 dma-names = "tx", "rx";
528 clock-names = "i2s_clk", "i2s_hclk";
529 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&i2s1_2ch_bus>;
532 status = "disabled";
533 };
534
535 i2s2: i2s@ff8a0000 {
536 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
537 reg = <0x0 0xff8a0000 0x0 0x1000>;
538 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
539 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
540 dma-names = "tx", "rx";
541 clock-names = "i2s_clk", "i2s_hclk";
542 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
543 status = "disabled";
544 };
545
546 pinctrl: pinctrl {
547 compatible = "rockchip,rk3399-pinctrl";
548 rockchip,grf = <&grf>;
549 rockchip,pmu = <&pmugrf>;
550 #address-cells = <2>;
551 #size-cells = <2>;
552 ranges;
553
554 gpio0: gpio0@ff720000 {
555 compatible = "rockchip,gpio-bank";
556 reg = <0x0 0xff720000 0x0 0x100>;
557 clocks = <&pmucru PCLK_GPIO0_PMU>;
558 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
559
560 gpio-controller;
561 #gpio-cells = <0x2>;
562
563 interrupt-controller;
564 #interrupt-cells = <0x2>;
565 };
566
567 gpio1: gpio1@ff730000 {
568 compatible = "rockchip,gpio-bank";
569 reg = <0x0 0xff730000 0x0 0x100>;
570 clocks = <&pmucru PCLK_GPIO1_PMU>;
571 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
572
573 gpio-controller;
574 #gpio-cells = <0x2>;
575
576 interrupt-controller;
577 #interrupt-cells = <0x2>;
578 };
579
580 gpio2: gpio2@ff780000 {
581 compatible = "rockchip,gpio-bank";
582 reg = <0x0 0xff780000 0x0 0x100>;
583 clocks = <&cru PCLK_GPIO2>;
584 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
585
586 gpio-controller;
587 #gpio-cells = <0x2>;
588
589 interrupt-controller;
590 #interrupt-cells = <0x2>;
591 };
592
593 gpio3: gpio3@ff788000 {
594 compatible = "rockchip,gpio-bank";
595 reg = <0x0 0xff788000 0x0 0x100>;
596 clocks = <&cru PCLK_GPIO3>;
597 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
598
599 gpio-controller;
600 #gpio-cells = <0x2>;
601
602 interrupt-controller;
603 #interrupt-cells = <0x2>;
604 };
605
606 gpio4: gpio4@ff790000 {
607 compatible = "rockchip,gpio-bank";
608 reg = <0x0 0xff790000 0x0 0x100>;
609 clocks = <&cru PCLK_GPIO4>;
610 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
611
612 gpio-controller;
613 #gpio-cells = <0x2>;
614
615 interrupt-controller;
616 #interrupt-cells = <0x2>;
617 };
618
619 pcfg_pull_up: pcfg-pull-up {
620 bias-pull-up;
621 };
622
623 pcfg_pull_down: pcfg-pull-down {
624 bias-pull-down;
625 };
626
627 pcfg_pull_none: pcfg-pull-none {
628 bias-disable;
629 };
630
631 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
632 bias-disable;
633 drive-strength = <12>;
634 };
635
636 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
637 bias-pull-up;
638 drive-strength = <8>;
639 };
640
641 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
642 bias-pull-down;
643 drive-strength = <4>;
644 };
645
646 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
647 bias-pull-up;
648 drive-strength = <2>;
649 };
650
651 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
652 bias-pull-down;
653 drive-strength = <12>;
654 };
655
656 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
657 bias-disable;
658 drive-strength = <13>;
659 };
660
661 i2c0 {
662 i2c0_xfer: i2c0-xfer {
663 rockchip,pins =
664 <1 15 RK_FUNC_2 &pcfg_pull_none>,
665 <1 16 RK_FUNC_2 &pcfg_pull_none>;
666 };
667 };
668
669 i2c1 {
670 i2c1_xfer: i2c1-xfer {
671 rockchip,pins =
672 <4 2 RK_FUNC_1 &pcfg_pull_none>,
673 <4 1 RK_FUNC_1 &pcfg_pull_none>;
674 };
675 };
676
677 i2c2 {
678 i2c2_xfer: i2c2-xfer {
679 rockchip,pins =
680 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
681 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
682 };
683 };
684
685 i2c3 {
686 i2c3_xfer: i2c3-xfer {
687 rockchip,pins =
688 <4 17 RK_FUNC_1 &pcfg_pull_none>,
689 <4 16 RK_FUNC_1 &pcfg_pull_none>;
690 };
691 };
692
693 i2c4 {
694 i2c4_xfer: i2c4-xfer {
695 rockchip,pins =
696 <1 12 RK_FUNC_1 &pcfg_pull_none>,
697 <1 11 RK_FUNC_1 &pcfg_pull_none>;
698 };
699 };
700
701 i2c5 {
702 i2c5_xfer: i2c5-xfer {
703 rockchip,pins =
704 <3 11 RK_FUNC_2 &pcfg_pull_none>,
705 <3 10 RK_FUNC_2 &pcfg_pull_none>;
706 };
707 };
708
709 i2c6 {
710 i2c6_xfer: i2c6-xfer {
711 rockchip,pins =
712 <2 10 RK_FUNC_2 &pcfg_pull_none>,
713 <2 9 RK_FUNC_2 &pcfg_pull_none>;
714 };
715 };
716
717 i2c7 {
718 i2c7_xfer: i2c7-xfer {
719 rockchip,pins =
720 <2 8 RK_FUNC_2 &pcfg_pull_none>,
721 <2 7 RK_FUNC_2 &pcfg_pull_none>;
722 };
723 };
724
725 i2c8 {
726 i2c8_xfer: i2c8-xfer {
727 rockchip,pins =
728 <1 21 RK_FUNC_1 &pcfg_pull_none>,
729 <1 20 RK_FUNC_1 &pcfg_pull_none>;
730 };
731 };
732
733 i2s0 {
734 i2s0_8ch_bus: i2s0-8ch-bus {
735 rockchip,pins =
736 <3 24 RK_FUNC_1 &pcfg_pull_none>,
737 <3 25 RK_FUNC_1 &pcfg_pull_none>,
738 <3 26 RK_FUNC_1 &pcfg_pull_none>,
739 <3 27 RK_FUNC_1 &pcfg_pull_none>,
740 <3 28 RK_FUNC_1 &pcfg_pull_none>,
741 <3 29 RK_FUNC_1 &pcfg_pull_none>,
742 <3 30 RK_FUNC_1 &pcfg_pull_none>,
743 <3 31 RK_FUNC_1 &pcfg_pull_none>,
744 <4 0 RK_FUNC_1 &pcfg_pull_none>;
745 };
746 };
747
748 i2s1 {
749 i2s1_2ch_bus: i2s1-2ch-bus {
750 rockchip,pins =
751 <4 3 RK_FUNC_1 &pcfg_pull_none>,
752 <4 4 RK_FUNC_1 &pcfg_pull_none>,
753 <4 5 RK_FUNC_1 &pcfg_pull_none>,
754 <4 6 RK_FUNC_1 &pcfg_pull_none>,
755 <4 7 RK_FUNC_1 &pcfg_pull_none>;
756 };
757 };
758
759 spdif {
760 spdif_bus: spdif-bus {
761 rockchip,pins =
762 <4 21 RK_FUNC_1 &pcfg_pull_none>;
763 };
764 };
765
766 spi0 {
767 spi0_clk: spi0-clk {
768 rockchip,pins =
769 <3 6 RK_FUNC_2 &pcfg_pull_up>;
770 };
771 spi0_cs0: spi0-cs0 {
772 rockchip,pins =
773 <3 7 RK_FUNC_2 &pcfg_pull_up>;
774 };
775 spi0_cs1: spi0-cs1 {
776 rockchip,pins =
777 <3 8 RK_FUNC_2 &pcfg_pull_up>;
778 };
779 spi0_tx: spi0-tx {
780 rockchip,pins =
781 <3 5 RK_FUNC_2 &pcfg_pull_up>;
782 };
783 spi0_rx: spi0-rx {
784 rockchip,pins =
785 <3 4 RK_FUNC_2 &pcfg_pull_up>;
786 };
787 };
788
789 spi1 {
790 spi1_clk: spi1-clk {
791 rockchip,pins =
792 <1 9 RK_FUNC_2 &pcfg_pull_up>;
793 };
794 spi1_cs0: spi1-cs0 {
795 rockchip,pins =
796 <1 10 RK_FUNC_2 &pcfg_pull_up>;
797 };
798 spi1_rx: spi1-rx {
799 rockchip,pins =
800 <1 7 RK_FUNC_2 &pcfg_pull_up>;
801 };
802 spi1_tx: spi1-tx {
803 rockchip,pins =
804 <1 8 RK_FUNC_2 &pcfg_pull_up>;
805 };
806 };
807
808 spi2 {
809 spi2_clk: spi2-clk {
810 rockchip,pins =
811 <2 11 RK_FUNC_1 &pcfg_pull_up>;
812 };
813 spi2_cs0: spi2-cs0 {
814 rockchip,pins =
815 <2 12 RK_FUNC_1 &pcfg_pull_up>;
816 };
817 spi2_rx: spi2-rx {
818 rockchip,pins =
819 <2 9 RK_FUNC_1 &pcfg_pull_up>;
820 };
821 spi2_tx: spi2-tx {
822 rockchip,pins =
823 <2 10 RK_FUNC_1 &pcfg_pull_up>;
824 };
825 };
826
827 spi3 {
828 spi3_clk: spi3-clk {
829 rockchip,pins =
830 <1 17 RK_FUNC_1 &pcfg_pull_up>;
831 };
832 spi3_cs0: spi3-cs0 {
833 rockchip,pins =
834 <1 18 RK_FUNC_1 &pcfg_pull_up>;
835 };
836 spi3_rx: spi3-rx {
837 rockchip,pins =
838 <1 15 RK_FUNC_1 &pcfg_pull_up>;
839 };
840 spi3_tx: spi3-tx {
841 rockchip,pins =
842 <1 16 RK_FUNC_1 &pcfg_pull_up>;
843 };
844 };
845
846 spi4 {
847 spi4_clk: spi4-clk {
848 rockchip,pins =
849 <3 2 RK_FUNC_2 &pcfg_pull_up>;
850 };
851 spi4_cs0: spi4-cs0 {
852 rockchip,pins =
853 <3 3 RK_FUNC_2 &pcfg_pull_up>;
854 };
855 spi4_rx: spi4-rx {
856 rockchip,pins =
857 <3 0 RK_FUNC_2 &pcfg_pull_up>;
858 };
859 spi4_tx: spi4-tx {
860 rockchip,pins =
861 <3 1 RK_FUNC_2 &pcfg_pull_up>;
862 };
863 };
864
865 spi5 {
866 spi5_clk: spi5-clk {
867 rockchip,pins =
868 <2 22 RK_FUNC_2 &pcfg_pull_up>;
869 };
870 spi5_cs0: spi5-cs0 {
871 rockchip,pins =
872 <2 23 RK_FUNC_2 &pcfg_pull_up>;
873 };
874 spi5_rx: spi5-rx {
875 rockchip,pins =
876 <2 20 RK_FUNC_2 &pcfg_pull_up>;
877 };
878 spi5_tx: spi5-tx {
879 rockchip,pins =
880 <2 21 RK_FUNC_2 &pcfg_pull_up>;
881 };
882 };
883
884 uart0 {
885 uart0_xfer: uart0-xfer {
886 rockchip,pins =
887 <2 16 RK_FUNC_1 &pcfg_pull_up>,
888 <2 17 RK_FUNC_1 &pcfg_pull_none>;
889 };
890
891 uart0_cts: uart0-cts {
892 rockchip,pins =
893 <2 18 RK_FUNC_1 &pcfg_pull_none>;
894 };
895
896 uart0_rts: uart0-rts {
897 rockchip,pins =
898 <2 19 RK_FUNC_1 &pcfg_pull_none>;
899 };
900 };
901
902 uart1 {
903 uart1_xfer: uart1-xfer {
904 rockchip,pins =
905 <3 12 RK_FUNC_2 &pcfg_pull_up>,
906 <3 13 RK_FUNC_2 &pcfg_pull_none>;
907 };
908 };
909
910 uart2a {
911 uart2a_xfer: uart2a-xfer {
912 rockchip,pins =
913 <4 8 RK_FUNC_2 &pcfg_pull_up>,
914 <4 9 RK_FUNC_2 &pcfg_pull_none>;
915 };
916 };
917
918 uart2b {
919 uart2b_xfer: uart2b-xfer {
920 rockchip,pins =
921 <4 16 RK_FUNC_2 &pcfg_pull_up>,
922 <4 17 RK_FUNC_2 &pcfg_pull_none>;
923 };
924 };
925
926 uart2c {
927 uart2c_xfer: uart2c-xfer {
928 rockchip,pins =
929 <4 19 RK_FUNC_1 &pcfg_pull_up>,
930 <4 20 RK_FUNC_1 &pcfg_pull_none>;
931 };
932 };
933
934 uart3 {
935 uart3_xfer: uart3-xfer {
936 rockchip,pins =
937 <3 14 RK_FUNC_2 &pcfg_pull_up>,
938 <3 15 RK_FUNC_2 &pcfg_pull_none>;
939 };
940
941 uart3_cts: uart3-cts {
942 rockchip,pins =
943 <3 18 RK_FUNC_2 &pcfg_pull_none>;
944 };
945
946 uart3_rts: uart3-rts {
947 rockchip,pins =
948 <3 19 RK_FUNC_2 &pcfg_pull_none>;
949 };
950 };
951
952 uart4 {
953 uart4_xfer: uart4-xfer {
954 rockchip,pins =
955 <1 7 RK_FUNC_1 &pcfg_pull_up>,
956 <1 8 RK_FUNC_1 &pcfg_pull_none>;
957 };
958 };
959
960 uarthdcp {
961 uarthdcp_xfer: uarthdcp-xfer {
962 rockchip,pins =
963 <4 21 RK_FUNC_2 &pcfg_pull_up>,
964 <4 22 RK_FUNC_2 &pcfg_pull_none>;
965 };
966 };
967
968 pwm0 {
969 pwm0_pin: pwm0-pin {
970 rockchip,pins =
971 <4 18 RK_FUNC_1 &pcfg_pull_none>;
972 };
973
974 vop0_pwm_pin: vop0-pwm-pin {
975 rockchip,pins =
976 <4 18 RK_FUNC_2 &pcfg_pull_none>;
977 };
978 };
979
980 pwm1 {
981 pwm1_pin: pwm1-pin {
982 rockchip,pins =
983 <4 22 RK_FUNC_1 &pcfg_pull_none>;
984 };
985
986 vop1_pwm_pin: vop1-pwm-pin {
987 rockchip,pins =
988 <4 18 RK_FUNC_3 &pcfg_pull_none>;
989 };
990 };
991
992 pwm2 {
993 pwm2_pin: pwm2-pin {
994 rockchip,pins =
995 <1 19 RK_FUNC_1 &pcfg_pull_none>;
996 };
997 };
998
999 pwm3a {
1000 pwm3a_pin: pwm3a-pin {
1001 rockchip,pins =
1002 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1003 };
1004 };
1005
1006 pwm3b {
1007 pwm3b_pin: pwm3b-pin {
1008 rockchip,pins =
1009 <1 14 RK_FUNC_1 &pcfg_pull_none>;
1010 };
1011 };
1012 };
1013};
diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
new file mode 100644
index 000000000000..50a44cffb070
--- /dev/null
+++ b/include/dt-bindings/clock/rk3399-cru.h
@@ -0,0 +1,755 @@
1/*
2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
17#define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
18
19/* core clocks */
20#define PLL_APLLL 1
21#define PLL_APLLB 2
22#define PLL_DPLL 3
23#define PLL_CPLL 4
24#define PLL_GPLL 5
25#define PLL_NPLL 6
26#define PLL_VPLL 7
27#define ARMCLKL 8
28#define ARMCLKB 9
29
30/* sclk gates (special clocks) */
31#define SCLK_I2C1 65
32#define SCLK_I2C2 66
33#define SCLK_I2C3 67
34#define SCLK_I2C5 68
35#define SCLK_I2C6 69
36#define SCLK_I2C7 70
37#define SCLK_SPI0 71
38#define SCLK_SPI1 72
39#define SCLK_SPI2 73
40#define SCLK_SPI4 74
41#define SCLK_SPI5 75
42#define SCLK_SDMMC 76
43#define SCLK_SDIO 77
44#define SCLK_EMMC 78
45#define SCLK_TSADC 79
46#define SCLK_SARADC 80
47#define SCLK_UART0 81
48#define SCLK_UART1 82
49#define SCLK_UART2 83
50#define SCLK_UART3 84
51#define SCLK_SPDIF_8CH 85
52#define SCLK_I2S0_8CH 86
53#define SCLK_I2S1_8CH 87
54#define SCLK_I2S2_8CH 88
55#define SCLK_I2S_8CH_OUT 89
56#define SCLK_TIMER00 90
57#define SCLK_TIMER01 91
58#define SCLK_TIMER02 92
59#define SCLK_TIMER03 93
60#define SCLK_TIMER04 94
61#define SCLK_TIMER05 95
62#define SCLK_TIMER06 96
63#define SCLK_TIMER07 97
64#define SCLK_TIMER08 98
65#define SCLK_TIMER09 99
66#define SCLK_TIMER10 100
67#define SCLK_TIMER11 101
68#define SCLK_MACREF 102
69#define SCLK_MAC_RX 103
70#define SCLK_MAC_TX 104
71#define SCLK_MAC 105
72#define SCLK_MACREF_OUT 106
73#define SCLK_VOP0_PWM 107
74#define SCLK_VOP1_PWM 108
75#define SCLK_RGA_CORE 109
76#define SCLK_ISP0 110
77#define SCLK_ISP1 111
78#define SCLK_HDMI_CEC 112
79#define SCLK_HDMI_SFR 113
80#define SCLK_DP_CORE 114
81#define SCLK_PVTM_CORE_L 115
82#define SCLK_PVTM_CORE_B 116
83#define SCLK_PVTM_GPU 117
84#define SCLK_PVTM_DDR 118
85#define SCLK_MIPIDPHY_REF 119
86#define SCLK_MIPIDPHY_CFG 120
87#define SCLK_HSICPHY 121
88#define SCLK_USBPHY480M 122
89#define SCLK_USB2PHY0_REF 123
90#define SCLK_USB2PHY1_REF 124
91#define SCLK_UPHY0_TCPDPHY_REF 125
92#define SCLK_UPHY0_TCPDCORE 126
93#define SCLK_UPHY1_TCPDPHY_REF 127
94#define SCLK_UPHY1_TCPDCORE 128
95#define SCLK_USB3OTG0_REF 129
96#define SCLK_USB3OTG1_REF 130
97#define SCLK_USB3OTG0_SUSPEND 131
98#define SCLK_USB3OTG1_SUSPEND 132
99#define SCLK_CRYPTO0 133
100#define SCLK_CRYPTO1 134
101#define SCLK_CCI_TRACE 135
102#define SCLK_CS 136
103#define SCLK_CIF_OUT 137
104#define SCLK_PCIEPHY_REF 138
105#define SCLK_PCIE_CORE 139
106#define SCLK_M0_PERILP 140
107#define SCLK_M0_PERILP_DEC 141
108#define SCLK_CM0S 142
109#define SCLK_DBG_NOC 143
110#define SCLK_DBG_PD_CORE_B 144
111#define SCLK_DBG_PD_CORE_L 145
112#define SCLK_DFIMON0_TIMER 146
113#define SCLK_DFIMON1_TIMER 147
114#define SCLK_INTMEM0 148
115#define SCLK_INTMEM1 149
116#define SCLK_INTMEM2 150
117#define SCLK_INTMEM3 151
118#define SCLK_INTMEM4 152
119#define SCLK_INTMEM5 153
120#define SCLK_SDMMC_DRV 154
121#define SCLK_SDMMC_SAMPLE 155
122#define SCLK_SDIO_DRV 156
123#define SCLK_SDIO_SAMPLE 157
124#define SCLK_VDU_CORE 158
125#define SCLK_VDU_CA 159
126#define SCLK_PCIE_PM 160
127#define SCLK_SPDIF_REC_DPTX 161
128#define SCLK_DPHY_PLL 162
129#define SCLK_DPHY_TX0_CFG 163
130#define SCLK_DPHY_TX1RX1_CFG 164
131#define SCLK_DPHY_RX0_CFG 165
132#define SCLK_RMII_SRC 166
133#define SCLK_PCIEPHY_REF100M 167
134
135#define DCLK_VOP0 180
136#define DCLK_VOP1 181
137#define DCLK_VOP0_DIV 182
138#define DCLK_VOP1_DIV 183
139#define DCLK_M0_PERILP 184
140
141#define FCLK_CM0S 190
142
143/* aclk gates */
144#define ACLK_PERIHP 192
145#define ACLK_PERIHP_NOC 193
146#define ACLK_PERILP0 194
147#define ACLK_PERILP0_NOC 195
148#define ACLK_PERF_PCIE 196
149#define ACLK_PCIE 197
150#define ACLK_INTMEM 198
151#define ACLK_TZMA 199
152#define ACLK_DCF 200
153#define ACLK_CCI 201
154#define ACLK_CCI_NOC0 202
155#define ACLK_CCI_NOC1 203
156#define ACLK_CCI_GRF 204
157#define ACLK_CENTER 205
158#define ACLK_CENTER_MAIN_NOC 206
159#define ACLK_CENTER_PERI_NOC 207
160#define ACLK_GPU 208
161#define ACLK_PERF_GPU 209
162#define ACLK_GPU_GRF 210
163#define ACLK_DMAC0_PERILP 211
164#define ACLK_DMAC1_PERILP 212
165#define ACLK_GMAC 213
166#define ACLK_GMAC_NOC 214
167#define ACLK_PERF_GMAC 215
168#define ACLK_VOP0_NOC 216
169#define ACLK_VOP0 217
170#define ACLK_VOP1_NOC 218
171#define ACLK_VOP1 219
172#define ACLK_RGA 220
173#define ACLK_RGA_NOC 221
174#define ACLK_HDCP 222
175#define ACLK_HDCP_NOC 223
176#define ACLK_HDCP22 224
177#define ACLK_IEP 225
178#define ACLK_IEP_NOC 226
179#define ACLK_VIO 227
180#define ACLK_VIO_NOC 228
181#define ACLK_ISP0 229
182#define ACLK_ISP1 230
183#define ACLK_ISP0_NOC 231
184#define ACLK_ISP1_NOC 232
185#define ACLK_ISP0_WRAPPER 233
186#define ACLK_ISP1_WRAPPER 234
187#define ACLK_VCODEC 235
188#define ACLK_VCODEC_NOC 236
189#define ACLK_VDU 237
190#define ACLK_VDU_NOC 238
191#define ACLK_PERI 239
192#define ACLK_EMMC 240
193#define ACLK_EMMC_CORE 241
194#define ACLK_EMMC_NOC 242
195#define ACLK_EMMC_GRF 243
196#define ACLK_USB3 244
197#define ACLK_USB3_NOC 245
198#define ACLK_USB3OTG0 246
199#define ACLK_USB3OTG1 247
200#define ACLK_USB3_RKSOC_AXI_PERF 248
201#define ACLK_USB3_GRF 249
202#define ACLK_GIC 250
203#define ACLK_GIC_NOC 251
204#define ACLK_GIC_ADB400_CORE_L_2_GIC 252
205#define ACLK_GIC_ADB400_CORE_B_2_GIC 253
206#define ACLK_GIC_ADB400_GIC_2_CORE_L 254
207#define ACLK_GIC_ADB400_GIC_2_CORE_B 255
208#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256
209#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
210#define ACLK_ADB400M_PD_CORE_L 258
211#define ACLK_ADB400M_PD_CORE_B 259
212#define ACLK_PERF_CORE_L 260
213#define ACLK_PERF_CORE_B 261
214#define ACLK_GIC_PRE 262
215#define ACLK_VOP0_PRE 263
216#define ACLK_VOP1_PRE 264
217
218/* pclk gates */
219#define PCLK_PERIHP 320
220#define PCLK_PERIHP_NOC 321
221#define PCLK_PERILP0 322
222#define PCLK_PERILP1 323
223#define PCLK_PERILP1_NOC 324
224#define PCLK_PERILP_SGRF 325
225#define PCLK_PERIHP_GRF 326
226#define PCLK_PCIE 327
227#define PCLK_SGRF 328
228#define PCLK_INTR_ARB 329
229#define PCLK_CENTER_MAIN_NOC 330
230#define PCLK_CIC 331
231#define PCLK_COREDBG_B 332
232#define PCLK_COREDBG_L 333
233#define PCLK_DBG_CXCS_PD_CORE_B 334
234#define PCLK_DCF 335
235#define PCLK_GPIO2 336
236#define PCLK_GPIO3 337
237#define PCLK_GPIO4 338
238#define PCLK_GRF 339
239#define PCLK_HSICPHY 340
240#define PCLK_I2C1 341
241#define PCLK_I2C2 342
242#define PCLK_I2C3 343
243#define PCLK_I2C5 344
244#define PCLK_I2C6 345
245#define PCLK_I2C7 346
246#define PCLK_SPI0 347
247#define PCLK_SPI1 348
248#define PCLK_SPI2 349
249#define PCLK_SPI4 350
250#define PCLK_SPI5 351
251#define PCLK_UART0 352
252#define PCLK_UART1 353
253#define PCLK_UART2 354
254#define PCLK_UART3 355
255#define PCLK_TSADC 356
256#define PCLK_SARADC 357
257#define PCLK_GMAC 358
258#define PCLK_GMAC_NOC 359
259#define PCLK_TIMER0 360
260#define PCLK_TIMER1 361
261#define PCLK_EDP 362
262#define PCLK_EDP_NOC 363
263#define PCLK_EDP_CTRL 364
264#define PCLK_VIO 365
265#define PCLK_VIO_NOC 366
266#define PCLK_VIO_GRF 367
267#define PCLK_MIPI_DSI0 368
268#define PCLK_MIPI_DSI1 369
269#define PCLK_HDCP 370
270#define PCLK_HDCP_NOC 371
271#define PCLK_HDMI_CTRL 372
272#define PCLK_DP_CTRL 373
273#define PCLK_HDCP22 374
274#define PCLK_GASKET 375
275#define PCLK_DDR 376
276#define PCLK_DDR_MON 377
277#define PCLK_DDR_SGRF 378
278#define PCLK_ISP1_WRAPPER 379
279#define PCLK_WDT 380
280#define PCLK_EFUSE1024NS 381
281#define PCLK_EFUSE1024S 382
282#define PCLK_PMU_INTR_ARB 383
283#define PCLK_MAILBOX0 384
284#define PCLK_USBPHY_MUX_G 385
285#define PCLK_UPHY0_TCPHY_G 386
286#define PCLK_UPHY0_TCPD_G 387
287#define PCLK_UPHY1_TCPHY_G 388
288#define PCLK_UPHY1_TCPD_G 389
289#define PCLK_ALIVE 390
290
291/* hclk gates */
292#define HCLK_PERIHP 448
293#define HCLK_PERILP0 449
294#define HCLK_PERILP1 450
295#define HCLK_PERILP0_NOC 451
296#define HCLK_PERILP1_NOC 452
297#define HCLK_M0_PERILP 453
298#define HCLK_M0_PERILP_NOC 454
299#define HCLK_AHB1TOM 455
300#define HCLK_HOST0 456
301#define HCLK_HOST0_ARB 457
302#define HCLK_HOST1 458
303#define HCLK_HOST1_ARB 459
304#define HCLK_HSIC 460
305#define HCLK_SD 461
306#define HCLK_SDMMC 462
307#define HCLK_SDMMC_NOC 463
308#define HCLK_M_CRYPTO0 464
309#define HCLK_M_CRYPTO1 465
310#define HCLK_S_CRYPTO0 466
311#define HCLK_S_CRYPTO1 467
312#define HCLK_I2S0_8CH 468
313#define HCLK_I2S1_8CH 469
314#define HCLK_I2S2_8CH 470
315#define HCLK_SPDIF 471
316#define HCLK_VOP0_NOC 472
317#define HCLK_VOP0 473
318#define HCLK_VOP1_NOC 474
319#define HCLK_VOP1 475
320#define HCLK_ROM 476
321#define HCLK_IEP 477
322#define HCLK_IEP_NOC 478
323#define HCLK_ISP0 479
324#define HCLK_ISP1 480
325#define HCLK_ISP0_NOC 481
326#define HCLK_ISP1_NOC 482
327#define HCLK_ISP0_WRAPPER 483
328#define HCLK_ISP1_WRAPPER 484
329#define HCLK_RGA 485
330#define HCLK_RGA_NOC 486
331#define HCLK_HDCP 487
332#define HCLK_HDCP_NOC 488
333#define HCLK_HDCP22 489
334#define HCLK_VCODEC 490
335#define HCLK_VCODEC_NOC 491
336#define HCLK_VDU 492
337#define HCLK_VDU_NOC 493
338#define HCLK_SDIO 494
339#define HCLK_SDIO_NOC 495
340#define HCLK_SDIOAUDIO_NOC 496
341
342#define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1)
343
344/* pmu-clocks indices */
345
346#define PLL_PPLL 1
347
348#define SCLK_32K_SUSPEND_PMU 2
349#define SCLK_SPI3_PMU 3
350#define SCLK_TIMER12_PMU 4
351#define SCLK_TIMER13_PMU 5
352#define SCLK_UART4_PMU 6
353#define SCLK_PVTM_PMU 7
354#define SCLK_WIFI_PMU 8
355#define SCLK_I2C0_PMU 9
356#define SCLK_I2C4_PMU 10
357#define SCLK_I2C8_PMU 11
358
359#define PCLK_SRC_PMU 19
360#define PCLK_PMU 20
361#define PCLK_PMUGRF_PMU 21
362#define PCLK_INTMEM1_PMU 22
363#define PCLK_GPIO0_PMU 23
364#define PCLK_GPIO1_PMU 24
365#define PCLK_SGRF_PMU 25
366#define PCLK_NOC_PMU 26
367#define PCLK_I2C0_PMU 27
368#define PCLK_I2C4_PMU 28
369#define PCLK_I2C8_PMU 29
370#define PCLK_RKPWM_PMU 30
371#define PCLK_SPI3_PMU 31
372#define PCLK_TIMER_PMU 32
373#define PCLK_MAILBOX_PMU 33
374#define PCLK_UART4_PMU 34
375#define PCLK_WDT_M0_PMU 35
376
377#define FCLK_CM0S_SRC_PMU 44
378#define FCLK_CM0S_PMU 45
379#define SCLK_CM0S_PMU 46
380#define HCLK_CM0S_PMU 47
381#define DCLK_CM0S_PMU 48
382#define PCLK_INTR_ARB_PMU 49
383#define HCLK_NOC_PMU 50
384
385#define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1)
386
387/* soft-reset indices */
388
389/* cru_softrst_con0 */
390#define SRST_CORE_L0 0
391#define SRST_CORE_B0 1
392#define SRST_CORE_PO_L0 2
393#define SRST_CORE_PO_B0 3
394#define SRST_L2_L 4
395#define SRST_L2_B 5
396#define SRST_ADB_L 6
397#define SRST_ADB_B 7
398#define SRST_A_CCI 8
399#define SRST_A_CCIM0_NOC 9
400#define SRST_A_CCIM1_NOC 10
401#define SRST_DBG_NOC 11
402
403/* cru_softrst_con1 */
404#define SRST_CORE_L0_T 16
405#define SRST_CORE_L1 17
406#define SRST_CORE_L2 18
407#define SRST_CORE_L3 19
408#define SRST_CORE_PO_L0_T 20
409#define SRST_CORE_PO_L1 21
410#define SRST_CORE_PO_L2 22
411#define SRST_CORE_PO_L3 23
412#define SRST_A_ADB400_GIC2COREL 24
413#define SRST_A_ADB400_COREL2GIC 25
414#define SRST_P_DBG_L 26
415#define SRST_L2_L_T 28
416#define SRST_ADB_L_T 29
417#define SRST_A_RKPERF_L 30
418#define SRST_PVTM_CORE_L 31
419
420/* cru_softrst_con2 */
421#define SRST_CORE_B0_T 32
422#define SRST_CORE_B1 33
423#define SRST_CORE_PO_B0_T 36
424#define SRST_CORE_PO_B1 37
425#define SRST_A_ADB400_GIC2COREB 40
426#define SRST_A_ADB400_COREB2GIC 41
427#define SRST_P_DBG_B 42
428#define SRST_L2_B_T 43
429#define SRST_ADB_B_T 45
430#define SRST_A_RKPERF_B 46
431#define SRST_PVTM_CORE_B 47
432
433/* cru_softrst_con3 */
434#define SRST_A_CCI_T 50
435#define SRST_A_CCIM0_NOC_T 51
436#define SRST_A_CCIM1_NOC_T 52
437#define SRST_A_ADB400M_PD_CORE_B_T 53
438#define SRST_A_ADB400M_PD_CORE_L_T 54
439#define SRST_DBG_NOC_T 55
440#define SRST_DBG_CXCS 56
441#define SRST_CCI_TRACE 57
442#define SRST_P_CCI_GRF 58
443
444/* cru_softrst_con4 */
445#define SRST_A_CENTER_MAIN_NOC 64
446#define SRST_A_CENTER_PERI_NOC 65
447#define SRST_P_CENTER_MAIN 66
448#define SRST_P_DDRMON 67
449#define SRST_P_CIC 68
450#define SRST_P_CENTER_SGRF 69
451#define SRST_DDR0_MSCH 70
452#define SRST_DDRCFG0_MSCH 71
453#define SRST_DDR0 72
454#define SRST_DDRPHY0 73
455#define SRST_DDR1_MSCH 74
456#define SRST_DDRCFG1_MSCH 75
457#define SRST_DDR1 76
458#define SRST_DDRPHY1 77
459#define SRST_DDR_CIC 78
460#define SRST_PVTM_DDR 79
461
462/* cru_softrst_con5 */
463#define SRST_A_VCODEC_NOC 80
464#define SRST_A_VCODEC 81
465#define SRST_H_VCODEC_NOC 82
466#define SRST_H_VCODEC 83
467#define SRST_A_VDU_NOC 88
468#define SRST_A_VDU 89
469#define SRST_H_VDU_NOC 90
470#define SRST_H_VDU 91
471#define SRST_VDU_CORE 92
472#define SRST_VDU_CA 93
473
474/* cru_softrst_con6 */
475#define SRST_A_IEP_NOC 96
476#define SRST_A_VOP_IEP 97
477#define SRST_A_IEP 98
478#define SRST_H_IEP_NOC 99
479#define SRST_H_IEP 100
480#define SRST_A_RGA_NOC 102
481#define SRST_A_RGA 103
482#define SRST_H_RGA_NOC 104
483#define SRST_H_RGA 105
484#define SRST_RGA_CORE 106
485#define SRST_EMMC_NOC 108
486#define SRST_EMMC 109
487#define SRST_EMMC_GRF 110
488
489/* cru_softrst_con7 */
490#define SRST_A_PERIHP_NOC 112
491#define SRST_P_PERIHP_GRF 113
492#define SRST_H_PERIHP_NOC 114
493#define SRST_USBHOST0 115
494#define SRST_HOSTC0_AUX 116
495#define SRST_HOST0_ARB 117
496#define SRST_USBHOST1 118
497#define SRST_HOSTC1_AUX 119
498#define SRST_HOST1_ARB 120
499#define SRST_SDIO0 121
500#define SRST_SDMMC 122
501#define SRST_HSIC 123
502#define SRST_HSIC_AUX 124
503#define SRST_AHB1TOM 125
504#define SRST_P_PERIHP_NOC 126
505#define SRST_HSICPHY 127
506
507/* cru_softrst_con8 */
508#define SRST_A_PCIE 128
509#define SRST_P_PCIE 129
510#define SRST_PCIE_CORE 130
511#define SRST_PCIE_MGMT 131
512#define SRST_PCIE_MGMT_STICKY 132
513#define SRST_PCIE_PIPE 133
514#define SRST_PCIE_PM 134
515#define SRST_PCIEPHY 135
516#define SRST_A_GMAC_NOC 136
517#define SRST_A_GMAC 137
518#define SRST_P_GMAC_NOC 138
519#define SRST_P_GMAC_GRF 140
520#define SRST_HSICPHY_POR 142
521#define SRST_HSICPHY_UTMI 143
522
523/* cru_softrst_con9 */
524#define SRST_USB2PHY0_POR 144
525#define SRST_USB2PHY0_UTMI_PORT0 145
526#define SRST_USB2PHY0_UTMI_PORT1 146
527#define SRST_USB2PHY0_EHCIPHY 147
528#define SRST_UPHY0_PIPE_L00 148
529#define SRST_UPHY0 149
530#define SRST_UPHY0_TCPDPWRUP 150
531#define SRST_USB2PHY1_POR 152
532#define SRST_USB2PHY1_UTMI_PORT0 153
533#define SRST_USB2PHY1_UTMI_PORT1 154
534#define SRST_USB2PHY1_EHCIPHY 155
535#define SRST_UPHY1_PIPE_L00 156
536#define SRST_UPHY1 157
537#define SRST_UPHY1_TCPDPWRUP 158
538
539/* cru_softrst_con10 */
540#define SRST_A_PERILP0_NOC 160
541#define SRST_A_DCF 161
542#define SRST_GIC500 162
543#define SRST_DMAC0_PERILP0 163
544#define SRST_DMAC1_PERILP0 164
545#define SRST_TZMA 165
546#define SRST_INTMEM 166
547#define SRST_ADB400_MST0 167
548#define SRST_ADB400_MST1 168
549#define SRST_ADB400_SLV0 169
550#define SRST_ADB400_SLV1 170
551#define SRST_H_PERILP0 171
552#define SRST_H_PERILP0_NOC 172
553#define SRST_ROM 173
554#define SRST_CRYPTO_S 174
555#define SRST_CRYPTO_M 175
556
557/* cru_softrst_con11 */
558#define SRST_P_DCF 176
559#define SRST_CM0S_NOC 177
560#define SRST_CM0S 178
561#define SRST_CM0S_DBG 179
562#define SRST_CM0S_PO 180
563#define SRST_CRYPTO 181
564#define SRST_P_PERILP1_SGRF 182
565#define SRST_P_PERILP1_GRF 183
566#define SRST_CRYPTO1_S 184
567#define SRST_CRYPTO1_M 185
568#define SRST_CRYPTO1 186
569#define SRST_GIC_NOC 188
570#define SRST_SD_NOC 189
571#define SRST_SDIOAUDIO_BRG 190
572
573/* cru_softrst_con12 */
574#define SRST_H_PERILP1 192
575#define SRST_H_PERILP1_NOC 193
576#define SRST_H_I2S0_8CH 194
577#define SRST_H_I2S1_8CH 195
578#define SRST_H_I2S2_8CH 196
579#define SRST_H_SPDIF_8CH 197
580#define SRST_P_PERILP1_NOC 198
581#define SRST_P_EFUSE_1024 199
582#define SRST_P_EFUSE_1024S 200
583#define SRST_P_I2C0 201
584#define SRST_P_I2C1 202
585#define SRST_P_I2C2 203
586#define SRST_P_I2C3 204
587#define SRST_P_I2C4 205
588#define SRST_P_I2C5 206
589#define SRST_P_MAILBOX0 207
590
591/* cru_softrst_con13 */
592#define SRST_P_UART0 208
593#define SRST_P_UART1 209
594#define SRST_P_UART2 210
595#define SRST_P_UART3 211
596#define SRST_P_SARADC 212
597#define SRST_P_TSADC 213
598#define SRST_P_SPI0 214
599#define SRST_P_SPI1 215
600#define SRST_P_SPI2 216
601#define SRST_P_SPI3 217
602#define SRST_P_SPI4 218
603#define SRST_SPI0 219
604#define SRST_SPI1 220
605#define SRST_SPI2 221
606#define SRST_SPI3 222
607#define SRST_SPI4 223
608
609/* cru_softrst_con14 */
610#define SRST_I2S0_8CH 224
611#define SRST_I2S1_8CH 225
612#define SRST_I2S2_8CH 226
613#define SRST_SPDIF_8CH 227
614#define SRST_UART0 228
615#define SRST_UART1 229
616#define SRST_UART2 230
617#define SRST_UART3 231
618#define SRST_TSADC 232
619#define SRST_I2C0 233
620#define SRST_I2C1 234
621#define SRST_I2C2 235
622#define SRST_I2C3 236
623#define SRST_I2C4 237
624#define SRST_I2C5 238
625#define SRST_SDIOAUDIO_NOC 239
626
627/* cru_softrst_con15 */
628#define SRST_A_VIO_NOC 240
629#define SRST_A_HDCP_NOC 241
630#define SRST_A_HDCP 242
631#define SRST_H_HDCP_NOC 243
632#define SRST_H_HDCP 244
633#define SRST_P_HDCP_NOC 245
634#define SRST_P_HDCP 246
635#define SRST_P_HDMI_CTRL 247
636#define SRST_P_DP_CTRL 248
637#define SRST_S_DP_CTRL 249
638#define SRST_C_DP_CTRL 250
639#define SRST_P_MIPI_DSI0 251
640#define SRST_P_MIPI_DSI1 252
641#define SRST_DP_CORE 253
642#define SRST_DP_I2S 254
643
644/* cru_softrst_con16 */
645#define SRST_GASKET 256
646#define SRST_VIO_GRF 258
647#define SRST_DPTX_SPDIF_REC 259
648#define SRST_HDMI_CTRL 260
649#define SRST_HDCP_CTRL 261
650#define SRST_A_ISP0_NOC 262
651#define SRST_A_ISP1_NOC 263
652#define SRST_H_ISP0_NOC 266
653#define SRST_H_ISP1_NOC 267
654#define SRST_H_ISP0 268
655#define SRST_H_ISP1 269
656#define SRST_ISP0 270
657#define SRST_ISP1 271
658
659/* cru_softrst_con17 */
660#define SRST_A_VOP0_NOC 272
661#define SRST_A_VOP1_NOC 273
662#define SRST_A_VOP0 274
663#define SRST_A_VOP1 275
664#define SRST_H_VOP0_NOC 276
665#define SRST_H_VOP1_NOC 277
666#define SRST_H_VOP0 278
667#define SRST_H_VOP1 279
668#define SRST_D_VOP0 280
669#define SRST_D_VOP1 281
670#define SRST_VOP0_PWM 282
671#define SRST_VOP1_PWM 283
672#define SRST_P_EDP_NOC 284
673#define SRST_P_EDP_CTRL 285
674
675/* cru_softrst_con18 */
676#define SRST_A_GPU 288
677#define SRST_A_GPU_NOC 289
678#define SRST_A_GPU_GRF 290
679#define SRST_PVTM_GPU 291
680#define SRST_A_USB3_NOC 292
681#define SRST_A_USB3_OTG0 293
682#define SRST_A_USB3_OTG1 294
683#define SRST_A_USB3_GRF 295
684#define SRST_PMU 296
685
686/* cru_softrst_con19 */
687#define SRST_P_TIMER0_5 304
688#define SRST_TIMER0 305
689#define SRST_TIMER1 306
690#define SRST_TIMER2 307
691#define SRST_TIMER3 308
692#define SRST_TIMER4 309
693#define SRST_TIMER5 310
694#define SRST_P_TIMER6_11 311
695#define SRST_TIMER6 312
696#define SRST_TIMER7 313
697#define SRST_TIMER8 314
698#define SRST_TIMER9 315
699#define SRST_TIMER10 316
700#define SRST_TIMER11 317
701#define SRST_P_INTR_ARB_PMU 318
702#define SRST_P_ALIVE_SGRF 319
703
704/* cru_softrst_con20 */
705#define SRST_P_GPIO2 320
706#define SRST_P_GPIO3 321
707#define SRST_P_GPIO4 322
708#define SRST_P_GRF 323
709#define SRST_P_ALIVE_NOC 324
710#define SRST_P_WDT0 325
711#define SRST_P_WDT1 326
712#define SRST_P_INTR_ARB 327
713#define SRST_P_UPHY0_DPTX 328
714#define SRST_P_UPHY0_APB 330
715#define SRST_P_UPHY0_TCPHY 332
716#define SRST_P_UPHY1_TCPHY 333
717#define SRST_P_UPHY0_TCPDCTRL 334
718#define SRST_P_UPHY1_TCPDCTRL 335
719
720/* pmu soft-reset indices */
721
722/* pmu_cru_softrst_con0 */
723#define SRST_P_NOC 0
724#define SRST_P_INTMEM 1
725#define SRST_H_CM0S 2
726#define SRST_H_CM0S_NOC 3
727#define SRST_DBG_CM0S 4
728#define SRST_PO_CM0S 5
729#define SRST_P_SPI6 6
730#define SRST_SPI6 7
731#define SRST_P_TIMER_0_1 8
732#define SRST_P_TIMER_0 9
733#define SRST_P_TIMER_1 10
734#define SRST_P_UART4 11
735#define SRST_UART4 12
736#define SRST_P_WDT 13
737
738/* pmu_cru_softrst_con1 */
739#define SRST_P_I2C6 16
740#define SRST_P_I2C7 17
741#define SRST_P_I2C8 18
742#define SRST_P_MAILBOX 19
743#define SRST_P_RKPWM 20
744#define SRST_P_PMUGRF 21
745#define SRST_P_SGRF 22
746#define SRST_P_GPIO0 23
747#define SRST_P_GPIO1 24
748#define SRST_P_CRU 25
749#define SRST_P_INTR 26
750#define SRST_PVTM 27
751#define SRST_I2C6 28
752#define SRST_I2C7 29
753#define SRST_I2C8 30
754
755#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-27 03:55:36 -0400