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-rw-r--r--drivers/gpu/drm/i915/intel_display.c46
1 files changed, 7 insertions, 39 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7a03fdc079b7..faf4d186caf7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12893,20 +12893,11 @@ intel_modeset_stage_output_state(struct drm_device *dev,
12893 return 0; 12893 return 0;
12894} 12894}
12895 12895
12896static bool primary_plane_visible(struct drm_crtc *crtc)
12897{
12898 struct intel_plane_state *plane_state =
12899 to_intel_plane_state(crtc->primary->state);
12900
12901 return plane_state->visible;
12902}
12903
12904static int intel_crtc_set_config(struct drm_mode_set *set) 12896static int intel_crtc_set_config(struct drm_mode_set *set)
12905{ 12897{
12906 struct drm_device *dev; 12898 struct drm_device *dev;
12907 struct drm_atomic_state *state = NULL; 12899 struct drm_atomic_state *state = NULL;
12908 struct intel_crtc_state *pipe_config; 12900 struct intel_crtc_state *pipe_config;
12909 bool primary_plane_was_visible;
12910 int ret; 12901 int ret;
12911 12902
12912 BUG_ON(!set); 12903 BUG_ON(!set);
@@ -12945,38 +12936,8 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
12945 12936
12946 intel_update_pipe_size(to_intel_crtc(set->crtc)); 12937 intel_update_pipe_size(to_intel_crtc(set->crtc));
12947 12938
12948 primary_plane_was_visible = primary_plane_visible(set->crtc);
12949
12950 ret = intel_set_mode_with_config(set->crtc, pipe_config, true); 12939 ret = intel_set_mode_with_config(set->crtc, pipe_config, true);
12951 12940
12952 if (ret == 0 &&
12953 pipe_config->base.enable &&
12954 pipe_config->base.planes_changed &&
12955 !needs_modeset(&pipe_config->base)) {
12956 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
12957
12958 /*
12959 * We need to make sure the primary plane is re-enabled if it
12960 * has previously been turned off.
12961 */
12962 if (ret == 0 && !primary_plane_was_visible &&
12963 primary_plane_visible(set->crtc)) {
12964 WARN_ON(!intel_crtc->active);
12965 intel_post_enable_primary(set->crtc);
12966 }
12967
12968 /*
12969 * In the fastboot case this may be our only check of the
12970 * state after boot. It would be better to only do it on
12971 * the first update, but we don't have a nice way of doing that
12972 * (and really, set_config isn't used much for high freq page
12973 * flipping, so increasing its cost here shouldn't be a big
12974 * deal).
12975 */
12976 if (i915.fastboot && ret == 0)
12977 intel_modeset_check_state(set->crtc->dev);
12978 }
12979
12980 if (ret) { 12941 if (ret) {
12981 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", 12942 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12982 set->crtc->base.id, ret); 12943 set->crtc->base.id, ret);
@@ -13307,6 +13268,9 @@ intel_check_primary_plane(struct drm_plane *plane,
13307 */ 13268 */
13308 if (IS_BROADWELL(dev)) 13269 if (IS_BROADWELL(dev))
13309 intel_crtc->atomic.wait_vblank = true; 13270 intel_crtc->atomic.wait_vblank = true;
13271
13272 if (crtc_state && !needs_modeset(&crtc_state->base))
13273 intel_crtc->atomic.post_enable_primary = true;
13310 } 13274 }
13311 13275
13312 /* 13276 /*
@@ -13319,6 +13283,10 @@ intel_check_primary_plane(struct drm_plane *plane,
13319 if (!state->visible || !fb) 13283 if (!state->visible || !fb)
13320 intel_crtc->atomic.disable_ips = true; 13284 intel_crtc->atomic.disable_ips = true;
13321 13285
13286 if (!state->visible && old_state->visible &&
13287 crtc_state && !needs_modeset(&crtc_state->base))
13288 intel_crtc->atomic.pre_disable_primary = true;
13289
13322 intel_crtc->atomic.fb_bits |= 13290 intel_crtc->atomic.fb_bits |=
13323 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); 13291 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13324 13292