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-rw-r--r--drivers/gpu/drm/sti/Kconfig6
-rw-r--r--drivers/gpu/drm/sti/Makefile1
-rw-r--r--drivers/gpu/drm/sti/sti_compositor.c51
-rw-r--r--drivers/gpu/drm/sti/sti_compositor.h14
-rw-r--r--drivers/gpu/drm/sti/sti_crtc.c26
-rw-r--r--drivers/gpu/drm/sti/sti_cursor.c8
-rw-r--r--drivers/gpu/drm/sti/sti_drv.c2
-rw-r--r--drivers/gpu/drm/sti/sti_dvo.c3
-rw-r--r--drivers/gpu/drm/sti/sti_gdp.c35
-rw-r--r--drivers/gpu/drm/sti/sti_hda.c39
-rw-r--r--drivers/gpu/drm/sti/sti_hdmi.c31
-rw-r--r--drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.c336
-rw-r--r--drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.h14
-rw-r--r--drivers/gpu/drm/sti/sti_hqvdp.c25
-rw-r--r--drivers/gpu/drm/sti/sti_mixer.c19
-rw-r--r--drivers/gpu/drm/sti/sti_tvout.c41
-rw-r--r--drivers/gpu/drm/sti/sti_vid.c4
-rw-r--r--drivers/gpu/drm/sti/sti_vtac.c2
-rw-r--r--drivers/gpu/drm/sti/sti_vtg.c3
19 files changed, 99 insertions, 561 deletions
diff --git a/drivers/gpu/drm/sti/Kconfig b/drivers/gpu/drm/sti/Kconfig
index 494ab257f77c..acd72865feac 100644
--- a/drivers/gpu/drm/sti/Kconfig
+++ b/drivers/gpu/drm/sti/Kconfig
@@ -1,6 +1,6 @@
1config DRM_STI 1config DRM_STI
2 tristate "DRM Support for STMicroelectronics SoC stiH41x Series" 2 tristate "DRM Support for STMicroelectronics SoC stiH4xx Series"
3 depends on DRM && (SOC_STIH415 || SOC_STIH416 || ARCH_MULTIPLATFORM) 3 depends on DRM && (ARCH_STI || ARCH_MULTIPLATFORM)
4 select RESET_CONTROLLER 4 select RESET_CONTROLLER
5 select DRM_KMS_HELPER 5 select DRM_KMS_HELPER
6 select DRM_GEM_CMA_HELPER 6 select DRM_GEM_CMA_HELPER
@@ -9,4 +9,4 @@ config DRM_STI
9 select FW_LOADER 9 select FW_LOADER
10 select SND_SOC_HDMI_CODEC if SND_SOC 10 select SND_SOC_HDMI_CODEC if SND_SOC
11 help 11 help
12 Choose this option to enable DRM on STM stiH41x chipset 12 Choose this option to enable DRM on STM stiH4xx chipset
diff --git a/drivers/gpu/drm/sti/Makefile b/drivers/gpu/drm/sti/Makefile
index b8057620b3b3..d20f7c0b4eac 100644
--- a/drivers/gpu/drm/sti/Makefile
+++ b/drivers/gpu/drm/sti/Makefile
@@ -9,7 +9,6 @@ sti-drm-y := \
9 sti_crtc.o \ 9 sti_crtc.o \
10 sti_plane.o \ 10 sti_plane.o \
11 sti_hdmi.o \ 11 sti_hdmi.o \
12 sti_hdmi_tx3g0c55phy.o \
13 sti_hdmi_tx3g4c28phy.o \ 12 sti_hdmi_tx3g4c28phy.o \
14 sti_dvo.o \ 13 sti_dvo.o \
15 sti_awg_utils.o \ 14 sti_awg_utils.o \
diff --git a/drivers/gpu/drm/sti/sti_compositor.c b/drivers/gpu/drm/sti/sti_compositor.c
index 134201ecc6fd..f62041fe8412 100644
--- a/drivers/gpu/drm/sti/sti_compositor.c
+++ b/drivers/gpu/drm/sti/sti_compositor.c
@@ -25,7 +25,7 @@
25/* 25/*
26 * stiH407 compositor properties 26 * stiH407 compositor properties
27 */ 27 */
28struct sti_compositor_data stih407_compositor_data = { 28static const struct sti_compositor_data stih407_compositor_data = {
29 .nb_subdev = 8, 29 .nb_subdev = 8,
30 .subdev_desc = { 30 .subdev_desc = {
31 {STI_CURSOR_SUBDEV, (int)STI_CURSOR, 0x000}, 31 {STI_CURSOR_SUBDEV, (int)STI_CURSOR, 0x000},
@@ -39,38 +39,18 @@ struct sti_compositor_data stih407_compositor_data = {
39 }, 39 },
40}; 40};
41 41
42/* 42int sti_compositor_debugfs_init(struct sti_compositor *compo,
43 * stiH416 compositor properties 43 struct drm_minor *minor)
44 * Note:
45 * on stih416 MIXER_AUX has a different base address from MIXER_MAIN
46 * Moreover, GDPx is different for Main and Aux Mixer. So this subdev map does
47 * not fit for stiH416 if we want to enable the MIXER_AUX.
48 */
49struct sti_compositor_data stih416_compositor_data = {
50 .nb_subdev = 3,
51 .subdev_desc = {
52 {STI_GPD_SUBDEV, (int)STI_GDP_0, 0x100},
53 {STI_GPD_SUBDEV, (int)STI_GDP_1, 0x200},
54 {STI_MIXER_MAIN_SUBDEV, STI_MIXER_MAIN, 0xC00}
55 },
56};
57
58int sti_compositor_debufs_init(struct sti_compositor *compo,
59 struct drm_minor *minor)
60{ 44{
61 int ret = 0, i; 45 unsigned int i;
62 46
63 for (i = 0; compo->vid[i]; i++) { 47 for (i = 0; i < STI_MAX_VID; i++)
64 ret = vid_debugfs_init(compo->vid[i], minor); 48 if (compo->vid[i])
65 if (ret) 49 vid_debugfs_init(compo->vid[i], minor);
66 return ret;
67 }
68 50
69 for (i = 0; compo->mixer[i]; i++) { 51 for (i = 0; i < STI_MAX_MIXER; i++)
70 ret = sti_mixer_debugfs_init(compo->mixer[i], minor); 52 if (compo->mixer[i])
71 if (ret) 53 sti_mixer_debugfs_init(compo->mixer[i], minor);
72 return ret;
73 }
74 54
75 return 0; 55 return 0;
76} 56}
@@ -183,9 +163,6 @@ static const struct component_ops sti_compositor_ops = {
183 163
184static const struct of_device_id compositor_of_match[] = { 164static const struct of_device_id compositor_of_match[] = {
185 { 165 {
186 .compatible = "st,stih416-compositor",
187 .data = &stih416_compositor_data,
188 }, {
189 .compatible = "st,stih407-compositor", 166 .compatible = "st,stih407-compositor",
190 .data = &stih407_compositor_data, 167 .data = &stih407_compositor_data,
191 }, { 168 }, {
@@ -201,6 +178,7 @@ static int sti_compositor_probe(struct platform_device *pdev)
201 struct device_node *vtg_np; 178 struct device_node *vtg_np;
202 struct sti_compositor *compo; 179 struct sti_compositor *compo;
203 struct resource *res; 180 struct resource *res;
181 unsigned int i;
204 182
205 compo = devm_kzalloc(dev, sizeof(*compo), GFP_KERNEL); 183 compo = devm_kzalloc(dev, sizeof(*compo), GFP_KERNEL);
206 if (!compo) { 184 if (!compo) {
@@ -208,7 +186,8 @@ static int sti_compositor_probe(struct platform_device *pdev)
208 return -ENOMEM; 186 return -ENOMEM;
209 } 187 }
210 compo->dev = dev; 188 compo->dev = dev;
211 compo->vtg_vblank_nb.notifier_call = sti_crtc_vblank_cb; 189 for (i = 0; i < STI_MAX_MIXER; i++)
190 compo->vtg_vblank_nb[i].notifier_call = sti_crtc_vblank_cb;
212 191
213 /* populate data structure depending on compatibility */ 192 /* populate data structure depending on compatibility */
214 BUG_ON(!of_match_node(compositor_of_match, np)->data); 193 BUG_ON(!of_match_node(compositor_of_match, np)->data);
@@ -266,12 +245,12 @@ static int sti_compositor_probe(struct platform_device *pdev)
266 245
267 vtg_np = of_parse_phandle(pdev->dev.of_node, "st,vtg", 0); 246 vtg_np = of_parse_phandle(pdev->dev.of_node, "st,vtg", 0);
268 if (vtg_np) 247 if (vtg_np)
269 compo->vtg_main = of_vtg_find(vtg_np); 248 compo->vtg[STI_MIXER_MAIN] = of_vtg_find(vtg_np);
270 of_node_put(vtg_np); 249 of_node_put(vtg_np);
271 250
272 vtg_np = of_parse_phandle(pdev->dev.of_node, "st,vtg", 1); 251 vtg_np = of_parse_phandle(pdev->dev.of_node, "st,vtg", 1);
273 if (vtg_np) 252 if (vtg_np)
274 compo->vtg_aux = of_vtg_find(vtg_np); 253 compo->vtg[STI_MIXER_AUX] = of_vtg_find(vtg_np);
275 of_node_put(vtg_np); 254 of_node_put(vtg_np);
276 255
277 platform_set_drvdata(pdev, compo); 256 platform_set_drvdata(pdev, compo);
diff --git a/drivers/gpu/drm/sti/sti_compositor.h b/drivers/gpu/drm/sti/sti_compositor.h
index 24444ef42a98..2952a2d25a52 100644
--- a/drivers/gpu/drm/sti/sti_compositor.h
+++ b/drivers/gpu/drm/sti/sti_compositor.h
@@ -60,9 +60,8 @@ struct sti_compositor_data {
60 * @rst_aux: reset control of the aux path 60 * @rst_aux: reset control of the aux path
61 * @mixer: array of mixers 61 * @mixer: array of mixers
62 * @vid: array of vids 62 * @vid: array of vids
63 * @vtg_main: vtg for main data path 63 * @vtg: array of vtgs
64 * @vtg_aux: vtg for auxillary data path 64 * @vtg_vblank_nb: array of callbacks for VTG VSYNC notification
65 * @vtg_vblank_nb: callback for VTG VSYNC notification
66 */ 65 */
67struct sti_compositor { 66struct sti_compositor {
68 struct device *dev; 67 struct device *dev;
@@ -76,12 +75,11 @@ struct sti_compositor {
76 struct reset_control *rst_aux; 75 struct reset_control *rst_aux;
77 struct sti_mixer *mixer[STI_MAX_MIXER]; 76 struct sti_mixer *mixer[STI_MAX_MIXER];
78 struct sti_vid *vid[STI_MAX_VID]; 77 struct sti_vid *vid[STI_MAX_VID];
79 struct sti_vtg *vtg_main; 78 struct sti_vtg *vtg[STI_MAX_MIXER];
80 struct sti_vtg *vtg_aux; 79 struct notifier_block vtg_vblank_nb[STI_MAX_MIXER];
81 struct notifier_block vtg_vblank_nb;
82}; 80};
83 81
84int sti_compositor_debufs_init(struct sti_compositor *compo, 82int sti_compositor_debugfs_init(struct sti_compositor *compo,
85 struct drm_minor *minor); 83 struct drm_minor *minor);
86 84
87#endif 85#endif
diff --git a/drivers/gpu/drm/sti/sti_crtc.c b/drivers/gpu/drm/sti/sti_crtc.c
index c7d734dc3cf4..e992bed98dcb 100644
--- a/drivers/gpu/drm/sti/sti_crtc.c
+++ b/drivers/gpu/drm/sti/sti_crtc.c
@@ -86,8 +86,7 @@ sti_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode)
86 goto pix_error; 86 goto pix_error;
87 } 87 }
88 88
89 sti_vtg_set_config(mixer->id == STI_MIXER_MAIN ? 89 sti_vtg_set_config(compo->vtg[mixer->id], &crtc->mode);
90 compo->vtg_main : compo->vtg_aux, &crtc->mode);
91 90
92 if (sti_mixer_active_video_area(mixer, &crtc->mode)) { 91 if (sti_mixer_active_video_area(mixer, &crtc->mode)) {
93 DRM_ERROR("Can't set active video area\n"); 92 DRM_ERROR("Can't set active video area\n");
@@ -166,6 +165,10 @@ static void sti_crtc_atomic_flush(struct drm_crtc *crtc,
166 165
167 switch (plane->status) { 166 switch (plane->status) {
168 case STI_PLANE_UPDATED: 167 case STI_PLANE_UPDATED:
168 /* ignore update for other CRTC */
169 if (p->state->crtc != crtc)
170 continue;
171
169 /* update planes tag as updated */ 172 /* update planes tag as updated */
170 DRM_DEBUG_DRIVER("update plane %s\n", 173 DRM_DEBUG_DRIVER("update plane %s\n",
171 sti_plane_to_str(plane)); 174 sti_plane_to_str(plane));
@@ -244,8 +247,7 @@ static int sti_crtc_set_property(struct drm_crtc *crtc,
244int sti_crtc_vblank_cb(struct notifier_block *nb, 247int sti_crtc_vblank_cb(struct notifier_block *nb,
245 unsigned long event, void *data) 248 unsigned long event, void *data)
246{ 249{
247 struct sti_compositor *compo = 250 struct sti_compositor *compo;
248 container_of(nb, struct sti_compositor, vtg_vblank_nb);
249 struct drm_crtc *crtc = data; 251 struct drm_crtc *crtc = data;
250 struct sti_mixer *mixer; 252 struct sti_mixer *mixer;
251 unsigned long flags; 253 unsigned long flags;
@@ -254,6 +256,7 @@ int sti_crtc_vblank_cb(struct notifier_block *nb,
254 256
255 priv = crtc->dev->dev_private; 257 priv = crtc->dev->dev_private;
256 pipe = drm_crtc_index(crtc); 258 pipe = drm_crtc_index(crtc);
259 compo = container_of(nb, struct sti_compositor, vtg_vblank_nb[pipe]);
257 mixer = compo->mixer[pipe]; 260 mixer = compo->mixer[pipe];
258 261
259 if ((event != VTG_TOP_FIELD_EVENT) && 262 if ((event != VTG_TOP_FIELD_EVENT) &&
@@ -295,14 +298,13 @@ int sti_crtc_enable_vblank(struct drm_device *dev, unsigned int pipe)
295{ 298{
296 struct sti_private *dev_priv = dev->dev_private; 299 struct sti_private *dev_priv = dev->dev_private;
297 struct sti_compositor *compo = dev_priv->compo; 300 struct sti_compositor *compo = dev_priv->compo;
298 struct notifier_block *vtg_vblank_nb = &compo->vtg_vblank_nb; 301 struct notifier_block *vtg_vblank_nb = &compo->vtg_vblank_nb[pipe];
299 struct drm_crtc *crtc = &compo->mixer[pipe]->drm_crtc; 302 struct drm_crtc *crtc = &compo->mixer[pipe]->drm_crtc;
303 struct sti_vtg *vtg = compo->vtg[pipe];
300 304
301 DRM_DEBUG_DRIVER("\n"); 305 DRM_DEBUG_DRIVER("\n");
302 306
303 if (sti_vtg_register_client(pipe == STI_MIXER_MAIN ? 307 if (sti_vtg_register_client(vtg, vtg_vblank_nb, crtc)) {
304 compo->vtg_main : compo->vtg_aux,
305 vtg_vblank_nb, crtc)) {
306 DRM_ERROR("Cannot register VTG notifier\n"); 308 DRM_ERROR("Cannot register VTG notifier\n");
307 return -EINVAL; 309 return -EINVAL;
308 } 310 }
@@ -314,13 +316,13 @@ void sti_crtc_disable_vblank(struct drm_device *drm_dev, unsigned int pipe)
314{ 316{
315 struct sti_private *priv = drm_dev->dev_private; 317 struct sti_private *priv = drm_dev->dev_private;
316 struct sti_compositor *compo = priv->compo; 318 struct sti_compositor *compo = priv->compo;
317 struct notifier_block *vtg_vblank_nb = &compo->vtg_vblank_nb; 319 struct notifier_block *vtg_vblank_nb = &compo->vtg_vblank_nb[pipe];
318 struct drm_crtc *crtc = &compo->mixer[pipe]->drm_crtc; 320 struct drm_crtc *crtc = &compo->mixer[pipe]->drm_crtc;
321 struct sti_vtg *vtg = compo->vtg[pipe];
319 322
320 DRM_DEBUG_DRIVER("\n"); 323 DRM_DEBUG_DRIVER("\n");
321 324
322 if (sti_vtg_unregister_client(pipe == STI_MIXER_MAIN ? 325 if (sti_vtg_unregister_client(vtg, vtg_vblank_nb))
323 compo->vtg_main : compo->vtg_aux, vtg_vblank_nb))
324 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n"); 326 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
325 327
326 /* free the resources of the pending requests */ 328 /* free the resources of the pending requests */
@@ -336,7 +338,7 @@ static int sti_crtc_late_register(struct drm_crtc *crtc)
336 struct sti_compositor *compo = dev_get_drvdata(mixer->dev); 338 struct sti_compositor *compo = dev_get_drvdata(mixer->dev);
337 339
338 if (drm_crtc_index(crtc) == 0) 340 if (drm_crtc_index(crtc) == 0)
339 return sti_compositor_debufs_init(compo, crtc->dev->primary); 341 return sti_compositor_debugfs_init(compo, crtc->dev->primary);
340 342
341 return 0; 343 return 0;
342} 344}
diff --git a/drivers/gpu/drm/sti/sti_cursor.c b/drivers/gpu/drm/sti/sti_cursor.c
index 3b53f7f2e3fc..cca75bddb9ad 100644
--- a/drivers/gpu/drm/sti/sti_cursor.c
+++ b/drivers/gpu/drm/sti/sti_cursor.c
@@ -309,15 +309,15 @@ static void sti_cursor_atomic_disable(struct drm_plane *drm_plane,
309{ 309{
310 struct sti_plane *plane = to_sti_plane(drm_plane); 310 struct sti_plane *plane = to_sti_plane(drm_plane);
311 311
312 if (!drm_plane->crtc) { 312 if (!oldstate->crtc) {
313 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n", 313 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n",
314 drm_plane->base.id); 314 drm_plane->base.id);
315 return; 315 return;
316 } 316 }
317 317
318 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n", 318 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n",
319 drm_plane->crtc->base.id, 319 oldstate->crtc->base.id,
320 sti_mixer_to_str(to_sti_mixer(drm_plane->crtc)), 320 sti_mixer_to_str(to_sti_mixer(oldstate->crtc)),
321 drm_plane->base.id, sti_plane_to_str(plane)); 321 drm_plane->base.id, sti_plane_to_str(plane));
322 322
323 plane->status = STI_PLANE_DISABLING; 323 plane->status = STI_PLANE_DISABLING;
@@ -345,7 +345,7 @@ static int sti_cursor_late_register(struct drm_plane *drm_plane)
345 return cursor_debugfs_init(cursor, drm_plane->dev->primary); 345 return cursor_debugfs_init(cursor, drm_plane->dev->primary);
346} 346}
347 347
348struct drm_plane_funcs sti_cursor_plane_helpers_funcs = { 348static const struct drm_plane_funcs sti_cursor_plane_helpers_funcs = {
349 .update_plane = drm_atomic_helper_update_plane, 349 .update_plane = drm_atomic_helper_update_plane,
350 .disable_plane = drm_atomic_helper_disable_plane, 350 .disable_plane = drm_atomic_helper_disable_plane,
351 .destroy = sti_cursor_destroy, 351 .destroy = sti_cursor_destroy,
diff --git a/drivers/gpu/drm/sti/sti_drv.c b/drivers/gpu/drm/sti/sti_drv.c
index 49ed3c4b7ac5..2784919a7366 100644
--- a/drivers/gpu/drm/sti/sti_drv.c
+++ b/drivers/gpu/drm/sti/sti_drv.c
@@ -140,7 +140,7 @@ err:
140 return ret; 140 return ret;
141} 141}
142 142
143void sti_drm_dbg_cleanup(struct drm_minor *minor) 143static void sti_drm_dbg_cleanup(struct drm_minor *minor)
144{ 144{
145 drm_debugfs_remove_files(sti_drm_dbg_list, 145 drm_debugfs_remove_files(sti_drm_dbg_list,
146 ARRAY_SIZE(sti_drm_dbg_list), minor); 146 ARRAY_SIZE(sti_drm_dbg_list), minor);
diff --git a/drivers/gpu/drm/sti/sti_dvo.c b/drivers/gpu/drm/sti/sti_dvo.c
index 00881eb4536e..e8c1ed08a9f7 100644
--- a/drivers/gpu/drm/sti/sti_dvo.c
+++ b/drivers/gpu/drm/sti/sti_dvo.c
@@ -17,6 +17,7 @@
17#include <drm/drm_panel.h> 17#include <drm/drm_panel.h>
18 18
19#include "sti_awg_utils.h" 19#include "sti_awg_utils.h"
20#include "sti_drv.h"
20#include "sti_mixer.h" 21#include "sti_mixer.h"
21 22
22/* DVO registers */ 23/* DVO registers */
@@ -106,7 +107,7 @@ struct sti_dvo_connector {
106 container_of(x, struct sti_dvo_connector, drm_connector) 107 container_of(x, struct sti_dvo_connector, drm_connector)
107 108
108#define BLANKING_LEVEL 16 109#define BLANKING_LEVEL 16
109int dvo_awg_generate_code(struct sti_dvo *dvo, u8 *ram_size, u32 *ram_code) 110static int dvo_awg_generate_code(struct sti_dvo *dvo, u8 *ram_size, u32 *ram_code)
110{ 111{
111 struct drm_display_mode *mode = &dvo->mode; 112 struct drm_display_mode *mode = &dvo->mode;
112 struct dvo_config *config = dvo->config; 113 struct dvo_config *config = dvo->config;
diff --git a/drivers/gpu/drm/sti/sti_gdp.c b/drivers/gpu/drm/sti/sti_gdp.c
index b8d942ca45e8..81df3097b545 100644
--- a/drivers/gpu/drm/sti/sti_gdp.c
+++ b/drivers/gpu/drm/sti/sti_gdp.c
@@ -460,6 +460,7 @@ static void sti_gdp_disable(struct sti_gdp *gdp)
460 clk_disable_unprepare(gdp->clk_pix); 460 clk_disable_unprepare(gdp->clk_pix);
461 461
462 gdp->plane.status = STI_PLANE_DISABLED; 462 gdp->plane.status = STI_PLANE_DISABLED;
463 gdp->vtg = NULL;
463} 464}
464 465
465/** 466/**
@@ -473,8 +474,8 @@ static void sti_gdp_disable(struct sti_gdp *gdp)
473 * RETURNS: 474 * RETURNS:
474 * 0 on success. 475 * 0 on success.
475 */ 476 */
476int sti_gdp_field_cb(struct notifier_block *nb, 477static int sti_gdp_field_cb(struct notifier_block *nb,
477 unsigned long event, void *data) 478 unsigned long event, void *data)
478{ 479{
479 struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb); 480 struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb);
480 481
@@ -611,7 +612,6 @@ static int sti_gdp_atomic_check(struct drm_plane *drm_plane,
611 struct drm_crtc *crtc = state->crtc; 612 struct drm_crtc *crtc = state->crtc;
612 struct sti_compositor *compo = dev_get_drvdata(gdp->dev); 613 struct sti_compositor *compo = dev_get_drvdata(gdp->dev);
613 struct drm_framebuffer *fb = state->fb; 614 struct drm_framebuffer *fb = state->fb;
614 bool first_prepare = plane->status == STI_PLANE_DISABLED ? true : false;
615 struct drm_crtc_state *crtc_state; 615 struct drm_crtc_state *crtc_state;
616 struct sti_mixer *mixer; 616 struct sti_mixer *mixer;
617 struct drm_display_mode *mode; 617 struct drm_display_mode *mode;
@@ -628,8 +628,8 @@ static int sti_gdp_atomic_check(struct drm_plane *drm_plane,
628 mode = &crtc_state->mode; 628 mode = &crtc_state->mode;
629 dst_x = state->crtc_x; 629 dst_x = state->crtc_x;
630 dst_y = state->crtc_y; 630 dst_y = state->crtc_y;
631 dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x); 631 dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x);
632 dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y); 632 dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y);
633 /* src_x are in 16.16 format */ 633 /* src_x are in 16.16 format */
634 src_x = state->src_x >> 16; 634 src_x = state->src_x >> 16;
635 src_y = state->src_y >> 16; 635 src_y = state->src_y >> 16;
@@ -648,10 +648,9 @@ static int sti_gdp_atomic_check(struct drm_plane *drm_plane,
648 return -EINVAL; 648 return -EINVAL;
649 } 649 }
650 650
651 if (first_prepare) { 651 if (!gdp->vtg) {
652 /* Register gdp callback */ 652 /* Register gdp callback */
653 gdp->vtg = mixer->id == STI_MIXER_MAIN ? 653 gdp->vtg = compo->vtg[mixer->id];
654 compo->vtg_main : compo->vtg_aux;
655 if (sti_vtg_register_client(gdp->vtg, 654 if (sti_vtg_register_client(gdp->vtg,
656 &gdp->vtg_field_nb, crtc)) { 655 &gdp->vtg_field_nb, crtc)) {
657 DRM_ERROR("Cannot register VTG notifier\n"); 656 DRM_ERROR("Cannot register VTG notifier\n");
@@ -719,7 +718,7 @@ static void sti_gdp_atomic_update(struct drm_plane *drm_plane,
719 u32 dma_updated_top; 718 u32 dma_updated_top;
720 u32 dma_updated_btm; 719 u32 dma_updated_btm;
721 int format; 720 int format;
722 unsigned int depth, bpp; 721 unsigned int bpp;
723 u32 ydo, xdo, yds, xds; 722 u32 ydo, xdo, yds, xds;
724 723
725 if (!crtc || !fb) 724 if (!crtc || !fb)
@@ -728,8 +727,8 @@ static void sti_gdp_atomic_update(struct drm_plane *drm_plane,
728 mode = &crtc->mode; 727 mode = &crtc->mode;
729 dst_x = state->crtc_x; 728 dst_x = state->crtc_x;
730 dst_y = state->crtc_y; 729 dst_y = state->crtc_y;
731 dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x); 730 dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x);
732 dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y); 731 dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y);
733 /* src_x are in 16.16 format */ 732 /* src_x are in 16.16 format */
734 src_x = state->src_x >> 16; 733 src_x = state->src_x >> 16;
735 src_y = state->src_y >> 16; 734 src_y = state->src_y >> 16;
@@ -758,9 +757,9 @@ static void sti_gdp_atomic_update(struct drm_plane *drm_plane,
758 (unsigned long)cma_obj->paddr); 757 (unsigned long)cma_obj->paddr);
759 758
760 /* pixel memory location */ 759 /* pixel memory location */
761 drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp); 760 bpp = drm_format_plane_cpp(fb->pixel_format, 0);
762 top_field->gam_gdp_pml = (u32)cma_obj->paddr + fb->offsets[0]; 761 top_field->gam_gdp_pml = (u32)cma_obj->paddr + fb->offsets[0];
763 top_field->gam_gdp_pml += src_x * (bpp >> 3); 762 top_field->gam_gdp_pml += src_x * bpp;
764 top_field->gam_gdp_pml += src_y * fb->pitches[0]; 763 top_field->gam_gdp_pml += src_y * fb->pitches[0];
765 764
766 /* output parameters (clamped / cropped) */ 765 /* output parameters (clamped / cropped) */
@@ -810,7 +809,7 @@ static void sti_gdp_atomic_update(struct drm_plane *drm_plane,
810 if (!curr_list) { 809 if (!curr_list) {
811 /* First update or invalid node should directly write in the 810 /* First update or invalid node should directly write in the
812 * hw register */ 811 * hw register */
813 DRM_DEBUG_DRIVER("%s first update (or invalid node)", 812 DRM_DEBUG_DRIVER("%s first update (or invalid node)\n",
814 sti_plane_to_str(plane)); 813 sti_plane_to_str(plane));
815 814
816 writel(gdp->is_curr_top ? 815 writel(gdp->is_curr_top ?
@@ -846,15 +845,15 @@ static void sti_gdp_atomic_disable(struct drm_plane *drm_plane,
846{ 845{
847 struct sti_plane *plane = to_sti_plane(drm_plane); 846 struct sti_plane *plane = to_sti_plane(drm_plane);
848 847
849 if (!drm_plane->crtc) { 848 if (!oldstate->crtc) {
850 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n", 849 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n",
851 drm_plane->base.id); 850 drm_plane->base.id);
852 return; 851 return;
853 } 852 }
854 853
855 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n", 854 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n",
856 drm_plane->crtc->base.id, 855 oldstate->crtc->base.id,
857 sti_mixer_to_str(to_sti_mixer(drm_plane->crtc)), 856 sti_mixer_to_str(to_sti_mixer(oldstate->crtc)),
858 drm_plane->base.id, sti_plane_to_str(plane)); 857 drm_plane->base.id, sti_plane_to_str(plane));
859 858
860 plane->status = STI_PLANE_DISABLING; 859 plane->status = STI_PLANE_DISABLING;
@@ -882,7 +881,7 @@ static int sti_gdp_late_register(struct drm_plane *drm_plane)
882 return gdp_debugfs_init(gdp, drm_plane->dev->primary); 881 return gdp_debugfs_init(gdp, drm_plane->dev->primary);
883} 882}
884 883
885struct drm_plane_funcs sti_gdp_plane_helpers_funcs = { 884static const struct drm_plane_funcs sti_gdp_plane_helpers_funcs = {
886 .update_plane = drm_atomic_helper_update_plane, 885 .update_plane = drm_atomic_helper_update_plane,
887 .disable_plane = drm_atomic_helper_disable_plane, 886 .disable_plane = drm_atomic_helper_disable_plane,
888 .destroy = sti_gdp_destroy, 887 .destroy = sti_gdp_destroy,
diff --git a/drivers/gpu/drm/sti/sti_hda.c b/drivers/gpu/drm/sti/sti_hda.c
index 8505569f75de..e7c243f70870 100644
--- a/drivers/gpu/drm/sti/sti_hda.c
+++ b/drivers/gpu/drm/sti/sti_hda.c
@@ -62,14 +62,8 @@
62#define SCALE_CTRL_CR_DFLT 0x00DB0249 62#define SCALE_CTRL_CR_DFLT 0x00DB0249
63 63
64/* Video DACs control */ 64/* Video DACs control */
65#define VIDEO_DACS_CONTROL_MASK 0x0FFF
66#define VIDEO_DACS_CONTROL_SYSCFG2535 0x085C /* for stih416 */
67#define DAC_CFG_HD_OFF_SHIFT 5
68#define DAC_CFG_HD_OFF_MASK (0x7 << DAC_CFG_HD_OFF_SHIFT)
69#define VIDEO_DACS_CONTROL_SYSCFG5072 0x0120 /* for stih407 */
70#define DAC_CFG_HD_HZUVW_OFF_MASK BIT(1) 65#define DAC_CFG_HD_HZUVW_OFF_MASK BIT(1)
71 66
72
73/* Upsampler values for the alternative 2X Filter */ 67/* Upsampler values for the alternative 2X Filter */
74#define SAMPLER_COEF_NB 8 68#define SAMPLER_COEF_NB 8
75#define HDA_ANA_SRC_Y_CFG_ALT_2X 0x01130000 69#define HDA_ANA_SRC_Y_CFG_ALT_2X 0x01130000
@@ -300,28 +294,14 @@ static bool hda_get_mode_idx(struct drm_display_mode mode, int *idx)
300 */ 294 */
301static void hda_enable_hd_dacs(struct sti_hda *hda, bool enable) 295static void hda_enable_hd_dacs(struct sti_hda *hda, bool enable)
302{ 296{
303 u32 mask;
304
305 if (hda->video_dacs_ctrl) { 297 if (hda->video_dacs_ctrl) {
306 u32 val; 298 u32 val;
307 299
308 switch ((u32)hda->video_dacs_ctrl & VIDEO_DACS_CONTROL_MASK) {
309 case VIDEO_DACS_CONTROL_SYSCFG2535:
310 mask = DAC_CFG_HD_OFF_MASK;
311 break;
312 case VIDEO_DACS_CONTROL_SYSCFG5072:
313 mask = DAC_CFG_HD_HZUVW_OFF_MASK;
314 break;
315 default:
316 DRM_INFO("Video DACS control register not supported!");
317 return;
318 }
319
320 val = readl(hda->video_dacs_ctrl); 300 val = readl(hda->video_dacs_ctrl);
321 if (enable) 301 if (enable)
322 val &= ~mask; 302 val &= ~DAC_CFG_HD_HZUVW_OFF_MASK;
323 else 303 else
324 val |= mask; 304 val |= DAC_CFG_HD_HZUVW_OFF_MASK;
325 305
326 writel(val, hda->video_dacs_ctrl); 306 writel(val, hda->video_dacs_ctrl);
327 } 307 }
@@ -352,24 +332,11 @@ static void hda_dbg_awg_microcode(struct seq_file *s, void __iomem *reg)
352static void hda_dbg_video_dacs_ctrl(struct seq_file *s, void __iomem *reg) 332static void hda_dbg_video_dacs_ctrl(struct seq_file *s, void __iomem *reg)
353{ 333{
354 u32 val = readl(reg); 334 u32 val = readl(reg);
355 u32 mask;
356
357 switch ((u32)reg & VIDEO_DACS_CONTROL_MASK) {
358 case VIDEO_DACS_CONTROL_SYSCFG2535:
359 mask = DAC_CFG_HD_OFF_MASK;
360 break;
361 case VIDEO_DACS_CONTROL_SYSCFG5072:
362 mask = DAC_CFG_HD_HZUVW_OFF_MASK;
363 break;
364 default:
365 DRM_DEBUG_DRIVER("Warning: DACS ctrl register not supported!");
366 return;
367 }
368 335
369 seq_puts(s, "\n"); 336 seq_puts(s, "\n");
370 seq_printf(s, "\n %-25s 0x%08X", "VIDEO_DACS_CONTROL", val); 337 seq_printf(s, "\n %-25s 0x%08X", "VIDEO_DACS_CONTROL", val);
371 seq_puts(s, "\tHD DACs "); 338 seq_puts(s, "\tHD DACs ");
372 seq_puts(s, val & mask ? "disabled" : "enabled"); 339 seq_puts(s, val & DAC_CFG_HD_HZUVW_OFF_MASK ? "disabled" : "enabled");
373} 340}
374 341
375static int hda_dbg_show(struct seq_file *s, void *data) 342static int hda_dbg_show(struct seq_file *s, void *data)
diff --git a/drivers/gpu/drm/sti/sti_hdmi.c b/drivers/gpu/drm/sti/sti_hdmi.c
index fedc17f98d9b..376b0763c874 100644
--- a/drivers/gpu/drm/sti/sti_hdmi.c
+++ b/drivers/gpu/drm/sti/sti_hdmi.c
@@ -22,7 +22,6 @@
22 22
23#include "sti_hdmi.h" 23#include "sti_hdmi.h"
24#include "sti_hdmi_tx3g4c28phy.h" 24#include "sti_hdmi_tx3g4c28phy.h"
25#include "sti_hdmi_tx3g0c55phy.h"
26#include "sti_vtg.h" 25#include "sti_vtg.h"
27 26
28#define HDMI_CFG 0x0000 27#define HDMI_CFG 0x0000
@@ -203,7 +202,7 @@ static irqreturn_t hdmi_irq_thread(int irq, void *arg)
203 202
204 /* Audio FIFO underrun IRQ */ 203 /* Audio FIFO underrun IRQ */
205 if (hdmi->irq_status & HDMI_INT_AUDIO_FIFO_XRUN) 204 if (hdmi->irq_status & HDMI_INT_AUDIO_FIFO_XRUN)
206 DRM_INFO("Warning: audio FIFO underrun occurs!"); 205 DRM_INFO("Warning: audio FIFO underrun occurs!\n");
207 206
208 return IRQ_HANDLED; 207 return IRQ_HANDLED;
209} 208}
@@ -569,7 +568,7 @@ static void hdmi_swreset(struct sti_hdmi *hdmi)
569 568
570 /* Wait reset completed */ 569 /* Wait reset completed */
571 wait_event_interruptible_timeout(hdmi->wait_event, 570 wait_event_interruptible_timeout(hdmi->wait_event,
572 hdmi->event_received == true, 571 hdmi->event_received,
573 msecs_to_jiffies 572 msecs_to_jiffies
574 (HDMI_TIMEOUT_SWRESET)); 573 (HDMI_TIMEOUT_SWRESET));
575 574
@@ -1054,6 +1053,7 @@ static int sti_hdmi_late_register(struct drm_connector *connector)
1054} 1053}
1055 1054
1056static const struct drm_connector_funcs sti_hdmi_connector_funcs = { 1055static const struct drm_connector_funcs sti_hdmi_connector_funcs = {
1056 .dpms = drm_atomic_helper_connector_dpms,
1057 .fill_modes = drm_helper_probe_single_connector_modes, 1057 .fill_modes = drm_helper_probe_single_connector_modes,
1058 .detect = sti_hdmi_connector_detect, 1058 .detect = sti_hdmi_connector_detect,
1059 .destroy = drm_connector_cleanup, 1059 .destroy = drm_connector_cleanup,
@@ -1181,7 +1181,7 @@ static void hdmi_audio_shutdown(struct device *dev, void *data)
1181 HDMI_AUD_CFG_ONE_BIT_INVALID; 1181 HDMI_AUD_CFG_ONE_BIT_INVALID;
1182 hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG); 1182 hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG);
1183 1183
1184 hdmi->audio.enabled = 0; 1184 hdmi->audio.enabled = false;
1185 hdmi_audio_infoframe_config(hdmi); 1185 hdmi_audio_infoframe_config(hdmi);
1186} 1186}
1187 1187
@@ -1213,7 +1213,7 @@ static int hdmi_audio_hw_params(struct device *dev,
1213 return -EINVAL; 1213 return -EINVAL;
1214 } 1214 }
1215 1215
1216 audio.enabled = 1; 1216 audio.enabled = true;
1217 1217
1218 ret = hdmi_audio_configure(hdmi, &audio); 1218 ret = hdmi_audio_configure(hdmi, &audio);
1219 if (ret < 0) 1219 if (ret < 0)
@@ -1265,7 +1265,7 @@ static int sti_hdmi_register_audio_driver(struct device *dev,
1265 1265
1266 DRM_DEBUG_DRIVER("\n"); 1266 DRM_DEBUG_DRIVER("\n");
1267 1267
1268 hdmi->audio.enabled = 0; 1268 hdmi->audio.enabled = false;
1269 1269
1270 hdmi->audio_pdev = platform_device_register_data( 1270 hdmi->audio_pdev = platform_device_register_data(
1271 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO, 1271 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
@@ -1373,9 +1373,6 @@ static const struct component_ops sti_hdmi_ops = {
1373 1373
1374static const struct of_device_id hdmi_of_match[] = { 1374static const struct of_device_id hdmi_of_match[] = {
1375 { 1375 {
1376 .compatible = "st,stih416-hdmi",
1377 .data = &tx3g0c55phy_ops,
1378 }, {
1379 .compatible = "st,stih407-hdmi", 1376 .compatible = "st,stih407-hdmi",
1380 .data = &tx3g4c28phy_ops, 1377 .data = &tx3g4c28phy_ops,
1381 }, { 1378 }, {
@@ -1422,22 +1419,6 @@ static int sti_hdmi_probe(struct platform_device *pdev)
1422 goto release_adapter; 1419 goto release_adapter;
1423 } 1420 }
1424 1421
1425 if (of_device_is_compatible(np, "st,stih416-hdmi")) {
1426 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1427 "syscfg");
1428 if (!res) {
1429 DRM_ERROR("Invalid syscfg resource\n");
1430 ret = -ENOMEM;
1431 goto release_adapter;
1432 }
1433 hdmi->syscfg = devm_ioremap_nocache(dev, res->start,
1434 resource_size(res));
1435 if (!hdmi->syscfg) {
1436 ret = -ENOMEM;
1437 goto release_adapter;
1438 }
1439 }
1440
1441 hdmi->phy_ops = (struct hdmi_phy_ops *) 1422 hdmi->phy_ops = (struct hdmi_phy_ops *)
1442 of_match_node(hdmi_of_match, np)->data; 1423 of_match_node(hdmi_of_match, np)->data;
1443 1424
diff --git a/drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.c b/drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.c
deleted file mode 100644
index 49ae8e44b285..000000000000
--- a/drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.c
+++ /dev/null
@@ -1,336 +0,0 @@
1/*
2 * Copyright (C) STMicroelectronics SA 2014
3 * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
4 * License terms: GNU General Public License (GPL), version 2
5 */
6
7#include "sti_hdmi_tx3g0c55phy.h"
8
9#define HDMI_SRZ_PLL_CFG 0x0504
10#define HDMI_SRZ_TAP_1 0x0508
11#define HDMI_SRZ_TAP_2 0x050C
12#define HDMI_SRZ_TAP_3 0x0510
13#define HDMI_SRZ_CTRL 0x0514
14
15#define HDMI_SRZ_PLL_CFG_POWER_DOWN BIT(0)
16#define HDMI_SRZ_PLL_CFG_VCOR_SHIFT 1
17#define HDMI_SRZ_PLL_CFG_VCOR_425MHZ 0
18#define HDMI_SRZ_PLL_CFG_VCOR_850MHZ 1
19#define HDMI_SRZ_PLL_CFG_VCOR_1700MHZ 2
20#define HDMI_SRZ_PLL_CFG_VCOR_3000MHZ 3
21#define HDMI_SRZ_PLL_CFG_VCOR_MASK 3
22#define HDMI_SRZ_PLL_CFG_VCOR(x) (x << HDMI_SRZ_PLL_CFG_VCOR_SHIFT)
23#define HDMI_SRZ_PLL_CFG_NDIV_SHIFT 8
24#define HDMI_SRZ_PLL_CFG_NDIV_MASK (0x1F << HDMI_SRZ_PLL_CFG_NDIV_SHIFT)
25#define HDMI_SRZ_PLL_CFG_MODE_SHIFT 16
26#define HDMI_SRZ_PLL_CFG_MODE_13_5_MHZ 0x1
27#define HDMI_SRZ_PLL_CFG_MODE_25_2_MHZ 0x4
28#define HDMI_SRZ_PLL_CFG_MODE_27_MHZ 0x5
29#define HDMI_SRZ_PLL_CFG_MODE_33_75_MHZ 0x6
30#define HDMI_SRZ_PLL_CFG_MODE_40_5_MHZ 0x7
31#define HDMI_SRZ_PLL_CFG_MODE_54_MHZ 0x8
32#define HDMI_SRZ_PLL_CFG_MODE_67_5_MHZ 0x9
33#define HDMI_SRZ_PLL_CFG_MODE_74_25_MHZ 0xA
34#define HDMI_SRZ_PLL_CFG_MODE_81_MHZ 0xB
35#define HDMI_SRZ_PLL_CFG_MODE_82_5_MHZ 0xC
36#define HDMI_SRZ_PLL_CFG_MODE_108_MHZ 0xD
37#define HDMI_SRZ_PLL_CFG_MODE_148_5_MHZ 0xE
38#define HDMI_SRZ_PLL_CFG_MODE_165_MHZ 0xF
39#define HDMI_SRZ_PLL_CFG_MODE_MASK 0xF
40#define HDMI_SRZ_PLL_CFG_MODE(x) (x << HDMI_SRZ_PLL_CFG_MODE_SHIFT)
41
42#define HDMI_SRZ_CTRL_POWER_DOWN (1 << 0)
43#define HDMI_SRZ_CTRL_EXTERNAL_DATA_EN (1 << 1)
44
45/* sysconf registers */
46#define HDMI_REJECTION_PLL_CONFIGURATION 0x0858 /* SYSTEM_CONFIG2534 */
47#define HDMI_REJECTION_PLL_STATUS 0x0948 /* SYSTEM_CONFIG2594 */
48
49#define REJECTION_PLL_HDMI_ENABLE_SHIFT 0
50#define REJECTION_PLL_HDMI_ENABLE_MASK (0x1 << REJECTION_PLL_HDMI_ENABLE_SHIFT)
51#define REJECTION_PLL_HDMI_PDIV_SHIFT 24
52#define REJECTION_PLL_HDMI_PDIV_MASK (0x7 << REJECTION_PLL_HDMI_PDIV_SHIFT)
53#define REJECTION_PLL_HDMI_NDIV_SHIFT 16
54#define REJECTION_PLL_HDMI_NDIV_MASK (0xFF << REJECTION_PLL_HDMI_NDIV_SHIFT)
55#define REJECTION_PLL_HDMI_MDIV_SHIFT 8
56#define REJECTION_PLL_HDMI_MDIV_MASK (0xFF << REJECTION_PLL_HDMI_MDIV_SHIFT)
57
58#define REJECTION_PLL_HDMI_REJ_PLL_LOCK BIT(0)
59
60#define HDMI_TIMEOUT_PLL_LOCK 50 /*milliseconds */
61
62/**
63 * pll mode structure
64 *
65 * A pointer to an array of these structures is passed to a TMDS (HDMI) output
66 * via the control interface to provide board and SoC specific
67 * configurations of the HDMI PHY. Each entry in the array specifies a hardware
68 * specific configuration for a given TMDS clock frequency range. The array
69 * should be terminated with an entry that has all fields set to zero.
70 *
71 * @min: Lower bound of TMDS clock frequency this entry applies to
72 * @max: Upper bound of TMDS clock frequency this entry applies to
73 * @mode: SoC specific register configuration
74 */
75struct pllmode {
76 u32 min;
77 u32 max;
78 u32 mode;
79};
80
81#define NB_PLL_MODE 7
82static struct pllmode pllmodes[NB_PLL_MODE] = {
83 {13500000, 13513500, HDMI_SRZ_PLL_CFG_MODE_13_5_MHZ},
84 {25174800, 25200000, HDMI_SRZ_PLL_CFG_MODE_25_2_MHZ},
85 {27000000, 27027000, HDMI_SRZ_PLL_CFG_MODE_27_MHZ},
86 {54000000, 54054000, HDMI_SRZ_PLL_CFG_MODE_54_MHZ},
87 {72000000, 74250000, HDMI_SRZ_PLL_CFG_MODE_74_25_MHZ},
88 {108000000, 108108000, HDMI_SRZ_PLL_CFG_MODE_108_MHZ},
89 {148351648, 297000000, HDMI_SRZ_PLL_CFG_MODE_148_5_MHZ}
90};
91
92#define NB_HDMI_PHY_CONFIG 5
93static struct hdmi_phy_config hdmiphy_config[NB_HDMI_PHY_CONFIG] = {
94 {0, 40000000, {0x00101010, 0x00101010, 0x00101010, 0x02} },
95 {40000000, 140000000, {0x00111111, 0x00111111, 0x00111111, 0x02} },
96 {140000000, 160000000, {0x00131313, 0x00101010, 0x00101010, 0x02} },
97 {160000000, 250000000, {0x00131313, 0x00111111, 0x00111111, 0x03FE} },
98 {250000000, 300000000, {0x00151515, 0x00101010, 0x00101010, 0x03FE} },
99};
100
101#define PLL_CHANGE_DELAY 1 /* ms */
102
103/**
104 * Disable the pll rejection
105 *
106 * @hdmi: pointer on the hdmi internal structure
107 *
108 * return true if the pll has been disabled
109 */
110static bool disable_pll_rejection(struct sti_hdmi *hdmi)
111{
112 u32 val;
113
114 DRM_DEBUG_DRIVER("\n");
115
116 val = readl(hdmi->syscfg + HDMI_REJECTION_PLL_CONFIGURATION);
117 val &= ~REJECTION_PLL_HDMI_ENABLE_MASK;
118 writel(val, hdmi->syscfg + HDMI_REJECTION_PLL_CONFIGURATION);
119
120 msleep(PLL_CHANGE_DELAY);
121 val = readl(hdmi->syscfg + HDMI_REJECTION_PLL_STATUS);
122
123 return !(val & REJECTION_PLL_HDMI_REJ_PLL_LOCK);
124}
125
126/**
127 * Enable the old BCH/rejection PLL is now reused to provide the CLKPXPLL
128 * clock input to the new PHY PLL that generates the serializer clock
129 * (TMDS*10) and the TMDS clock which is now fed back into the HDMI
130 * formatter instead of the TMDS clock line from ClockGenB.
131 *
132 * @hdmi: pointer on the hdmi internal structure
133 *
134 * return true if pll has been correctly set
135 */
136static bool enable_pll_rejection(struct sti_hdmi *hdmi)
137{
138 unsigned int inputclock;
139 u32 mdiv, ndiv, pdiv, val;
140
141 DRM_DEBUG_DRIVER("\n");
142
143 if (!disable_pll_rejection(hdmi))
144 return false;
145
146 inputclock = hdmi->mode.clock * 1000;
147
148 DRM_DEBUG_DRIVER("hdmi rejection pll input clock = %dHz\n", inputclock);
149
150
151 /* Power up the HDMI rejection PLL
152 * Note: On this SoC (stiH416) we are forced to have the input clock
153 * be equal to the HDMI pixel clock.
154 *
155 * The values here have been suggested by validation however they are
156 * still provisional and subject to change.
157 *
158 * PLLout = (Fin*Mdiv) / ((2 * Ndiv) / 2^Pdiv)
159 */
160 if (inputclock < 50000000) {
161 /*
162 * For slower clocks we need to multiply more to keep the
163 * internal VCO frequency within the physical specification
164 * of the PLL.
165 */
166 pdiv = 4;
167 ndiv = 240;
168 mdiv = 30;
169 } else {
170 pdiv = 2;
171 ndiv = 60;
172 mdiv = 30;
173 }
174
175 val = readl(hdmi->syscfg + HDMI_REJECTION_PLL_CONFIGURATION);
176
177 val &= ~(REJECTION_PLL_HDMI_PDIV_MASK |
178 REJECTION_PLL_HDMI_NDIV_MASK |
179 REJECTION_PLL_HDMI_MDIV_MASK |
180 REJECTION_PLL_HDMI_ENABLE_MASK);
181
182 val |= (pdiv << REJECTION_PLL_HDMI_PDIV_SHIFT) |
183 (ndiv << REJECTION_PLL_HDMI_NDIV_SHIFT) |
184 (mdiv << REJECTION_PLL_HDMI_MDIV_SHIFT) |
185 (0x1 << REJECTION_PLL_HDMI_ENABLE_SHIFT);
186
187 writel(val, hdmi->syscfg + HDMI_REJECTION_PLL_CONFIGURATION);
188
189 msleep(PLL_CHANGE_DELAY);
190 val = readl(hdmi->syscfg + HDMI_REJECTION_PLL_STATUS);
191
192 return (val & REJECTION_PLL_HDMI_REJ_PLL_LOCK);
193}
194
195/**
196 * Start hdmi phy macro cell tx3g0c55
197 *
198 * @hdmi: pointer on the hdmi internal structure
199 *
200 * Return false if an error occur
201 */
202static bool sti_hdmi_tx3g0c55phy_start(struct sti_hdmi *hdmi)
203{
204 u32 ckpxpll = hdmi->mode.clock * 1000;
205 u32 val, tmdsck, freqvco, pllctrl = 0;
206 unsigned int i;
207
208 if (!enable_pll_rejection(hdmi))
209 return false;
210
211 DRM_DEBUG_DRIVER("ckpxpll = %dHz\n", ckpxpll);
212
213 /* Assuming no pixel repetition and 24bits color */
214 tmdsck = ckpxpll;
215 pllctrl = 2 << HDMI_SRZ_PLL_CFG_NDIV_SHIFT;
216
217 /*
218 * Setup the PLL mode parameter based on the ckpxpll. If we haven't got
219 * a clock frequency supported by one of the specific PLL modes then we
220 * will end up using the generic mode (0) which only supports a 10x
221 * multiplier, hence only 24bit color.
222 */
223 for (i = 0; i < NB_PLL_MODE; i++) {
224 if (ckpxpll >= pllmodes[i].min && ckpxpll <= pllmodes[i].max)
225 pllctrl |= HDMI_SRZ_PLL_CFG_MODE(pllmodes[i].mode);
226 }
227
228 freqvco = tmdsck * 10;
229 if (freqvco <= 425000000UL)
230 pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_425MHZ);
231 else if (freqvco <= 850000000UL)
232 pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_850MHZ);
233 else if (freqvco <= 1700000000UL)
234 pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_1700MHZ);
235 else if (freqvco <= 2970000000UL)
236 pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_3000MHZ);
237 else {
238 DRM_ERROR("PHY serializer clock out of range\n");
239 goto err;
240 }
241
242 /*
243 * Configure and power up the PHY PLL
244 */
245 hdmi->event_received = false;
246 DRM_DEBUG_DRIVER("pllctrl = 0x%x\n", pllctrl);
247 hdmi_write(hdmi, pllctrl, HDMI_SRZ_PLL_CFG);
248
249 /* wait PLL interrupt */
250 wait_event_interruptible_timeout(hdmi->wait_event,
251 hdmi->event_received == true,
252 msecs_to_jiffies
253 (HDMI_TIMEOUT_PLL_LOCK));
254
255 if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_DLL_LCK) == 0) {
256 DRM_ERROR("hdmi phy pll not locked\n");
257 goto err;
258 }
259
260 DRM_DEBUG_DRIVER("got PHY PLL Lock\n");
261
262 /*
263 * To configure the source termination and pre-emphasis appropriately
264 * for different high speed TMDS clock frequencies a phy configuration
265 * table must be provided, tailored to the SoC and board combination.
266 */
267 for (i = 0; i < NB_HDMI_PHY_CONFIG; i++) {
268 if ((hdmiphy_config[i].min_tmds_freq <= tmdsck) &&
269 (hdmiphy_config[i].max_tmds_freq >= tmdsck)) {
270 val = hdmiphy_config[i].config[0];
271 hdmi_write(hdmi, val, HDMI_SRZ_TAP_1);
272 val = hdmiphy_config[i].config[1];
273 hdmi_write(hdmi, val, HDMI_SRZ_TAP_2);
274 val = hdmiphy_config[i].config[2];
275 hdmi_write(hdmi, val, HDMI_SRZ_TAP_3);
276 val = hdmiphy_config[i].config[3];
277 val |= HDMI_SRZ_CTRL_EXTERNAL_DATA_EN;
278 val &= ~HDMI_SRZ_CTRL_POWER_DOWN;
279 hdmi_write(hdmi, val, HDMI_SRZ_CTRL);
280
281 DRM_DEBUG_DRIVER("serializer cfg 0x%x 0x%x 0x%x 0x%x\n",
282 hdmiphy_config[i].config[0],
283 hdmiphy_config[i].config[1],
284 hdmiphy_config[i].config[2],
285 hdmiphy_config[i].config[3]);
286 return true;
287 }
288 }
289
290 /*
291 * Default, power up the serializer with no pre-emphasis or source
292 * termination.
293 */
294 hdmi_write(hdmi, 0x0, HDMI_SRZ_TAP_1);
295 hdmi_write(hdmi, 0x0, HDMI_SRZ_TAP_2);
296 hdmi_write(hdmi, 0x0, HDMI_SRZ_TAP_3);
297 hdmi_write(hdmi, HDMI_SRZ_CTRL_EXTERNAL_DATA_EN, HDMI_SRZ_CTRL);
298
299 return true;
300
301err:
302 disable_pll_rejection(hdmi);
303
304 return false;
305}
306
307/**
308 * Stop hdmi phy macro cell tx3g0c55
309 *
310 * @hdmi: pointer on the hdmi internal structure
311 */
312static void sti_hdmi_tx3g0c55phy_stop(struct sti_hdmi *hdmi)
313{
314 DRM_DEBUG_DRIVER("\n");
315
316 hdmi->event_received = false;
317
318 hdmi_write(hdmi, HDMI_SRZ_CTRL_POWER_DOWN, HDMI_SRZ_CTRL);
319 hdmi_write(hdmi, HDMI_SRZ_PLL_CFG_POWER_DOWN, HDMI_SRZ_PLL_CFG);
320
321 /* wait PLL interrupt */
322 wait_event_interruptible_timeout(hdmi->wait_event,
323 hdmi->event_received == true,
324 msecs_to_jiffies
325 (HDMI_TIMEOUT_PLL_LOCK));
326
327 if (hdmi_read(hdmi, HDMI_STA) & HDMI_STA_DLL_LCK)
328 DRM_ERROR("hdmi phy pll not well disabled\n");
329
330 disable_pll_rejection(hdmi);
331}
332
333struct hdmi_phy_ops tx3g0c55phy_ops = {
334 .start = sti_hdmi_tx3g0c55phy_start,
335 .stop = sti_hdmi_tx3g0c55phy_stop,
336};
diff --git a/drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.h b/drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.h
deleted file mode 100644
index 068237b3a303..000000000000
--- a/drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.h
+++ /dev/null
@@ -1,14 +0,0 @@
1/*
2 * Copyright (C) STMicroelectronics SA 2014
3 * Author: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
4 * License terms: GNU General Public License (GPL), version 2
5 */
6
7#ifndef _STI_HDMI_TX3G0C55PHY_H_
8#define _STI_HDMI_TX3G0C55PHY_H_
9
10#include "sti_hdmi.h"
11
12extern struct hdmi_phy_ops tx3g0c55phy_ops;
13
14#endif
diff --git a/drivers/gpu/drm/sti/sti_hqvdp.c b/drivers/gpu/drm/sti/sti_hqvdp.c
index b5ee783e3e7c..f88130f2eb48 100644
--- a/drivers/gpu/drm/sti/sti_hqvdp.c
+++ b/drivers/gpu/drm/sti/sti_hqvdp.c
@@ -17,6 +17,7 @@
17#include "sti_hqvdp_lut.h" 17#include "sti_hqvdp_lut.h"
18#include "sti_plane.h" 18#include "sti_plane.h"
19#include "sti_vtg.h" 19#include "sti_vtg.h"
20#include "sti_drv.h"
20 21
21/* Firmware name */ 22/* Firmware name */
22#define HQVDP_FMW_NAME "hqvdp-stih407.bin" 23#define HQVDP_FMW_NAME "hqvdp-stih407.bin"
@@ -770,6 +771,7 @@ static void sti_hqvdp_disable(struct sti_hqvdp *hqvdp)
770 DRM_ERROR("XP70 could not revert to idle\n"); 771 DRM_ERROR("XP70 could not revert to idle\n");
771 772
772 hqvdp->plane.status = STI_PLANE_DISABLED; 773 hqvdp->plane.status = STI_PLANE_DISABLED;
774 hqvdp->xp70_initialized = false;
773} 775}
774 776
775/** 777/**
@@ -783,7 +785,7 @@ static void sti_hqvdp_disable(struct sti_hqvdp *hqvdp)
783 * RETURNS: 785 * RETURNS:
784 * 0 on success. 786 * 0 on success.
785 */ 787 */
786int sti_hqvdp_vtg_cb(struct notifier_block *nb, unsigned long evt, void *data) 788static int sti_hqvdp_vtg_cb(struct notifier_block *nb, unsigned long evt, void *data)
787{ 789{
788 struct sti_hqvdp *hqvdp = container_of(nb, struct sti_hqvdp, vtg_nb); 790 struct sti_hqvdp *hqvdp = container_of(nb, struct sti_hqvdp, vtg_nb);
789 int btm_cmd_offset, top_cmd_offest; 791 int btm_cmd_offset, top_cmd_offest;
@@ -1012,7 +1014,6 @@ static int sti_hqvdp_atomic_check(struct drm_plane *drm_plane,
1012 struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane); 1014 struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane);
1013 struct drm_crtc *crtc = state->crtc; 1015 struct drm_crtc *crtc = state->crtc;
1014 struct drm_framebuffer *fb = state->fb; 1016 struct drm_framebuffer *fb = state->fb;
1015 bool first_prepare = plane->status == STI_PLANE_DISABLED ? true : false;
1016 struct drm_crtc_state *crtc_state; 1017 struct drm_crtc_state *crtc_state;
1017 struct drm_display_mode *mode; 1018 struct drm_display_mode *mode;
1018 int dst_x, dst_y, dst_w, dst_h; 1019 int dst_x, dst_y, dst_w, dst_h;
@@ -1026,8 +1027,8 @@ static int sti_hqvdp_atomic_check(struct drm_plane *drm_plane,
1026 mode = &crtc_state->mode; 1027 mode = &crtc_state->mode;
1027 dst_x = state->crtc_x; 1028 dst_x = state->crtc_x;
1028 dst_y = state->crtc_y; 1029 dst_y = state->crtc_y;
1029 dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x); 1030 dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x);
1030 dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y); 1031 dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y);
1031 /* src_x are in 16.16 format */ 1032 /* src_x are in 16.16 format */
1032 src_x = state->src_x >> 16; 1033 src_x = state->src_x >> 16;
1033 src_y = state->src_y >> 16; 1034 src_y = state->src_y >> 16;
@@ -1063,7 +1064,7 @@ static int sti_hqvdp_atomic_check(struct drm_plane *drm_plane,
1063 return -EINVAL; 1064 return -EINVAL;
1064 } 1065 }
1065 1066
1066 if (first_prepare) { 1067 if (!hqvdp->xp70_initialized) {
1067 /* Start HQVDP XP70 coprocessor */ 1068 /* Start HQVDP XP70 coprocessor */
1068 sti_hqvdp_start_xp70(hqvdp); 1069 sti_hqvdp_start_xp70(hqvdp);
1069 1070
@@ -1115,8 +1116,8 @@ static void sti_hqvdp_atomic_update(struct drm_plane *drm_plane,
1115 mode = &crtc->mode; 1116 mode = &crtc->mode;
1116 dst_x = state->crtc_x; 1117 dst_x = state->crtc_x;
1117 dst_y = state->crtc_y; 1118 dst_y = state->crtc_y;
1118 dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x); 1119 dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x);
1119 dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y); 1120 dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y);
1120 /* src_x are in 16.16 format */ 1121 /* src_x are in 16.16 format */
1121 src_x = state->src_x >> 16; 1122 src_x = state->src_x >> 16;
1122 src_y = state->src_y >> 16; 1123 src_y = state->src_y >> 16;
@@ -1214,15 +1215,15 @@ static void sti_hqvdp_atomic_disable(struct drm_plane *drm_plane,
1214{ 1215{
1215 struct sti_plane *plane = to_sti_plane(drm_plane); 1216 struct sti_plane *plane = to_sti_plane(drm_plane);
1216 1217
1217 if (!drm_plane->crtc) { 1218 if (!oldstate->crtc) {
1218 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n", 1219 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n",
1219 drm_plane->base.id); 1220 drm_plane->base.id);
1220 return; 1221 return;
1221 } 1222 }
1222 1223
1223 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n", 1224 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n",
1224 drm_plane->crtc->base.id, 1225 oldstate->crtc->base.id,
1225 sti_mixer_to_str(to_sti_mixer(drm_plane->crtc)), 1226 sti_mixer_to_str(to_sti_mixer(oldstate->crtc)),
1226 drm_plane->base.id, sti_plane_to_str(plane)); 1227 drm_plane->base.id, sti_plane_to_str(plane));
1227 1228
1228 plane->status = STI_PLANE_DISABLING; 1229 plane->status = STI_PLANE_DISABLING;
@@ -1250,7 +1251,7 @@ static int sti_hqvdp_late_register(struct drm_plane *drm_plane)
1250 return hqvdp_debugfs_init(hqvdp, drm_plane->dev->primary); 1251 return hqvdp_debugfs_init(hqvdp, drm_plane->dev->primary);
1251} 1252}
1252 1253
1253struct drm_plane_funcs sti_hqvdp_plane_helpers_funcs = { 1254static const struct drm_plane_funcs sti_hqvdp_plane_helpers_funcs = {
1254 .update_plane = drm_atomic_helper_update_plane, 1255 .update_plane = drm_atomic_helper_update_plane,
1255 .disable_plane = drm_atomic_helper_disable_plane, 1256 .disable_plane = drm_atomic_helper_disable_plane,
1256 .destroy = sti_hqvdp_destroy, 1257 .destroy = sti_hqvdp_destroy,
@@ -1289,7 +1290,7 @@ static struct drm_plane *sti_hqvdp_create(struct drm_device *drm_dev,
1289 return &hqvdp->plane.drm_plane; 1290 return &hqvdp->plane.drm_plane;
1290} 1291}
1291 1292
1292int sti_hqvdp_bind(struct device *dev, struct device *master, void *data) 1293static int sti_hqvdp_bind(struct device *dev, struct device *master, void *data)
1293{ 1294{
1294 struct sti_hqvdp *hqvdp = dev_get_drvdata(dev); 1295 struct sti_hqvdp *hqvdp = dev_get_drvdata(dev);
1295 struct drm_device *drm_dev = data; 1296 struct drm_device *drm_dev = data;
diff --git a/drivers/gpu/drm/sti/sti_mixer.c b/drivers/gpu/drm/sti/sti_mixer.c
index 7d9aea805eab..4ddc58f7fe2e 100644
--- a/drivers/gpu/drm/sti/sti_mixer.c
+++ b/drivers/gpu/drm/sti/sti_mixer.c
@@ -16,12 +16,6 @@ static unsigned int bkg_color = 0x000000;
16MODULE_PARM_DESC(bkgcolor, "Value of the background color 0xRRGGBB"); 16MODULE_PARM_DESC(bkgcolor, "Value of the background color 0xRRGGBB");
17module_param_named(bkgcolor, bkg_color, int, 0644); 17module_param_named(bkgcolor, bkg_color, int, 0644);
18 18
19/* Identity: G=Y , B=Cb , R=Cr */
20static const u32 mixerColorSpaceMatIdentity[] = {
21 0x10000000, 0x00000000, 0x10000000, 0x00001000,
22 0x00000000, 0x00000000, 0x00000000, 0x00000000
23};
24
25/* regs offset */ 19/* regs offset */
26#define GAM_MIXER_CTL 0x00 20#define GAM_MIXER_CTL 0x00
27#define GAM_MIXER_BKC 0x04 21#define GAM_MIXER_BKC 0x04
@@ -358,22 +352,12 @@ int sti_mixer_set_plane_status(struct sti_mixer *mixer,
358 return 0; 352 return 0;
359} 353}
360 354
361void sti_mixer_set_matrix(struct sti_mixer *mixer)
362{
363 unsigned int i;
364
365 for (i = 0; i < ARRAY_SIZE(mixerColorSpaceMatIdentity); i++)
366 sti_mixer_reg_write(mixer, GAM_MIXER_MX0 + (i * 4),
367 mixerColorSpaceMatIdentity[i]);
368}
369
370struct sti_mixer *sti_mixer_create(struct device *dev, 355struct sti_mixer *sti_mixer_create(struct device *dev,
371 struct drm_device *drm_dev, 356 struct drm_device *drm_dev,
372 int id, 357 int id,
373 void __iomem *baseaddr) 358 void __iomem *baseaddr)
374{ 359{
375 struct sti_mixer *mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL); 360 struct sti_mixer *mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL);
376 struct device_node *np = dev->of_node;
377 361
378 dev_dbg(dev, "%s\n", __func__); 362 dev_dbg(dev, "%s\n", __func__);
379 if (!mixer) { 363 if (!mixer) {
@@ -384,9 +368,6 @@ struct sti_mixer *sti_mixer_create(struct device *dev,
384 mixer->dev = dev; 368 mixer->dev = dev;
385 mixer->id = id; 369 mixer->id = id;
386 370
387 if (of_device_is_compatible(np, "st,stih416-compositor"))
388 sti_mixer_set_matrix(mixer);
389
390 DRM_DEBUG_DRIVER("%s created. Regs=%p\n", 371 DRM_DEBUG_DRIVER("%s created. Regs=%p\n",
391 sti_mixer_to_str(mixer), mixer->regs); 372 sti_mixer_to_str(mixer), mixer->regs);
392 373
diff --git a/drivers/gpu/drm/sti/sti_tvout.c b/drivers/gpu/drm/sti/sti_tvout.c
index e25995b35715..ad46d3558d91 100644
--- a/drivers/gpu/drm/sti/sti_tvout.c
+++ b/drivers/gpu/drm/sti/sti_tvout.c
@@ -18,6 +18,7 @@
18#include <drm/drm_crtc_helper.h> 18#include <drm/drm_crtc_helper.h>
19 19
20#include "sti_crtc.h" 20#include "sti_crtc.h"
21#include "sti_drv.h"
21#include "sti_vtg.h" 22#include "sti_vtg.h"
22 23
23/* glue registers */ 24/* glue registers */
@@ -209,13 +210,11 @@ static void tvout_vip_set_rnd(struct sti_tvout *tvout, int reg, u32 rnd)
209 * @tvout: tvout structure 210 * @tvout: tvout structure
210 * @reg: register to set 211 * @reg: register to set
211 * @main_path: main or auxiliary path 212 * @main_path: main or auxiliary path
212 * @sel_input_logic_inverted: need to invert the logic
213 * @sel_input: selected_input (main/aux + conv) 213 * @sel_input: selected_input (main/aux + conv)
214 */ 214 */
215static void tvout_vip_set_sel_input(struct sti_tvout *tvout, 215static void tvout_vip_set_sel_input(struct sti_tvout *tvout,
216 int reg, 216 int reg,
217 bool main_path, 217 bool main_path,
218 bool sel_input_logic_inverted,
219 enum sti_tvout_video_out_type video_out) 218 enum sti_tvout_video_out_type video_out)
220{ 219{
221 u32 sel_input; 220 u32 sel_input;
@@ -236,8 +235,7 @@ static void tvout_vip_set_sel_input(struct sti_tvout *tvout,
236 } 235 }
237 236
238 /* on stih407 chip the sel_input bypass mode logic is inverted */ 237 /* on stih407 chip the sel_input bypass mode logic is inverted */
239 if (sel_input_logic_inverted) 238 sel_input = sel_input ^ TVO_VIP_SEL_INPUT_BYPASS_MASK;
240 sel_input = sel_input ^ TVO_VIP_SEL_INPUT_BYPASS_MASK;
241 239
242 val &= ~TVO_VIP_SEL_INPUT_MASK; 240 val &= ~TVO_VIP_SEL_INPUT_MASK;
243 val |= sel_input; 241 val |= sel_input;
@@ -295,8 +293,6 @@ static void tvout_preformatter_set_matrix(struct sti_tvout *tvout,
295 */ 293 */
296static void tvout_dvo_start(struct sti_tvout *tvout, bool main_path) 294static void tvout_dvo_start(struct sti_tvout *tvout, bool main_path)
297{ 295{
298 struct device_node *node = tvout->dev->of_node;
299 bool sel_input_logic_inverted = false;
300 u32 tvo_in_vid_format; 296 u32 tvo_in_vid_format;
301 int val, tmp; 297 int val, tmp;
302 298
@@ -334,16 +330,11 @@ static void tvout_dvo_start(struct sti_tvout *tvout, bool main_path)
334 /* Set round mode (rounded to 8-bit per component) */ 330 /* Set round mode (rounded to 8-bit per component) */
335 tvout_vip_set_rnd(tvout, TVO_VIP_DVO, TVO_VIP_RND_8BIT_ROUNDED); 331 tvout_vip_set_rnd(tvout, TVO_VIP_DVO, TVO_VIP_RND_8BIT_ROUNDED);
336 332
337 if (of_device_is_compatible(node, "st,stih407-tvout")) { 333 /* Set input video format */
338 /* Set input video format */ 334 tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format, TVO_IN_FMT_SIGNED);
339 tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format,
340 TVO_IN_FMT_SIGNED);
341 sel_input_logic_inverted = true;
342 }
343 335
344 /* Input selection */ 336 /* Input selection */
345 tvout_vip_set_sel_input(tvout, TVO_VIP_DVO, main_path, 337 tvout_vip_set_sel_input(tvout, TVO_VIP_DVO, main_path,
346 sel_input_logic_inverted,
347 STI_TVOUT_VIDEO_OUT_RGB); 338 STI_TVOUT_VIDEO_OUT_RGB);
348} 339}
349 340
@@ -356,8 +347,6 @@ static void tvout_dvo_start(struct sti_tvout *tvout, bool main_path)
356 */ 347 */
357static void tvout_hdmi_start(struct sti_tvout *tvout, bool main_path) 348static void tvout_hdmi_start(struct sti_tvout *tvout, bool main_path)
358{ 349{
359 struct device_node *node = tvout->dev->of_node;
360 bool sel_input_logic_inverted = false;
361 u32 tvo_in_vid_format; 350 u32 tvo_in_vid_format;
362 351
363 dev_dbg(tvout->dev, "%s\n", __func__); 352 dev_dbg(tvout->dev, "%s\n", __func__);
@@ -390,16 +379,12 @@ static void tvout_hdmi_start(struct sti_tvout *tvout, bool main_path)
390 /* set round mode (rounded to 8-bit per component) */ 379 /* set round mode (rounded to 8-bit per component) */
391 tvout_vip_set_rnd(tvout, TVO_VIP_HDMI, TVO_VIP_RND_8BIT_ROUNDED); 380 tvout_vip_set_rnd(tvout, TVO_VIP_HDMI, TVO_VIP_RND_8BIT_ROUNDED);
392 381
393 if (of_device_is_compatible(node, "st,stih407-tvout")) { 382 /* set input video format */
394 /* set input video format */ 383 tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format, TVO_IN_FMT_SIGNED);
395 tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format,
396 TVO_IN_FMT_SIGNED);
397 sel_input_logic_inverted = true;
398 }
399 384
400 /* input selection */ 385 /* input selection */
401 tvout_vip_set_sel_input(tvout, TVO_VIP_HDMI, main_path, 386 tvout_vip_set_sel_input(tvout, TVO_VIP_HDMI, main_path,
402 sel_input_logic_inverted, STI_TVOUT_VIDEO_OUT_RGB); 387 STI_TVOUT_VIDEO_OUT_RGB);
403} 388}
404 389
405/** 390/**
@@ -411,8 +396,6 @@ static void tvout_hdmi_start(struct sti_tvout *tvout, bool main_path)
411 */ 396 */
412static void tvout_hda_start(struct sti_tvout *tvout, bool main_path) 397static void tvout_hda_start(struct sti_tvout *tvout, bool main_path)
413{ 398{
414 struct device_node *node = tvout->dev->of_node;
415 bool sel_input_logic_inverted = false;
416 u32 tvo_in_vid_format; 399 u32 tvo_in_vid_format;
417 int val; 400 int val;
418 401
@@ -448,16 +431,11 @@ static void tvout_hda_start(struct sti_tvout *tvout, bool main_path)
448 /* set round mode (rounded to 10-bit per component) */ 431 /* set round mode (rounded to 10-bit per component) */
449 tvout_vip_set_rnd(tvout, TVO_VIP_HDF, TVO_VIP_RND_10BIT_ROUNDED); 432 tvout_vip_set_rnd(tvout, TVO_VIP_HDF, TVO_VIP_RND_10BIT_ROUNDED);
450 433
451 if (of_device_is_compatible(node, "st,stih407-tvout")) { 434 /* Set input video format */
452 /* set input video format */ 435 tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format, TVO_IN_FMT_SIGNED);
453 tvout_vip_set_in_vid_fmt(tvout,
454 tvo_in_vid_format, TVO_IN_FMT_SIGNED);
455 sel_input_logic_inverted = true;
456 }
457 436
458 /* Input selection */ 437 /* Input selection */
459 tvout_vip_set_sel_input(tvout, TVO_VIP_HDF, main_path, 438 tvout_vip_set_sel_input(tvout, TVO_VIP_HDF, main_path,
460 sel_input_logic_inverted,
461 STI_TVOUT_VIDEO_OUT_YUV); 439 STI_TVOUT_VIDEO_OUT_YUV);
462 440
463 /* power up HD DAC */ 441 /* power up HD DAC */
@@ -905,7 +883,6 @@ static int sti_tvout_remove(struct platform_device *pdev)
905} 883}
906 884
907static const struct of_device_id tvout_of_match[] = { 885static const struct of_device_id tvout_of_match[] = {
908 { .compatible = "st,stih416-tvout", },
909 { .compatible = "st,stih407-tvout", }, 886 { .compatible = "st,stih407-tvout", },
910 { /* end node */ } 887 { /* end node */ }
911}; 888};
diff --git a/drivers/gpu/drm/sti/sti_vid.c b/drivers/gpu/drm/sti/sti_vid.c
index 47634a0251fc..2ad59892b57e 100644
--- a/drivers/gpu/drm/sti/sti_vid.c
+++ b/drivers/gpu/drm/sti/sti_vid.c
@@ -142,8 +142,8 @@ void sti_vid_commit(struct sti_vid *vid,
142 struct drm_display_mode *mode = &crtc->mode; 142 struct drm_display_mode *mode = &crtc->mode;
143 int dst_x = state->crtc_x; 143 int dst_x = state->crtc_x;
144 int dst_y = state->crtc_y; 144 int dst_y = state->crtc_y;
145 int dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x); 145 int dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x);
146 int dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y); 146 int dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y);
147 int src_h = state->src_h >> 16; 147 int src_h = state->src_h >> 16;
148 u32 val, ydo, xdo, yds, xds; 148 u32 val, ydo, xdo, yds, xds;
149 149
diff --git a/drivers/gpu/drm/sti/sti_vtac.c b/drivers/gpu/drm/sti/sti_vtac.c
index b1eb0d77630d..cf7fe8a1db42 100644
--- a/drivers/gpu/drm/sti/sti_vtac.c
+++ b/drivers/gpu/drm/sti/sti_vtac.c
@@ -12,6 +12,8 @@
12 12
13#include <drm/drmP.h> 13#include <drm/drmP.h>
14 14
15#include "sti_drv.h"
16
15/* registers offset */ 17/* registers offset */
16#define VTAC_CONFIG 0x00 18#define VTAC_CONFIG 0x00
17#define VTAC_RX_FIFO_CONFIG 0x04 19#define VTAC_RX_FIFO_CONFIG 0x04
diff --git a/drivers/gpu/drm/sti/sti_vtg.c b/drivers/gpu/drm/sti/sti_vtg.c
index 0bdc385eec17..a8882bdd0f8b 100644
--- a/drivers/gpu/drm/sti/sti_vtg.c
+++ b/drivers/gpu/drm/sti/sti_vtg.c
@@ -13,6 +13,7 @@
13 13
14#include <drm/drmP.h> 14#include <drm/drmP.h>
15 15
16#include "sti_drv.h"
16#include "sti_vtg.h" 17#include "sti_vtg.h"
17 18
18#define VTG_MODE_MASTER 0 19#define VTG_MODE_MASTER 0
@@ -72,7 +73,7 @@
72#define AWG_DELAY_ED (-8) 73#define AWG_DELAY_ED (-8)
73#define AWG_DELAY_SD (-7) 74#define AWG_DELAY_SD (-7)
74 75
75LIST_HEAD(vtg_lookup); 76static LIST_HEAD(vtg_lookup);
76 77
77/* 78/*
78 * STI VTG register offset structure 79 * STI VTG register offset structure