7 files changed, 14 insertions, 14 deletions
diff --git a/arch/m68k/include/asm/MC68328.h b/arch/m68k/include/asm/MC68328.h
index 4ebf098b8a1f..1a8080c4cc40 100644
--- a/arch/m68k/include/asm/MC68328.h
+++ b/arch/m68k/include/asm/MC68328.h
@@ -798,7 +798,7 @@
 /**********
 *
- * 0xFFFFF7xx -- Serial Periferial Interface Slave (SPIS)
+ * 0xFFFFF7xx -- Serial Peripheral Interface Slave (SPIS)
 *
 **********/
@@ -824,7 +824,7 @@
 /**********
 *
- * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
+ * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
 *
 **********/
@@ -904,7 +904,7 @@
 #define UBAUD_PRESCALER_MASK    0x003f  /* Actual divisor is 65 - PRESCALER */
 #define UBAUD_PRESCALER_SHIFT   0
-#define UBAUD_DIVIDE_MASK       0x0700  /* Baud Rate freq. divizor */
+#define UBAUD_DIVIDE_MASK       0x0700  /* Baud Rate freq. divisor */
 #define UBAUD_DIVIDE_SHIFT      8
 #define UBAUD_BAUD_SRC          0x0800  /* Baud Rate Source */
 #define UBAUD_GPIOSRC           0x1000  /* GPIO source */
diff --git a/arch/m68k/include/asm/MC68EZ328.h b/arch/m68k/include/asm/MC68EZ328.h
index d1bde58ab0dd..fedac87c5d13 100644
--- a/arch/m68k/include/asm/MC68EZ328.h
+++ b/arch/m68k/include/asm/MC68EZ328.h
@@ -631,7 +631,7 @@
 /**********
 *
- * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
+ * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
 *
 **********/
@@ -712,7 +712,7 @@
 #define UBAUD_PRESCALER_MASK    0x003f  /* Actual divisor is 65 - PRESCALER */
 #define UBAUD_PRESCALER_SHIFT   0
-#define UBAUD_DIVIDE_MASK       0x0700  /* Baud Rate freq. divizor */
+#define UBAUD_DIVIDE_MASK       0x0700  /* Baud Rate freq. divisor */
 #define UBAUD_DIVIDE_SHIFT      8
 #define UBAUD_BAUD_SRC          0x0800  /* Baud Rate Source */
 #define UBAUD_UCLKDIR           0x2000  /* UCLK Direction */
@@ -1160,7 +1160,7 @@ typedef volatile struct {
 #define DRAMMC_COL10            0x0080  /* Col address bit for MD10 PA11/PA0  */
 #define DRAMMC_COL9             0x0040  /* Col address bit for MD9  PA10/PA0  */
 #define DRAMMC_COL8             0x0020  /* Col address bit for MD8  PA9/PA0   */
-#define DRAMMC_REF_MASK         0x001f  /* Reresh Cycle */
+#define DRAMMC_REF_MASK         0x001f  /* Refresh Cycle */
 #define DRAMMC_REF_SHIFT        0
 /*
diff --git a/arch/m68k/include/asm/MC68VZ328.h b/arch/m68k/include/asm/MC68VZ328.h
index 6bd1bf1f85ea..34a51b2c784f 100644
--- a/arch/m68k/include/asm/MC68VZ328.h
+++ b/arch/m68k/include/asm/MC68VZ328.h
@@ -724,7 +724,7 @@
 /**********
 *
- * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
+ * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
 *
 **********/
@@ -806,7 +806,7 @@
 #define UBAUD_PRESCALER_MASK    0x003f  /* Actual divisor is 65 - PRESCALER */
 #define UBAUD_PRESCALER_SHIFT   0
-#define UBAUD_DIVIDE_MASK       0x0700  /* Baud Rate freq. divizor */
+#define UBAUD_DIVIDE_MASK       0x0700  /* Baud Rate freq. divisor */
 #define UBAUD_DIVIDE_SHIFT      8
 #define UBAUD_BAUD_SRC          0x0800  /* Baud Rate Source */
 #define UBAUD_UCLKDIR           0x2000  /* UCLK Direction */
@@ -1256,7 +1256,7 @@ typedef struct {
 #define DRAMMC_COL10            0x0080  /* Col address bit for MD10 PA11/PA0  */
 #define DRAMMC_COL9             0x0040  /* Col address bit for MD9  PA10/PA0  */
 #define DRAMMC_COL8             0x0020  /* Col address bit for MD8  PA9/PA0   */
-#define DRAMMC_REF_MASK         0x001f  /* Reresh Cycle */
+#define DRAMMC_REF_MASK         0x001f  /* Refresh Cycle */
 #define DRAMMC_REF_SHIFT        0
 /*
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h
index 6d13cae44af5..59e171063c2f 100644
--- a/arch/m68k/include/asm/m54xxacr.h
+++ b/arch/m68k/include/asm/m54xxacr.h
@@ -23,8 +23,8 @@
 #define CACR_IEC        0x00008000      /* Enable instruction cache */
 #define CACR_DNFB       0x00002000      /* Inhibited fill buffer */
 #define CACR_IDPI       0x00001000      /* Disable CPUSHL */
-#define CACR_IHLCK      0x00000800      /* Intruction cache half lock */
+#define CACR_IHLCK      0x00000800      /* Instruction cache half lock */
-#define CACR_IDCM       0x00000400      /* Intruction cache inhibit */
+#define CACR_IDCM       0x00000400      /* Instruction cache inhibit */
 #define CACR_ICINVA     0x00000100      /* Invalidate instr cache */
 #define CACR_EUSP       0x00000020      /* Enable separate user a7 */
diff --git a/arch/m68k/include/asm/mac_iop.h b/arch/m68k/include/asm/mac_iop.h
index fde874a01e20..42566fd052bc 100644
--- a/arch/m68k/include/asm/mac_iop.h
+++ b/arch/m68k/include/asm/mac_iop.h
@@ -48,7 +48,7 @@
 /* IOP message status codes */
-#define IOP_MSGSTATUS_UNUSED    0       /* Unusued message structure       */
+#define IOP_MSGSTATUS_UNUSED    0       /* Unused message structure        */
 #define IOP_MSGSTATUS_WAITING   1       /* waiting for channel             */
 #define IOP_MSGSTATUS_SENT      2       /* message sent, awaiting reply    */
 #define IOP_MSGSTATUS_COMPLETE  3       /* message complete and reply rcvd */
diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h
index 089f0f150bbf..1150e42c3f19 100644
--- a/arch/m68k/include/asm/mcftimer.h
+++ b/arch/m68k/include/asm/mcftimer.h
@@ -51,7 +51,7 @@
 *      Bit definitions for the Timer Event Registers (TER).
 */
 #define MCFTIMER_TER_CAP        0x01            /* Capture event */
-#define MCFTIMER_TER_REF        0x02            /* Refernece event */
+#define MCFTIMER_TER_REF        0x02            /* Reference event */
 /****************************************************************************/
 #endif  /* mcftimer_h */
diff --git a/arch/m68k/mac/via.c b/arch/m68k/mac/via.c
index ce56e04386e7..920ff63d4a81 100644
--- a/arch/m68k/mac/via.c
+++ b/arch/m68k/mac/via.c
@@ -68,7 +68,7 @@ static int gIER,gIFR,gBufA,gBufB;
 * interrupt. This limitation also seems to apply to VIA clone logic cores in
 * Quadra-like ASICs. (RBV and OSS machines don't have this limitation.)
 *
- * We used to fake it by configuring the relevent VIA pin as an output
+ * We used to fake it by configuring the relevant VIA pin as an output
 * (to mask the interrupt) or input (to unmask). That scheme did not work on
 * (at least) the Quadra 700. A NuBus card's /NMRQ signal is an open-collector
 * circuit (see Designing Cards and Drivers for Macintosh II and Macintosh SE,

diff --git a/arch/m68k/include/asm/MC68328.h b/arch/m68k/include/asm/MC68328.h index 4ebf098b8a1f..1a8080c4cc40 100644 --- a/arch/m68k/include/asm/MC68328.h +++ b/arch/m68k/include/asm/MC68328.h
@@ -798,7 +798,7 @@
798		798
799	/**********	799	/**********
800	*	800	*
801	* 0xFFFFF7xx -- Serial Periferial Interface Slave (SPIS)	801	* 0xFFFFF7xx -- Serial Peripheral Interface Slave (SPIS)
802	*	802	*
803	**********/	803	**********/
804		804
@@ -824,7 +824,7 @@
824		824
825	/**********	825	/**********
826	*	826	*
827	* 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)	827	* 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
828	*	828	*
829	**********/	829	**********/
830		830
@@ -904,7 +904,7 @@
904		904
905	#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */	905	#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
906	#define UBAUD_PRESCALER_SHIFT 0	906	#define UBAUD_PRESCALER_SHIFT 0
907	#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */	907	#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divisor */
908	#define UBAUD_DIVIDE_SHIFT 8	908	#define UBAUD_DIVIDE_SHIFT 8
909	#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */	909	#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
910	#define UBAUD_GPIOSRC 0x1000 /* GPIO source */	910	#define UBAUD_GPIOSRC 0x1000 /* GPIO source */


diff --git a/arch/m68k/include/asm/MC68EZ328.h b/arch/m68k/include/asm/MC68EZ328.h index d1bde58ab0dd..fedac87c5d13 100644 --- a/arch/m68k/include/asm/MC68EZ328.h +++ b/arch/m68k/include/asm/MC68EZ328.h
@@ -631,7 +631,7 @@
631		631
632	/**********	632	/**********
633	*	633	*
634	* 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)	634	* 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
635	*	635	*
636	**********/	636	**********/
637		637
@@ -712,7 +712,7 @@
712		712
713	#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */	713	#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
714	#define UBAUD_PRESCALER_SHIFT 0	714	#define UBAUD_PRESCALER_SHIFT 0
715	#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */	715	#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divisor */
716	#define UBAUD_DIVIDE_SHIFT 8	716	#define UBAUD_DIVIDE_SHIFT 8
717	#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */	717	#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
718	#define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */	718	#define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */
@@ -1160,7 +1160,7 @@ typedef volatile struct {
1160	#define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */	1160	#define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */
1161	#define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */	1161	#define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */
1162	#define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */	1162	#define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */
1163	#define DRAMMC_REF_MASK 0x001f /* Reresh Cycle */	1163	#define DRAMMC_REF_MASK 0x001f /* Refresh Cycle */
1164	#define DRAMMC_REF_SHIFT 0	1164	#define DRAMMC_REF_SHIFT 0
1165		1165
1166	/*	1166	/*


diff --git a/arch/m68k/include/asm/MC68VZ328.h b/arch/m68k/include/asm/MC68VZ328.h index 6bd1bf1f85ea..34a51b2c784f 100644 --- a/arch/m68k/include/asm/MC68VZ328.h +++ b/arch/m68k/include/asm/MC68VZ328.h
@@ -724,7 +724,7 @@
724		724
725	/**********	725	/**********
726	*	726	*
727	* 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)	727	* 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
728	*	728	*
729	**********/	729	**********/
730		730
@@ -806,7 +806,7 @@
806		806
807	#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */	807	#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
808	#define UBAUD_PRESCALER_SHIFT 0	808	#define UBAUD_PRESCALER_SHIFT 0
809	#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */	809	#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divisor */
810	#define UBAUD_DIVIDE_SHIFT 8	810	#define UBAUD_DIVIDE_SHIFT 8
811	#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */	811	#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
812	#define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */	812	#define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */
@@ -1256,7 +1256,7 @@ typedef struct {
1256	#define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */	1256	#define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */
1257	#define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */	1257	#define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */
1258	#define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */	1258	#define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */
1259	#define DRAMMC_REF_MASK 0x001f /* Reresh Cycle */	1259	#define DRAMMC_REF_MASK 0x001f /* Refresh Cycle */
1260	#define DRAMMC_REF_SHIFT 0	1260	#define DRAMMC_REF_SHIFT 0
1261		1261
1262	/*	1262	/*


diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index 6d13cae44af5..59e171063c2f 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h
@@ -23,8 +23,8 @@
23	#define CACR_IEC 0x00008000 /* Enable instruction cache */	23	#define CACR_IEC 0x00008000 /* Enable instruction cache */
24	#define CACR_DNFB 0x00002000 /* Inhibited fill buffer */	24	#define CACR_DNFB 0x00002000 /* Inhibited fill buffer */
25	#define CACR_IDPI 0x00001000 /* Disable CPUSHL */	25	#define CACR_IDPI 0x00001000 /* Disable CPUSHL */
26	#define CACR_IHLCK 0x00000800 /* Intruction cache half lock */	26	#define CACR_IHLCK 0x00000800 /* Instruction cache half lock */
27	#define CACR_IDCM 0x00000400 /* Intruction cache inhibit */	27	#define CACR_IDCM 0x00000400 /* Instruction cache inhibit */
28	#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */	28	#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */
29	#define CACR_EUSP 0x00000020 /* Enable separate user a7 */	29	#define CACR_EUSP 0x00000020 /* Enable separate user a7 */
30		30


diff --git a/arch/m68k/include/asm/mac_iop.h b/arch/m68k/include/asm/mac_iop.h index fde874a01e20..42566fd052bc 100644 --- a/arch/m68k/include/asm/mac_iop.h +++ b/arch/m68k/include/asm/mac_iop.h
@@ -48,7 +48,7 @@
48		48
49	/* IOP message status codes */	49	/* IOP message status codes */
50		50
51	#define IOP_MSGSTATUS_UNUSED 0 /* Unusued message structure */	51	#define IOP_MSGSTATUS_UNUSED 0 /* Unused message structure */
52	#define IOP_MSGSTATUS_WAITING 1 /* waiting for channel */	52	#define IOP_MSGSTATUS_WAITING 1 /* waiting for channel */
53	#define IOP_MSGSTATUS_SENT 2 /* message sent, awaiting reply */	53	#define IOP_MSGSTATUS_SENT 2 /* message sent, awaiting reply */
54	#define IOP_MSGSTATUS_COMPLETE 3 /* message complete and reply rcvd */	54	#define IOP_MSGSTATUS_COMPLETE 3 /* message complete and reply rcvd */


diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h index 089f0f150bbf..1150e42c3f19 100644 --- a/arch/m68k/include/asm/mcftimer.h +++ b/arch/m68k/include/asm/mcftimer.h
@@ -51,7 +51,7 @@
51	* Bit definitions for the Timer Event Registers (TER).	51	* Bit definitions for the Timer Event Registers (TER).
52	*/	52	*/
53	#define MCFTIMER_TER_CAP 0x01 /* Capture event */	53	#define MCFTIMER_TER_CAP 0x01 /* Capture event */
54	#define MCFTIMER_TER_REF 0x02 /* Refernece event */	54	#define MCFTIMER_TER_REF 0x02 /* Reference event */
55		55
56	/****************************************************************************/	56	/****************************************************************************/
57	#endif /* mcftimer_h */	57	#endif /* mcftimer_h */


diff --git a/arch/m68k/mac/via.c b/arch/m68k/mac/via.c index ce56e04386e7..920ff63d4a81 100644 --- a/arch/m68k/mac/via.c +++ b/arch/m68k/mac/via.c
@@ -68,7 +68,7 @@ static int gIER,gIFR,gBufA,gBufB;
68	* interrupt. This limitation also seems to apply to VIA clone logic cores in	68	* interrupt. This limitation also seems to apply to VIA clone logic cores in
69	* Quadra-like ASICs. (RBV and OSS machines don't have this limitation.)	69	* Quadra-like ASICs. (RBV and OSS machines don't have this limitation.)
70	*	70	*
71	* We used to fake it by configuring the relevent VIA pin as an output	71	* We used to fake it by configuring the relevant VIA pin as an output
72	* (to mask the interrupt) or input (to unmask). That scheme did not work on	72	* (to mask the interrupt) or input (to unmask). That scheme did not work on
73	* (at least) the Quadra 700. A NuBus card's /NMRQ signal is an open-collector	73	* (at least) the Quadra 700. A NuBus card's /NMRQ signal is an open-collector
74	* circuit (see Designing Cards and Drivers for Macintosh II and Macintosh SE,	74	* circuit (see Designing Cards and Drivers for Macintosh II and Macintosh SE,