2 files changed, 5 insertions, 21 deletions

diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig
index 366dc83019a5..bd920ccbef6f 100644
--- a/arch/cris/Kconfig
+++ b/arch/cris/Kconfig
@@ -55,6 +55,7 @@ config CRIS
         select IRQ_DOMAIN if ETRAX_ARCH_V32
         select OF if ETRAX_ARCH_V32
         select OF_EARLY_FLATTREE if ETRAX_ARCH_V32
+        select CLKSRC_MMIO if ETRAX_ARCH_V32
         select GENERIC_CLOCKEVENTS if ETRAX_ARCH_V32
 
 config HZ
diff --git a/arch/cris/arch-v32/kernel/time.c b/arch/cris/arch-v32/kernel/time.c
index 77e241d6fa3d..7c802121c0c3 100644
--- a/arch/cris/arch-v32/kernel/time.c
+++ b/arch/cris/arch-v32/kernel/time.c
@@ -39,27 +39,6 @@
 
 #define CRISV32_TIMER_FREQ      (100000000lu)
 
-/* Register the continuos readonly timer available in FS and ARTPEC-3.  */
-static cycle_t read_cont_rotime(struct clocksource *cs)
-{
-        return (u32)REG_RD(timer, regi_timer0, r_time);
-}
-
-static struct clocksource cont_rotime = {
-        .name   = "crisv32_rotime",
-        .rating = 300,
-        .read   = read_cont_rotime,
-        .mask   = CLOCKSOURCE_MASK(32),
-        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static int __init etrax_init_cont_rotime(void)
-{
-        clocksource_register_khz(&cont_rotime, 100000);
-        return 0;
-}
-arch_initcall(etrax_init_cont_rotime);
-
 unsigned long timer_regs[NR_CPUS] =
 {
         regi_timer0,
@@ -296,6 +275,10 @@ void __init time_init(void)
 
         crisv32_timer_init();
 
+        clocksource_mmio_init(timer_base + REG_RD_ADDR_timer_r_time,
+                              "crisv32-timer", CRISV32_TIMER_FREQ,
+                              300, 32, clocksource_mmio_readl_up);
+
         crisv32_clockevent.cpumask = cpu_possible_mask;
         crisv32_clockevent.irq = irq;