17 files changed, 130 insertions, 28 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index d5376011c753..2d3d750b19c0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5259,7 +5259,8 @@ S:	Maintained
 F:      drivers/iommu/exynos-iommu.c
 
 EZchip NPS platform support
-M:      Noam Camus <noamc@ezchip.com>
+M:      Elad Kanfi <eladkan@mellanox.com>
+M:      Vineet Gupta <vgupta@synopsys.com>
 S:      Supported
 F:      arch/arc/plat-eznps
 F:      arch/arc/boot/dts/eznps.dts
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index a598641eed98..c84e67fdea09 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -24,7 +24,7 @@ config ARC
         select GENERIC_SMP_IDLE_THREAD
         select HAVE_ARCH_KGDB
         select HAVE_ARCH_TRACEHOOK
-        select HAVE_FUTEX_CMPXCHG
+        select HAVE_FUTEX_CMPXCHG if FUTEX
         select HAVE_IOREMAP_PROT
         select HAVE_KPROBES
         select HAVE_KRETPROBES
diff --git a/arch/arc/Makefile b/arch/arc/Makefile
index 3a4b52b7e09d..d37f49d6a27f 100644
--- a/arch/arc/Makefile
+++ b/arch/arc/Makefile
@@ -6,8 +6,6 @@
 # published by the Free Software Foundation.
 #
 
-UTS_MACHINE := arc
-
 ifeq ($(CROSS_COMPILE),)
 ifndef CONFIG_CPU_BIG_ENDIAN
 CROSS_COMPILE := arc-linux-
diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
index 2367a67c5f10..e114000a84f5 100644
--- a/arch/arc/boot/dts/axs10x_mb.dtsi
+++ b/arch/arc/boot/dts/axs10x_mb.dtsi
@@ -44,7 +44,14 @@
 
                         mmcclk: mmcclk {
                                 compatible = "fixed-clock";
-                                clock-frequency = <50000000>;
+                                /*
+                                 * DW sdio controller has external ciu clock divider
+                                 * controlled via register in SDIO IP. It divides
+                                 * sdio_ref_clk (which comes from CGU) by 16 for
+                                 * default. So default mmcclk clock (which comes
+                                 * to sdk_in) is 25000000 Hz.
+                                 */
+                                clock-frequency = <25000000>;
                                 #clock-cells = <0>;
                         };
 
diff --git a/arch/arc/boot/dts/hsdk.dts b/arch/arc/boot/dts/hsdk.dts
index 229d13adbce4..8adde1b492f1 100644
--- a/arch/arc/boot/dts/hsdk.dts
+++ b/arch/arc/boot/dts/hsdk.dts
@@ -12,6 +12,7 @@
 /dts-v1/;
 
 #include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/reset/snps,hsdk-reset.h>
 
 / {
         model = "snps,hsdk";
@@ -57,10 +58,10 @@
                 };
         };
 
-        core_clk: core-clk {
+        input_clk: input-clk {
                 #clock-cells = <0>;
                 compatible = "fixed-clock";
-                clock-frequency = <500000000>;
+                clock-frequency = <33333333>;
         };
 
         cpu_intc: cpu-interrupt-controller {
@@ -102,6 +103,19 @@
 
                 ranges = <0x00000000 0xf0000000 0x10000000>;
 
+                cgu_rst: reset-controller@8a0 {
+                        compatible = "snps,hsdk-reset";
+                        #reset-cells = <1>;
+                        reg = <0x8A0 0x4>, <0xFF0 0x4>;
+                };
+
+                core_clk: core-clk@0 {
+                        compatible = "snps,hsdk-core-pll-clock";
+                        reg = <0x00 0x10>, <0x14B8 0x4>;
+                        #clock-cells = <0>;
+                        clocks = <&input_clk>;
+                };
+
                 serial: serial@5000 {
                         compatible = "snps,dw-apb-uart";
                         reg = <0x5000 0x100>;
@@ -120,7 +134,17 @@
 
                 mmcclk_ciu: mmcclk-ciu {
                         compatible = "fixed-clock";
-                        clock-frequency = <100000000>;
+                        /*
+                         * DW sdio controller has external ciu clock divider
+                         * controlled via register in SDIO IP. Due to its
+                         * unexpected default value (it should devide by 1
+                         * but it devides by 8) SDIO IP uses wrong clock and
+                         * works unstable (see STAR 9001204800)
+                         * So add temporary fix and change clock frequency
+                         * from 100000000 to 12500000 Hz until we fix dw sdio
+                         * driver itself.
+                         */
+                        clock-frequency = <12500000>;
                         #clock-cells = <0>;
                 };
 
@@ -141,6 +165,8 @@
                         clocks = <&gmacclk>;
                         clock-names = "stmmaceth";
                         phy-handle = <&phy0>;
+                        resets = <&cgu_rst HSDK_ETH_RESET>;
+                        reset-names = "stmmaceth";
 
                         mdio {
                                 #address-cells = <1>;
diff --git a/arch/arc/configs/axs101_defconfig b/arch/arc/configs/axs101_defconfig
index 6980b966a364..ec7c849a5c8e 100644
--- a/arch/arc/configs/axs101_defconfig
+++ b/arch/arc/configs/axs101_defconfig
@@ -105,7 +105,7 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_STRIP_ASM_SYMS=y
-CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
diff --git a/arch/arc/configs/axs103_defconfig b/arch/arc/configs/axs103_defconfig
index 2233f5777a71..63d3cf69e0b0 100644
--- a/arch/arc/configs/axs103_defconfig
+++ b/arch/arc/configs/axs103_defconfig
@@ -104,7 +104,7 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_STRIP_ASM_SYMS=y
-CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
diff --git a/arch/arc/configs/axs103_smp_defconfig b/arch/arc/configs/axs103_smp_defconfig
index 30a3d4cf53d2..f613ecac14a7 100644
--- a/arch/arc/configs/axs103_smp_defconfig
+++ b/arch/arc/configs/axs103_smp_defconfig
@@ -107,7 +107,7 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_STRIP_ASM_SYMS=y
-CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
diff --git a/arch/arc/configs/haps_hs_smp_defconfig b/arch/arc/configs/haps_hs_smp_defconfig
index 821a2e562f3f..3507be2af6fe 100644
--- a/arch/arc/configs/haps_hs_smp_defconfig
+++ b/arch/arc/configs/haps_hs_smp_defconfig
@@ -84,5 +84,5 @@ CONFIG_TMPFS=y
 CONFIG_NFS_FS=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
 # CONFIG_DEBUG_PREEMPT is not set
diff --git a/arch/arc/configs/hsdk_defconfig b/arch/arc/configs/hsdk_defconfig
index 9a3fcf446388..15f0f6b5fec1 100644
--- a/arch/arc/configs/hsdk_defconfig
+++ b/arch/arc/configs/hsdk_defconfig
@@ -63,6 +63,7 @@ CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_DW=y
 # CONFIG_IOMMU_SUPPORT is not set
+CONFIG_RESET_HSDK=y
 CONFIG_EXT3_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
@@ -72,7 +73,7 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_STRIP_ASM_SYMS=y
-CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
diff --git a/arch/arc/configs/vdk_hs38_defconfig b/arch/arc/configs/vdk_hs38_defconfig
index c0d6a010751a..4fcf4f2503f6 100644
--- a/arch/arc/configs/vdk_hs38_defconfig
+++ b/arch/arc/configs/vdk_hs38_defconfig
@@ -94,7 +94,7 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_SHIRQ=y
-CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
diff --git a/arch/arc/configs/vdk_hs38_smp_defconfig b/arch/arc/configs/vdk_hs38_smp_defconfig
index 5c0971787acf..7b71464f6c2f 100644
--- a/arch/arc/configs/vdk_hs38_smp_defconfig
+++ b/arch/arc/configs/vdk_hs38_smp_defconfig
@@ -98,7 +98,7 @@ CONFIG_NLS_ISO8859_1=y
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_SHIRQ=y
-CONFIG_LOCKUP_DETECTOR=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
 CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index ba8e802dba80..b1c56d35f2a9 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -98,6 +98,7 @@
 
 /* Auxiliary registers */
 #define AUX_IDENTITY            4
+#define AUX_EXEC_CTRL           8
 #define AUX_INTR_VEC_BASE       0x25
 #define AUX_VOL                 0x5e
 
@@ -135,12 +136,12 @@ struct bcr_identity {
 #endif
 };
 
-struct bcr_isa {
+struct bcr_isa_arcv2 {
 #ifdef CONFIG_CPU_BIG_ENDIAN
         unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
-                     pad1:11, atomic1:1, ver:8;
+                     pad1:12, ver:8;
 #else
-        unsigned int ver:8, atomic1:1, pad1:11, be:1, atomic:1, unalign:1,
+        unsigned int ver:8, pad1:12, be:1, atomic:1, unalign:1,
                      ldd:1, pad2:4, div_rem:4;
 #endif
 };
@@ -263,13 +264,13 @@ struct cpuinfo_arc {
         struct cpuinfo_arc_mmu mmu;
         struct cpuinfo_arc_bpu bpu;
         struct bcr_identity core;
-        struct bcr_isa isa;
+        struct bcr_isa_arcv2 isa;
         const char *details, *name;
         unsigned int vec_base;
         struct cpuinfo_arc_ccm iccm, dccm;
         struct {
                 unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
-                             fpu_sp:1, fpu_dp:1, pad2:6,
+                             fpu_sp:1, fpu_dp:1, dual_iss_enb:1, dual_iss_exist:1, pad2:4,
                              debug:1, ap:1, smart:1, rtt:1, pad3:4,
                              timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
         } extn;
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 877cec8f5ea2..fb83844daeea 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -51,6 +51,7 @@ static const struct id_to_str arc_cpu_rel[] = {
         { 0x51, "R2.0" },
         { 0x52, "R2.1" },
         { 0x53, "R3.0" },
+        { 0x54, "R4.0" },
 #endif
         { 0x00, NULL   }
 };
@@ -62,6 +63,7 @@ static const struct id_to_str arc_cpu_nm[] = {
 #else
         { 0x40, "ARC EM"  },
         { 0x50, "ARC HS38"  },
+        { 0x54, "ARC HS48"  },
 #endif
         { 0x00, "Unknown"   }
 };
@@ -119,11 +121,11 @@ static void read_arc_build_cfg_regs(void)
         struct bcr_generic bcr;
         struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
         const struct id_to_str *tbl;
+        struct bcr_isa_arcv2 isa;
 
         FIX_PTR(cpu);
 
         READ_BCR(AUX_IDENTITY, cpu->core);
-        READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa);
 
         for (tbl = &arc_cpu_rel[0]; tbl->id != 0; tbl++) {
                 if (cpu->core.family == tbl->id) {
@@ -133,7 +135,7 @@ static void read_arc_build_cfg_regs(void)
         }
 
         for (tbl = &arc_cpu_nm[0]; tbl->id != 0; tbl++) {
-                if ((cpu->core.family & 0xF0) == tbl->id)
+                if ((cpu->core.family & 0xF4) == tbl->id)
                         break;
         }
         cpu->name = tbl->str;
@@ -192,6 +194,14 @@ static void read_arc_build_cfg_regs(void)
                 cpu->bpu.full = bpu.ft;
                 cpu->bpu.num_cache = 256 << bpu.bce;
                 cpu->bpu.num_pred = 2048 << bpu.pte;
+
+                if (cpu->core.family >= 0x54) {
+                        unsigned int exec_ctrl;
+
+                        READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
+                        cpu->extn.dual_iss_exist = 1;
+                        cpu->extn.dual_iss_enb = exec_ctrl & 1;
+                }
         }
 
         READ_BCR(ARC_REG_AP_BCR, bcr);
@@ -205,18 +215,25 @@ static void read_arc_build_cfg_regs(void)
 
         cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt;
 
+        READ_BCR(ARC_REG_ISA_CFG_BCR, isa);
+
         /* some hacks for lack of feature BCR info in old ARC700 cores */
         if (is_isa_arcompact()) {
-                if (!cpu->isa.ver)      /* ISA BCR absent, use Kconfig info */
+                if (!isa.ver)   /* ISA BCR absent, use Kconfig info */
                         cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
-                else
-                        cpu->isa.atomic = cpu->isa.atomic1;
+                else {
+                        /* ARC700_BUILD only has 2 bits of isa info */
+                        struct bcr_generic bcr = *(struct bcr_generic *)&isa;
+                        cpu->isa.atomic = bcr.info & 1;
+                }
 
                 cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
 
                  /* there's no direct way to distinguish 750 vs. 770 */
                 if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3))
                         cpu->name = "ARC750";
+        } else {
+                cpu->isa = isa;
         }
 }
 
@@ -232,10 +249,11 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
                        "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",
                        core->family, core->cpu_id, core->chip_id);
 
-        n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s\n",
+        n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n",
                        cpu_id, cpu->name, cpu->details,
                        is_isa_arcompact() ? "ARCompact" : "ARCv2",
-                       IS_AVAIL1(cpu->isa.be, "[Big-Endian]"));
+                       IS_AVAIL1(cpu->isa.be, "[Big-Endian]"),
+                       IS_AVAIL3(cpu->extn.dual_iss_exist, cpu->extn.dual_iss_enb, " Dual-Issue"));
 
         n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ",
                        IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c
index f1ac6790da5f..cf14ebc36916 100644
--- a/arch/arc/plat-axs10x/axs10x.c
+++ b/arch/arc/plat-axs10x/axs10x.c
@@ -111,6 +111,13 @@ static void __init axs10x_early_init(void)
 
         axs10x_enable_gpio_intc_wire();
 
+        /*
+         * Reset ethernet IP core.
+         * TODO: get rid of this quirk after axs10x reset driver (or simple
+         * reset driver) will be available in upstream.
+         */
+        iowrite32((1 << 5), (void __iomem *) CREG_MB_SW_RESET);
+
         scnprintf(mb, 32, "MainBoard v%d", mb_rev);
         axs10x_print_board_ver(CREG_MB_VER, mb);
 }
diff --git a/arch/arc/plat-hsdk/Kconfig b/arch/arc/plat-hsdk/Kconfig
index 5a6ed5afb009..bd08de4be75e 100644
--- a/arch/arc/plat-hsdk/Kconfig
+++ b/arch/arc/plat-hsdk/Kconfig
@@ -6,4 +6,5 @@
 #
 
 menuconfig ARC_SOC_HSDK
-       bool "ARC HS Development Kit SOC"
+        bool "ARC HS Development Kit SOC"
+        select CLK_HSDK
diff --git a/arch/arc/plat-hsdk/platform.c b/arch/arc/plat-hsdk/platform.c
index a2e7fd17e36d..744e62e58788 100644
--- a/arch/arc/plat-hsdk/platform.c
+++ b/arch/arc/plat-hsdk/platform.c
@@ -38,6 +38,42 @@ static void __init hsdk_init_per_cpu(unsigned int cpu)
 #define CREG_PAE                (CREG_BASE + 0x180)
 #define CREG_PAE_UPDATE         (CREG_BASE + 0x194)
 
+#define CREG_CORE_IF_CLK_DIV    (CREG_BASE + 0x4B8)
+#define CREG_CORE_IF_CLK_DIV_2  0x1
+#define CGU_BASE                ARC_PERIPHERAL_BASE
+#define CGU_PLL_STATUS          (ARC_PERIPHERAL_BASE + 0x4)
+#define CGU_PLL_CTRL            (ARC_PERIPHERAL_BASE + 0x0)
+#define CGU_PLL_STATUS_LOCK     BIT(0)
+#define CGU_PLL_STATUS_ERR      BIT(1)
+#define CGU_PLL_CTRL_1GHZ       0x3A10
+#define HSDK_PLL_LOCK_TIMEOUT   500
+
+#define HSDK_PLL_LOCKED() \
+        !!(ioread32((void __iomem *) CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK)
+
+#define HSDK_PLL_ERR() \
+        !!(ioread32((void __iomem *) CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR)
+
+static void __init hsdk_set_cpu_freq_1ghz(void)
+{
+        u32 timeout = HSDK_PLL_LOCK_TIMEOUT;
+
+        /*
+         * As we set cpu clock which exceeds 500MHz, the divider for the interface
+         * clock must be programmed to div-by-2.
+         */
+        iowrite32(CREG_CORE_IF_CLK_DIV_2, (void __iomem *) CREG_CORE_IF_CLK_DIV);
+
+        /* Set cpu clock to 1GHz */
+        iowrite32(CGU_PLL_CTRL_1GHZ, (void __iomem *) CGU_PLL_CTRL);
+
+        while (!HSDK_PLL_LOCKED() && timeout--)
+                cpu_relax();
+
+        if (!HSDK_PLL_LOCKED() || HSDK_PLL_ERR())
+                pr_err("Failed to setup CPU frequency to 1GHz!");
+}
+
 static void __init hsdk_init_early(void)
 {
         /*
@@ -52,6 +88,12 @@ static void __init hsdk_init_early(void)
 
         /* Really apply settings made above */
         writel(1, (void __iomem *) CREG_PAE_UPDATE);
+
+        /*
+         * Setup CPU frequency to 1GHz.
+         * TODO: remove it after smart hsdk pll driver will be introduced.
+         */
+        hsdk_set_cpu_freq_1ghz();
 }
 
 static const char *hsdk_compat[] __initconst = {