diff options
| -rw-r--r-- | drivers/irqchip/irq-xtensa-mx.c | 34 |
1 files changed, 20 insertions, 14 deletions
diff --git a/drivers/irqchip/irq-xtensa-mx.c b/drivers/irqchip/irq-xtensa-mx.c index 0bd3fe3b969e..27933338f7b3 100644 --- a/drivers/irqchip/irq-xtensa-mx.c +++ b/drivers/irqchip/irq-xtensa-mx.c | |||
| @@ -71,14 +71,17 @@ static void xtensa_mx_irq_mask(struct irq_data *d) | |||
| 71 | unsigned int mask = 1u << d->hwirq; | 71 | unsigned int mask = 1u << d->hwirq; |
| 72 | 72 | ||
| 73 | if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE | | 73 | if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE | |
| 74 | XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) { | 74 | XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) { |
| 75 | set_er(1u << (xtensa_get_ext_irq_no(d->hwirq) - | 75 | unsigned int ext_irq = xtensa_get_ext_irq_no(d->hwirq); |
| 76 | HW_IRQ_MX_BASE), MIENG); | 76 | |
| 77 | } else { | 77 | if (ext_irq >= HW_IRQ_MX_BASE) { |
| 78 | mask = __this_cpu_read(cached_irq_mask) & ~mask; | 78 | set_er(1u << (ext_irq - HW_IRQ_MX_BASE), MIENG); |
| 79 | __this_cpu_write(cached_irq_mask, mask); | 79 | return; |
| 80 | xtensa_set_sr(mask, intenable); | 80 | } |
| 81 | } | 81 | } |
| 82 | mask = __this_cpu_read(cached_irq_mask) & ~mask; | ||
| 83 | __this_cpu_write(cached_irq_mask, mask); | ||
| 84 | xtensa_set_sr(mask, intenable); | ||
| 82 | } | 85 | } |
| 83 | 86 | ||
| 84 | static void xtensa_mx_irq_unmask(struct irq_data *d) | 87 | static void xtensa_mx_irq_unmask(struct irq_data *d) |
| @@ -86,14 +89,17 @@ static void xtensa_mx_irq_unmask(struct irq_data *d) | |||
| 86 | unsigned int mask = 1u << d->hwirq; | 89 | unsigned int mask = 1u << d->hwirq; |
| 87 | 90 | ||
| 88 | if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE | | 91 | if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE | |
| 89 | XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) { | 92 | XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) { |
| 90 | set_er(1u << (xtensa_get_ext_irq_no(d->hwirq) - | 93 | unsigned int ext_irq = xtensa_get_ext_irq_no(d->hwirq); |
| 91 | HW_IRQ_MX_BASE), MIENGSET); | 94 | |
| 92 | } else { | 95 | if (ext_irq >= HW_IRQ_MX_BASE) { |
| 93 | mask |= __this_cpu_read(cached_irq_mask); | 96 | set_er(1u << (ext_irq - HW_IRQ_MX_BASE), MIENGSET); |
| 94 | __this_cpu_write(cached_irq_mask, mask); | 97 | return; |
| 95 | xtensa_set_sr(mask, intenable); | 98 | } |
| 96 | } | 99 | } |
| 100 | mask |= __this_cpu_read(cached_irq_mask); | ||
| 101 | __this_cpu_write(cached_irq_mask, mask); | ||
| 102 | xtensa_set_sr(mask, intenable); | ||
| 97 | } | 103 | } |
| 98 | 104 | ||
| 99 | static void xtensa_mx_irq_enable(struct irq_data *d) | 105 | static void xtensa_mx_irq_enable(struct irq_data *d) |
