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-rw-r--r--Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt60
-rw-r--r--drivers/clk/Kconfig26
-rw-r--r--drivers/clk/Makefile5
-rw-r--r--drivers/clk/clk-gpio.c4
-rw-r--r--drivers/clk/clk-stm32f4.c14
-rw-r--r--drivers/clk/clk-stm32mp1.c2117
-rw-r--r--drivers/clk/sprd/sc9860-clk.c76
-rw-r--r--include/dt-bindings/clock/sprd,sc9860-clk.h21
-rw-r--r--include/dt-bindings/clock/stm32fx-clock.h7
-rw-r--r--include/dt-bindings/clock/stm32mp1-clks.h254
10 files changed, 2572 insertions, 12 deletions
diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt
new file mode 100644
index 000000000000..fb9495ea582c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt
@@ -0,0 +1,60 @@
1STMicroelectronics STM32 Peripheral Reset Clock Controller
2==========================================================
3
4The RCC IP is both a reset and a clock controller.
5
6RCC makes also power management (resume/supend and wakeup interrupt).
7
8Please also refer to reset.txt for common reset controller binding usage.
9
10Please also refer to clock-bindings.txt for common clock controller
11binding usage.
12
13
14Required properties:
15- compatible: "st,stm32mp1-rcc", "syscon"
16- reg: should be register base and length as documented in the datasheet
17- #clock-cells: 1, device nodes should specify the clock in their
18 "clocks" property, containing a phandle to the clock device node,
19 an index specifying the clock to use.
20- #reset-cells: Shall be 1
21- interrupts: Should contain a general interrupt line and a interrupt line
22 to the wake-up of processor (CSTOP).
23
24Example:
25 rcc: rcc@50000000 {
26 compatible = "st,stm32mp1-rcc", "syscon";
27 reg = <0x50000000 0x1000>;
28 #clock-cells = <1>;
29 #reset-cells = <1>;
30 interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>,
31 <GIC_SPI 145 IRQ_TYPE_NONE>;
32 };
33
34Specifying clocks
35=================
36
37All available clocks are defined as preprocessor macros in
38dt-bindings/clock/stm32mp1-clks.h header and can be used in device
39tree sources.
40
41Specifying softreset control of devices
42=======================================
43
44Device nodes should specify the reset channel required in their "resets"
45property, containing a phandle to the reset device node and an index specifying
46which channel to use.
47The index is the bit number within the RCC registers bank, starting from RCC
48base address.
49It is calculated as: index = register_offset / 4 * 32 + bit_offset.
50Where bit_offset is the bit offset within the register.
51
52For example on STM32MP1, for LTDC reset:
53 ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset
54 = 0x180 / 4 * 32 + 0 = 3072
55
56The list of valid indices for STM32MP1 is available in:
57include/dt-bindings/reset-controller/stm32mp1-resets.h
58
59This file implements defines like:
60#define LTDC_R 3072
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 98ce9fc6e6c0..ede9cb0b79d6 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -55,8 +55,10 @@ config COMMON_CLK_RK808
55 by control register. 55 by control register.
56 56
57config COMMON_CLK_HI655X 57config COMMON_CLK_HI655X
58 tristate "Clock driver for Hi655x" 58 tristate "Clock driver for Hi655x" if EXPERT
59 depends on MFD_HI655X_PMIC || COMPILE_TEST 59 depends on (MFD_HI655X_PMIC || COMPILE_TEST)
60 depends on REGMAP
61 default MFD_HI655X_PMIC
60 ---help--- 62 ---help---
61 This driver supports the hi655x PMIC clock. This 63 This driver supports the hi655x PMIC clock. This
62 multi-function device has one fixed-rate oscillator, clocked 64 multi-function device has one fixed-rate oscillator, clocked
@@ -238,6 +240,26 @@ config COMMON_CLK_VC5
238 This driver supports the IDT VersaClock 5 and VersaClock 6 240 This driver supports the IDT VersaClock 5 and VersaClock 6
239 programmable clock generators. 241 programmable clock generators.
240 242
243config COMMON_CLK_STM32MP157
244 def_bool COMMON_CLK && MACH_STM32MP157
245 help
246 ---help---
247 Support for stm32mp157 SoC family clocks
248
249config COMMON_CLK_STM32F
250 bool "Clock driver for stm32f4 and stm32f7 SoC families"
251 depends on MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746
252 help
253 ---help---
254 Support for stm32f4 and stm32f7 SoC families clocks
255
256config COMMON_CLK_STM32H7
257 bool "Clock driver for stm32h7 SoC family"
258 depends on MACH_STM32H743
259 help
260 ---help---
261 Support for stm32h7 SoC family clocks
262
241source "drivers/clk/bcm/Kconfig" 263source "drivers/clk/bcm/Kconfig"
242source "drivers/clk/hisilicon/Kconfig" 264source "drivers/clk/hisilicon/Kconfig"
243source "drivers/clk/imgtec/Kconfig" 265source "drivers/clk/imgtec/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 71ec41e6364f..e0c106ed9407 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -45,8 +45,9 @@ obj-$(CONFIG_COMMON_CLK_SCPI) += clk-scpi.o
45obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o 45obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o
46obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o 46obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o
47obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o 47obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
48obj-$(CONFIG_ARCH_STM32) += clk-stm32f4.o 48obj-$(CONFIG_COMMON_CLK_STM32F) += clk-stm32f4.o
49obj-$(CONFIG_ARCH_STM32) += clk-stm32h7.o 49obj-$(CONFIG_COMMON_CLK_STM32H7) += clk-stm32h7.o
50obj-$(CONFIG_COMMON_CLK_STM32MP157) += clk-stm32mp1.o
50obj-$(CONFIG_ARCH_TANGO) += clk-tango4.o 51obj-$(CONFIG_ARCH_TANGO) += clk-tango4.o
51obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o 52obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
52obj-$(CONFIG_ARCH_U300) += clk-u300.o 53obj-$(CONFIG_ARCH_U300) += clk-u300.o
diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c
index 151513c655c3..40af4fbab4d2 100644
--- a/drivers/clk/clk-gpio.c
+++ b/drivers/clk/clk-gpio.c
@@ -73,14 +73,14 @@ static u8 clk_gpio_mux_get_parent(struct clk_hw *hw)
73{ 73{
74 struct clk_gpio *clk = to_clk_gpio(hw); 74 struct clk_gpio *clk = to_clk_gpio(hw);
75 75
76 return gpiod_get_value(clk->gpiod); 76 return gpiod_get_value_cansleep(clk->gpiod);
77} 77}
78 78
79static int clk_gpio_mux_set_parent(struct clk_hw *hw, u8 index) 79static int clk_gpio_mux_set_parent(struct clk_hw *hw, u8 index)
80{ 80{
81 struct clk_gpio *clk = to_clk_gpio(hw); 81 struct clk_gpio *clk = to_clk_gpio(hw);
82 82
83 gpiod_set_value(clk->gpiod, index); 83 gpiod_set_value_cansleep(clk->gpiod, index);
84 84
85 return 0; 85 return 0;
86} 86}
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index da44f8dc1d29..294850bdc195 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -282,6 +282,7 @@ static const struct stm32f4_gate_data stm32f746_gates[] __initconst = {
282 282
283 { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" }, 283 { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
284 { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" }, 284 { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
285 { STM32F4_RCC_APB2ENR, 7, "sdmmc2", "sdmux" },
285 { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" }, 286 { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
286 { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" }, 287 { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
287 { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" }, 288 { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
@@ -315,7 +316,7 @@ static const u64 stm32f46xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
315 316
316static const u64 stm32f746_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull, 317static const u64 stm32f746_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
317 0x0000000000000003ull, 318 0x0000000000000003ull,
318 0x04f77f033e01c9ffull }; 319 0x04f77f833e01c9ffull };
319 320
320static const u64 *stm32f4_gate_map; 321static const u64 *stm32f4_gate_map;
321 322
@@ -521,7 +522,7 @@ static const struct stm32f4_pll_data stm32f429_pll[MAX_PLL_DIV] = {
521}; 522};
522 523
523static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = { 524static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
524 { PLL, 50, { "pll", "pll-q", NULL } }, 525 { PLL, 50, { "pll", "pll-q", "pll-r" } },
525 { PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } }, 526 { PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
526 { PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } }, 527 { PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
527}; 528};
@@ -1047,6 +1048,8 @@ static const char *rtc_parents[4] = {
1047 "no-clock", "lse", "lsi", "hse-rtc" 1048 "no-clock", "lse", "lsi", "hse-rtc"
1048}; 1049};
1049 1050
1051static const char *dsi_parent[2] = { NULL, "pll-r" };
1052
1050static const char *lcd_parent[1] = { "pllsai-r-div" }; 1053static const char *lcd_parent[1] = { "pllsai-r-div" };
1051 1054
1052static const char *i2s_parents[2] = { "plli2s-r", NULL }; 1055static const char *i2s_parents[2] = { "plli2s-r", NULL };
@@ -1156,6 +1159,12 @@ static const struct stm32_aux_clk stm32f469_aux_clk[] = {
1156 NO_GATE, 0, 1159 NO_GATE, 0,
1157 0 1160 0
1158 }, 1161 },
1162 {
1163 CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent),
1164 STM32F4_RCC_DCKCFGR, 29, 1,
1165 STM32F4_RCC_APB2ENR, 27,
1166 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
1167 },
1159}; 1168};
1160 1169
1161static const struct stm32_aux_clk stm32f746_aux_clk[] = { 1170static const struct stm32_aux_clk stm32f746_aux_clk[] = {
@@ -1450,6 +1459,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
1450 stm32f4_gate_map = data->gates_map; 1459 stm32f4_gate_map = data->gates_map;
1451 1460
1452 hse_clk = of_clk_get_parent_name(np, 0); 1461 hse_clk = of_clk_get_parent_name(np, 0);
1462 dsi_parent[0] = hse_clk;
1453 1463
1454 i2s_in_clk = of_clk_get_parent_name(np, 1); 1464 i2s_in_clk = of_clk_get_parent_name(np, 1);
1455 1465
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
new file mode 100644
index 000000000000..f1d5967b4b39
--- /dev/null
+++ b/drivers/clk/clk-stm32mp1.c
@@ -0,0 +1,2117 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
4 * Author: Olivier Bideau <olivier.bideau@st.com> for STMicroelectronics.
5 * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
6 */
7
8#include <linux/clk.h>
9#include <linux/clk-provider.h>
10#include <linux/delay.h>
11#include <linux/err.h>
12#include <linux/io.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17
18#include <dt-bindings/clock/stm32mp1-clks.h>
19
20static DEFINE_SPINLOCK(rlock);
21
22#define RCC_OCENSETR 0x0C
23#define RCC_HSICFGR 0x18
24#define RCC_RDLSICR 0x144
25#define RCC_PLL1CR 0x80
26#define RCC_PLL1CFGR1 0x84
27#define RCC_PLL1CFGR2 0x88
28#define RCC_PLL2CR 0x94
29#define RCC_PLL2CFGR1 0x98
30#define RCC_PLL2CFGR2 0x9C
31#define RCC_PLL3CR 0x880
32#define RCC_PLL3CFGR1 0x884
33#define RCC_PLL3CFGR2 0x888
34#define RCC_PLL4CR 0x894
35#define RCC_PLL4CFGR1 0x898
36#define RCC_PLL4CFGR2 0x89C
37#define RCC_APB1ENSETR 0xA00
38#define RCC_APB2ENSETR 0xA08
39#define RCC_APB3ENSETR 0xA10
40#define RCC_APB4ENSETR 0x200
41#define RCC_APB5ENSETR 0x208
42#define RCC_AHB2ENSETR 0xA18
43#define RCC_AHB3ENSETR 0xA20
44#define RCC_AHB4ENSETR 0xA28
45#define RCC_AHB5ENSETR 0x210
46#define RCC_AHB6ENSETR 0x218
47#define RCC_AHB6LPENSETR 0x318
48#define RCC_RCK12SELR 0x28
49#define RCC_RCK3SELR 0x820
50#define RCC_RCK4SELR 0x824
51#define RCC_MPCKSELR 0x20
52#define RCC_ASSCKSELR 0x24
53#define RCC_MSSCKSELR 0x48
54#define RCC_SPI6CKSELR 0xC4
55#define RCC_SDMMC12CKSELR 0x8F4
56#define RCC_SDMMC3CKSELR 0x8F8
57#define RCC_FMCCKSELR 0x904
58#define RCC_I2C46CKSELR 0xC0
59#define RCC_I2C12CKSELR 0x8C0
60#define RCC_I2C35CKSELR 0x8C4
61#define RCC_UART1CKSELR 0xC8
62#define RCC_QSPICKSELR 0x900
63#define RCC_ETHCKSELR 0x8FC
64#define RCC_RNG1CKSELR 0xCC
65#define RCC_RNG2CKSELR 0x920
66#define RCC_GPUCKSELR 0x938
67#define RCC_USBCKSELR 0x91C
68#define RCC_STGENCKSELR 0xD4
69#define RCC_SPDIFCKSELR 0x914
70#define RCC_SPI2S1CKSELR 0x8D8
71#define RCC_SPI2S23CKSELR 0x8DC
72#define RCC_SPI2S45CKSELR 0x8E0
73#define RCC_CECCKSELR 0x918
74#define RCC_LPTIM1CKSELR 0x934
75#define RCC_LPTIM23CKSELR 0x930
76#define RCC_LPTIM45CKSELR 0x92C
77#define RCC_UART24CKSELR 0x8E8
78#define RCC_UART35CKSELR 0x8EC
79#define RCC_UART6CKSELR 0x8E4
80#define RCC_UART78CKSELR 0x8F0
81#define RCC_FDCANCKSELR 0x90C
82#define RCC_SAI1CKSELR 0x8C8
83#define RCC_SAI2CKSELR 0x8CC
84#define RCC_SAI3CKSELR 0x8D0
85#define RCC_SAI4CKSELR 0x8D4
86#define RCC_ADCCKSELR 0x928
87#define RCC_MPCKDIVR 0x2C
88#define RCC_DSICKSELR 0x924
89#define RCC_CPERCKSELR 0xD0
90#define RCC_MCO1CFGR 0x800
91#define RCC_MCO2CFGR 0x804
92#define RCC_BDCR 0x140
93#define RCC_AXIDIVR 0x30
94#define RCC_MCUDIVR 0x830
95#define RCC_APB1DIVR 0x834
96#define RCC_APB2DIVR 0x838
97#define RCC_APB3DIVR 0x83C
98#define RCC_APB4DIVR 0x3C
99#define RCC_APB5DIVR 0x40
100#define RCC_TIMG1PRER 0x828
101#define RCC_TIMG2PRER 0x82C
102#define RCC_RTCDIVR 0x44
103#define RCC_DBGCFGR 0x80C
104
105#define RCC_CLR 0x4
106
107static const char * const ref12_parents[] = {
108 "ck_hsi", "ck_hse"
109};
110
111static const char * const ref3_parents[] = {
112 "ck_hsi", "ck_hse", "ck_csi"
113};
114
115static const char * const ref4_parents[] = {
116 "ck_hsi", "ck_hse", "ck_csi"
117};
118
119static const char * const cpu_src[] = {
120 "ck_hsi", "ck_hse", "pll1_p"
121};
122
123static const char * const axi_src[] = {
124 "ck_hsi", "ck_hse", "pll2_p", "pll3_p"
125};
126
127static const char * const per_src[] = {
128 "ck_hsi", "ck_csi", "ck_hse"
129};
130
131static const char * const mcu_src[] = {
132 "ck_hsi", "ck_hse", "ck_csi", "pll3_p"
133};
134
135static const char * const sdmmc12_src[] = {
136 "ck_axi", "pll3_r", "pll4_p", "ck_hsi"
137};
138
139static const char * const sdmmc3_src[] = {
140 "ck_mcu", "pll3_r", "pll4_p", "ck_hsi"
141};
142
143static const char * const fmc_src[] = {
144 "ck_axi", "pll3_r", "pll4_p", "ck_per"
145};
146
147static const char * const qspi_src[] = {
148 "ck_axi", "pll3_r", "pll4_p", "ck_per"
149};
150
151static const char * const eth_src[] = {
152 "pll4_p", "pll3_q"
153};
154
155static const char * const rng_src[] = {
156 "ck_csi", "pll4_r", "ck_lse", "ck_lsi"
157};
158
159static const char * const usbphy_src[] = {
160 "ck_hse", "pll4_r", "clk-hse-div2"
161};
162
163static const char * const usbo_src[] = {
164 "pll4_r", "ck_usbo_48m"
165};
166
167static const char * const stgen_src[] = {
168 "ck_hsi", "ck_hse"
169};
170
171static const char * const spdif_src[] = {
172 "pll4_p", "pll3_q", "ck_hsi"
173};
174
175static const char * const spi123_src[] = {
176 "pll4_p", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
177};
178
179static const char * const spi45_src[] = {
180 "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
181};
182
183static const char * const spi6_src[] = {
184 "pclk5", "pll4_q", "ck_hsi", "ck_csi", "ck_hse", "pll3_q"
185};
186
187static const char * const cec_src[] = {
188 "ck_lse", "ck_lsi", "ck_csi"
189};
190
191static const char * const i2c12_src[] = {
192 "pclk1", "pll4_r", "ck_hsi", "ck_csi"
193};
194
195static const char * const i2c35_src[] = {
196 "pclk1", "pll4_r", "ck_hsi", "ck_csi"
197};
198
199static const char * const i2c46_src[] = {
200 "pclk5", "pll3_q", "ck_hsi", "ck_csi"
201};
202
203static const char * const lptim1_src[] = {
204 "pclk1", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
205};
206
207static const char * const lptim23_src[] = {
208 "pclk3", "pll4_q", "ck_per", "ck_lse", "ck_lsi"
209};
210
211static const char * const lptim45_src[] = {
212 "pclk3", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per"
213};
214
215static const char * const usart1_src[] = {
216 "pclk5", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse"
217};
218
219const char * const usart234578_src[] = {
220 "pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
221};
222
223static const char * const usart6_src[] = {
224 "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse"
225};
226
227static const char * const dfsdm_src[] = {
228 "pclk2", "ck_mcu"
229};
230
231static const char * const fdcan_src[] = {
232 "ck_hse", "pll3_q", "pll4_q"
233};
234
235static const char * const sai_src[] = {
236 "pll4_q", "pll3_q", "i2s_ckin", "ck_per"
237};
238
239static const char * const sai2_src[] = {
240 "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb"
241};
242
243static const char * const adc12_src[] = {
244 "pll4_q", "ck_per"
245};
246
247static const char * const dsi_src[] = {
248 "ck_dsi_phy", "pll4_p"
249};
250
251static const char * const rtc_src[] = {
252 "off", "ck_lse", "ck_lsi", "ck_hse_rtc"
253};
254
255static const char * const mco1_src[] = {
256 "ck_hsi", "ck_hse", "ck_csi", "ck_lsi", "ck_lse"
257};
258
259static const char * const mco2_src[] = {
260 "ck_mpu", "ck_axi", "ck_mcu", "pll4_p", "ck_hse", "ck_hsi"
261};
262
263static const char * const ck_trace_src[] = {
264 "ck_axi"
265};
266
267static const struct clk_div_table axi_div_table[] = {
268 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
269 { 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 },
270 { 0 },
271};
272
273static const struct clk_div_table mcu_div_table[] = {
274 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
275 { 4, 16 }, { 5, 32 }, { 6, 64 }, { 7, 128 },
276 { 8, 512 }, { 9, 512 }, { 10, 512}, { 11, 512 },
277 { 12, 512 }, { 13, 512 }, { 14, 512}, { 15, 512 },
278 { 0 },
279};
280
281static const struct clk_div_table apb_div_table[] = {
282 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
283 { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
284 { 0 },
285};
286
287static const struct clk_div_table ck_trace_div_table[] = {
288 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
289 { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
290 { 0 },
291};
292
293#define MAX_MUX_CLK 2
294
295struct stm32_mmux {
296 u8 nbr_clk;
297 struct clk_hw *hws[MAX_MUX_CLK];
298};
299
300struct stm32_clk_mmux {
301 struct clk_mux mux;
302 struct stm32_mmux *mmux;
303};
304
305struct stm32_mgate {
306 u8 nbr_clk;
307 u32 flag;
308};
309
310struct stm32_clk_mgate {
311 struct clk_gate gate;
312 struct stm32_mgate *mgate;
313 u32 mask;
314};
315
316struct clock_config {
317 u32 id;
318 const char *name;
319 union {
320 const char *parent_name;
321 const char * const *parent_names;
322 };
323 int num_parents;
324 unsigned long flags;
325 void *cfg;
326 struct clk_hw * (*func)(struct device *dev,
327 struct clk_hw_onecell_data *clk_data,
328 void __iomem *base, spinlock_t *lock,
329 const struct clock_config *cfg);
330};
331
332#define NO_ID ~0
333
334struct gate_cfg {
335 u32 reg_off;
336 u8 bit_idx;
337 u8 gate_flags;
338};
339
340struct fixed_factor_cfg {
341 unsigned int mult;
342 unsigned int div;
343};
344
345struct div_cfg {
346 u32 reg_off;
347 u8 shift;
348 u8 width;
349 u8 div_flags;
350 const struct clk_div_table *table;
351};
352
353struct mux_cfg {
354 u32 reg_off;
355 u8 shift;
356 u8 width;
357 u8 mux_flags;
358 u32 *table;
359};
360
361struct stm32_gate_cfg {
362 struct gate_cfg *gate;
363 struct stm32_mgate *mgate;
364 const struct clk_ops *ops;
365};
366
367struct stm32_div_cfg {
368 struct div_cfg *div;
369 const struct clk_ops *ops;
370};
371
372struct stm32_mux_cfg {
373 struct mux_cfg *mux;
374 struct stm32_mmux *mmux;
375 const struct clk_ops *ops;
376};
377
378/* STM32 Composite clock */
379struct stm32_composite_cfg {
380 const struct stm32_gate_cfg *gate;
381 const struct stm32_div_cfg *div;
382 const struct stm32_mux_cfg *mux;
383};
384
385static struct clk_hw *
386_clk_hw_register_gate(struct device *dev,
387 struct clk_hw_onecell_data *clk_data,
388 void __iomem *base, spinlock_t *lock,
389 const struct clock_config *cfg)
390{
391 struct gate_cfg *gate_cfg = cfg->cfg;
392
393 return clk_hw_register_gate(dev,
394 cfg->name,
395 cfg->parent_name,
396 cfg->flags,
397 gate_cfg->reg_off + base,
398 gate_cfg->bit_idx,
399 gate_cfg->gate_flags,
400 lock);
401}
402
403static struct clk_hw *
404_clk_hw_register_fixed_factor(struct device *dev,
405 struct clk_hw_onecell_data *clk_data,
406 void __iomem *base, spinlock_t *lock,
407 const struct clock_config *cfg)
408{
409 struct fixed_factor_cfg *ff_cfg = cfg->cfg;
410
411 return clk_hw_register_fixed_factor(dev, cfg->name, cfg->parent_name,
412 cfg->flags, ff_cfg->mult,
413 ff_cfg->div);
414}
415
416static struct clk_hw *
417_clk_hw_register_divider_table(struct device *dev,
418 struct clk_hw_onecell_data *clk_data,
419 void __iomem *base, spinlock_t *lock,
420 const struct clock_config *cfg)
421{
422 struct div_cfg *div_cfg = cfg->cfg;
423
424 return clk_hw_register_divider_table(dev,
425 cfg->name,
426 cfg->parent_name,
427 cfg->flags,
428 div_cfg->reg_off + base,
429 div_cfg->shift,
430 div_cfg->width,
431 div_cfg->div_flags,
432 div_cfg->table,
433 lock);
434}
435
436static struct clk_hw *
437_clk_hw_register_mux(struct device *dev,
438 struct clk_hw_onecell_data *clk_data,
439 void __iomem *base, spinlock_t *lock,
440 const struct clock_config *cfg)
441{
442 struct mux_cfg *mux_cfg = cfg->cfg;
443
444 return clk_hw_register_mux(dev, cfg->name, cfg->parent_names,
445 cfg->num_parents, cfg->flags,
446 mux_cfg->reg_off + base, mux_cfg->shift,
447 mux_cfg->width, mux_cfg->mux_flags, lock);
448}
449
450/* MP1 Gate clock with set & clear registers */
451
452static int mp1_gate_clk_enable(struct clk_hw *hw)
453{
454 if (!clk_gate_ops.is_enabled(hw))
455 clk_gate_ops.enable(hw);
456
457 return 0;
458}
459
460static void mp1_gate_clk_disable(struct clk_hw *hw)
461{
462 struct clk_gate *gate = to_clk_gate(hw);
463 unsigned long flags = 0;
464
465 if (clk_gate_ops.is_enabled(hw)) {
466 spin_lock_irqsave(gate->lock, flags);
467 writel_relaxed(BIT(gate->bit_idx), gate->reg + RCC_CLR);
468 spin_unlock_irqrestore(gate->lock, flags);
469 }
470}
471
472const struct clk_ops mp1_gate_clk_ops = {
473 .enable = mp1_gate_clk_enable,
474 .disable = mp1_gate_clk_disable,
475 .is_enabled = clk_gate_is_enabled,
476};
477
478static struct clk_hw *_get_stm32_mux(void __iomem *base,
479 const struct stm32_mux_cfg *cfg,
480 spinlock_t *lock)
481{
482 struct stm32_clk_mmux *mmux;
483 struct clk_mux *mux;
484 struct clk_hw *mux_hw;
485
486 if (cfg->mmux) {
487 mmux = kzalloc(sizeof(*mmux), GFP_KERNEL);
488 if (!mmux)
489 return ERR_PTR(-ENOMEM);
490
491 mmux->mux.reg = cfg->mux->reg_off + base;
492 mmux->mux.shift = cfg->mux->shift;
493 mmux->mux.mask = (1 << cfg->mux->width) - 1;
494 mmux->mux.flags = cfg->mux->mux_flags;
495 mmux->mux.table = cfg->mux->table;
496 mmux->mux.lock = lock;
497 mmux->mmux = cfg->mmux;
498 mux_hw = &mmux->mux.hw;
499 cfg->mmux->hws[cfg->mmux->nbr_clk++] = mux_hw;
500
501 } else {
502 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
503 if (!mux)
504 return ERR_PTR(-ENOMEM);
505
506 mux->reg = cfg->mux->reg_off + base;
507 mux->shift = cfg->mux->shift;
508 mux->mask = (1 << cfg->mux->width) - 1;
509 mux->flags = cfg->mux->mux_flags;
510 mux->table = cfg->mux->table;
511 mux->lock = lock;
512 mux_hw = &mux->hw;
513 }
514
515 return mux_hw;
516}
517
518static struct clk_hw *_get_stm32_div(void __iomem *base,
519 const struct stm32_div_cfg *cfg,
520 spinlock_t *lock)
521{
522 struct clk_divider *div;
523
524 div = kzalloc(sizeof(*div), GFP_KERNEL);
525
526 if (!div)
527 return ERR_PTR(-ENOMEM);
528
529 div->reg = cfg->div->reg_off + base;
530 div->shift = cfg->div->shift;
531 div->width = cfg->div->width;
532 div->flags = cfg->div->div_flags;
533 div->table = cfg->div->table;
534 div->lock = lock;
535
536 return &div->hw;
537}
538
539static struct clk_hw *
540_get_stm32_gate(void __iomem *base,
541 const struct stm32_gate_cfg *cfg, spinlock_t *lock)
542{
543 struct stm32_clk_mgate *mgate;
544 struct clk_gate *gate;
545 struct clk_hw *gate_hw;
546
547 if (cfg->mgate) {
548 mgate = kzalloc(sizeof(*mgate), GFP_KERNEL);
549 if (!mgate)
550 return ERR_PTR(-ENOMEM);
551
552 mgate->gate.reg = cfg->gate->reg_off + base;
553 mgate->gate.bit_idx = cfg->gate->bit_idx;
554 mgate->gate.flags = cfg->gate->gate_flags;
555 mgate->gate.lock = lock;
556 mgate->mask = BIT(cfg->mgate->nbr_clk++);
557
558 mgate->mgate = cfg->mgate;
559
560 gate_hw = &mgate->gate.hw;
561
562 } else {
563 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
564 if (!gate)
565 return ERR_PTR(-ENOMEM);
566
567 gate->reg = cfg->gate->reg_off + base;
568 gate->bit_idx = cfg->gate->bit_idx;
569 gate->flags = cfg->gate->gate_flags;
570 gate->lock = lock;
571
572 gate_hw = &gate->hw;
573 }
574
575 return gate_hw;
576}
577
578static struct clk_hw *
579clk_stm32_register_gate_ops(struct device *dev,
580 const char *name,
581 const char *parent_name,
582 unsigned long flags,
583 void __iomem *base,
584 const struct stm32_gate_cfg *cfg,
585 spinlock_t *lock)
586{
587 struct clk_init_data init = { NULL };
588 struct clk_gate *gate;
589 struct clk_hw *hw;
590 int ret;
591
592 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
593 if (!gate)
594 return ERR_PTR(-ENOMEM);
595
596 init.name = name;
597 init.parent_names = &parent_name;
598 init.num_parents = 1;
599 init.flags = flags;
600
601 init.ops = &clk_gate_ops;
602
603 if (cfg->ops)
604 init.ops = cfg->ops;
605
606 hw = _get_stm32_gate(base, cfg, lock);
607 if (IS_ERR(hw))
608 return ERR_PTR(-ENOMEM);
609
610 hw->init = &init;
611
612 ret = clk_hw_register(dev, hw);
613 if (ret) {
614 kfree(gate);
615 hw = ERR_PTR(ret);
616 }
617
618 return hw;
619}
620
621static struct clk_hw *
622clk_stm32_register_composite(struct device *dev,
623 const char *name, const char * const *parent_names,
624 int num_parents, void __iomem *base,
625 const struct stm32_composite_cfg *cfg,
626 unsigned long flags, spinlock_t *lock)
627{
628 const struct clk_ops *mux_ops, *div_ops, *gate_ops;
629 struct clk_hw *mux_hw, *div_hw, *gate_hw;
630
631 mux_hw = NULL;
632 div_hw = NULL;
633 gate_hw = NULL;
634 mux_ops = NULL;
635 div_ops = NULL;
636 gate_ops = NULL;
637
638 if (cfg->mux) {
639 mux_hw = _get_stm32_mux(base, cfg->mux, lock);
640
641 if (!IS_ERR(mux_hw)) {
642 mux_ops = &clk_mux_ops;
643
644 if (cfg->mux->ops)
645 mux_ops = cfg->mux->ops;
646 }
647 }
648
649 if (cfg->div) {
650 div_hw = _get_stm32_div(base, cfg->div, lock);
651
652 if (!IS_ERR(div_hw)) {
653 div_ops = &clk_divider_ops;
654
655 if (cfg->div->ops)
656 div_ops = cfg->div->ops;
657 }
658 }
659
660 if (cfg->gate) {
661 gate_hw = _get_stm32_gate(base, cfg->gate, lock);
662
663 if (!IS_ERR(gate_hw)) {
664 gate_ops = &clk_gate_ops;
665
666 if (cfg->gate->ops)
667 gate_ops = cfg->gate->ops;
668 }
669 }
670
671 return clk_hw_register_composite(dev, name, parent_names, num_parents,
672 mux_hw, mux_ops, div_hw, div_ops,
673 gate_hw, gate_ops, flags);
674}
675
676#define to_clk_mgate(_gate) container_of(_gate, struct stm32_clk_mgate, gate)
677
678static int mp1_mgate_clk_enable(struct clk_hw *hw)
679{
680 struct clk_gate *gate = to_clk_gate(hw);
681 struct stm32_clk_mgate *clk_mgate = to_clk_mgate(gate);
682
683 clk_mgate->mgate->flag |= clk_mgate->mask;
684
685 mp1_gate_clk_enable(hw);
686
687 return 0;
688}
689
690static void mp1_mgate_clk_disable(struct clk_hw *hw)
691{
692 struct clk_gate *gate = to_clk_gate(hw);
693 struct stm32_clk_mgate *clk_mgate = to_clk_mgate(gate);
694
695 clk_mgate->mgate->flag &= ~clk_mgate->mask;
696
697 if (clk_mgate->mgate->flag == 0)
698 mp1_gate_clk_disable(hw);
699}
700
701const struct clk_ops mp1_mgate_clk_ops = {
702 .enable = mp1_mgate_clk_enable,
703 .disable = mp1_mgate_clk_disable,
704 .is_enabled = clk_gate_is_enabled,
705
706};
707
708#define to_clk_mmux(_mux) container_of(_mux, struct stm32_clk_mmux, mux)
709
710static u8 clk_mmux_get_parent(struct clk_hw *hw)
711{
712 return clk_mux_ops.get_parent(hw);
713}
714
715static int clk_mmux_set_parent(struct clk_hw *hw, u8 index)
716{
717 struct clk_mux *mux = to_clk_mux(hw);
718 struct stm32_clk_mmux *clk_mmux = to_clk_mmux(mux);
719 struct clk_hw *hwp;
720 int ret, n;
721
722 ret = clk_mux_ops.set_parent(hw, index);
723 if (ret)
724 return ret;
725
726 hwp = clk_hw_get_parent(hw);
727
728 for (n = 0; n < clk_mmux->mmux->nbr_clk; n++)
729 if (clk_mmux->mmux->hws[n] != hw)
730 clk_hw_reparent(clk_mmux->mmux->hws[n], hwp);
731
732 return 0;
733}
734
735const struct clk_ops clk_mmux_ops = {
736 .get_parent = clk_mmux_get_parent,
737 .set_parent = clk_mmux_set_parent,
738 .determine_rate = __clk_mux_determine_rate,
739};
740
741/* STM32 PLL */
742struct stm32_pll_obj {
743 /* lock pll enable/disable registers */
744 spinlock_t *lock;
745 void __iomem *reg;
746 struct clk_hw hw;
747};
748
749#define to_pll(_hw) container_of(_hw, struct stm32_pll_obj, hw)
750
751#define PLL_ON BIT(0)
752#define PLL_RDY BIT(1)
753#define DIVN_MASK 0x1FF
754#define DIVM_MASK 0x3F
755#define DIVM_SHIFT 16
756#define DIVN_SHIFT 0
757#define FRAC_OFFSET 0xC
758#define FRAC_MASK 0x1FFF
759#define FRAC_SHIFT 3
760#define FRACLE BIT(16)
761
762static int __pll_is_enabled(struct clk_hw *hw)
763{
764 struct stm32_pll_obj *clk_elem = to_pll(hw);
765
766 return readl_relaxed(clk_elem->reg) & PLL_ON;
767}
768
769#define TIMEOUT 5
770
771static int pll_enable(struct clk_hw *hw)
772{
773 struct stm32_pll_obj *clk_elem = to_pll(hw);
774 u32 reg;
775 unsigned long flags = 0;
776 unsigned int timeout = TIMEOUT;
777 int bit_status = 0;
778
779 spin_lock_irqsave(clk_elem->lock, flags);
780
781 if (__pll_is_enabled(hw))
782 goto unlock;
783
784 reg = readl_relaxed(clk_elem->reg);
785 reg |= PLL_ON;
786 writel_relaxed(reg, clk_elem->reg);
787
788 /* We can't use readl_poll_timeout() because we can be blocked if
789 * someone enables this clock before clocksource changes.
790 * Only jiffies counter is available. Jiffies are incremented by
791 * interruptions and enable op does not allow to be interrupted.
792 */
793 do {
794 bit_status = !(readl_relaxed(clk_elem->reg) & PLL_RDY);
795
796 if (bit_status)
797 udelay(120);
798
799 } while (bit_status && --timeout);
800
801unlock:
802 spin_unlock_irqrestore(clk_elem->lock, flags);
803
804 return bit_status;
805}
806
807static void pll_disable(struct clk_hw *hw)
808{
809 struct stm32_pll_obj *clk_elem = to_pll(hw);
810 u32 reg;
811 unsigned long flags = 0;
812
813 spin_lock_irqsave(clk_elem->lock, flags);
814
815 reg = readl_relaxed(clk_elem->reg);
816 reg &= ~PLL_ON;
817 writel_relaxed(reg, clk_elem->reg);
818
819 spin_unlock_irqrestore(clk_elem->lock, flags);
820}
821
822static u32 pll_frac_val(struct clk_hw *hw)
823{
824 struct stm32_pll_obj *clk_elem = to_pll(hw);
825 u32 reg, frac = 0;
826
827 reg = readl_relaxed(clk_elem->reg + FRAC_OFFSET);
828 if (reg & FRACLE)
829 frac = (reg >> FRAC_SHIFT) & FRAC_MASK;
830
831 return frac;
832}
833
834static unsigned long pll_recalc_rate(struct clk_hw *hw,
835 unsigned long parent_rate)
836{
837 struct stm32_pll_obj *clk_elem = to_pll(hw);
838 u32 reg;
839 u32 frac, divm, divn;
840 u64 rate, rate_frac = 0;
841
842 reg = readl_relaxed(clk_elem->reg + 4);
843
844 divm = ((reg >> DIVM_SHIFT) & DIVM_MASK) + 1;
845 divn = ((reg >> DIVN_SHIFT) & DIVN_MASK) + 1;
846 rate = (u64)parent_rate * divn;
847
848 do_div(rate, divm);
849
850 frac = pll_frac_val(hw);
851 if (frac) {
852 rate_frac = (u64)parent_rate * (u64)frac;
853 do_div(rate_frac, (divm * 8192));
854 }
855
856 return rate + rate_frac;
857}
858
859static int pll_is_enabled(struct clk_hw *hw)
860{
861 struct stm32_pll_obj *clk_elem = to_pll(hw);
862 unsigned long flags = 0;
863 int ret;
864
865 spin_lock_irqsave(clk_elem->lock, flags);
866 ret = __pll_is_enabled(hw);
867 spin_unlock_irqrestore(clk_elem->lock, flags);
868
869 return ret;
870}
871
872static const struct clk_ops pll_ops = {
873 .enable = pll_enable,
874 .disable = pll_disable,
875 .recalc_rate = pll_recalc_rate,
876 .is_enabled = pll_is_enabled,
877};
878
879static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
880 const char *parent_name,
881 void __iomem *reg,
882 unsigned long flags,
883 spinlock_t *lock)
884{
885 struct stm32_pll_obj *element;
886 struct clk_init_data init;
887 struct clk_hw *hw;
888 int err;
889
890 element = kzalloc(sizeof(*element), GFP_KERNEL);
891 if (!element)
892 return ERR_PTR(-ENOMEM);
893
894 init.name = name;
895 init.ops = &pll_ops;
896 init.flags = flags;
897 init.parent_names = &parent_name;
898 init.num_parents = 1;
899
900 element->hw.init = &init;
901 element->reg = reg;
902 element->lock = lock;
903
904 hw = &element->hw;
905 err = clk_hw_register(dev, hw);
906
907 if (err) {
908 kfree(element);
909 return ERR_PTR(err);
910 }
911
912 return hw;
913}
914
915/* Kernel Timer */
916struct timer_cker {
917 /* lock the kernel output divider register */
918 spinlock_t *lock;
919 void __iomem *apbdiv;
920 void __iomem *timpre;
921 struct clk_hw hw;
922};
923
924#define to_timer_cker(_hw) container_of(_hw, struct timer_cker, hw)
925
926#define APB_DIV_MASK 0x07
927#define TIM_PRE_MASK 0x01
928
929static unsigned long __bestmult(struct clk_hw *hw, unsigned long rate,
930 unsigned long parent_rate)
931{
932 struct timer_cker *tim_ker = to_timer_cker(hw);
933 u32 prescaler;
934 unsigned int mult = 0;
935
936 prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK;
937 if (prescaler < 2)
938 return 1;
939
940 mult = 2;
941
942 if (rate / parent_rate >= 4)
943 mult = 4;
944
945 return mult;
946}
947
948static long timer_ker_round_rate(struct clk_hw *hw, unsigned long rate,
949 unsigned long *parent_rate)
950{
951 unsigned long factor = __bestmult(hw, rate, *parent_rate);
952
953 return *parent_rate * factor;
954}
955
956static int timer_ker_set_rate(struct clk_hw *hw, unsigned long rate,
957 unsigned long parent_rate)
958{
959 struct timer_cker *tim_ker = to_timer_cker(hw);
960 unsigned long flags = 0;
961 unsigned long factor = __bestmult(hw, rate, parent_rate);
962 int ret = 0;
963
964 spin_lock_irqsave(tim_ker->lock, flags);
965
966 switch (factor) {
967 case 1:
968 break;
969 case 2:
970 writel_relaxed(0, tim_ker->timpre);
971 break;
972 case 4:
973 writel_relaxed(1, tim_ker->timpre);
974 break;
975 default:
976 ret = -EINVAL;
977 }
978 spin_unlock_irqrestore(tim_ker->lock, flags);
979
980 return ret;
981}
982
983static unsigned long timer_ker_recalc_rate(struct clk_hw *hw,
984 unsigned long parent_rate)
985{
986 struct timer_cker *tim_ker = to_timer_cker(hw);
987 u32 prescaler, timpre;
988 u32 mul;
989
990 prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK;
991
992 timpre = readl_relaxed(tim_ker->timpre) & TIM_PRE_MASK;
993
994 if (!prescaler)
995 return parent_rate;
996
997 mul = (timpre + 1) * 2;
998
999 return parent_rate * mul;
1000}
1001
1002static const struct clk_ops timer_ker_ops = {
1003 .recalc_rate = timer_ker_recalc_rate,
1004 .round_rate = timer_ker_round_rate,
1005 .set_rate = timer_ker_set_rate,
1006
1007};
1008
1009static struct clk_hw *clk_register_cktim(struct device *dev, const char *name,
1010 const char *parent_name,
1011 unsigned long flags,
1012 void __iomem *apbdiv,
1013 void __iomem *timpre,
1014 spinlock_t *lock)
1015{
1016 struct timer_cker *tim_ker;
1017 struct clk_init_data init;
1018 struct clk_hw *hw;
1019 int err;
1020
1021 tim_ker = kzalloc(sizeof(*tim_ker), GFP_KERNEL);
1022 if (!tim_ker)
1023 return ERR_PTR(-ENOMEM);
1024
1025 init.name = name;
1026 init.ops = &timer_ker_ops;
1027 init.flags = flags;
1028 init.parent_names = &parent_name;
1029 init.num_parents = 1;
1030
1031 tim_ker->hw.init = &init;
1032 tim_ker->lock = lock;
1033 tim_ker->apbdiv = apbdiv;
1034 tim_ker->timpre = timpre;
1035
1036 hw = &tim_ker->hw;
1037 err = clk_hw_register(dev, hw);
1038
1039 if (err) {
1040 kfree(tim_ker);
1041 return ERR_PTR(err);
1042 }
1043
1044 return hw;
1045}
1046
1047struct stm32_pll_cfg {
1048 u32 offset;
1049};
1050
1051struct clk_hw *_clk_register_pll(struct device *dev,
1052 struct clk_hw_onecell_data *clk_data,
1053 void __iomem *base, spinlock_t *lock,
1054 const struct clock_config *cfg)
1055{
1056 struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
1057
1058 return clk_register_pll(dev, cfg->name, cfg->parent_name,
1059 base + stm_pll_cfg->offset, cfg->flags, lock);
1060}
1061
1062struct stm32_cktim_cfg {
1063 u32 offset_apbdiv;
1064 u32 offset_timpre;
1065};
1066
1067static struct clk_hw *_clk_register_cktim(struct device *dev,
1068 struct clk_hw_onecell_data *clk_data,
1069 void __iomem *base, spinlock_t *lock,
1070 const struct clock_config *cfg)
1071{
1072 struct stm32_cktim_cfg *cktim_cfg = cfg->cfg;
1073
1074 return clk_register_cktim(dev, cfg->name, cfg->parent_name, cfg->flags,
1075 cktim_cfg->offset_apbdiv + base,
1076 cktim_cfg->offset_timpre + base, lock);
1077}
1078
1079static struct clk_hw *
1080_clk_stm32_register_gate(struct device *dev,
1081 struct clk_hw_onecell_data *clk_data,
1082 void __iomem *base, spinlock_t *lock,
1083 const struct clock_config *cfg)
1084{
1085 return clk_stm32_register_gate_ops(dev,
1086 cfg->name,
1087 cfg->parent_name,
1088 cfg->flags,
1089 base,
1090 cfg->cfg,
1091 lock);
1092}
1093
1094static struct clk_hw *
1095_clk_stm32_register_composite(struct device *dev,
1096 struct clk_hw_onecell_data *clk_data,
1097 void __iomem *base, spinlock_t *lock,
1098 const struct clock_config *cfg)
1099{
1100 return clk_stm32_register_composite(dev, cfg->name, cfg->parent_names,
1101 cfg->num_parents, base, cfg->cfg,
1102 cfg->flags, lock);
1103}
1104
1105#define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\
1106{\
1107 .id = _id,\
1108 .name = _name,\
1109 .parent_name = _parent,\
1110 .flags = _flags,\
1111 .cfg = &(struct gate_cfg) {\
1112 .reg_off = _offset,\
1113 .bit_idx = _bit_idx,\
1114 .gate_flags = _gate_flags,\
1115 },\
1116 .func = _clk_hw_register_gate,\
1117}
1118
1119#define FIXED_FACTOR(_id, _name, _parent, _flags, _mult, _div)\
1120{\
1121 .id = _id,\
1122 .name = _name,\
1123 .parent_name = _parent,\
1124 .flags = _flags,\
1125 .cfg = &(struct fixed_factor_cfg) {\
1126 .mult = _mult,\
1127 .div = _div,\
1128 },\
1129 .func = _clk_hw_register_fixed_factor,\
1130}
1131
1132#define DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
1133 _div_flags, _div_table)\
1134{\
1135 .id = _id,\
1136 .name = _name,\
1137 .parent_name = _parent,\
1138 .flags = _flags,\
1139 .cfg = &(struct div_cfg) {\
1140 .reg_off = _offset,\
1141 .shift = _shift,\
1142 .width = _width,\
1143 .div_flags = _div_flags,\
1144 .table = _div_table,\
1145 },\
1146 .func = _clk_hw_register_divider_table,\
1147}
1148
1149#define DIV(_id, _name, _parent, _flags, _offset, _shift, _width, _div_flags)\
1150 DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
1151 _div_flags, NULL)
1152
1153#define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\
1154{\
1155 .id = _id,\
1156 .name = _name,\
1157 .parent_names = _parents,\
1158 .num_parents = ARRAY_SIZE(_parents),\
1159 .flags = _flags,\
1160 .cfg = &(struct mux_cfg) {\
1161 .reg_off = _offset,\
1162 .shift = _shift,\
1163 .width = _width,\
1164 .mux_flags = _mux_flags,\
1165 },\
1166 .func = _clk_hw_register_mux,\
1167}
1168
1169#define PLL(_id, _name, _parent, _flags, _offset)\
1170{\
1171 .id = _id,\
1172 .name = _name,\
1173 .parent_name = _parent,\
1174 .flags = _flags,\
1175 .cfg = &(struct stm32_pll_cfg) {\
1176 .offset = _offset,\
1177 },\
1178 .func = _clk_register_pll,\
1179}
1180
1181#define STM32_CKTIM(_name, _parent, _flags, _offset_apbdiv, _offset_timpre)\
1182{\
1183 .id = NO_ID,\
1184 .name = _name,\
1185 .parent_name = _parent,\
1186 .flags = _flags,\
1187 .cfg = &(struct stm32_cktim_cfg) {\
1188 .offset_apbdiv = _offset_apbdiv,\
1189 .offset_timpre = _offset_timpre,\
1190 },\
1191 .func = _clk_register_cktim,\
1192}
1193
1194#define STM32_TIM(_id, _name, _parent, _offset_set, _bit_idx)\
1195 GATE_MP1(_id, _name, _parent, CLK_SET_RATE_PARENT,\
1196 _offset_set, _bit_idx, 0)
1197
1198/* STM32 GATE */
1199#define STM32_GATE(_id, _name, _parent, _flags, _gate)\
1200{\
1201 .id = _id,\
1202 .name = _name,\
1203 .parent_name = _parent,\
1204 .flags = _flags,\
1205 .cfg = (struct stm32_gate_cfg *) {_gate},\
1206 .func = _clk_stm32_register_gate,\
1207}
1208
1209#define _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags, _mgate, _ops)\
1210 (&(struct stm32_gate_cfg) {\
1211 &(struct gate_cfg) {\
1212 .reg_off = _gate_offset,\
1213 .bit_idx = _gate_bit_idx,\
1214 .gate_flags = _gate_flags,\
1215 },\
1216 .mgate = _mgate,\
1217 .ops = _ops,\
1218 })
1219
1220#define _STM32_MGATE(_mgate)\
1221 (&per_gate_cfg[_mgate])
1222
1223#define _GATE(_gate_offset, _gate_bit_idx, _gate_flags)\
1224 _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags,\
1225 NULL, NULL)\
1226
1227#define _GATE_MP1(_gate_offset, _gate_bit_idx, _gate_flags)\
1228 _STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags,\
1229 NULL, &mp1_gate_clk_ops)\
1230
1231#define _MGATE_MP1(_mgate)\
1232 .gate = &per_gate_cfg[_mgate]
1233
1234#define GATE_MP1(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\
1235 STM32_GATE(_id, _name, _parent, _flags,\
1236 _GATE_MP1(_offset, _bit_idx, _gate_flags))
1237
1238#define MGATE_MP1(_id, _name, _parent, _flags, _mgate)\
1239 STM32_GATE(_id, _name, _parent, _flags,\
1240 _STM32_MGATE(_mgate))
1241
1242#define _STM32_DIV(_div_offset, _div_shift, _div_width,\
1243 _div_flags, _div_table, _ops)\
1244 .div = &(struct stm32_div_cfg) {\
1245 &(struct div_cfg) {\
1246 .reg_off = _div_offset,\
1247 .shift = _div_shift,\
1248 .width = _div_width,\
1249 .div_flags = _div_flags,\
1250 .table = _div_table,\
1251 },\
1252 .ops = _ops,\
1253 }
1254
1255#define _DIV(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\
1256 _STM32_DIV(_div_offset, _div_shift, _div_width,\
1257 _div_flags, _div_table, NULL)\
1258
1259#define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\
1260 .mux = &(struct stm32_mux_cfg) {\
1261 &(struct mux_cfg) {\
1262 .reg_off = _offset,\
1263 .shift = _shift,\
1264 .width = _width,\
1265 .mux_flags = _mux_flags,\
1266 .table = NULL,\
1267 },\
1268 .mmux = _mmux,\
1269 .ops = _ops,\
1270 }
1271
1272#define _MUX(_offset, _shift, _width, _mux_flags)\
1273 _STM32_MUX(_offset, _shift, _width, _mux_flags, NULL, NULL)\
1274
1275#define _MMUX(_mmux) .mux = &ker_mux_cfg[_mmux]
1276
1277#define PARENT(_parent) ((const char *[]) { _parent})
1278
1279#define _NO_MUX .mux = NULL
1280#define _NO_DIV .div = NULL
1281#define _NO_GATE .gate = NULL
1282
1283#define COMPOSITE(_id, _name, _parents, _flags, _gate, _mux, _div)\
1284{\
1285 .id = _id,\
1286 .name = _name,\
1287 .parent_names = _parents,\
1288 .num_parents = ARRAY_SIZE(_parents),\
1289 .flags = _flags,\
1290 .cfg = &(struct stm32_composite_cfg) {\
1291 _gate,\
1292 _mux,\
1293 _div,\
1294 },\
1295 .func = _clk_stm32_register_composite,\
1296}
1297
1298#define PCLK(_id, _name, _parent, _flags, _mgate)\
1299 MGATE_MP1(_id, _name, _parent, _flags, _mgate)
1300
1301#define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\
1302 COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE | _flags,\
1303 _MGATE_MP1(_mgate),\
1304 _MMUX(_mmux),\
1305 _NO_DIV)
1306
1307enum {
1308 G_SAI1,
1309 G_SAI2,
1310 G_SAI3,
1311 G_SAI4,
1312 G_SPI1,
1313 G_SPI2,
1314 G_SPI3,
1315 G_SPI4,
1316 G_SPI5,
1317 G_SPI6,
1318 G_SPDIF,
1319 G_I2C1,
1320 G_I2C2,
1321 G_I2C3,
1322 G_I2C4,
1323 G_I2C5,
1324 G_I2C6,
1325 G_USART2,
1326 G_UART4,
1327 G_USART3,
1328 G_UART5,
1329 G_USART1,
1330 G_USART6,
1331 G_UART7,
1332 G_UART8,
1333 G_LPTIM1,
1334 G_LPTIM2,
1335 G_LPTIM3,
1336 G_LPTIM4,
1337 G_LPTIM5,
1338 G_LTDC,
1339 G_DSI,
1340 G_QSPI,
1341 G_FMC,
1342 G_SDMMC1,
1343 G_SDMMC2,
1344 G_SDMMC3,
1345 G_USBO,
1346 G_USBPHY,
1347 G_RNG1,
1348 G_RNG2,
1349 G_FDCAN,
1350 G_DAC12,
1351 G_CEC,
1352 G_ADC12,
1353 G_GPU,
1354 G_STGEN,
1355 G_DFSDM,
1356 G_ADFSDM,
1357 G_TIM2,
1358 G_TIM3,
1359 G_TIM4,
1360 G_TIM5,
1361 G_TIM6,
1362 G_TIM7,
1363 G_TIM12,
1364 G_TIM13,
1365 G_TIM14,
1366 G_MDIO,
1367 G_TIM1,
1368 G_TIM8,
1369 G_TIM15,
1370 G_TIM16,
1371 G_TIM17,
1372 G_SYSCFG,
1373 G_VREF,
1374 G_TMPSENS,
1375 G_PMBCTRL,
1376 G_HDP,
1377 G_IWDG2,
1378 G_STGENRO,
1379 G_DMA1,
1380 G_DMA2,
1381 G_DMAMUX,
1382 G_DCMI,
1383 G_CRYP2,
1384 G_HASH2,
1385 G_CRC2,
1386 G_HSEM,
1387 G_IPCC,
1388 G_GPIOA,
1389 G_GPIOB,
1390 G_GPIOC,
1391 G_GPIOD,
1392 G_GPIOE,
1393 G_GPIOF,
1394 G_GPIOG,
1395 G_GPIOH,
1396 G_GPIOI,
1397 G_GPIOJ,
1398 G_GPIOK,
1399 G_MDMA,
1400 G_ETHCK,
1401 G_ETHTX,
1402 G_ETHRX,
1403 G_ETHMAC,
1404 G_CRC1,
1405 G_USBH,
1406 G_ETHSTP,
1407 G_RTCAPB,
1408 G_TZC,
1409 G_TZPC,
1410 G_IWDG1,
1411 G_BSEC,
1412 G_GPIOZ,
1413 G_CRYP1,
1414 G_HASH1,
1415 G_BKPSRAM,
1416
1417 G_LAST
1418};
1419
1420struct stm32_mgate mp1_mgate[G_LAST];
1421
1422#define _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
1423 _mgate, _ops)\
1424 [_id] = {\
1425 &(struct gate_cfg) {\
1426 .reg_off = _gate_offset,\
1427 .bit_idx = _gate_bit_idx,\
1428 .gate_flags = _gate_flags,\
1429 },\
1430 .mgate = _mgate,\
1431 .ops = _ops,\
1432 }
1433
1434#define K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags)\
1435 _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
1436 NULL, &mp1_gate_clk_ops)
1437
1438#define K_MGATE(_id, _gate_offset, _gate_bit_idx, _gate_flags)\
1439 _K_GATE(_id, _gate_offset, _gate_bit_idx, _gate_flags,\
1440 &mp1_mgate[_id], &mp1_mgate_clk_ops)
1441
1442/* Peripheral gates */
1443struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
1444 /* Multi gates */
1445 K_GATE(G_MDIO, RCC_APB1ENSETR, 31, 0),
1446 K_MGATE(G_DAC12, RCC_APB1ENSETR, 29, 0),
1447 K_MGATE(G_CEC, RCC_APB1ENSETR, 27, 0),
1448 K_MGATE(G_SPDIF, RCC_APB1ENSETR, 26, 0),
1449 K_MGATE(G_I2C5, RCC_APB1ENSETR, 24, 0),
1450 K_MGATE(G_I2C3, RCC_APB1ENSETR, 23, 0),
1451 K_MGATE(G_I2C2, RCC_APB1ENSETR, 22, 0),
1452 K_MGATE(G_I2C1, RCC_APB1ENSETR, 21, 0),
1453 K_MGATE(G_UART8, RCC_APB1ENSETR, 19, 0),
1454 K_MGATE(G_UART7, RCC_APB1ENSETR, 18, 0),
1455 K_MGATE(G_UART5, RCC_APB1ENSETR, 17, 0),
1456 K_MGATE(G_UART4, RCC_APB1ENSETR, 16, 0),
1457 K_MGATE(G_USART3, RCC_APB1ENSETR, 15, 0),
1458 K_MGATE(G_USART2, RCC_APB1ENSETR, 14, 0),
1459 K_MGATE(G_SPI3, RCC_APB1ENSETR, 12, 0),
1460 K_MGATE(G_SPI2, RCC_APB1ENSETR, 11, 0),
1461 K_MGATE(G_LPTIM1, RCC_APB1ENSETR, 9, 0),
1462 K_GATE(G_TIM14, RCC_APB1ENSETR, 8, 0),
1463 K_GATE(G_TIM13, RCC_APB1ENSETR, 7, 0),
1464 K_GATE(G_TIM12, RCC_APB1ENSETR, 6, 0),
1465 K_GATE(G_TIM7, RCC_APB1ENSETR, 5, 0),
1466 K_GATE(G_TIM6, RCC_APB1ENSETR, 4, 0),
1467 K_GATE(G_TIM5, RCC_APB1ENSETR, 3, 0),
1468 K_GATE(G_TIM4, RCC_APB1ENSETR, 2, 0),
1469 K_GATE(G_TIM3, RCC_APB1ENSETR, 1, 0),
1470 K_GATE(G_TIM2, RCC_APB1ENSETR, 0, 0),
1471
1472 K_MGATE(G_FDCAN, RCC_APB2ENSETR, 24, 0),
1473 K_GATE(G_ADFSDM, RCC_APB2ENSETR, 21, 0),
1474 K_GATE(G_DFSDM, RCC_APB2ENSETR, 20, 0),
1475 K_MGATE(G_SAI3, RCC_APB2ENSETR, 18, 0),
1476 K_MGATE(G_SAI2, RCC_APB2ENSETR, 17, 0),
1477 K_MGATE(G_SAI1, RCC_APB2ENSETR, 16, 0),
1478 K_MGATE(G_USART6, RCC_APB2ENSETR, 13, 0),
1479 K_MGATE(G_SPI5, RCC_APB2ENSETR, 10, 0),
1480 K_MGATE(G_SPI4, RCC_APB2ENSETR, 9, 0),
1481 K_MGATE(G_SPI1, RCC_APB2ENSETR, 8, 0),
1482 K_GATE(G_TIM17, RCC_APB2ENSETR, 4, 0),
1483 K_GATE(G_TIM16, RCC_APB2ENSETR, 3, 0),
1484 K_GATE(G_TIM15, RCC_APB2ENSETR, 2, 0),
1485 K_GATE(G_TIM8, RCC_APB2ENSETR, 1, 0),
1486 K_GATE(G_TIM1, RCC_APB2ENSETR, 0, 0),
1487
1488 K_GATE(G_HDP, RCC_APB3ENSETR, 20, 0),
1489 K_GATE(G_PMBCTRL, RCC_APB3ENSETR, 17, 0),
1490 K_GATE(G_TMPSENS, RCC_APB3ENSETR, 16, 0),
1491 K_GATE(G_VREF, RCC_APB3ENSETR, 13, 0),
1492 K_GATE(G_SYSCFG, RCC_APB3ENSETR, 11, 0),
1493 K_MGATE(G_SAI4, RCC_APB3ENSETR, 8, 0),
1494 K_MGATE(G_LPTIM5, RCC_APB3ENSETR, 3, 0),
1495 K_MGATE(G_LPTIM4, RCC_APB3ENSETR, 2, 0),
1496 K_MGATE(G_LPTIM3, RCC_APB3ENSETR, 1, 0),
1497 K_MGATE(G_LPTIM2, RCC_APB3ENSETR, 0, 0),
1498
1499 K_GATE(G_STGENRO, RCC_APB4ENSETR, 20, 0),
1500 K_MGATE(G_USBPHY, RCC_APB4ENSETR, 16, 0),
1501 K_GATE(G_IWDG2, RCC_APB4ENSETR, 15, 0),
1502 K_MGATE(G_DSI, RCC_APB4ENSETR, 4, 0),
1503 K_MGATE(G_LTDC, RCC_APB4ENSETR, 0, 0),
1504
1505 K_GATE(G_STGEN, RCC_APB5ENSETR, 20, 0),
1506 K_GATE(G_BSEC, RCC_APB5ENSETR, 16, 0),
1507 K_GATE(G_IWDG1, RCC_APB5ENSETR, 15, 0),
1508 K_GATE(G_TZPC, RCC_APB5ENSETR, 13, 0),
1509 K_GATE(G_TZC, RCC_APB5ENSETR, 12, 0),
1510 K_GATE(G_RTCAPB, RCC_APB5ENSETR, 8, 0),
1511 K_MGATE(G_USART1, RCC_APB5ENSETR, 4, 0),
1512 K_MGATE(G_I2C6, RCC_APB5ENSETR, 3, 0),
1513 K_MGATE(G_I2C4, RCC_APB5ENSETR, 2, 0),
1514 K_MGATE(G_SPI6, RCC_APB5ENSETR, 0, 0),
1515
1516 K_MGATE(G_SDMMC3, RCC_AHB2ENSETR, 16, 0),
1517 K_MGATE(G_USBO, RCC_AHB2ENSETR, 8, 0),
1518 K_MGATE(G_ADC12, RCC_AHB2ENSETR, 5, 0),
1519 K_GATE(G_DMAMUX, RCC_AHB2ENSETR, 2, 0),
1520 K_GATE(G_DMA2, RCC_AHB2ENSETR, 1, 0),
1521 K_GATE(G_DMA1, RCC_AHB2ENSETR, 0, 0),
1522
1523 K_GATE(G_IPCC, RCC_AHB3ENSETR, 12, 0),
1524 K_GATE(G_HSEM, RCC_AHB3ENSETR, 11, 0),
1525 K_GATE(G_CRC2, RCC_AHB3ENSETR, 7, 0),
1526 K_MGATE(G_RNG2, RCC_AHB3ENSETR, 6, 0),
1527 K_GATE(G_HASH2, RCC_AHB3ENSETR, 5, 0),
1528 K_GATE(G_CRYP2, RCC_AHB3ENSETR, 4, 0),
1529 K_GATE(G_DCMI, RCC_AHB3ENSETR, 0, 0),
1530
1531 K_GATE(G_GPIOK, RCC_AHB4ENSETR, 10, 0),
1532 K_GATE(G_GPIOJ, RCC_AHB4ENSETR, 9, 0),
1533 K_GATE(G_GPIOI, RCC_AHB4ENSETR, 8, 0),
1534 K_GATE(G_GPIOH, RCC_AHB4ENSETR, 7, 0),
1535 K_GATE(G_GPIOG, RCC_AHB4ENSETR, 6, 0),
1536 K_GATE(G_GPIOF, RCC_AHB4ENSETR, 5, 0),
1537 K_GATE(G_GPIOE, RCC_AHB4ENSETR, 4, 0),
1538 K_GATE(G_GPIOD, RCC_AHB4ENSETR, 3, 0),
1539 K_GATE(G_GPIOC, RCC_AHB4ENSETR, 2, 0),
1540 K_GATE(G_GPIOB, RCC_AHB4ENSETR, 1, 0),
1541 K_GATE(G_GPIOA, RCC_AHB4ENSETR, 0, 0),
1542
1543 K_GATE(G_BKPSRAM, RCC_AHB5ENSETR, 8, 0),
1544 K_MGATE(G_RNG1, RCC_AHB5ENSETR, 6, 0),
1545 K_GATE(G_HASH1, RCC_AHB5ENSETR, 5, 0),
1546 K_GATE(G_CRYP1, RCC_AHB5ENSETR, 4, 0),
1547 K_GATE(G_GPIOZ, RCC_AHB5ENSETR, 0, 0),
1548
1549 K_GATE(G_USBH, RCC_AHB6ENSETR, 24, 0),
1550 K_GATE(G_CRC1, RCC_AHB6ENSETR, 20, 0),
1551 K_MGATE(G_SDMMC2, RCC_AHB6ENSETR, 17, 0),
1552 K_MGATE(G_SDMMC1, RCC_AHB6ENSETR, 16, 0),
1553 K_MGATE(G_QSPI, RCC_AHB6ENSETR, 14, 0),
1554 K_MGATE(G_FMC, RCC_AHB6ENSETR, 12, 0),
1555 K_GATE(G_ETHMAC, RCC_AHB6ENSETR, 10, 0),
1556 K_GATE(G_ETHRX, RCC_AHB6ENSETR, 9, 0),
1557 K_GATE(G_ETHTX, RCC_AHB6ENSETR, 8, 0),
1558 K_GATE(G_ETHCK, RCC_AHB6ENSETR, 7, 0),
1559 K_MGATE(G_GPU, RCC_AHB6ENSETR, 5, 0),
1560 K_GATE(G_MDMA, RCC_AHB6ENSETR, 0, 0),
1561 K_GATE(G_ETHSTP, RCC_AHB6LPENSETR, 11, 0),
1562};
1563
1564enum {
1565 M_SDMMC12,
1566 M_SDMMC3,
1567 M_FMC,
1568 M_QSPI,
1569 M_RNG1,
1570 M_RNG2,
1571 M_USBPHY,
1572 M_USBO,
1573 M_STGEN,
1574 M_SPDIF,
1575 M_SPI1,
1576 M_SPI23,
1577 M_SPI45,
1578 M_SPI6,
1579 M_CEC,
1580 M_I2C12,
1581 M_I2C35,
1582 M_I2C46,
1583 M_LPTIM1,
1584 M_LPTIM23,
1585 M_LPTIM45,
1586 M_USART1,
1587 M_UART24,
1588 M_UART35,
1589 M_USART6,
1590 M_UART78,
1591 M_SAI1,
1592 M_SAI2,
1593 M_SAI3,
1594 M_SAI4,
1595 M_DSI,
1596 M_FDCAN,
1597 M_ADC12,
1598 M_ETHCK,
1599 M_CKPER,
1600 M_LAST
1601};
1602
1603struct stm32_mmux ker_mux[M_LAST];
1604
1605#define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\
1606 [_id] = {\
1607 &(struct mux_cfg) {\
1608 .reg_off = _offset,\
1609 .shift = _shift,\
1610 .width = _width,\
1611 .mux_flags = _mux_flags,\
1612 .table = NULL,\
1613 },\
1614 .mmux = _mmux,\
1615 .ops = _ops,\
1616 }
1617
1618#define K_MUX(_id, _offset, _shift, _width, _mux_flags)\
1619 _K_MUX(_id, _offset, _shift, _width, _mux_flags,\
1620 NULL, NULL)
1621
1622#define K_MMUX(_id, _offset, _shift, _width, _mux_flags)\
1623 _K_MUX(_id, _offset, _shift, _width, _mux_flags,\
1624 &ker_mux[_id], &clk_mmux_ops)
1625
1626const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
1627 /* Kernel multi mux */
1628 K_MMUX(M_SDMMC12, RCC_SDMMC12CKSELR, 0, 3, 0),
1629 K_MMUX(M_SPI23, RCC_SPI2S23CKSELR, 0, 3, 0),
1630 K_MMUX(M_SPI45, RCC_SPI2S45CKSELR, 0, 3, 0),
1631 K_MMUX(M_I2C12, RCC_I2C12CKSELR, 0, 3, 0),
1632 K_MMUX(M_I2C35, RCC_I2C35CKSELR, 0, 3, 0),
1633 K_MMUX(M_LPTIM23, RCC_LPTIM23CKSELR, 0, 3, 0),
1634 K_MMUX(M_LPTIM45, RCC_LPTIM45CKSELR, 0, 3, 0),
1635 K_MMUX(M_UART24, RCC_UART24CKSELR, 0, 3, 0),
1636 K_MMUX(M_UART35, RCC_UART35CKSELR, 0, 3, 0),
1637 K_MMUX(M_UART78, RCC_UART78CKSELR, 0, 3, 0),
1638 K_MMUX(M_SAI1, RCC_SAI1CKSELR, 0, 3, 0),
1639 K_MMUX(M_ETHCK, RCC_ETHCKSELR, 0, 2, 0),
1640 K_MMUX(M_I2C46, RCC_I2C46CKSELR, 0, 3, 0),
1641
1642 /* Kernel simple mux */
1643 K_MUX(M_RNG2, RCC_RNG2CKSELR, 0, 2, 0),
1644 K_MUX(M_SDMMC3, RCC_SDMMC3CKSELR, 0, 3, 0),
1645 K_MUX(M_FMC, RCC_FMCCKSELR, 0, 2, 0),
1646 K_MUX(M_QSPI, RCC_QSPICKSELR, 0, 2, 0),
1647 K_MUX(M_USBPHY, RCC_USBCKSELR, 0, 2, 0),
1648 K_MUX(M_USBO, RCC_USBCKSELR, 4, 1, 0),
1649 K_MUX(M_SPDIF, RCC_SPDIFCKSELR, 0, 2, 0),
1650 K_MUX(M_SPI1, RCC_SPI2S1CKSELR, 0, 3, 0),
1651 K_MUX(M_CEC, RCC_CECCKSELR, 0, 2, 0),
1652 K_MUX(M_LPTIM1, RCC_LPTIM1CKSELR, 0, 3, 0),
1653 K_MUX(M_USART6, RCC_UART6CKSELR, 0, 3, 0),
1654 K_MUX(M_FDCAN, RCC_FDCANCKSELR, 0, 2, 0),
1655 K_MUX(M_SAI2, RCC_SAI2CKSELR, 0, 3, 0),
1656 K_MUX(M_SAI3, RCC_SAI3CKSELR, 0, 3, 0),
1657 K_MUX(M_SAI4, RCC_SAI4CKSELR, 0, 3, 0),
1658 K_MUX(M_ADC12, RCC_ADCCKSELR, 0, 2, 0),
1659 K_MUX(M_DSI, RCC_DSICKSELR, 0, 1, 0),
1660 K_MUX(M_CKPER, RCC_CPERCKSELR, 0, 2, 0),
1661 K_MUX(M_RNG1, RCC_RNG1CKSELR, 0, 2, 0),
1662 K_MUX(M_STGEN, RCC_STGENCKSELR, 0, 2, 0),
1663 K_MUX(M_USART1, RCC_UART1CKSELR, 0, 3, 0),
1664 K_MUX(M_SPI6, RCC_SPI6CKSELR, 0, 3, 0),
1665};
1666
1667static const struct clock_config stm32mp1_clock_cfg[] = {
1668 /* Oscillator divider */
1669 DIV(NO_ID, "clk-hsi-div", "clk-hsi", 0, RCC_HSICFGR, 0, 2,
1670 CLK_DIVIDER_READ_ONLY),
1671
1672 /* External / Internal Oscillators */
1673 GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
1674 GATE_MP1(CK_CSI, "ck_csi", "clk-csi", 0, RCC_OCENSETR, 4, 0),
1675 GATE_MP1(CK_HSI, "ck_hsi", "clk-hsi-div", 0, RCC_OCENSETR, 0, 0),
1676 GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
1677 GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
1678
1679 FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2),
1680
1681 /* ref clock pll */
1682 MUX(NO_ID, "ref1", ref12_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK12SELR,
1683 0, 2, CLK_MUX_READ_ONLY),
1684
1685 MUX(NO_ID, "ref3", ref3_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK3SELR,
1686 0, 2, CLK_MUX_READ_ONLY),
1687
1688 MUX(NO_ID, "ref4", ref4_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK4SELR,
1689 0, 2, CLK_MUX_READ_ONLY),
1690
1691 /* PLLs */
1692 PLL(PLL1, "pll1", "ref1", CLK_IGNORE_UNUSED, RCC_PLL1CR),
1693 PLL(PLL2, "pll2", "ref1", CLK_IGNORE_UNUSED, RCC_PLL2CR),
1694 PLL(PLL3, "pll3", "ref3", CLK_IGNORE_UNUSED, RCC_PLL3CR),
1695 PLL(PLL4, "pll4", "ref4", CLK_IGNORE_UNUSED, RCC_PLL4CR),
1696
1697 /* ODF */
1698 COMPOSITE(PLL1_P, "pll1_p", PARENT("pll1"), 0,
1699 _GATE(RCC_PLL1CR, 4, 0),
1700 _NO_MUX,
1701 _DIV(RCC_PLL1CFGR2, 0, 7, 0, NULL)),
1702
1703 COMPOSITE(PLL2_P, "pll2_p", PARENT("pll2"), 0,
1704 _GATE(RCC_PLL2CR, 4, 0),
1705 _NO_MUX,
1706 _DIV(RCC_PLL2CFGR2, 0, 7, 0, NULL)),
1707
1708 COMPOSITE(PLL2_Q, "pll2_q", PARENT("pll2"), 0,
1709 _GATE(RCC_PLL2CR, 5, 0),
1710 _NO_MUX,
1711 _DIV(RCC_PLL2CFGR2, 8, 7, 0, NULL)),
1712
1713 COMPOSITE(PLL2_R, "pll2_r", PARENT("pll2"), CLK_IS_CRITICAL,
1714 _GATE(RCC_PLL2CR, 6, 0),
1715 _NO_MUX,
1716 _DIV(RCC_PLL2CFGR2, 16, 7, 0, NULL)),
1717
1718 COMPOSITE(PLL3_P, "pll3_p", PARENT("pll3"), 0,
1719 _GATE(RCC_PLL3CR, 4, 0),
1720 _NO_MUX,
1721 _DIV(RCC_PLL3CFGR2, 0, 7, 0, NULL)),
1722
1723 COMPOSITE(PLL3_Q, "pll3_q", PARENT("pll3"), 0,
1724 _GATE(RCC_PLL3CR, 5, 0),
1725 _NO_MUX,
1726 _DIV(RCC_PLL3CFGR2, 8, 7, 0, NULL)),
1727
1728 COMPOSITE(PLL3_R, "pll3_r", PARENT("pll3"), 0,
1729 _GATE(RCC_PLL3CR, 6, 0),
1730 _NO_MUX,
1731 _DIV(RCC_PLL3CFGR2, 16, 7, 0, NULL)),
1732
1733 COMPOSITE(PLL4_P, "pll4_p", PARENT("pll4"), 0,
1734 _GATE(RCC_PLL4CR, 4, 0),
1735 _NO_MUX,
1736 _DIV(RCC_PLL4CFGR2, 0, 7, 0, NULL)),
1737
1738 COMPOSITE(PLL4_Q, "pll4_q", PARENT("pll4"), 0,
1739 _GATE(RCC_PLL4CR, 5, 0),
1740 _NO_MUX,
1741 _DIV(RCC_PLL4CFGR2, 8, 7, 0, NULL)),
1742
1743 COMPOSITE(PLL4_R, "pll4_r", PARENT("pll4"), 0,
1744 _GATE(RCC_PLL4CR, 6, 0),
1745 _NO_MUX,
1746 _DIV(RCC_PLL4CFGR2, 16, 7, 0, NULL)),
1747
1748 /* MUX system clocks */
1749 MUX(CK_PER, "ck_per", per_src, CLK_OPS_PARENT_ENABLE,
1750 RCC_CPERCKSELR, 0, 2, 0),
1751
1752 MUX(CK_MPU, "ck_mpu", cpu_src, CLK_OPS_PARENT_ENABLE |
1753 CLK_IS_CRITICAL, RCC_MPCKSELR, 0, 2, 0),
1754
1755 COMPOSITE(CK_AXI, "ck_axi", axi_src, CLK_IS_CRITICAL |
1756 CLK_OPS_PARENT_ENABLE,
1757 _NO_GATE,
1758 _MUX(RCC_ASSCKSELR, 0, 2, 0),
1759 _DIV(RCC_AXIDIVR, 0, 3, 0, axi_div_table)),
1760
1761 COMPOSITE(CK_MCU, "ck_mcu", mcu_src, CLK_IS_CRITICAL |
1762 CLK_OPS_PARENT_ENABLE,
1763 _NO_GATE,
1764 _MUX(RCC_MSSCKSELR, 0, 2, 0),
1765 _DIV(RCC_MCUDIVR, 0, 4, 0, mcu_div_table)),
1766
1767 DIV_TABLE(NO_ID, "pclk1", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB1DIVR, 0,
1768 3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1769
1770 DIV_TABLE(NO_ID, "pclk2", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB2DIVR, 0,
1771 3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1772
1773 DIV_TABLE(NO_ID, "pclk3", "ck_mcu", CLK_IGNORE_UNUSED, RCC_APB3DIVR, 0,
1774 3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1775
1776 DIV_TABLE(NO_ID, "pclk4", "ck_axi", CLK_IGNORE_UNUSED, RCC_APB4DIVR, 0,
1777 3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1778
1779 DIV_TABLE(NO_ID, "pclk5", "ck_axi", CLK_IGNORE_UNUSED, RCC_APB5DIVR, 0,
1780 3, CLK_DIVIDER_READ_ONLY, apb_div_table),
1781
1782 /* Kernel Timers */
1783 STM32_CKTIM("ck1_tim", "pclk1", 0, RCC_APB1DIVR, RCC_TIMG1PRER),
1784 STM32_CKTIM("ck2_tim", "pclk2", 0, RCC_APB2DIVR, RCC_TIMG2PRER),
1785
1786 STM32_TIM(TIM2_K, "tim2_k", "ck1_tim", RCC_APB1ENSETR, 0),
1787 STM32_TIM(TIM3_K, "tim3_k", "ck1_tim", RCC_APB1ENSETR, 1),
1788 STM32_TIM(TIM4_K, "tim4_k", "ck1_tim", RCC_APB1ENSETR, 2),
1789 STM32_TIM(TIM5_K, "tim5_k", "ck1_tim", RCC_APB1ENSETR, 3),
1790 STM32_TIM(TIM6_K, "tim6_k", "ck1_tim", RCC_APB1ENSETR, 4),
1791 STM32_TIM(TIM7_K, "tim7_k", "ck1_tim", RCC_APB1ENSETR, 5),
1792 STM32_TIM(TIM12_K, "tim12_k", "ck1_tim", RCC_APB1ENSETR, 6),
1793 STM32_TIM(TIM13_K, "tim13_k", "ck1_tim", RCC_APB1ENSETR, 7),
1794 STM32_TIM(TIM14_K, "tim14_k", "ck1_tim", RCC_APB1ENSETR, 8),
1795 STM32_TIM(TIM1_K, "tim1_k", "ck2_tim", RCC_APB2ENSETR, 0),
1796 STM32_TIM(TIM8_K, "tim8_k", "ck2_tim", RCC_APB2ENSETR, 1),
1797 STM32_TIM(TIM15_K, "tim15_k", "ck2_tim", RCC_APB2ENSETR, 2),
1798 STM32_TIM(TIM16_K, "tim16_k", "ck2_tim", RCC_APB2ENSETR, 3),
1799 STM32_TIM(TIM17_K, "tim17_k", "ck2_tim", RCC_APB2ENSETR, 4),
1800
1801 /* Peripheral clocks */
1802 PCLK(TIM2, "tim2", "pclk1", CLK_IGNORE_UNUSED, G_TIM2),
1803 PCLK(TIM3, "tim3", "pclk1", CLK_IGNORE_UNUSED, G_TIM3),
1804 PCLK(TIM4, "tim4", "pclk1", CLK_IGNORE_UNUSED, G_TIM4),
1805 PCLK(TIM5, "tim5", "pclk1", CLK_IGNORE_UNUSED, G_TIM5),
1806 PCLK(TIM6, "tim6", "pclk1", CLK_IGNORE_UNUSED, G_TIM6),
1807 PCLK(TIM7, "tim7", "pclk1", CLK_IGNORE_UNUSED, G_TIM7),
1808 PCLK(TIM12, "tim12", "pclk1", CLK_IGNORE_UNUSED, G_TIM12),
1809 PCLK(TIM13, "tim13", "pclk1", CLK_IGNORE_UNUSED, G_TIM13),
1810 PCLK(TIM14, "tim14", "pclk1", CLK_IGNORE_UNUSED, G_TIM14),
1811 PCLK(LPTIM1, "lptim1", "pclk1", 0, G_LPTIM1),
1812 PCLK(SPI2, "spi2", "pclk1", 0, G_SPI2),
1813 PCLK(SPI3, "spi3", "pclk1", 0, G_SPI3),
1814 PCLK(USART2, "usart2", "pclk1", 0, G_USART2),
1815 PCLK(USART3, "usart3", "pclk1", 0, G_USART3),
1816 PCLK(UART4, "uart4", "pclk1", 0, G_UART4),
1817 PCLK(UART5, "uart5", "pclk1", 0, G_UART5),
1818 PCLK(UART7, "uart7", "pclk1", 0, G_UART7),
1819 PCLK(UART8, "uart8", "pclk1", 0, G_UART8),
1820 PCLK(I2C1, "i2c1", "pclk1", 0, G_I2C1),
1821 PCLK(I2C2, "i2c2", "pclk1", 0, G_I2C2),
1822 PCLK(I2C3, "i2c3", "pclk1", 0, G_I2C3),
1823 PCLK(I2C5, "i2c5", "pclk1", 0, G_I2C5),
1824 PCLK(SPDIF, "spdif", "pclk1", 0, G_SPDIF),
1825 PCLK(CEC, "cec", "pclk1", 0, G_CEC),
1826 PCLK(DAC12, "dac12", "pclk1", 0, G_DAC12),
1827 PCLK(MDIO, "mdio", "pclk1", 0, G_MDIO),
1828 PCLK(TIM1, "tim1", "pclk2", CLK_IGNORE_UNUSED, G_TIM1),
1829 PCLK(TIM8, "tim8", "pclk2", CLK_IGNORE_UNUSED, G_TIM8),
1830 PCLK(TIM15, "tim15", "pclk2", CLK_IGNORE_UNUSED, G_TIM15),
1831 PCLK(TIM16, "tim16", "pclk2", CLK_IGNORE_UNUSED, G_TIM16),
1832 PCLK(TIM17, "tim17", "pclk2", CLK_IGNORE_UNUSED, G_TIM17),
1833 PCLK(SPI1, "spi1", "pclk2", 0, G_SPI1),
1834 PCLK(SPI4, "spi4", "pclk2", 0, G_SPI4),
1835 PCLK(SPI5, "spi5", "pclk2", 0, G_SPI5),
1836 PCLK(USART6, "usart6", "pclk2", 0, G_USART6),
1837 PCLK(SAI1, "sai1", "pclk2", 0, G_SAI1),
1838 PCLK(SAI2, "sai2", "pclk2", 0, G_SAI2),
1839 PCLK(SAI3, "sai3", "pclk2", 0, G_SAI3),
1840 PCLK(DFSDM, "dfsdm", "pclk2", 0, G_DFSDM),
1841 PCLK(FDCAN, "fdcan", "pclk2", 0, G_FDCAN),
1842 PCLK(LPTIM2, "lptim2", "pclk3", 0, G_LPTIM2),
1843 PCLK(LPTIM3, "lptim3", "pclk3", 0, G_LPTIM3),
1844 PCLK(LPTIM4, "lptim4", "pclk3", 0, G_LPTIM4),
1845 PCLK(LPTIM5, "lptim5", "pclk3", 0, G_LPTIM5),
1846 PCLK(SAI4, "sai4", "pclk3", 0, G_SAI4),
1847 PCLK(SYSCFG, "syscfg", "pclk3", 0, G_SYSCFG),
1848 PCLK(VREF, "vref", "pclk3", 13, G_VREF),
1849 PCLK(TMPSENS, "tmpsens", "pclk3", 0, G_TMPSENS),
1850 PCLK(PMBCTRL, "pmbctrl", "pclk3", 0, G_PMBCTRL),
1851 PCLK(HDP, "hdp", "pclk3", 0, G_HDP),
1852 PCLK(LTDC, "ltdc", "pclk4", 0, G_LTDC),
1853 PCLK(DSI, "dsi", "pclk4", 0, G_DSI),
1854 PCLK(IWDG2, "iwdg2", "pclk4", 0, G_IWDG2),
1855 PCLK(USBPHY, "usbphy", "pclk4", 0, G_USBPHY),
1856 PCLK(STGENRO, "stgenro", "pclk4", 0, G_STGENRO),
1857 PCLK(SPI6, "spi6", "pclk5", 0, G_SPI6),
1858 PCLK(I2C4, "i2c4", "pclk5", 0, G_I2C4),
1859 PCLK(I2C6, "i2c6", "pclk5", 0, G_I2C6),
1860 PCLK(USART1, "usart1", "pclk5", 0, G_USART1),
1861 PCLK(RTCAPB, "rtcapb", "pclk5", CLK_IGNORE_UNUSED |
1862 CLK_IS_CRITICAL, G_RTCAPB),
1863 PCLK(TZC, "tzc", "pclk5", CLK_IGNORE_UNUSED, G_TZC),
1864 PCLK(TZPC, "tzpc", "pclk5", CLK_IGNORE_UNUSED, G_TZPC),
1865 PCLK(IWDG1, "iwdg1", "pclk5", 0, G_IWDG1),
1866 PCLK(BSEC, "bsec", "pclk5", CLK_IGNORE_UNUSED, G_BSEC),
1867 PCLK(STGEN, "stgen", "pclk5", CLK_IGNORE_UNUSED, G_STGEN),
1868 PCLK(DMA1, "dma1", "ck_mcu", 0, G_DMA1),
1869 PCLK(DMA2, "dma2", "ck_mcu", 0, G_DMA2),
1870 PCLK(DMAMUX, "dmamux", "ck_mcu", 0, G_DMAMUX),
1871 PCLK(ADC12, "adc12", "ck_mcu", 0, G_ADC12),
1872 PCLK(USBO, "usbo", "ck_mcu", 0, G_USBO),
1873 PCLK(SDMMC3, "sdmmc3", "ck_mcu", 0, G_SDMMC3),
1874 PCLK(DCMI, "dcmi", "ck_mcu", 0, G_DCMI),
1875 PCLK(CRYP2, "cryp2", "ck_mcu", 0, G_CRYP2),
1876 PCLK(HASH2, "hash2", "ck_mcu", 0, G_HASH2),
1877 PCLK(RNG2, "rng2", "ck_mcu", 0, G_RNG2),
1878 PCLK(CRC2, "crc2", "ck_mcu", 0, G_CRC2),
1879 PCLK(HSEM, "hsem", "ck_mcu", 0, G_HSEM),
1880 PCLK(IPCC, "ipcc", "ck_mcu", 0, G_IPCC),
1881 PCLK(GPIOA, "gpioa", "ck_mcu", 0, G_GPIOA),
1882 PCLK(GPIOB, "gpiob", "ck_mcu", 0, G_GPIOB),
1883 PCLK(GPIOC, "gpioc", "ck_mcu", 0, G_GPIOC),
1884 PCLK(GPIOD, "gpiod", "ck_mcu", 0, G_GPIOD),
1885 PCLK(GPIOE, "gpioe", "ck_mcu", 0, G_GPIOE),
1886 PCLK(GPIOF, "gpiof", "ck_mcu", 0, G_GPIOF),
1887 PCLK(GPIOG, "gpiog", "ck_mcu", 0, G_GPIOG),
1888 PCLK(GPIOH, "gpioh", "ck_mcu", 0, G_GPIOH),
1889 PCLK(GPIOI, "gpioi", "ck_mcu", 0, G_GPIOI),
1890 PCLK(GPIOJ, "gpioj", "ck_mcu", 0, G_GPIOJ),
1891 PCLK(GPIOK, "gpiok", "ck_mcu", 0, G_GPIOK),
1892 PCLK(GPIOZ, "gpioz", "ck_axi", CLK_IGNORE_UNUSED, G_GPIOZ),
1893 PCLK(CRYP1, "cryp1", "ck_axi", CLK_IGNORE_UNUSED, G_CRYP1),
1894 PCLK(HASH1, "hash1", "ck_axi", CLK_IGNORE_UNUSED, G_HASH1),
1895 PCLK(RNG1, "rng1", "ck_axi", 0, G_RNG1),
1896 PCLK(BKPSRAM, "bkpsram", "ck_axi", CLK_IGNORE_UNUSED, G_BKPSRAM),
1897 PCLK(MDMA, "mdma", "ck_axi", 0, G_MDMA),
1898 PCLK(GPU, "gpu", "ck_axi", 0, G_GPU),
1899 PCLK(ETHTX, "ethtx", "ck_axi", 0, G_ETHTX),
1900 PCLK(ETHRX, "ethrx", "ck_axi", 0, G_ETHRX),
1901 PCLK(ETHMAC, "ethmac", "ck_axi", 0, G_ETHMAC),
1902 PCLK(FMC, "fmc", "ck_axi", CLK_IGNORE_UNUSED, G_FMC),
1903 PCLK(QSPI, "qspi", "ck_axi", CLK_IGNORE_UNUSED, G_QSPI),
1904 PCLK(SDMMC1, "sdmmc1", "ck_axi", 0, G_SDMMC1),
1905 PCLK(SDMMC2, "sdmmc2", "ck_axi", 0, G_SDMMC2),
1906 PCLK(CRC1, "crc1", "ck_axi", 0, G_CRC1),
1907 PCLK(USBH, "usbh", "ck_axi", 0, G_USBH),
1908 PCLK(ETHSTP, "ethstp", "ck_axi", 0, G_ETHSTP),
1909
1910 /* Kernel clocks */
1911 KCLK(SDMMC1_K, "sdmmc1_k", sdmmc12_src, 0, G_SDMMC1, M_SDMMC12),
1912 KCLK(SDMMC2_K, "sdmmc2_k", sdmmc12_src, 0, G_SDMMC2, M_SDMMC12),
1913 KCLK(SDMMC3_K, "sdmmc3_k", sdmmc3_src, 0, G_SDMMC3, M_SDMMC3),
1914 KCLK(FMC_K, "fmc_k", fmc_src, 0, G_FMC, M_FMC),
1915 KCLK(QSPI_K, "qspi_k", qspi_src, 0, G_QSPI, M_QSPI),
1916 KCLK(RNG1_K, "rng1_k", rng_src, 0, G_RNG1, M_RNG1),
1917 KCLK(RNG2_K, "rng2_k", rng_src, 0, G_RNG2, M_RNG2),
1918 KCLK(USBPHY_K, "usbphy_k", usbphy_src, 0, G_USBPHY, M_USBPHY),
1919 KCLK(STGEN_K, "stgen_k", stgen_src, CLK_IGNORE_UNUSED,
1920 G_STGEN, M_STGEN),
1921 KCLK(SPDIF_K, "spdif_k", spdif_src, 0, G_SPDIF, M_SPDIF),
1922 KCLK(SPI1_K, "spi1_k", spi123_src, 0, G_SPI1, M_SPI1),
1923 KCLK(SPI2_K, "spi2_k", spi123_src, 0, G_SPI2, M_SPI23),
1924 KCLK(SPI3_K, "spi3_k", spi123_src, 0, G_SPI3, M_SPI23),
1925 KCLK(SPI4_K, "spi4_k", spi45_src, 0, G_SPI4, M_SPI45),
1926 KCLK(SPI5_K, "spi5_k", spi45_src, 0, G_SPI5, M_SPI45),
1927 KCLK(SPI6_K, "spi6_k", spi6_src, 0, G_SPI6, M_SPI6),
1928 KCLK(CEC_K, "cec_k", cec_src, 0, G_CEC, M_CEC),
1929 KCLK(I2C1_K, "i2c1_k", i2c12_src, 0, G_I2C1, M_I2C12),
1930 KCLK(I2C2_K, "i2c2_k", i2c12_src, 0, G_I2C2, M_I2C12),
1931 KCLK(I2C3_K, "i2c3_k", i2c35_src, 0, G_I2C3, M_I2C35),
1932 KCLK(I2C5_K, "i2c5_k", i2c35_src, 0, G_I2C5, M_I2C35),
1933 KCLK(I2C4_K, "i2c4_k", i2c46_src, 0, G_I2C4, M_I2C46),
1934 KCLK(I2C6_K, "i2c6_k", i2c46_src, 0, G_I2C6, M_I2C46),
1935 KCLK(LPTIM1_K, "lptim1_k", lptim1_src, 0, G_LPTIM1, M_LPTIM1),
1936 KCLK(LPTIM2_K, "lptim2_k", lptim23_src, 0, G_LPTIM2, M_LPTIM23),
1937 KCLK(LPTIM3_K, "lptim3_k", lptim23_src, 0, G_LPTIM3, M_LPTIM23),
1938 KCLK(LPTIM4_K, "lptim4_k", lptim45_src, 0, G_LPTIM4, M_LPTIM45),
1939 KCLK(LPTIM5_K, "lptim5_k", lptim45_src, 0, G_LPTIM5, M_LPTIM45),
1940 KCLK(USART1_K, "usart1_k", usart1_src, 0, G_USART1, M_USART1),
1941 KCLK(USART2_K, "usart2_k", usart234578_src, 0, G_USART2, M_UART24),
1942 KCLK(USART3_K, "usart3_k", usart234578_src, 0, G_USART3, M_UART35),
1943 KCLK(UART4_K, "uart4_k", usart234578_src, 0, G_UART4, M_UART24),
1944 KCLK(UART5_K, "uart5_k", usart234578_src, 0, G_UART5, M_UART35),
1945 KCLK(USART6_K, "uart6_k", usart6_src, 0, G_USART6, M_USART6),
1946 KCLK(UART7_K, "uart7_k", usart234578_src, 0, G_UART7, M_UART78),
1947 KCLK(UART8_K, "uart8_k", usart234578_src, 0, G_UART8, M_UART78),
1948 KCLK(FDCAN_K, "fdcan_k", fdcan_src, 0, G_FDCAN, M_FDCAN),
1949 KCLK(SAI1_K, "sai1_k", sai_src, 0, G_SAI1, M_SAI1),
1950 KCLK(SAI2_K, "sai2_k", sai2_src, 0, G_SAI2, M_SAI2),
1951 KCLK(SAI3_K, "sai3_k", sai_src, 0, G_SAI2, M_SAI3),
1952 KCLK(SAI4_K, "sai4_k", sai_src, 0, G_SAI2, M_SAI4),
1953 KCLK(ADC12_K, "adc12_k", adc12_src, 0, G_ADC12, M_ADC12),
1954 KCLK(DSI_K, "dsi_k", dsi_src, 0, G_DSI, M_DSI),
1955 KCLK(ADFSDM_K, "adfsdm_k", sai_src, 0, G_ADFSDM, M_SAI1),
1956 KCLK(USBO_K, "usbo_k", usbo_src, 0, G_USBO, M_USBO),
1957 KCLK(ETHCK_K, "ethck_k", eth_src, 0, G_ETHCK, M_ETHCK),
1958
1959 /* Particulary Kernel Clocks (no mux or no gate) */
1960 MGATE_MP1(DFSDM_K, "dfsdm_k", "ck_mcu", 0, G_DFSDM),
1961 MGATE_MP1(DSI_PX, "dsi_px", "pll4_q", CLK_SET_RATE_PARENT, G_DSI),
1962 MGATE_MP1(LTDC_PX, "ltdc_px", "pll4_q", CLK_SET_RATE_PARENT, G_LTDC),
1963 MGATE_MP1(GPU_K, "gpu_k", "pll2_q", 0, G_GPU),
1964 MGATE_MP1(DAC12_K, "dac12_k", "ck_lsi", 0, G_DAC12),
1965
1966 COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE,
1967 _NO_GATE,
1968 _MMUX(M_ETHCK),
1969 _DIV(RCC_ETHCKSELR, 4, 4, CLK_DIVIDER_ALLOW_ZERO, NULL)),
1970
1971 /* RTC clock */
1972 DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 7,
1973 CLK_DIVIDER_ALLOW_ZERO),
1974
1975 COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
1976 CLK_SET_RATE_PARENT,
1977 _GATE(RCC_BDCR, 20, 0),
1978 _MUX(RCC_BDCR, 16, 2, 0),
1979 _NO_DIV),
1980
1981 /* MCO clocks */
1982 COMPOSITE(CK_MCO1, "ck_mco1", mco1_src, CLK_OPS_PARENT_ENABLE |
1983 CLK_SET_RATE_NO_REPARENT,
1984 _GATE(RCC_MCO1CFGR, 12, 0),
1985 _MUX(RCC_MCO1CFGR, 0, 3, 0),
1986 _DIV(RCC_MCO1CFGR, 4, 4, 0, NULL)),
1987
1988 COMPOSITE(CK_MCO2, "ck_mco2", mco2_src, CLK_OPS_PARENT_ENABLE |
1989 CLK_SET_RATE_NO_REPARENT,
1990 _GATE(RCC_MCO2CFGR, 12, 0),
1991 _MUX(RCC_MCO2CFGR, 0, 3, 0),
1992 _DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
1993
1994 /* Debug clocks */
1995 FIXED_FACTOR(NO_ID, "ck_axi_div2", "ck_axi", 0, 1, 2),
1996
1997 GATE(DBG, "ck_apb_dbg", "ck_axi_div2", 0, RCC_DBGCFGR, 8, 0),
1998
1999 GATE(CK_DBG, "ck_sys_dbg", "ck_axi", 0, RCC_DBGCFGR, 8, 0),
2000
2001 COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
2002 _GATE(RCC_DBGCFGR, 9, 0),
2003 _NO_MUX,
2004 _DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
2005};
2006
2007struct stm32_clock_match_data {
2008 const struct clock_config *cfg;
2009 unsigned int num;
2010 unsigned int maxbinding;
2011};
2012
2013static struct stm32_clock_match_data stm32mp1_data = {
2014 .cfg = stm32mp1_clock_cfg,
2015 .num = ARRAY_SIZE(stm32mp1_clock_cfg),
2016 .maxbinding = STM32MP1_LAST_CLK,
2017};
2018
2019static const struct of_device_id stm32mp1_match_data[] = {
2020 {
2021 .compatible = "st,stm32mp1-rcc",
2022 .data = &stm32mp1_data,
2023 },
2024 { }
2025};
2026
2027static int stm32_register_hw_clk(struct device *dev,
2028 struct clk_hw_onecell_data *clk_data,
2029 void __iomem *base, spinlock_t *lock,
2030 const struct clock_config *cfg)
2031{
2032 static struct clk_hw **hws;
2033 struct clk_hw *hw = ERR_PTR(-ENOENT);
2034
2035 hws = clk_data->hws;
2036
2037 if (cfg->func)
2038 hw = (*cfg->func)(dev, clk_data, base, lock, cfg);
2039
2040 if (IS_ERR(hw)) {
2041 pr_err("Unable to register %s\n", cfg->name);
2042 return PTR_ERR(hw);
2043 }
2044
2045 if (cfg->id != NO_ID)
2046 hws[cfg->id] = hw;
2047
2048 return 0;
2049}
2050
2051static int stm32_rcc_init(struct device_node *np,
2052 void __iomem *base,
2053 const struct of_device_id *match_data)
2054{
2055 struct clk_hw_onecell_data *clk_data;
2056 struct clk_hw **hws;
2057 const struct of_device_id *match;
2058 const struct stm32_clock_match_data *data;
2059 int err, n, max_binding;
2060
2061 match = of_match_node(match_data, np);
2062 if (!match) {
2063 pr_err("%s: match data not found\n", __func__);
2064 return -ENODEV;
2065 }
2066
2067 data = match->data;
2068
2069 max_binding = data->maxbinding;
2070
2071 clk_data = kzalloc(sizeof(*clk_data) +
2072 sizeof(*clk_data->hws) * max_binding,
2073 GFP_KERNEL);
2074 if (!clk_data)
2075 return -ENOMEM;
2076
2077 clk_data->num = max_binding;
2078
2079 hws = clk_data->hws;
2080
2081 for (n = 0; n < max_binding; n++)
2082 hws[n] = ERR_PTR(-ENOENT);
2083
2084 for (n = 0; n < data->num; n++) {
2085 err = stm32_register_hw_clk(NULL, clk_data, base, &rlock,
2086 &data->cfg[n]);
2087 if (err) {
2088 pr_err("%s: can't register %s\n", __func__,
2089 data->cfg[n].name);
2090
2091 kfree(clk_data);
2092
2093 return err;
2094 }
2095 }
2096
2097 return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
2098}
2099
2100static void stm32mp1_rcc_init(struct device_node *np)
2101{
2102 void __iomem *base;
2103
2104 base = of_iomap(np, 0);
2105 if (!base) {
2106 pr_err("%s: unable to map resource", np->name);
2107 of_node_put(np);
2108 return;
2109 }
2110
2111 if (stm32_rcc_init(np, base, stm32mp1_match_data)) {
2112 iounmap(base);
2113 of_node_put(np);
2114 }
2115}
2116
2117CLK_OF_DECLARE_DRIVER(stm32mp1_rcc, "st,stm32mp1-rcc", stm32mp1_rcc_init);
diff --git a/drivers/clk/sprd/sc9860-clk.c b/drivers/clk/sprd/sc9860-clk.c
index ed5c027df0f4..9980ab55271b 100644
--- a/drivers/clk/sprd/sc9860-clk.c
+++ b/drivers/clk/sprd/sc9860-clk.c
@@ -959,6 +959,44 @@ static SPRD_SC_GATE_CLK(sdio2_2x_en, "sdio2-2x-en", "aon-apb", 0x13c,
959 0x1000, BIT(6), 0, 0); 959 0x1000, BIT(6), 0, 0);
960static SPRD_SC_GATE_CLK(emmc_2x_en, "emmc-2x-en", "aon-apb", 0x13c, 960static SPRD_SC_GATE_CLK(emmc_2x_en, "emmc-2x-en", "aon-apb", 0x13c,
961 0x1000, BIT(9), 0, 0); 961 0x1000, BIT(9), 0, 0);
962static SPRD_SC_GATE_CLK(arch_rtc_eb, "arch-rtc-eb", "aon-apb", 0x10,
963 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);
964static SPRD_SC_GATE_CLK(kpb_rtc_eb, "kpb-rtc-eb", "aon-apb", 0x10,
965 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);
966static SPRD_SC_GATE_CLK(aon_syst_rtc_eb, "aon-syst-rtc-eb", "aon-apb", 0x10,
967 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);
968static SPRD_SC_GATE_CLK(ap_syst_rtc_eb, "ap-syst-rtc-eb", "aon-apb", 0x10,
969 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);
970static SPRD_SC_GATE_CLK(aon_tmr_rtc_eb, "aon-tmr-rtc-eb", "aon-apb", 0x10,
971 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);
972static SPRD_SC_GATE_CLK(ap_tmr0_rtc_eb, "ap-tmr0-rtc-eb", "aon-apb", 0x10,
973 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);
974static SPRD_SC_GATE_CLK(eic_rtc_eb, "eic-rtc-eb", "aon-apb", 0x10,
975 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);
976static SPRD_SC_GATE_CLK(eic_rtcdv5_eb, "eic-rtcdv5-eb", "aon-apb", 0x10,
977 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);
978static SPRD_SC_GATE_CLK(ap_wdg_rtc_eb, "ap-wdg-rtc-eb", "aon-apb", 0x10,
979 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);
980static SPRD_SC_GATE_CLK(ap_tmr1_rtc_eb, "ap-tmr1-rtc-eb", "aon-apb", 0x10,
981 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);
982static SPRD_SC_GATE_CLK(ap_tmr2_rtc_eb, "ap-tmr2-rtc-eb", "aon-apb", 0x10,
983 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);
984static SPRD_SC_GATE_CLK(dcxo_tmr_rtc_eb, "dcxo-tmr-rtc-eb", "aon-apb", 0x10,
985 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);
986static SPRD_SC_GATE_CLK(bb_cal_rtc_eb, "bb-cal-rtc-eb", "aon-apb", 0x10,
987 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);
988static SPRD_SC_GATE_CLK(avs_big_rtc_eb, "avs-big-rtc-eb", "aon-apb", 0x10,
989 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);
990static SPRD_SC_GATE_CLK(avs_lit_rtc_eb, "avs-lit-rtc-eb", "aon-apb", 0x10,
991 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0);
992static SPRD_SC_GATE_CLK(avs_gpu0_rtc_eb, "avs-gpu0-rtc-eb", "aon-apb", 0x10,
993 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);
994static SPRD_SC_GATE_CLK(avs_gpu1_rtc_eb, "avs-gpu1-rtc-eb", "aon-apb", 0x10,
995 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);
996static SPRD_SC_GATE_CLK(gpu_ts_eb, "gpu-ts-eb", "aon-apb", 0x10,
997 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);
998static SPRD_SC_GATE_CLK(rtcdv10_eb, "rtcdv10-eb", "aon-apb", 0x10,
999 0x1000, BIT(27), CLK_IGNORE_UNUSED, 0);
962 1000
963static struct sprd_clk_common *sc9860_aon_gate[] = { 1001static struct sprd_clk_common *sc9860_aon_gate[] = {
964 /* address base is 0x402e0000 */ 1002 /* address base is 0x402e0000 */
@@ -1030,6 +1068,25 @@ static struct sprd_clk_common *sc9860_aon_gate[] = {
1030 &sdio1_2x_en.common, 1068 &sdio1_2x_en.common,
1031 &sdio2_2x_en.common, 1069 &sdio2_2x_en.common,
1032 &emmc_2x_en.common, 1070 &emmc_2x_en.common,
1071 &arch_rtc_eb.common,
1072 &kpb_rtc_eb.common,
1073 &aon_syst_rtc_eb.common,
1074 &ap_syst_rtc_eb.common,
1075 &aon_tmr_rtc_eb.common,
1076 &ap_tmr0_rtc_eb.common,
1077 &eic_rtc_eb.common,
1078 &eic_rtcdv5_eb.common,
1079 &ap_wdg_rtc_eb.common,
1080 &ap_tmr1_rtc_eb.common,
1081 &ap_tmr2_rtc_eb.common,
1082 &dcxo_tmr_rtc_eb.common,
1083 &bb_cal_rtc_eb.common,
1084 &avs_big_rtc_eb.common,
1085 &avs_lit_rtc_eb.common,
1086 &avs_gpu0_rtc_eb.common,
1087 &avs_gpu1_rtc_eb.common,
1088 &gpu_ts_eb.common,
1089 &rtcdv10_eb.common,
1033}; 1090};
1034 1091
1035static struct clk_hw_onecell_data sc9860_aon_gate_hws = { 1092static struct clk_hw_onecell_data sc9860_aon_gate_hws = {
@@ -1102,6 +1159,25 @@ static struct clk_hw_onecell_data sc9860_aon_gate_hws = {
1102 [CLK_SDIO1_2X_EN] = &sdio1_2x_en.common.hw, 1159 [CLK_SDIO1_2X_EN] = &sdio1_2x_en.common.hw,
1103 [CLK_SDIO2_2X_EN] = &sdio2_2x_en.common.hw, 1160 [CLK_SDIO2_2X_EN] = &sdio2_2x_en.common.hw,
1104 [CLK_EMMC_2X_EN] = &emmc_2x_en.common.hw, 1161 [CLK_EMMC_2X_EN] = &emmc_2x_en.common.hw,
1162 [CLK_ARCH_RTC_EB] = &arch_rtc_eb.common.hw,
1163 [CLK_KPB_RTC_EB] = &kpb_rtc_eb.common.hw,
1164 [CLK_AON_SYST_RTC_EB] = &aon_syst_rtc_eb.common.hw,
1165 [CLK_AP_SYST_RTC_EB] = &ap_syst_rtc_eb.common.hw,
1166 [CLK_AON_TMR_RTC_EB] = &aon_tmr_rtc_eb.common.hw,
1167 [CLK_AP_TMR0_RTC_EB] = &ap_tmr0_rtc_eb.common.hw,
1168 [CLK_EIC_RTC_EB] = &eic_rtc_eb.common.hw,
1169 [CLK_EIC_RTCDV5_EB] = &eic_rtcdv5_eb.common.hw,
1170 [CLK_AP_WDG_RTC_EB] = &ap_wdg_rtc_eb.common.hw,
1171 [CLK_AP_TMR1_RTC_EB] = &ap_tmr1_rtc_eb.common.hw,
1172 [CLK_AP_TMR2_RTC_EB] = &ap_tmr2_rtc_eb.common.hw,
1173 [CLK_DCXO_TMR_RTC_EB] = &dcxo_tmr_rtc_eb.common.hw,
1174 [CLK_BB_CAL_RTC_EB] = &bb_cal_rtc_eb.common.hw,
1175 [CLK_AVS_BIG_RTC_EB] = &avs_big_rtc_eb.common.hw,
1176 [CLK_AVS_LIT_RTC_EB] = &avs_lit_rtc_eb.common.hw,
1177 [CLK_AVS_GPU0_RTC_EB] = &avs_gpu0_rtc_eb.common.hw,
1178 [CLK_AVS_GPU1_RTC_EB] = &avs_gpu1_rtc_eb.common.hw,
1179 [CLK_GPU_TS_EB] = &gpu_ts_eb.common.hw,
1180 [CLK_RTCDV10_EB] = &rtcdv10_eb.common.hw,
1105 }, 1181 },
1106 .num = CLK_AON_GATE_NUM, 1182 .num = CLK_AON_GATE_NUM,
1107}; 1183};
diff --git a/include/dt-bindings/clock/sprd,sc9860-clk.h b/include/dt-bindings/clock/sprd,sc9860-clk.h
index 4cb202f090c2..f2ab4631df0d 100644
--- a/include/dt-bindings/clock/sprd,sc9860-clk.h
+++ b/include/dt-bindings/clock/sprd,sc9860-clk.h
@@ -229,7 +229,26 @@
229#define CLK_SDIO1_2X_EN 65 229#define CLK_SDIO1_2X_EN 65
230#define CLK_SDIO2_2X_EN 66 230#define CLK_SDIO2_2X_EN 66
231#define CLK_EMMC_2X_EN 67 231#define CLK_EMMC_2X_EN 67
232#define CLK_AON_GATE_NUM (CLK_EMMC_2X_EN + 1) 232#define CLK_ARCH_RTC_EB 68
233#define CLK_KPB_RTC_EB 69
234#define CLK_AON_SYST_RTC_EB 70
235#define CLK_AP_SYST_RTC_EB 71
236#define CLK_AON_TMR_RTC_EB 72
237#define CLK_AP_TMR0_RTC_EB 73
238#define CLK_EIC_RTC_EB 74
239#define CLK_EIC_RTCDV5_EB 75
240#define CLK_AP_WDG_RTC_EB 76
241#define CLK_AP_TMR1_RTC_EB 77
242#define CLK_AP_TMR2_RTC_EB 78
243#define CLK_DCXO_TMR_RTC_EB 79
244#define CLK_BB_CAL_RTC_EB 80
245#define CLK_AVS_BIG_RTC_EB 81
246#define CLK_AVS_LIT_RTC_EB 82
247#define CLK_AVS_GPU0_RTC_EB 83
248#define CLK_AVS_GPU1_RTC_EB 84
249#define CLK_GPU_TS_EB 85
250#define CLK_RTCDV10_EB 86
251#define CLK_AON_GATE_NUM (CLK_RTCDV10_EB + 1)
233 252
234#define CLK_LIT_MCU 0 253#define CLK_LIT_MCU 0
235#define CLK_BIG_MCU 1 254#define CLK_BIG_MCU 1
diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
index 49bb3c203e5c..58d8b515be55 100644
--- a/include/dt-bindings/clock/stm32fx-clock.h
+++ b/include/dt-bindings/clock/stm32fx-clock.h
@@ -33,11 +33,12 @@
33#define CLK_SAI2 11 33#define CLK_SAI2 11
34#define CLK_I2SQ_PDIV 12 34#define CLK_I2SQ_PDIV 12
35#define CLK_SAIQ_PDIV 13 35#define CLK_SAIQ_PDIV 13
36
37#define END_PRIMARY_CLK 14
38
39#define CLK_HSI 14 36#define CLK_HSI 14
40#define CLK_SYSCLK 15 37#define CLK_SYSCLK 15
38#define CLK_F469_DSI 16
39
40#define END_PRIMARY_CLK 17
41
41#define CLK_HDMI_CEC 16 42#define CLK_HDMI_CEC 16
42#define CLK_SPDIF 17 43#define CLK_SPDIF 17
43#define CLK_USART1 18 44#define CLK_USART1 18
diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h
new file mode 100644
index 000000000000..86e3ec662ef4
--- /dev/null
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -0,0 +1,254 @@
1/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
2/*
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
4 * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
5 */
6
7#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_
8#define _DT_BINDINGS_STM32MP1_CLKS_H_
9
10/* OSCILLATOR clocks */
11#define CK_HSE 0
12#define CK_CSI 1
13#define CK_LSI 2
14#define CK_LSE 3
15#define CK_HSI 4
16#define CK_HSE_DIV2 5
17
18/* Bus clocks */
19#define TIM2 6
20#define TIM3 7
21#define TIM4 8
22#define TIM5 9
23#define TIM6 10
24#define TIM7 11
25#define TIM12 12
26#define TIM13 13
27#define TIM14 14
28#define LPTIM1 15
29#define SPI2 16
30#define SPI3 17
31#define USART2 18
32#define USART3 19
33#define UART4 20
34#define UART5 21
35#define UART7 22
36#define UART8 23
37#define I2C1 24
38#define I2C2 25
39#define I2C3 26
40#define I2C5 27
41#define SPDIF 28
42#define CEC 29
43#define DAC12 30
44#define MDIO 31
45#define TIM1 32
46#define TIM8 33
47#define TIM15 34
48#define TIM16 35
49#define TIM17 36
50#define SPI1 37
51#define SPI4 38
52#define SPI5 39
53#define USART6 40
54#define SAI1 41
55#define SAI2 42
56#define SAI3 43
57#define DFSDM 44
58#define FDCAN 45
59#define LPTIM2 46
60#define LPTIM3 47
61#define LPTIM4 48
62#define LPTIM5 49
63#define SAI4 50
64#define SYSCFG 51
65#define VREF 52
66#define TMPSENS 53
67#define PMBCTRL 54
68#define HDP 55
69#define LTDC 56
70#define DSI 57
71#define IWDG2 58
72#define USBPHY 59
73#define STGENRO 60
74#define SPI6 61
75#define I2C4 62
76#define I2C6 63
77#define USART1 64
78#define RTCAPB 65
79#define TZC 66
80#define TZPC 67
81#define IWDG1 68
82#define BSEC 69
83#define STGEN 70
84#define DMA1 71
85#define DMA2 72
86#define DMAMUX 73
87#define ADC12 74
88#define USBO 75
89#define SDMMC3 76
90#define DCMI 77
91#define CRYP2 78
92#define HASH2 79
93#define RNG2 80
94#define CRC2 81
95#define HSEM 82
96#define IPCC 83
97#define GPIOA 84
98#define GPIOB 85
99#define GPIOC 86
100#define GPIOD 87
101#define GPIOE 88
102#define GPIOF 89
103#define GPIOG 90
104#define GPIOH 91
105#define GPIOI 92
106#define GPIOJ 93
107#define GPIOK 94
108#define GPIOZ 95
109#define CRYP1 96
110#define HASH1 97
111#define RNG1 98
112#define BKPSRAM 99
113#define MDMA 100
114#define GPU 101
115#define ETHCK 102
116#define ETHTX 103
117#define ETHRX 104
118#define ETHMAC 105
119#define FMC 106
120#define QSPI 107
121#define SDMMC1 108
122#define SDMMC2 109
123#define CRC1 110
124#define USBH 111
125#define ETHSTP 112
126
127/* Kernel clocks */
128#define SDMMC1_K 118
129#define SDMMC2_K 119
130#define SDMMC3_K 120
131#define FMC_K 121
132#define QSPI_K 122
133#define ETHCK_K 123
134#define RNG1_K 124
135#define RNG2_K 125
136#define GPU_K 126
137#define USBPHY_K 127
138#define STGEN_K 128
139#define SPDIF_K 129
140#define SPI1_K 130
141#define SPI2_K 131
142#define SPI3_K 132
143#define SPI4_K 133
144#define SPI5_K 134
145#define SPI6_K 135
146#define CEC_K 136
147#define I2C1_K 137
148#define I2C2_K 138
149#define I2C3_K 139
150#define I2C4_K 140
151#define I2C5_K 141
152#define I2C6_K 142
153#define LPTIM1_K 143
154#define LPTIM2_K 144
155#define LPTIM3_K 145
156#define LPTIM4_K 146
157#define LPTIM5_K 147
158#define USART1_K 148
159#define USART2_K 149
160#define USART3_K 150
161#define UART4_K 151
162#define UART5_K 152
163#define USART6_K 153
164#define UART7_K 154
165#define UART8_K 155
166#define DFSDM_K 156
167#define FDCAN_K 157
168#define SAI1_K 158
169#define SAI2_K 159
170#define SAI3_K 160
171#define SAI4_K 161
172#define ADC12_K 162
173#define DSI_K 163
174#define DSI_PX 164
175#define ADFSDM_K 165
176#define USBO_K 166
177#define LTDC_PX 167
178#define DAC12_K 168
179#define ETHPTP_K 169
180
181/* PLL */
182#define PLL1 176
183#define PLL2 177
184#define PLL3 178
185#define PLL4 179
186
187/* ODF */
188#define PLL1_P 180
189#define PLL1_Q 181
190#define PLL1_R 182
191#define PLL2_P 183
192#define PLL2_Q 184
193#define PLL2_R 185
194#define PLL3_P 186
195#define PLL3_Q 187
196#define PLL3_R 188
197#define PLL4_P 189
198#define PLL4_Q 190
199#define PLL4_R 191
200
201/* AUX */
202#define RTC 192
203
204/* MCLK */
205#define CK_PER 193
206#define CK_MPU 194
207#define CK_AXI 195
208#define CK_MCU 196
209
210/* Time base */
211#define TIM2_K 197
212#define TIM3_K 198
213#define TIM4_K 199
214#define TIM5_K 200
215#define TIM6_K 201
216#define TIM7_K 202
217#define TIM12_K 203
218#define TIM13_K 204
219#define TIM14_K 205
220#define TIM1_K 206
221#define TIM8_K 207
222#define TIM15_K 208
223#define TIM16_K 209
224#define TIM17_K 210
225
226/* MCO clocks */
227#define CK_MCO1 211
228#define CK_MCO2 212
229
230/* TRACE & DEBUG clocks */
231#define DBG 213
232#define CK_DBG 214
233#define CK_TRACE 215
234
235/* DDR */
236#define DDRC1 220
237#define DDRC1LP 221
238#define DDRC2 222
239#define DDRC2LP 223
240#define DDRPHYC 224
241#define DDRPHYCLP 225
242#define DDRCAPB 226
243#define DDRCAPBLP 227
244#define AXIDCG 228
245#define DDRPHYCAPB 229
246#define DDRPHYCAPBLP 230
247#define DDRPERFM 231
248
249#define STM32MP1_LAST_CLK 232
250
251#define LTDC_K LTDC_PX
252#define ETHMAC_K ETHCK_K
253
254#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-31 23:01:00 -0400