aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--arch/parisc/kernel/syscall.S12
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/parisc/kernel/syscall.S b/arch/parisc/kernel/syscall.S
index e54d5e4d3489..97ac707c6bff 100644
--- a/arch/parisc/kernel/syscall.S
+++ b/arch/parisc/kernel/syscall.S
@@ -641,7 +641,8 @@ cas_action:
6412: stw %r24, 0(%r26) 6412: stw %r24, 0(%r26)
642 /* Free lock */ 642 /* Free lock */
643#ifdef CONFIG_SMP 643#ifdef CONFIG_SMP
644 LDCW 0(%sr2,%r20), %r1 /* Barrier */ 64498: LDCW 0(%sr2,%r20), %r1 /* Barrier */
64599: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
645#endif 646#endif
646 stw %r20, 0(%sr2,%r20) 647 stw %r20, 0(%sr2,%r20)
647#if ENABLE_LWS_DEBUG 648#if ENABLE_LWS_DEBUG
@@ -658,7 +659,8 @@ cas_action:
658 /* Error occurred on load or store */ 659 /* Error occurred on load or store */
659 /* Free lock */ 660 /* Free lock */
660#ifdef CONFIG_SMP 661#ifdef CONFIG_SMP
661 LDCW 0(%sr2,%r20), %r1 /* Barrier */ 66298: LDCW 0(%sr2,%r20), %r1 /* Barrier */
66399: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
662#endif 664#endif
663 stw %r20, 0(%sr2,%r20) 665 stw %r20, 0(%sr2,%r20)
664#if ENABLE_LWS_DEBUG 666#if ENABLE_LWS_DEBUG
@@ -862,7 +864,8 @@ cas2_action:
862cas2_end: 864cas2_end:
863 /* Free lock */ 865 /* Free lock */
864#ifdef CONFIG_SMP 866#ifdef CONFIG_SMP
865 LDCW 0(%sr2,%r20), %r1 /* Barrier */ 86798: LDCW 0(%sr2,%r20), %r1 /* Barrier */
86899: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
866#endif 869#endif
867 stw %r20, 0(%sr2,%r20) 870 stw %r20, 0(%sr2,%r20)
868 /* Enable interrupts */ 871 /* Enable interrupts */
@@ -875,7 +878,8 @@ cas2_end:
875 /* Error occurred on load or store */ 878 /* Error occurred on load or store */
876 /* Free lock */ 879 /* Free lock */
877#ifdef CONFIG_SMP 880#ifdef CONFIG_SMP
878 LDCW 0(%sr2,%r20), %r1 /* Barrier */ 88198: LDCW 0(%sr2,%r20), %r1 /* Barrier */
88299: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
879#endif 883#endif
880 stw %r20, 0(%sr2,%r20) 884 stw %r20, 0(%sr2,%r20)
881 ssm PSW_SM_I, %r0 885 ssm PSW_SM_I, %r0