5 files changed, 46 insertions, 7 deletions

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index d767c45a57e2..53115bdae12b 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -948,7 +948,16 @@ static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
 
         if (e->type != GTT_TYPE_PPGTT_ROOT_L3_ENTRY
                 && e->type != GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
-                cur_pt_type = get_next_pt_type(e->type) + 1;
+                cur_pt_type = get_next_pt_type(e->type);
+
+                if (!gtt_type_is_pt(cur_pt_type) ||
+                                !gtt_type_is_pt(cur_pt_type + 1)) {
+                        WARN(1, "Invalid page table type, cur_pt_type is: %d\n", cur_pt_type);
+                        return -EINVAL;
+                }
+
+                cur_pt_type += 1;
+
                 if (ops->get_pfn(e) ==
                         vgpu->gtt.scratch_pt[cur_pt_type].page_mfn)
                         return 0;
@@ -1108,6 +1117,7 @@ static struct intel_vgpu_ppgtt_spt *ppgtt_populate_spt_by_guest_entry(
 
 err_free_spt:
         ppgtt_free_spt(spt);
+        spt = NULL;
 err:
         gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
                      spt, we->val64, we->type);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 7732caa1a546..a6ade66349bd 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1924,7 +1924,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
         MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
         MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
         MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
-        MMIO_DFH(_MMIO(0x20e4), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+        MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
+                 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
         MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
         MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
         MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
@@ -3028,7 +3029,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
         MMIO_D(CSR_HTP_SKL, D_SKL_PLUS);
         MMIO_D(CSR_LAST_WRITE, D_SKL_PLUS);
 
-        MMIO_D(BDW_SCRATCH1, D_SKL_PLUS);
+        MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
 
         MMIO_D(SKL_DFSM, D_SKL_PLUS);
         MMIO_D(DISPIO_CR_TX_BMU_CR0, D_SKL_PLUS);
@@ -3041,8 +3042,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
         MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
         MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
         MMIO_D(RC6_LOCATION, D_SKL_PLUS);
-        MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS, F_MODE_MASK,
-                NULL, NULL);
+        MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
+                 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
         MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
                 NULL, NULL);
 
@@ -3061,7 +3062,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
         MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
 
         MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
-        MMIO_D(_MMIO(0xb004), D_SKL_PLUS);
+        MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
         MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
 
         MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
@@ -3273,7 +3274,7 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt)
         MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
         MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
         MMIO_D(GEN6_GFXPAUSE, D_BXT);
-        MMIO_D(GEN8_L3SQCREG1, D_BXT);
+        MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
 
         MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
 
diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
index 33aaa14bfdde..5b66e14c5b7b 100644
--- a/drivers/gpu/drm/i915/gvt/reg.h
+++ b/drivers/gpu/drm/i915/gvt/reg.h
@@ -102,6 +102,8 @@
 #define FORCEWAKE_ACK_MEDIA_GEN9_REG 0x0D88
 #define FORCEWAKE_ACK_HSW_REG 0x130044
 
+#define RB_HEAD_WRAP_CNT_MAX    ((1 << 11) - 1)
+#define RB_HEAD_WRAP_CNT_OFF    21
 #define RB_HEAD_OFF_MASK        ((1U << 21) - (1U << 2))
 #define RB_TAIL_OFF_MASK        ((1U << 21) - (1U << 3))
 #define RB_TAIL_SIZE_MASK       ((1U << 21) - (1U << 12))
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index 13632dba8b2a..0f919f0a43d4 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -812,10 +812,31 @@ static void update_guest_context(struct intel_vgpu_workload *workload)
         void *src;
         unsigned long context_gpa, context_page_num;
         int i;
+        struct drm_i915_private *dev_priv = gvt->dev_priv;
+        u32 ring_base;
+        u32 head, tail;
+        u16 wrap_count;
 
         gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id,
                       workload->ctx_desc.lrca);
 
+        head = workload->rb_head;
+        tail = workload->rb_tail;
+        wrap_count = workload->guest_rb_head >> RB_HEAD_WRAP_CNT_OFF;
+
+        if (tail < head) {
+                if (wrap_count == RB_HEAD_WRAP_CNT_MAX)
+                        wrap_count = 0;
+                else
+                        wrap_count += 1;
+        }
+
+        head = (wrap_count << RB_HEAD_WRAP_CNT_OFF) | tail;
+
+        ring_base = dev_priv->engine[workload->ring_id]->mmio_base;
+        vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail;
+        vgpu_vreg_t(vgpu, RING_HEAD(ring_base)) = head;
+
         context_page_num = rq->engine->context_size;
         context_page_num = context_page_num >> PAGE_SHIFT;
 
@@ -1415,6 +1436,7 @@ intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id,
         struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
         u64 ring_context_gpa;
         u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx;
+        u32 guest_head;
         int ret;
 
         ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
@@ -1430,6 +1452,8 @@ intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id,
         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
                         RING_CTX_OFF(ring_tail.val), &tail, 4);
 
+        guest_head = head;
+
         head &= RB_HEAD_OFF_MASK;
         tail &= RB_TAIL_OFF_MASK;
 
@@ -1462,6 +1486,7 @@ intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id,
         workload->ctx_desc = *desc;
         workload->ring_context_gpa = ring_context_gpa;
         workload->rb_head = head;
+        workload->guest_rb_head = guest_head;
         workload->rb_tail = tail;
         workload->rb_start = start;
         workload->rb_ctl = ctl;
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.h b/drivers/gpu/drm/i915/gvt/scheduler.h
index 90c6756f5453..c50d14a9ce85 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.h
+++ b/drivers/gpu/drm/i915/gvt/scheduler.h
@@ -100,6 +100,7 @@ struct intel_vgpu_workload {
         struct execlist_ctx_descriptor_format ctx_desc;
         struct execlist_ring_context *ring_context;
         unsigned long rb_head, rb_tail, rb_ctl, rb_start, rb_len;
+        unsigned long guest_rb_head;
         bool restore_inhibit;
         struct intel_vgpu_elsp_dwords elsp_dwords;
         bool emulate_schedule_in;