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-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c39
1 files changed, 29 insertions, 10 deletions
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 9794cad131cd..ecfa38949aea 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -293,7 +293,6 @@ static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms,
293 return encoder; 293 return encoder;
294 } 294 }
295 295
296 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
297 priv->encoders[priv->num_encoders++] = encoder; 296 priv->encoders[priv->num_encoders++] = encoder;
298 297
299 return encoder; 298 return encoder;
@@ -411,16 +410,35 @@ static int modeset_init(struct mdp5_kms *mdp5_kms)
411 struct drm_device *dev = mdp5_kms->dev; 410 struct drm_device *dev = mdp5_kms->dev;
412 struct msm_drm_private *priv = dev->dev_private; 411 struct msm_drm_private *priv = dev->dev_private;
413 const struct mdp5_cfg_hw *hw_cfg; 412 const struct mdp5_cfg_hw *hw_cfg;
413 unsigned int num_crtcs;
414 int i, ret; 414 int i, ret;
415 415
416 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 416 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
417 417
418 /* Construct planes equaling the number of hw pipes, and CRTCs 418 /*
419 * for the N layer-mixers (LM). The first N planes become primary 419 * Construct encoders and modeset initialize connector devices
420 * for each external display interface.
421 */
422 for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) {
423 ret = modeset_init_intf(mdp5_kms, i);
424 if (ret)
425 goto fail;
426 }
427
428 /*
429 * We should ideally have less number of encoders (set up by parsing
430 * the MDP5 interfaces) than the number of layer mixers present in HW,
431 * but let's be safe here anyway
432 */
433 num_crtcs = min(priv->num_encoders, mdp5_cfg->lm.count);
434
435 /*
436 * Construct planes equaling the number of hw pipes, and CRTCs for the
437 * N encoders set up by the driver. The first N planes become primary
420 * planes for the CRTCs, with the remainder as overlay planes: 438 * planes for the CRTCs, with the remainder as overlay planes:
421 */ 439 */
422 for (i = 0; i < mdp5_kms->num_hwpipes; i++) { 440 for (i = 0; i < mdp5_kms->num_hwpipes; i++) {
423 bool primary = i < mdp5_cfg->lm.count; 441 bool primary = i < num_crtcs;
424 struct drm_plane *plane; 442 struct drm_plane *plane;
425 struct drm_crtc *crtc; 443 struct drm_crtc *crtc;
426 444
@@ -444,13 +462,14 @@ static int modeset_init(struct mdp5_kms *mdp5_kms)
444 priv->crtcs[priv->num_crtcs++] = crtc; 462 priv->crtcs[priv->num_crtcs++] = crtc;
445 } 463 }
446 464
447 /* Construct encoders and modeset initialize connector devices 465 /*
448 * for each external display interface. 466 * Now that we know the number of crtcs we've created, set the possible
467 * crtcs for the encoders
449 */ 468 */
450 for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) { 469 for (i = 0; i < priv->num_encoders; i++) {
451 ret = modeset_init_intf(mdp5_kms, i); 470 struct drm_encoder *encoder = priv->encoders[i];
452 if (ret) 471
453 goto fail; 472 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
454 } 473 }
455 474
456 return 0; 475 return 0;