2 files changed, 10 insertions, 4 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 19ca7f000506..18dbd0bd7874 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -407,6 +407,7 @@ struct dce_hwseq_registers {
         HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
         HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
+        HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\
         HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\
         HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\
         HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
@@ -495,7 +496,8 @@ struct dce_hwseq_registers {
         type DENTIST_DPPCLK_WDIVIDER; \
         type DENTIST_DISPCLK_WDIVIDER; \
         type VGA_TEST_ENABLE; \
-        type VGA_TEST_RENDER_START;
+        type VGA_TEST_RENDER_START; \
+        type D1VGA_MODE_ENABLE;
 
 struct dce_hwseq_shift {
         HWSEQ_REG_FIELD_LIST(uint8_t)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 0874d4a3fd72..50088b674795 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -220,10 +220,14 @@ static void enable_power_gating_plane(
 static void disable_vga(
         struct dce_hwseq *hws)
 {
+        unsigned int in_vga_mode = 0;
+
+        REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga_mode);
+
+        if (in_vga_mode == 0)
+                return;
+
         REG_WRITE(D1VGA_CONTROL, 0);
-        REG_WRITE(D2VGA_CONTROL, 0);
-        REG_WRITE(D3VGA_CONTROL, 0);
-        REG_WRITE(D4VGA_CONTROL, 0);
 
         /* HW Engineer's Notes:
          *  During switch from vga->extended, if we set the VGA_TEST_ENABLE and