1 files changed, 15 insertions, 1 deletions

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 6c7ccb428c07..7135820f76d4 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -1438,7 +1438,21 @@ ENTRY(efi_stub_entry)
 
                 @ Preserve return value of efi_entry() in r4
                 mov     r4, r0
-                bl      cache_clean_flush
+
+                @ our cache maintenance code relies on CP15 barrier instructions
+                @ but since we arrived here with the MMU and caches configured
+                @ by UEFI, we must check that the CP15BEN bit is set in SCTLR.
+                @ Note that this bit is RAO/WI on v6 and earlier, so the ISB in
+                @ the enable path will be executed on v7+ only.
+                mrc     p15, 0, r1, c1, c0, 0   @ read SCTLR
+                tst     r1, #(1 << 5)           @ CP15BEN bit set?
+                bne     0f
+                orr     r1, r1, #(1 << 5)       @ CP15 barrier instructions
+                mcr     p15, 0, r1, c1, c0, 0   @ write SCTLR
+ ARM(           .inst   0xf57ff06f              @ v7+ isb       )
+ THUMB(         isb                                             )
+
+0:              bl      cache_clean_flush
                 bl      cache_off
 
                 @ Set parameters for booting zImage according to boot protocol