diff options
-rw-r--r-- | drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index f1a7c7b46420..edf74110ced7 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | |||
@@ -99,16 +99,14 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, | |||
99 | dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_1(i), 0); | 99 | dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_1(i), 0); |
100 | dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_2(i), 0); | 100 | dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_2(i), 0); |
101 | dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_3(i), 0); | 101 | dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_3(i), 0); |
102 | dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(i), 0); | ||
102 | dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i), 0); | 103 | dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i), 0); |
103 | dsi_phy_write(base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i), 0); | 104 | dsi_phy_write(base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i), 0); |
104 | dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i), 0x1); | 105 | dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i), 0x1); |
105 | dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i), 0x97); | 106 | dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i), 0x97); |
106 | } | 107 | } |
107 | dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(0), 0); | ||
108 | dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(1), 0x5); | ||
109 | dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(2), 0xa); | ||
110 | dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(3), 0xf); | ||
111 | 108 | ||
109 | dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_4, 0); | ||
112 | dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_1, 0xc0); | 110 | dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_1, 0xc0); |
113 | dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR0, 0x1); | 111 | dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR0, 0x1); |
114 | dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR1, 0xbb); | 112 | dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR1, 0xbb); |