2 files changed, 32 insertions, 38 deletions

diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 0b7c6ce629a6..6bb8813ca275 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -106,6 +106,7 @@ struct pl08x_driver_data;
 
 /**
  * struct vendor_data - vendor-specific config parameters for PL08x derivatives
+ * @config_offset: offset to the configuration register
  * @channels: the number of channels available in this variant
  * @signals: the number of request signals available from the hardware
  * @dualmaster: whether this version supports dual AHB masters or not.
@@ -145,6 +146,8 @@ struct pl08x_bus_data {
 /**
  * struct pl08x_phy_chan - holder for the physical channels
  * @id: physical index to this channel
+ * @base: memory base address for this physical channel
+ * @reg_config: configuration address for this physical channel
  * @lock: a lock to use when altering an instance of this struct
  * @serving: the virtual channel currently being served by this physical
  * channel
@@ -203,7 +206,7 @@ struct pl08x_txd {
 };
 
 /**
- * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
+ * enum pl08x_dma_chan_state - holds the PL08x specific virtual channel
  * states
  * @PL08X_CHAN_IDLE: the channel is idle
  * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
@@ -226,9 +229,8 @@ enum pl08x_dma_chan_state {
  * @phychan: the physical channel utilized by this channel, if there is one
  * @name: name of channel
  * @cd: channel platform data
- * @runtime_addr: address for RX/TX according to the runtime config
+ * @cfg: slave configuration
  * @at: active transaction on this channel
- * @lock: a lock for this channel data
  * @host: a pointer to the host (internal use)
  * @state: whether the channel is idle, paused, running etc
  * @slave: whether this channel is a device (slave) or for memcpy
@@ -262,7 +264,7 @@ struct pl08x_dma_chan {
  * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
  * fetches
  * @mem_buses: set to indicate memory transfers on AHB2.
- * @lock: a spinlock for this struct
+ * @lli_words: how many words are used in each LLI item for this variant
  */
 struct pl08x_driver_data {
         struct dma_device slave;
@@ -417,7 +419,7 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
 
         /* Enable the DMA channel */
         /* Do not access config register until channel shows as disabled */
-        while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
+        while (readl(pl08x->base + PL080_EN_CHAN) & BIT(phychan->id))
                 cpu_relax();
 
         /* Do not access config register until channel shows as inactive */
@@ -484,8 +486,8 @@ static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
 
         writel(val, ch->reg_config);
 
-        writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR);
-        writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR);
+        writel(BIT(ch->id), pl08x->base + PL080_ERR_CLEAR);
+        writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR);
 }
 
 static inline u32 get_bytes_in_cctl(u32 cctl)
@@ -1834,7 +1836,7 @@ static irqreturn_t pl08x_irq(int irq, void *dev)
                 return IRQ_NONE;
 
         for (i = 0; i < pl08x->vd->channels; i++) {
-                if (((1 << i) & err) || ((1 << i) & tc)) {
+                if ((BIT(i) & err) || (BIT(i) & tc)) {
                         /* Locate physical channel */
                         struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
                         struct pl08x_dma_chan *plchan = phychan->serving;
@@ -1872,7 +1874,7 @@ static irqreturn_t pl08x_irq(int irq, void *dev)
                         }
                         spin_unlock(&plchan->vc.lock);
 
-                        mask |= (1 << i);
+                        mask |= BIT(i);
                 }
         }
 
diff --git a/include/linux/amba/pl080.h b/include/linux/amba/pl080.h
index 91b84a7f0539..580b5323a717 100644
--- a/include/linux/amba/pl080.h
+++ b/include/linux/amba/pl080.h
@@ -38,24 +38,16 @@
 #define PL080_SOFT_LSREQ                        (0x2C)
 
 #define PL080_CONFIG                            (0x30)
-#define PL080_CONFIG_M2_BE                      (1 << 2)
-#define PL080_CONFIG_M1_BE                      (1 << 1)
-#define PL080_CONFIG_ENABLE                     (1 << 0)
+#define PL080_CONFIG_M2_BE                      BIT(2)
+#define PL080_CONFIG_M1_BE                      BIT(1)
+#define PL080_CONFIG_ENABLE                     BIT(0)
 
 #define PL080_SYNC                              (0x34)
 
 /* Per channel configuration registers */
 
-#define PL080_Cx_STRIDE                         (0x20)
+/* Per channel configuration registers */
 #define PL080_Cx_BASE(x)                        ((0x100 + (x * 0x20)))
-#define PL080_Cx_SRC_ADDR(x)                    ((0x100 + (x * 0x20)))
-#define PL080_Cx_DST_ADDR(x)                    ((0x104 + (x * 0x20)))
-#define PL080_Cx_LLI(x)                         ((0x108 + (x * 0x20)))
-#define PL080_Cx_CONTROL(x)                     ((0x10C + (x * 0x20)))
-#define PL080_Cx_CONFIG(x)                      ((0x110 + (x * 0x20)))
-#define PL080S_Cx_CONTROL2(x)                   ((0x110 + (x * 0x20)))
-#define PL080S_Cx_CONFIG(x)                     ((0x114 + (x * 0x20)))
-
 #define PL080_CH_SRC_ADDR                       (0x00)
 #define PL080_CH_DST_ADDR                       (0x04)
 #define PL080_CH_LLI                            (0x08)
@@ -66,18 +58,18 @@
 
 #define PL080_LLI_ADDR_MASK                     (0x3fffffff << 2)
 #define PL080_LLI_ADDR_SHIFT                    (2)
-#define PL080_LLI_LM_AHB2                       (1 << 0)
+#define PL080_LLI_LM_AHB2                       BIT(0)
 
-#define PL080_CONTROL_TC_IRQ_EN                 (1 << 31)
+#define PL080_CONTROL_TC_IRQ_EN                 BIT(31)
 #define PL080_CONTROL_PROT_MASK                 (0x7 << 28)
 #define PL080_CONTROL_PROT_SHIFT                (28)
-#define PL080_CONTROL_PROT_CACHE                (1 << 30)
-#define PL080_CONTROL_PROT_BUFF                 (1 << 29)
-#define PL080_CONTROL_PROT_SYS                  (1 << 28)
-#define PL080_CONTROL_DST_INCR                  (1 << 27)
-#define PL080_CONTROL_SRC_INCR                  (1 << 26)
-#define PL080_CONTROL_DST_AHB2                  (1 << 25)
-#define PL080_CONTROL_SRC_AHB2                  (1 << 24)
+#define PL080_CONTROL_PROT_CACHE                BIT(30)
+#define PL080_CONTROL_PROT_BUFF                 BIT(29)
+#define PL080_CONTROL_PROT_SYS                  BIT(28)
+#define PL080_CONTROL_DST_INCR                  BIT(27)
+#define PL080_CONTROL_SRC_INCR                  BIT(26)
+#define PL080_CONTROL_DST_AHB2                  BIT(25)
+#define PL080_CONTROL_SRC_AHB2                  BIT(24)
 #define PL080_CONTROL_DWIDTH_MASK               (0x7 << 21)
 #define PL080_CONTROL_DWIDTH_SHIFT              (21)
 #define PL080_CONTROL_SWIDTH_MASK               (0x7 << 18)
@@ -103,20 +95,20 @@
 #define PL080_WIDTH_16BIT                       (0x1)
 #define PL080_WIDTH_32BIT                       (0x2)
 
-#define PL080N_CONFIG_ITPROT                    (1 << 20)
-#define PL080N_CONFIG_SECPROT                   (1 << 19)
-#define PL080_CONFIG_HALT                       (1 << 18)
-#define PL080_CONFIG_ACTIVE                     (1 << 17)  /* RO */
-#define PL080_CONFIG_LOCK                       (1 << 16)
-#define PL080_CONFIG_TC_IRQ_MASK                (1 << 15)
-#define PL080_CONFIG_ERR_IRQ_MASK               (1 << 14)
+#define PL080N_CONFIG_ITPROT                    BIT(20)
+#define PL080N_CONFIG_SECPROT                   BIT(19)
+#define PL080_CONFIG_HALT                       BIT(18)
+#define PL080_CONFIG_ACTIVE                     BIT(17)  /* RO */
+#define PL080_CONFIG_LOCK                       BIT(16)
+#define PL080_CONFIG_TC_IRQ_MASK                BIT(15)
+#define PL080_CONFIG_ERR_IRQ_MASK               BIT(14)
 #define PL080_CONFIG_FLOW_CONTROL_MASK          (0x7 << 11)
 #define PL080_CONFIG_FLOW_CONTROL_SHIFT         (11)
 #define PL080_CONFIG_DST_SEL_MASK               (0xf << 6)
 #define PL080_CONFIG_DST_SEL_SHIFT              (6)
 #define PL080_CONFIG_SRC_SEL_MASK               (0xf << 1)
 #define PL080_CONFIG_SRC_SEL_SHIFT              (1)
-#define PL080_CONFIG_ENABLE                     (1 << 0)
+#define PL080_CONFIG_ENABLE                     BIT(0)
 
 #define PL080_FLOW_MEM2MEM                      (0x0)
 #define PL080_FLOW_MEM2PER                      (0x1)