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-rw-r--r--Documentation/ABI/stable/sysfs-driver-mlxreg-io14
-rw-r--r--MAINTAINERS1
-rw-r--r--drivers/acpi/scan.c1
-rw-r--r--drivers/leds/leds-mlxreg.c19
-rw-r--r--drivers/platform/mellanox/mlxreg-hotplug.c28
-rw-r--r--drivers/platform/x86/asus-wmi.c9
-rw-r--r--drivers/platform/x86/dell-smbios-wmi.c2
-rw-r--r--drivers/platform/x86/dell-wmi-descriptor.c2
-rw-r--r--drivers/platform/x86/dell-wmi.c7
-rw-r--r--drivers/platform/x86/dell_rbu.c50
-rw-r--r--drivers/platform/x86/huawei-wmi.c3
-rw-r--r--drivers/platform/x86/i2c-multi-instantiate.c9
-rw-r--r--drivers/platform/x86/ideapad-laptop.c37
-rw-r--r--drivers/platform/x86/intel-hid.c7
-rw-r--r--drivers/platform/x86/intel-wmi-thunderbolt.c2
-rw-r--r--drivers/platform/x86/intel_int0002_vgpio.c32
-rw-r--r--drivers/platform/x86/intel_pmc_core.c159
-rw-r--r--drivers/platform/x86/intel_pmc_core.h14
-rw-r--r--drivers/platform/x86/mlx-platform.c105
-rw-r--r--drivers/platform/x86/touchscreen_dmi.c79
-rw-r--r--drivers/platform/x86/wmi-bmof.c2
-rw-r--r--drivers/platform/x86/wmi.c5
-rw-r--r--include/linux/mod_devicetable.h12
-rw-r--r--include/linux/platform_data/mlxreg.h6
-rw-r--r--include/linux/wmi.h5
-rw-r--r--scripts/mod/devicetable-offsets.c3
-rw-r--r--scripts/mod/file2alias.c28
27 files changed, 541 insertions, 100 deletions
diff --git a/Documentation/ABI/stable/sysfs-driver-mlxreg-io b/Documentation/ABI/stable/sysfs-driver-mlxreg-io
index 169fe08a649b..156319fc5b80 100644
--- a/Documentation/ABI/stable/sysfs-driver-mlxreg-io
+++ b/Documentation/ABI/stable/sysfs-driver-mlxreg-io
@@ -21,7 +21,19 @@ Description: These files show with which CPLD versions have been burned
21 The files are read only. 21 The files are read only.
22 22
23What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/ 23What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/
24 cpld3_version 24 fan_dir
25
26Date: December 2018
27KernelVersion: 5.0
28Contact: Vadim Pasternak <vadimpmellanox.com>
29Description: This file shows the system fans direction:
30 forward direction - relevant bit is set 0;
31 reversed direction - relevant bit is set 1.
32
33 The files are read only.
34
35What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/
36 jtag_enable
25 37
26Date: November 2018 38Date: November 2018
27KernelVersion: 5.0 39KernelVersion: 5.0
diff --git a/MAINTAINERS b/MAINTAINERS
index 08995da6e16a..17b59b66474b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9900,6 +9900,7 @@ M: Vadim Pasternak <vadimp@mellanox.com>
9900L: platform-driver-x86@vger.kernel.org 9900L: platform-driver-x86@vger.kernel.org
9901S: Supported 9901S: Supported
9902F: drivers/platform/mellanox/ 9902F: drivers/platform/mellanox/
9903F: include/linux/platform_data/mlxreg.h
9903 9904
9904MELLANOX MLX4 core VPI driver 9905MELLANOX MLX4 core VPI driver
9905M: Tariq Toukan <tariqt@mellanox.com> 9906M: Tariq Toukan <tariqt@mellanox.com>
diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c
index 5efd4219f112..446c959a8f08 100644
--- a/drivers/acpi/scan.c
+++ b/drivers/acpi/scan.c
@@ -1545,6 +1545,7 @@ static bool acpi_device_enumeration_by_parent(struct acpi_device *device)
1545 */ 1545 */
1546 static const struct acpi_device_id i2c_multi_instantiate_ids[] = { 1546 static const struct acpi_device_id i2c_multi_instantiate_ids[] = {
1547 {"BSG1160", }, 1547 {"BSG1160", },
1548 {"BSG2150", },
1548 {"INT33FE", }, 1549 {"INT33FE", },
1549 {"INT3515", }, 1550 {"INT3515", },
1550 {} 1551 {}
diff --git a/drivers/leds/leds-mlxreg.c b/drivers/leds/leds-mlxreg.c
index 1ee48cb21df9..cabe379071a7 100644
--- a/drivers/leds/leds-mlxreg.c
+++ b/drivers/leds/leds-mlxreg.c
@@ -22,6 +22,7 @@
22#define MLXREG_LED_AMBER_SOLID 0x09 /* Solid amber */ 22#define MLXREG_LED_AMBER_SOLID 0x09 /* Solid amber */
23#define MLXREG_LED_BLINK_3HZ 167 /* ~167 msec off/on - HW support */ 23#define MLXREG_LED_BLINK_3HZ 167 /* ~167 msec off/on - HW support */
24#define MLXREG_LED_BLINK_6HZ 83 /* ~83 msec off/on - HW support */ 24#define MLXREG_LED_BLINK_6HZ 83 /* ~83 msec off/on - HW support */
25#define MLXREG_LED_CAPABILITY_CLEAR GENMASK(31, 8) /* Clear mask */
25 26
26/** 27/**
27 * struct mlxreg_led_data - led control data: 28 * struct mlxreg_led_data - led control data:
@@ -187,6 +188,7 @@ static int mlxreg_led_config(struct mlxreg_led_priv_data *priv)
187 struct mlxreg_led_data *led_data; 188 struct mlxreg_led_data *led_data;
188 struct led_classdev *led_cdev; 189 struct led_classdev *led_cdev;
189 enum led_brightness brightness; 190 enum led_brightness brightness;
191 u32 regval;
190 int i; 192 int i;
191 int err; 193 int err;
192 194
@@ -196,6 +198,23 @@ static int mlxreg_led_config(struct mlxreg_led_priv_data *priv)
196 if (!led_data) 198 if (!led_data)
197 return -ENOMEM; 199 return -ENOMEM;
198 200
201 if (data->capability) {
202 err = regmap_read(led_pdata->regmap, data->capability,
203 &regval);
204 if (err) {
205 dev_err(&priv->pdev->dev, "Failed to query capability register\n");
206 return err;
207 }
208 if (!(regval & data->bit))
209 continue;
210 /*
211 * Field "bit" can contain one capability bit in 0 byte
212 * and offset bit in 1-3 bytes. Clear capability bit and
213 * keep only offset bit.
214 */
215 data->bit &= MLXREG_LED_CAPABILITY_CLEAR;
216 }
217
199 led_cdev = &led_data->led_cdev; 218 led_cdev = &led_data->led_cdev;
200 led_data->data_parent = priv; 219 led_data->data_parent = priv;
201 if (strstr(data->label, "red") || 220 if (strstr(data->label, "red") ||
diff --git a/drivers/platform/mellanox/mlxreg-hotplug.c b/drivers/platform/mellanox/mlxreg-hotplug.c
index b6d44550d98c..687ce6817d0d 100644
--- a/drivers/platform/mellanox/mlxreg-hotplug.c
+++ b/drivers/platform/mellanox/mlxreg-hotplug.c
@@ -248,7 +248,8 @@ mlxreg_hotplug_work_helper(struct mlxreg_hotplug_priv_data *priv,
248 struct mlxreg_core_item *item) 248 struct mlxreg_core_item *item)
249{ 249{
250 struct mlxreg_core_data *data; 250 struct mlxreg_core_data *data;
251 u32 asserted, regval, bit; 251 unsigned long asserted;
252 u32 regval, bit;
252 int ret; 253 int ret;
253 254
254 /* 255 /*
@@ -281,7 +282,7 @@ mlxreg_hotplug_work_helper(struct mlxreg_hotplug_priv_data *priv,
281 asserted = item->cache ^ regval; 282 asserted = item->cache ^ regval;
282 item->cache = regval; 283 item->cache = regval;
283 284
284 for_each_set_bit(bit, (unsigned long *)&asserted, 8) { 285 for_each_set_bit(bit, &asserted, 8) {
285 data = item->data + bit; 286 data = item->data + bit;
286 if (regval & BIT(bit)) { 287 if (regval & BIT(bit)) {
287 if (item->inversed) 288 if (item->inversed)
@@ -495,7 +496,9 @@ static int mlxreg_hotplug_set_irq(struct mlxreg_hotplug_priv_data *priv)
495{ 496{
496 struct mlxreg_core_hotplug_platform_data *pdata; 497 struct mlxreg_core_hotplug_platform_data *pdata;
497 struct mlxreg_core_item *item; 498 struct mlxreg_core_item *item;
498 int i, ret; 499 struct mlxreg_core_data *data;
500 u32 regval;
501 int i, j, ret;
499 502
500 pdata = dev_get_platdata(&priv->pdev->dev); 503 pdata = dev_get_platdata(&priv->pdev->dev);
501 item = pdata->items; 504 item = pdata->items;
@@ -507,6 +510,25 @@ static int mlxreg_hotplug_set_irq(struct mlxreg_hotplug_priv_data *priv)
507 if (ret) 510 if (ret)
508 goto out; 511 goto out;
509 512
513 /*
514 * Verify if hardware configuration requires to disable
515 * interrupt capability for some of components.
516 */
517 data = item->data;
518 for (j = 0; j < item->count; j++, data++) {
519 /* Verify if the attribute has capability register. */
520 if (data->capability) {
521 /* Read capability register. */
522 ret = regmap_read(priv->regmap,
523 data->capability, &regval);
524 if (ret)
525 goto out;
526
527 if (!(regval & data->bit))
528 item->mask &= ~BIT(j);
529 }
530 }
531
510 /* Set group initial status as mask and unmask group event. */ 532 /* Set group initial status as mask and unmask group event. */
511 if (item->inversed) { 533 if (item->inversed) {
512 item->cache = item->mask; 534 item->cache = item->mask;
diff --git a/drivers/platform/x86/asus-wmi.c b/drivers/platform/x86/asus-wmi.c
index 37b5de541270..ee1fa93708ec 100644
--- a/drivers/platform/x86/asus-wmi.c
+++ b/drivers/platform/x86/asus-wmi.c
@@ -2265,12 +2265,12 @@ static int asus_wmi_probe(struct platform_device *pdev)
2265 int ret; 2265 int ret;
2266 2266
2267 if (!wmi_has_guid(ASUS_WMI_MGMT_GUID)) { 2267 if (!wmi_has_guid(ASUS_WMI_MGMT_GUID)) {
2268 pr_warn("Management GUID not found\n"); 2268 pr_warn("ASUS Management GUID not found\n");
2269 return -ENODEV; 2269 return -ENODEV;
2270 } 2270 }
2271 2271
2272 if (wdrv->event_guid && !wmi_has_guid(wdrv->event_guid)) { 2272 if (wdrv->event_guid && !wmi_has_guid(wdrv->event_guid)) {
2273 pr_warn("Event GUID not found\n"); 2273 pr_warn("ASUS Event GUID not found\n");
2274 return -ENODEV; 2274 return -ENODEV;
2275 } 2275 }
2276 2276
@@ -2320,11 +2320,6 @@ EXPORT_SYMBOL_GPL(asus_wmi_unregister_driver);
2320 2320
2321static int __init asus_wmi_init(void) 2321static int __init asus_wmi_init(void)
2322{ 2322{
2323 if (!wmi_has_guid(ASUS_WMI_MGMT_GUID)) {
2324 pr_info("Asus Management GUID not found\n");
2325 return -ENODEV;
2326 }
2327
2328 pr_info("ASUS WMI generic driver loaded\n"); 2323 pr_info("ASUS WMI generic driver loaded\n");
2329 return 0; 2324 return 0;
2330} 2325}
diff --git a/drivers/platform/x86/dell-smbios-wmi.c b/drivers/platform/x86/dell-smbios-wmi.c
index cf2229ece9ff..c3ed3c8c17b9 100644
--- a/drivers/platform/x86/dell-smbios-wmi.c
+++ b/drivers/platform/x86/dell-smbios-wmi.c
@@ -277,4 +277,4 @@ void exit_dell_smbios_wmi(void)
277 wmi_driver_unregister(&dell_smbios_wmi_driver); 277 wmi_driver_unregister(&dell_smbios_wmi_driver);
278} 278}
279 279
280MODULE_ALIAS("wmi:" DELL_WMI_SMBIOS_GUID); 280MODULE_DEVICE_TABLE(wmi, dell_smbios_wmi_id_table);
diff --git a/drivers/platform/x86/dell-wmi-descriptor.c b/drivers/platform/x86/dell-wmi-descriptor.c
index 072821aa47fc..14ab250b7d5a 100644
--- a/drivers/platform/x86/dell-wmi-descriptor.c
+++ b/drivers/platform/x86/dell-wmi-descriptor.c
@@ -207,7 +207,7 @@ static struct wmi_driver dell_wmi_descriptor_driver = {
207 207
208module_wmi_driver(dell_wmi_descriptor_driver); 208module_wmi_driver(dell_wmi_descriptor_driver);
209 209
210MODULE_ALIAS("wmi:" DELL_WMI_DESCRIPTOR_GUID); 210MODULE_DEVICE_TABLE(wmi, dell_wmi_descriptor_id_table);
211MODULE_AUTHOR("Mario Limonciello <mario.limonciello@dell.com>"); 211MODULE_AUTHOR("Mario Limonciello <mario.limonciello@dell.com>");
212MODULE_DESCRIPTION("Dell WMI descriptor driver"); 212MODULE_DESCRIPTION("Dell WMI descriptor driver");
213MODULE_LICENSE("GPL"); 213MODULE_LICENSE("GPL");
diff --git a/drivers/platform/x86/dell-wmi.c b/drivers/platform/x86/dell-wmi.c
index 16c7f3d9a335..d118bb73fcae 100644
--- a/drivers/platform/x86/dell-wmi.c
+++ b/drivers/platform/x86/dell-wmi.c
@@ -50,8 +50,6 @@ MODULE_LICENSE("GPL");
50 50
51static bool wmi_requires_smbios_request; 51static bool wmi_requires_smbios_request;
52 52
53MODULE_ALIAS("wmi:"DELL_EVENT_GUID);
54
55struct dell_wmi_priv { 53struct dell_wmi_priv {
56 struct input_dev *input_dev; 54 struct input_dev *input_dev;
57 u32 interface_version; 55 u32 interface_version;
@@ -267,6 +265,9 @@ static const struct key_entry dell_wmi_keymap_type_0010[] = {
267 /* Fn-lock switched to multimedia keys */ 265 /* Fn-lock switched to multimedia keys */
268 { KE_IGNORE, 0x1, { KEY_RESERVED } }, 266 { KE_IGNORE, 0x1, { KEY_RESERVED } },
269 267
268 /* Keyboard backlight change notification */
269 { KE_IGNORE, 0x3f, { KEY_RESERVED } },
270
270 /* Mic mute */ 271 /* Mic mute */
271 { KE_KEY, 0x150, { KEY_MICMUTE } }, 272 { KE_KEY, 0x150, { KEY_MICMUTE } },
272 273
@@ -738,3 +739,5 @@ static void __exit dell_wmi_exit(void)
738 wmi_driver_unregister(&dell_wmi_driver); 739 wmi_driver_unregister(&dell_wmi_driver);
739} 740}
740module_exit(dell_wmi_exit); 741module_exit(dell_wmi_exit);
742
743MODULE_DEVICE_TABLE(wmi, dell_wmi_id_table);
diff --git a/drivers/platform/x86/dell_rbu.c b/drivers/platform/x86/dell_rbu.c
index ccefa84f7305..031c68903583 100644
--- a/drivers/platform/x86/dell_rbu.c
+++ b/drivers/platform/x86/dell_rbu.c
@@ -59,7 +59,6 @@ static struct _rbu_data {
59 unsigned long image_update_buffer_size; 59 unsigned long image_update_buffer_size;
60 unsigned long bios_image_size; 60 unsigned long bios_image_size;
61 int image_update_ordernum; 61 int image_update_ordernum;
62 int dma_alloc;
63 spinlock_t lock; 62 spinlock_t lock;
64 unsigned long packet_read_count; 63 unsigned long packet_read_count;
65 unsigned long num_packets; 64 unsigned long num_packets;
@@ -89,7 +88,6 @@ static struct packet_data packet_data_head;
89 88
90static struct platform_device *rbu_device; 89static struct platform_device *rbu_device;
91static int context; 90static int context;
92static dma_addr_t dell_rbu_dmaaddr;
93 91
94static void init_packet_head(void) 92static void init_packet_head(void)
95{ 93{
@@ -380,12 +378,8 @@ static void img_update_free(void)
380 */ 378 */
381 memset(rbu_data.image_update_buffer, 0, 379 memset(rbu_data.image_update_buffer, 0,
382 rbu_data.image_update_buffer_size); 380 rbu_data.image_update_buffer_size);
383 if (rbu_data.dma_alloc == 1) 381 free_pages((unsigned long) rbu_data.image_update_buffer,
384 dma_free_coherent(NULL, rbu_data.bios_image_size, 382 rbu_data.image_update_ordernum);
385 rbu_data.image_update_buffer, dell_rbu_dmaaddr);
386 else
387 free_pages((unsigned long) rbu_data.image_update_buffer,
388 rbu_data.image_update_ordernum);
389 383
390 /* 384 /*
391 * Re-initialize the rbu_data variables after a free 385 * Re-initialize the rbu_data variables after a free
@@ -394,7 +388,6 @@ static void img_update_free(void)
394 rbu_data.image_update_buffer = NULL; 388 rbu_data.image_update_buffer = NULL;
395 rbu_data.image_update_buffer_size = 0; 389 rbu_data.image_update_buffer_size = 0;
396 rbu_data.bios_image_size = 0; 390 rbu_data.bios_image_size = 0;
397 rbu_data.dma_alloc = 0;
398} 391}
399 392
400/* 393/*
@@ -410,10 +403,8 @@ static void img_update_free(void)
410static int img_update_realloc(unsigned long size) 403static int img_update_realloc(unsigned long size)
411{ 404{
412 unsigned char *image_update_buffer = NULL; 405 unsigned char *image_update_buffer = NULL;
413 unsigned long rc;
414 unsigned long img_buf_phys_addr; 406 unsigned long img_buf_phys_addr;
415 int ordernum; 407 int ordernum;
416 int dma_alloc = 0;
417 408
418 /* 409 /*
419 * check if the buffer of sufficient size has been 410 * check if the buffer of sufficient size has been
@@ -444,36 +435,23 @@ static int img_update_realloc(unsigned long size)
444 435
445 ordernum = get_order(size); 436 ordernum = get_order(size);
446 image_update_buffer = 437 image_update_buffer =
447 (unsigned char *) __get_free_pages(GFP_KERNEL, ordernum); 438 (unsigned char *)__get_free_pages(GFP_DMA32, ordernum);
448
449 img_buf_phys_addr =
450 (unsigned long) virt_to_phys(image_update_buffer);
451
452 if (img_buf_phys_addr > BIOS_SCAN_LIMIT) {
453 free_pages((unsigned long) image_update_buffer, ordernum);
454 ordernum = -1;
455 image_update_buffer = dma_alloc_coherent(NULL, size,
456 &dell_rbu_dmaaddr, GFP_KERNEL);
457 dma_alloc = 1;
458 }
459
460 spin_lock(&rbu_data.lock); 439 spin_lock(&rbu_data.lock);
461 440 if (!image_update_buffer) {
462 if (image_update_buffer != NULL) {
463 rbu_data.image_update_buffer = image_update_buffer;
464 rbu_data.image_update_buffer_size = size;
465 rbu_data.bios_image_size =
466 rbu_data.image_update_buffer_size;
467 rbu_data.image_update_ordernum = ordernum;
468 rbu_data.dma_alloc = dma_alloc;
469 rc = 0;
470 } else {
471 pr_debug("Not enough memory for image update:" 441 pr_debug("Not enough memory for image update:"
472 "size = %ld\n", size); 442 "size = %ld\n", size);
473 rc = -ENOMEM; 443 return -ENOMEM;
474 } 444 }
475 445
476 return rc; 446 img_buf_phys_addr = (unsigned long)virt_to_phys(image_update_buffer);
447 if (WARN_ON_ONCE(img_buf_phys_addr > BIOS_SCAN_LIMIT))
448 return -EINVAL; /* can't happen per definition */
449
450 rbu_data.image_update_buffer = image_update_buffer;
451 rbu_data.image_update_buffer_size = size;
452 rbu_data.bios_image_size = rbu_data.image_update_buffer_size;
453 rbu_data.image_update_ordernum = ordernum;
454 return 0;
477} 455}
478 456
479static ssize_t read_packet_data(char *buffer, loff_t pos, size_t count) 457static ssize_t read_packet_data(char *buffer, loff_t pos, size_t count)
diff --git a/drivers/platform/x86/huawei-wmi.c b/drivers/platform/x86/huawei-wmi.c
index 59872f87b741..52fcac5b393a 100644
--- a/drivers/platform/x86/huawei-wmi.c
+++ b/drivers/platform/x86/huawei-wmi.c
@@ -201,8 +201,7 @@ static struct wmi_driver huawei_wmi_driver = {
201 201
202module_wmi_driver(huawei_wmi_driver); 202module_wmi_driver(huawei_wmi_driver);
203 203
204MODULE_ALIAS("wmi:"WMI0_EVENT_GUID); 204MODULE_DEVICE_TABLE(wmi, huawei_wmi_id_table);
205MODULE_ALIAS("wmi:"AMW0_EVENT_GUID);
206MODULE_AUTHOR("Ayman Bagabas <ayman.bagabas@gmail.com>"); 205MODULE_AUTHOR("Ayman Bagabas <ayman.bagabas@gmail.com>");
207MODULE_DESCRIPTION("Huawei WMI hotkeys"); 206MODULE_DESCRIPTION("Huawei WMI hotkeys");
208MODULE_LICENSE("GPL v2"); 207MODULE_LICENSE("GPL v2");
diff --git a/drivers/platform/x86/i2c-multi-instantiate.c b/drivers/platform/x86/i2c-multi-instantiate.c
index 3d893e0ac250..197d8a192721 100644
--- a/drivers/platform/x86/i2c-multi-instantiate.c
+++ b/drivers/platform/x86/i2c-multi-instantiate.c
@@ -159,6 +159,14 @@ static const struct i2c_inst_data bsg1160_data[] = {
159 {} 159 {}
160}; 160};
161 161
162static const struct i2c_inst_data bsg2150_data[] = {
163 { "bmc150_accel", IRQ_RESOURCE_GPIO, 0 },
164 { "bmc150_magn" },
165 /* The resources describe a 3th client, but it is not really there. */
166 { "bsg2150_dummy_dev" },
167 {}
168};
169
162static const struct i2c_inst_data int3515_data[] = { 170static const struct i2c_inst_data int3515_data[] = {
163 { "tps6598x", IRQ_RESOURCE_APIC, 0 }, 171 { "tps6598x", IRQ_RESOURCE_APIC, 0 },
164 { "tps6598x", IRQ_RESOURCE_APIC, 1 }, 172 { "tps6598x", IRQ_RESOURCE_APIC, 1 },
@@ -173,6 +181,7 @@ static const struct i2c_inst_data int3515_data[] = {
173 */ 181 */
174static const struct acpi_device_id i2c_multi_inst_acpi_ids[] = { 182static const struct acpi_device_id i2c_multi_inst_acpi_ids[] = {
175 { "BSG1160", (unsigned long)bsg1160_data }, 183 { "BSG1160", (unsigned long)bsg1160_data },
184 { "BSG2150", (unsigned long)bsg2150_data },
176 { "INT3515", (unsigned long)int3515_data }, 185 { "INT3515", (unsigned long)int3515_data },
177 { } 186 { }
178}; 187};
diff --git a/drivers/platform/x86/ideapad-laptop.c b/drivers/platform/x86/ideapad-laptop.c
index 1589dffab9fa..c53ae86b59c7 100644
--- a/drivers/platform/x86/ideapad-laptop.c
+++ b/drivers/platform/x86/ideapad-laptop.c
@@ -989,7 +989,7 @@ static const struct dmi_system_id no_hw_rfkill_list[] = {
989 .ident = "Lenovo RESCUER R720-15IKBN", 989 .ident = "Lenovo RESCUER R720-15IKBN",
990 .matches = { 990 .matches = {
991 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 991 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
992 DMI_MATCH(DMI_BOARD_NAME, "80WW"), 992 DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo R720-15IKBN"),
993 }, 993 },
994 }, 994 },
995 { 995 {
@@ -1091,6 +1091,27 @@ static const struct dmi_system_id no_hw_rfkill_list[] = {
1091 }, 1091 },
1092 }, 1092 },
1093 { 1093 {
1094 .ident = "Lenovo ideapad 330-15ICH",
1095 .matches = {
1096 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1097 DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo ideapad 330-15ICH"),
1098 },
1099 },
1100 {
1101 .ident = "Lenovo ideapad 530S-14ARR",
1102 .matches = {
1103 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1104 DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo ideapad 530S-14ARR"),
1105 },
1106 },
1107 {
1108 .ident = "Lenovo ideapad S130-14IGM",
1109 .matches = {
1110 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1111 DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo ideapad S130-14IGM"),
1112 },
1113 },
1114 {
1094 .ident = "Lenovo ideapad Y700-14ISK", 1115 .ident = "Lenovo ideapad Y700-14ISK",
1095 .matches = { 1116 .matches = {
1096 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1117 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
@@ -1154,6 +1175,13 @@ static const struct dmi_system_id no_hw_rfkill_list[] = {
1154 }, 1175 },
1155 }, 1176 },
1156 { 1177 {
1178 .ident = "Lenovo Legion Y530-15ICH-1060",
1179 .matches = {
1180 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1181 DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo Legion Y530-15ICH-1060"),
1182 },
1183 },
1184 {
1157 .ident = "Lenovo Legion Y720-15IKB", 1185 .ident = "Lenovo Legion Y720-15IKB",
1158 .matches = { 1186 .matches = {
1159 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1187 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
@@ -1245,6 +1273,13 @@ static const struct dmi_system_id no_hw_rfkill_list[] = {
1245 }, 1273 },
1246 }, 1274 },
1247 { 1275 {
1276 .ident = "Lenovo YOGA C930-13IKB",
1277 .matches = {
1278 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1279 DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo YOGA C930-13IKB"),
1280 },
1281 },
1282 {
1248 .ident = "Lenovo Zhaoyang E42-80", 1283 .ident = "Lenovo Zhaoyang E42-80",
1249 .matches = { 1284 .matches = {
1250 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 1285 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
diff --git a/drivers/platform/x86/intel-hid.c b/drivers/platform/x86/intel-hid.c
index e28bcf61b126..bc0d55a59015 100644
--- a/drivers/platform/x86/intel-hid.c
+++ b/drivers/platform/x86/intel-hid.c
@@ -363,7 +363,7 @@ wakeup:
363 * the 5-button array, but still send notifies with power button 363 * the 5-button array, but still send notifies with power button
364 * event code to this device object on power button actions. 364 * event code to this device object on power button actions.
365 * 365 *
366 * Report the power button press; catch and ignore the button release. 366 * Report the power button press and release.
367 */ 367 */
368 if (!priv->array) { 368 if (!priv->array) {
369 if (event == 0xce) { 369 if (event == 0xce) {
@@ -372,8 +372,11 @@ wakeup:
372 return; 372 return;
373 } 373 }
374 374
375 if (event == 0xcf) 375 if (event == 0xcf) {
376 input_report_key(priv->input_dev, KEY_POWER, 0);
377 input_sync(priv->input_dev);
376 return; 378 return;
379 }
377 } 380 }
378 381
379 /* 0xC0 is for HID events, other values are for 5 button array */ 382 /* 0xC0 is for HID events, other values are for 5 button array */
diff --git a/drivers/platform/x86/intel-wmi-thunderbolt.c b/drivers/platform/x86/intel-wmi-thunderbolt.c
index 9ded8e2af312..4dfa61434a76 100644
--- a/drivers/platform/x86/intel-wmi-thunderbolt.c
+++ b/drivers/platform/x86/intel-wmi-thunderbolt.c
@@ -88,7 +88,7 @@ static struct wmi_driver intel_wmi_thunderbolt_driver = {
88 88
89module_wmi_driver(intel_wmi_thunderbolt_driver); 89module_wmi_driver(intel_wmi_thunderbolt_driver);
90 90
91MODULE_ALIAS("wmi:" INTEL_WMI_THUNDERBOLT_GUID); 91MODULE_DEVICE_TABLE(wmi, intel_wmi_thunderbolt_id_table);
92MODULE_AUTHOR("Mario Limonciello <mario.limonciello@dell.com>"); 92MODULE_AUTHOR("Mario Limonciello <mario.limonciello@dell.com>");
93MODULE_DESCRIPTION("Intel WMI Thunderbolt force power driver"); 93MODULE_DESCRIPTION("Intel WMI Thunderbolt force power driver");
94MODULE_LICENSE("GPL v2"); 94MODULE_LICENSE("GPL v2");
diff --git a/drivers/platform/x86/intel_int0002_vgpio.c b/drivers/platform/x86/intel_int0002_vgpio.c
index 4b8f7305fc8a..1694a9aec77c 100644
--- a/drivers/platform/x86/intel_int0002_vgpio.c
+++ b/drivers/platform/x86/intel_int0002_vgpio.c
@@ -51,11 +51,14 @@
51#define GPE0A_STS_PORT 0x420 51#define GPE0A_STS_PORT 0x420
52#define GPE0A_EN_PORT 0x428 52#define GPE0A_EN_PORT 0x428
53 53
54#define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, } 54#define BAYTRAIL 0x01
55#define CHERRYTRAIL 0x02
56
57#define ICPU(model, data) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, data }
55 58
56static const struct x86_cpu_id int0002_cpu_ids[] = { 59static const struct x86_cpu_id int0002_cpu_ids[] = {
57 ICPU(INTEL_FAM6_ATOM_SILVERMONT), /* Valleyview, Bay Trail */ 60 ICPU(INTEL_FAM6_ATOM_SILVERMONT, BAYTRAIL), /* Valleyview, Bay Trail */
58 ICPU(INTEL_FAM6_ATOM_AIRMONT), /* Braswell, Cherry Trail */ 61 ICPU(INTEL_FAM6_ATOM_AIRMONT, CHERRYTRAIL), /* Braswell, Cherry Trail */
59 {} 62 {}
60}; 63};
61 64
@@ -135,7 +138,7 @@ static irqreturn_t int0002_irq(int irq, void *data)
135 return IRQ_HANDLED; 138 return IRQ_HANDLED;
136} 139}
137 140
138static struct irq_chip int0002_irqchip = { 141static struct irq_chip int0002_byt_irqchip = {
139 .name = DRV_NAME, 142 .name = DRV_NAME,
140 .irq_ack = int0002_irq_ack, 143 .irq_ack = int0002_irq_ack,
141 .irq_mask = int0002_irq_mask, 144 .irq_mask = int0002_irq_mask,
@@ -143,10 +146,22 @@ static struct irq_chip int0002_irqchip = {
143 .irq_set_wake = int0002_irq_set_wake, 146 .irq_set_wake = int0002_irq_set_wake,
144}; 147};
145 148
149static struct irq_chip int0002_cht_irqchip = {
150 .name = DRV_NAME,
151 .irq_ack = int0002_irq_ack,
152 .irq_mask = int0002_irq_mask,
153 .irq_unmask = int0002_irq_unmask,
154 /*
155 * No set_wake, on CHT the IRQ is typically shared with the ACPI SCI
156 * and we don't want to mess with the ACPI SCI irq settings.
157 */
158};
159
146static int int0002_probe(struct platform_device *pdev) 160static int int0002_probe(struct platform_device *pdev)
147{ 161{
148 struct device *dev = &pdev->dev; 162 struct device *dev = &pdev->dev;
149 const struct x86_cpu_id *cpu_id; 163 const struct x86_cpu_id *cpu_id;
164 struct irq_chip *irq_chip;
150 struct gpio_chip *chip; 165 struct gpio_chip *chip;
151 int irq, ret; 166 int irq, ret;
152 167
@@ -195,14 +210,19 @@ static int int0002_probe(struct platform_device *pdev)
195 return ret; 210 return ret;
196 } 211 }
197 212
198 ret = gpiochip_irqchip_add(chip, &int0002_irqchip, 0, handle_edge_irq, 213 if (cpu_id->driver_data == BAYTRAIL)
214 irq_chip = &int0002_byt_irqchip;
215 else
216 irq_chip = &int0002_cht_irqchip;
217
218 ret = gpiochip_irqchip_add(chip, irq_chip, 0, handle_edge_irq,
199 IRQ_TYPE_NONE); 219 IRQ_TYPE_NONE);
200 if (ret) { 220 if (ret) {
201 dev_err(dev, "Error adding irqchip: %d\n", ret); 221 dev_err(dev, "Error adding irqchip: %d\n", ret);
202 return ret; 222 return ret;
203 } 223 }
204 224
205 gpiochip_set_chained_irqchip(chip, &int0002_irqchip, irq, NULL); 225 gpiochip_set_chained_irqchip(chip, irq_chip, irq, NULL);
206 226
207 return 0; 227 return 0;
208} 228}
diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index 22dbf115782e..f2c621b55f49 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -15,6 +15,7 @@
15#include <linux/bitfield.h> 15#include <linux/bitfield.h>
16#include <linux/debugfs.h> 16#include <linux/debugfs.h>
17#include <linux/delay.h> 17#include <linux/delay.h>
18#include <linux/dmi.h>
18#include <linux/io.h> 19#include <linux/io.h>
19#include <linux/module.h> 20#include <linux/module.h>
20#include <linux/pci.h> 21#include <linux/pci.h>
@@ -22,14 +23,24 @@
22 23
23#include <asm/cpu_device_id.h> 24#include <asm/cpu_device_id.h>
24#include <asm/intel-family.h> 25#include <asm/intel-family.h>
26#include <asm/msr.h>
25 27
26#include "intel_pmc_core.h" 28#include "intel_pmc_core.h"
27 29
28#define ICPU(model, data) \
29 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (kernel_ulong_t)data }
30
31static struct pmc_dev pmc; 30static struct pmc_dev pmc;
32 31
32/* PKGC MSRs are common across Intel Core SoCs */
33static const struct pmc_bit_map msr_map[] = {
34 {"Package C2", MSR_PKG_C2_RESIDENCY},
35 {"Package C3", MSR_PKG_C3_RESIDENCY},
36 {"Package C6", MSR_PKG_C6_RESIDENCY},
37 {"Package C7", MSR_PKG_C7_RESIDENCY},
38 {"Package C8", MSR_PKG_C8_RESIDENCY},
39 {"Package C9", MSR_PKG_C9_RESIDENCY},
40 {"Package C10", MSR_PKG_C10_RESIDENCY},
41 {}
42};
43
33static const struct pmc_bit_map spt_pll_map[] = { 44static const struct pmc_bit_map spt_pll_map[] = {
34 {"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0}, 45 {"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0},
35 {"GEN2 USB2PCIE2 PLL", SPT_PMC_BIT_MPHY_CMN_LANE1}, 46 {"GEN2 USB2PCIE2 PLL", SPT_PMC_BIT_MPHY_CMN_LANE1},
@@ -108,6 +119,7 @@ static const struct pmc_bit_map spt_ltr_show_map[] = {
108 {"SATA", SPT_PMC_LTR_SATA}, 119 {"SATA", SPT_PMC_LTR_SATA},
109 {"GIGABIT_ETHERNET", SPT_PMC_LTR_GBE}, 120 {"GIGABIT_ETHERNET", SPT_PMC_LTR_GBE},
110 {"XHCI", SPT_PMC_LTR_XHCI}, 121 {"XHCI", SPT_PMC_LTR_XHCI},
122 {"Reserved", SPT_PMC_LTR_RESERVED},
111 {"ME", SPT_PMC_LTR_ME}, 123 {"ME", SPT_PMC_LTR_ME},
112 /* EVA is Enterprise Value Add, doesn't really exist on PCH */ 124 /* EVA is Enterprise Value Add, doesn't really exist on PCH */
113 {"EVA", SPT_PMC_LTR_EVA}, 125 {"EVA", SPT_PMC_LTR_EVA},
@@ -131,6 +143,7 @@ static const struct pmc_reg_map spt_reg_map = {
131 .mphy_sts = spt_mphy_map, 143 .mphy_sts = spt_mphy_map,
132 .pll_sts = spt_pll_map, 144 .pll_sts = spt_pll_map,
133 .ltr_show_sts = spt_ltr_show_map, 145 .ltr_show_sts = spt_ltr_show_map,
146 .msr_sts = msr_map,
134 .slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET, 147 .slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
135 .ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET, 148 .ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
136 .regmap_length = SPT_PMC_MMIO_REG_LEN, 149 .regmap_length = SPT_PMC_MMIO_REG_LEN,
@@ -139,6 +152,7 @@ static const struct pmc_reg_map spt_reg_map = {
139 .pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET, 152 .pm_cfg_offset = SPT_PMC_PM_CFG_OFFSET,
140 .pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT, 153 .pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT,
141 .ltr_ignore_max = SPT_NUM_IP_IGN_ALLOWED, 154 .ltr_ignore_max = SPT_NUM_IP_IGN_ALLOWED,
155 .pm_vric1_offset = SPT_PMC_VRIC1_OFFSET,
142}; 156};
143 157
144/* Cannonlake: PGD PFET Enable Ack Status Register(s) bitmap */ 158/* Cannonlake: PGD PFET Enable Ack Status Register(s) bitmap */
@@ -168,25 +182,26 @@ static const struct pmc_bit_map cnp_pfear_map[] = {
168 {"SDX", BIT(4)}, 182 {"SDX", BIT(4)},
169 {"SPE", BIT(5)}, 183 {"SPE", BIT(5)},
170 {"Fuse", BIT(6)}, 184 {"Fuse", BIT(6)},
171 {"Res_23", BIT(7)}, 185 /* Reserved for Cannonlake but valid for Icelake */
186 {"SBR8", BIT(7)},
172 187
173 {"CSME_FSC", BIT(0)}, 188 {"CSME_FSC", BIT(0)},
174 {"USB3_OTG", BIT(1)}, 189 {"USB3_OTG", BIT(1)},
175 {"EXI", BIT(2)}, 190 {"EXI", BIT(2)},
176 {"CSE", BIT(3)}, 191 {"CSE", BIT(3)},
177 {"csme_kvm", BIT(4)}, 192 {"CSME_KVM", BIT(4)},
178 {"csme_pmt", BIT(5)}, 193 {"CSME_PMT", BIT(5)},
179 {"csme_clink", BIT(6)}, 194 {"CSME_CLINK", BIT(6)},
180 {"csme_ptio", BIT(7)}, 195 {"CSME_PTIO", BIT(7)},
181 196
182 {"csme_usbr", BIT(0)}, 197 {"CSME_USBR", BIT(0)},
183 {"csme_susram", BIT(1)}, 198 {"CSME_SUSRAM", BIT(1)},
184 {"csme_smt1", BIT(2)}, 199 {"CSME_SMT1", BIT(2)},
185 {"CSME_SMT4", BIT(3)}, 200 {"CSME_SMT4", BIT(3)},
186 {"csme_sms2", BIT(4)}, 201 {"CSME_SMS2", BIT(4)},
187 {"csme_sms1", BIT(5)}, 202 {"CSME_SMS1", BIT(5)},
188 {"csme_rtc", BIT(6)}, 203 {"CSME_RTC", BIT(6)},
189 {"csme_psf", BIT(7)}, 204 {"CSME_PSF", BIT(7)},
190 205
191 {"SBR0", BIT(0)}, 206 {"SBR0", BIT(0)},
192 {"SBR1", BIT(1)}, 207 {"SBR1", BIT(1)},
@@ -203,7 +218,7 @@ static const struct pmc_bit_map cnp_pfear_map[] = {
203 {"CNVI", BIT(3)}, 218 {"CNVI", BIT(3)},
204 {"UFS0", BIT(4)}, 219 {"UFS0", BIT(4)},
205 {"EMMC", BIT(5)}, 220 {"EMMC", BIT(5)},
206 {"Res_6", BIT(6)}, 221 {"SPF", BIT(6)},
207 {"SBR6", BIT(7)}, 222 {"SBR6", BIT(7)},
208 223
209 {"SBR7", BIT(0)}, 224 {"SBR7", BIT(0)},
@@ -211,6 +226,20 @@ static const struct pmc_bit_map cnp_pfear_map[] = {
211 {"HDA_PGD4", BIT(2)}, 226 {"HDA_PGD4", BIT(2)},
212 {"HDA_PGD5", BIT(3)}, 227 {"HDA_PGD5", BIT(3)},
213 {"HDA_PGD6", BIT(4)}, 228 {"HDA_PGD6", BIT(4)},
229 /* Reserved for Cannonlake but valid for Icelake */
230 {"PSF6", BIT(5)},
231 {"PSF7", BIT(6)},
232 {"PSF8", BIT(7)},
233
234 /* Icelake generation onwards only */
235 {"RES_65", BIT(0)},
236 {"RES_66", BIT(1)},
237 {"RES_67", BIT(2)},
238 {"TAM", BIT(3)},
239 {"GBETSN", BIT(4)},
240 {"TBTLSX", BIT(5)},
241 {"RES_71", BIT(6)},
242 {"RES_72", BIT(7)},
214 {} 243 {}
215}; 244};
216 245
@@ -276,6 +305,7 @@ static const struct pmc_bit_map cnp_ltr_show_map[] = {
276 {"SATA", CNP_PMC_LTR_SATA}, 305 {"SATA", CNP_PMC_LTR_SATA},
277 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, 306 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
278 {"XHCI", CNP_PMC_LTR_XHCI}, 307 {"XHCI", CNP_PMC_LTR_XHCI},
308 {"Reserved", CNP_PMC_LTR_RESERVED},
279 {"ME", CNP_PMC_LTR_ME}, 309 {"ME", CNP_PMC_LTR_ME},
280 /* EVA is Enterprise Value Add, doesn't really exist on PCH */ 310 /* EVA is Enterprise Value Add, doesn't really exist on PCH */
281 {"EVA", CNP_PMC_LTR_EVA}, 311 {"EVA", CNP_PMC_LTR_EVA},
@@ -291,6 +321,8 @@ static const struct pmc_bit_map cnp_ltr_show_map[] = {
291 {"ISH", CNP_PMC_LTR_ISH}, 321 {"ISH", CNP_PMC_LTR_ISH},
292 {"UFSX2", CNP_PMC_LTR_UFSX2}, 322 {"UFSX2", CNP_PMC_LTR_UFSX2},
293 {"EMMC", CNP_PMC_LTR_EMMC}, 323 {"EMMC", CNP_PMC_LTR_EMMC},
324 /* Reserved for Cannonlake but valid for Icelake */
325 {"WIGIG", ICL_PMC_LTR_WIGIG},
294 /* Below two cannot be used for LTR_IGNORE */ 326 /* Below two cannot be used for LTR_IGNORE */
295 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT}, 327 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
296 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, 328 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
@@ -302,6 +334,7 @@ static const struct pmc_reg_map cnp_reg_map = {
302 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, 334 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
303 .slps0_dbg_maps = cnp_slps0_dbg_maps, 335 .slps0_dbg_maps = cnp_slps0_dbg_maps,
304 .ltr_show_sts = cnp_ltr_show_map, 336 .ltr_show_sts = cnp_ltr_show_map,
337 .msr_sts = msr_map,
305 .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET, 338 .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
306 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 339 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
307 .regmap_length = CNP_PMC_MMIO_REG_LEN, 340 .regmap_length = CNP_PMC_MMIO_REG_LEN,
@@ -312,6 +345,22 @@ static const struct pmc_reg_map cnp_reg_map = {
312 .ltr_ignore_max = CNP_NUM_IP_IGN_ALLOWED, 345 .ltr_ignore_max = CNP_NUM_IP_IGN_ALLOWED,
313}; 346};
314 347
348static const struct pmc_reg_map icl_reg_map = {
349 .pfear_sts = cnp_pfear_map,
350 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
351 .slps0_dbg_maps = cnp_slps0_dbg_maps,
352 .ltr_show_sts = cnp_ltr_show_map,
353 .msr_sts = msr_map,
354 .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
355 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
356 .regmap_length = CNP_PMC_MMIO_REG_LEN,
357 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
358 .ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
359 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
360 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
361 .ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,
362};
363
315static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset) 364static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
316{ 365{
317 return readb(pmcdev->regbase + offset); 366 return readb(pmcdev->regbase + offset);
@@ -328,9 +377,9 @@ static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
328 writel(val, pmcdev->regbase + reg_offset); 377 writel(val, pmcdev->regbase + reg_offset);
329} 378}
330 379
331static inline u32 pmc_core_adjust_slp_s0_step(u32 value) 380static inline u64 pmc_core_adjust_slp_s0_step(u32 value)
332{ 381{
333 return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP; 382 return (u64)value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
334} 383}
335 384
336static int pmc_core_dev_state_get(void *data, u64 *val) 385static int pmc_core_dev_state_get(void *data, u64 *val)
@@ -380,7 +429,8 @@ static int pmc_core_ppfear_show(struct seq_file *s, void *unused)
380 index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++) 429 index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)
381 pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter); 430 pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);
382 431
383 for (index = 0; map[index].name; index++) 432 for (index = 0; map[index].name &&
433 index < pmcdev->map->ppfear_buckets * 8; index++)
384 pmc_core_display_map(s, index, pf_regs[index / 8], map); 434 pmc_core_display_map(s, index, pf_regs[index / 8], map);
385 435
386 return 0; 436 return 0;
@@ -677,6 +727,25 @@ static int pmc_core_ltr_show(struct seq_file *s, void *unused)
677} 727}
678DEFINE_SHOW_ATTRIBUTE(pmc_core_ltr); 728DEFINE_SHOW_ATTRIBUTE(pmc_core_ltr);
679 729
730static int pmc_core_pkgc_show(struct seq_file *s, void *unused)
731{
732 struct pmc_dev *pmcdev = s->private;
733 const struct pmc_bit_map *map = pmcdev->map->msr_sts;
734 u64 pcstate_count;
735 int index;
736
737 for (index = 0; map[index].name ; index++) {
738 if (rdmsrl_safe(map[index].bit_mask, &pcstate_count))
739 continue;
740
741 seq_printf(s, "%-8s : 0x%llx\n", map[index].name,
742 pcstate_count);
743 }
744
745 return 0;
746}
747DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc);
748
680static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev) 749static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
681{ 750{
682 debugfs_remove_recursive(pmcdev->dbgfs_dir); 751 debugfs_remove_recursive(pmcdev->dbgfs_dir);
@@ -701,7 +770,10 @@ static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
701 debugfs_create_file("ltr_ignore", 0644, dir, pmcdev, 770 debugfs_create_file("ltr_ignore", 0644, dir, pmcdev,
702 &pmc_core_ltr_ignore_ops); 771 &pmc_core_ltr_ignore_ops);
703 772
704 debugfs_create_file("ltr_show", 0644, dir, pmcdev, &pmc_core_ltr_fops); 773 debugfs_create_file("ltr_show", 0444, dir, pmcdev, &pmc_core_ltr_fops);
774
775 debugfs_create_file("package_cstate_show", 0444, dir, pmcdev,
776 &pmc_core_pkgc_fops);
705 777
706 if (pmcdev->map->pll_sts) 778 if (pmcdev->map->pll_sts)
707 debugfs_create_file("pll_status", 0444, dir, pmcdev, 779 debugfs_create_file("pll_status", 0444, dir, pmcdev,
@@ -735,11 +807,12 @@ static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
735#endif /* CONFIG_DEBUG_FS */ 807#endif /* CONFIG_DEBUG_FS */
736 808
737static const struct x86_cpu_id intel_pmc_core_ids[] = { 809static const struct x86_cpu_id intel_pmc_core_ids[] = {
738 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, &spt_reg_map), 810 INTEL_CPU_FAM6(SKYLAKE_MOBILE, spt_reg_map),
739 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, &spt_reg_map), 811 INTEL_CPU_FAM6(SKYLAKE_DESKTOP, spt_reg_map),
740 ICPU(INTEL_FAM6_KABYLAKE_MOBILE, &spt_reg_map), 812 INTEL_CPU_FAM6(KABYLAKE_MOBILE, spt_reg_map),
741 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, &spt_reg_map), 813 INTEL_CPU_FAM6(KABYLAKE_DESKTOP, spt_reg_map),
742 ICPU(INTEL_FAM6_CANNONLAKE_MOBILE, &cnp_reg_map), 814 INTEL_CPU_FAM6(CANNONLAKE_MOBILE, cnp_reg_map),
815 INTEL_CPU_FAM6(ICELAKE_MOBILE, icl_reg_map),
743 {} 816 {}
744}; 817};
745 818
@@ -750,6 +823,37 @@ static const struct pci_device_id pmc_pci_ids[] = {
750 { 0, }, 823 { 0, },
751}; 824};
752 825
826/*
827 * This quirk can be used on those platforms where
828 * the platform BIOS enforces 24Mhx Crystal to shutdown
829 * before PMC can assert SLP_S0#.
830 */
831int quirk_xtal_ignore(const struct dmi_system_id *id)
832{
833 struct pmc_dev *pmcdev = &pmc;
834 u32 value;
835
836 value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_vric1_offset);
837 /* 24MHz Crystal Shutdown Qualification Disable */
838 value |= SPT_PMC_VRIC1_XTALSDQDIS;
839 /* Low Voltage Mode Enable */
840 value &= ~SPT_PMC_VRIC1_SLPS0LVEN;
841 pmc_core_reg_write(pmcdev, pmcdev->map->pm_vric1_offset, value);
842 return 0;
843}
844
845static const struct dmi_system_id pmc_core_dmi_table[] = {
846 {
847 .callback = quirk_xtal_ignore,
848 .ident = "HP Elite x2 1013 G3",
849 .matches = {
850 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
851 DMI_MATCH(DMI_PRODUCT_NAME, "HP Elite x2 1013 G3"),
852 },
853 },
854 {}
855};
856
753static int __init pmc_core_probe(void) 857static int __init pmc_core_probe(void)
754{ 858{
755 struct pmc_dev *pmcdev = &pmc; 859 struct pmc_dev *pmcdev = &pmc;
@@ -768,7 +872,7 @@ static int __init pmc_core_probe(void)
768 * Sunrisepoint PCH regmap can't be used. Use Cannonlake PCH regmap 872 * Sunrisepoint PCH regmap can't be used. Use Cannonlake PCH regmap
769 * in this case. 873 * in this case.
770 */ 874 */
771 if (!pci_dev_present(pmc_pci_ids)) 875 if (pmcdev->map == &spt_reg_map && !pci_dev_present(pmc_pci_ids))
772 pmcdev->map = &cnp_reg_map; 876 pmcdev->map = &cnp_reg_map;
773 877
774 if (lpit_read_residency_count_address(&slp_s0_addr)) 878 if (lpit_read_residency_count_address(&slp_s0_addr))
@@ -791,6 +895,7 @@ static int __init pmc_core_probe(void)
791 return err; 895 return err;
792 } 896 }
793 897
898 dmi_check_system(pmc_core_dmi_table);
794 pr_info(" initialized\n"); 899 pr_info(" initialized\n");
795 return 0; 900 return 0;
796} 901}
diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h
index 89554cba5758..88d9c0653a5f 100644
--- a/drivers/platform/x86/intel_pmc_core.h
+++ b/drivers/platform/x86/intel_pmc_core.h
@@ -25,6 +25,7 @@
25#define SPT_PMC_MTPMC_OFFSET 0x20 25#define SPT_PMC_MTPMC_OFFSET 0x20
26#define SPT_PMC_MFPMC_OFFSET 0x38 26#define SPT_PMC_MFPMC_OFFSET 0x38
27#define SPT_PMC_LTR_IGNORE_OFFSET 0x30C 27#define SPT_PMC_LTR_IGNORE_OFFSET 0x30C
28#define SPT_PMC_VRIC1_OFFSET 0x31c
28#define SPT_PMC_MPHY_CORE_STS_0 0x1143 29#define SPT_PMC_MPHY_CORE_STS_0 0x1143
29#define SPT_PMC_MPHY_CORE_STS_1 0x1142 30#define SPT_PMC_MPHY_CORE_STS_1 0x1142
30#define SPT_PMC_MPHY_COM_STS_0 0x1155 31#define SPT_PMC_MPHY_COM_STS_0 0x1155
@@ -32,7 +33,7 @@
32#define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x64 33#define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x64
33#define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1) 34#define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1)
34#define MTPMC_MASK 0xffff0000 35#define MTPMC_MASK 0xffff0000
35#define PPFEAR_MAX_NUM_ENTRIES 5 36#define PPFEAR_MAX_NUM_ENTRIES 12
36#define SPT_PPFEAR_NUM_ENTRIES 5 37#define SPT_PPFEAR_NUM_ENTRIES 5
37#define SPT_PMC_READ_DISABLE_BIT 0x16 38#define SPT_PMC_READ_DISABLE_BIT 0x16
38#define SPT_PMC_MSG_FULL_STS_BIT 0x18 39#define SPT_PMC_MSG_FULL_STS_BIT 0x18
@@ -46,6 +47,7 @@
46#define SPT_PMC_LTR_SATA 0x368 47#define SPT_PMC_LTR_SATA 0x368
47#define SPT_PMC_LTR_GBE 0x36C 48#define SPT_PMC_LTR_GBE 0x36C
48#define SPT_PMC_LTR_XHCI 0x370 49#define SPT_PMC_LTR_XHCI 0x370
50#define SPT_PMC_LTR_RESERVED 0x374
49#define SPT_PMC_LTR_ME 0x378 51#define SPT_PMC_LTR_ME 0x378
50#define SPT_PMC_LTR_EVA 0x37C 52#define SPT_PMC_LTR_EVA 0x37C
51#define SPT_PMC_LTR_SPC 0x380 53#define SPT_PMC_LTR_SPC 0x380
@@ -135,6 +137,9 @@ enum ppfear_regs {
135#define SPT_PMC_BIT_MPHY_CMN_LANE2 BIT(2) 137#define SPT_PMC_BIT_MPHY_CMN_LANE2 BIT(2)
136#define SPT_PMC_BIT_MPHY_CMN_LANE3 BIT(3) 138#define SPT_PMC_BIT_MPHY_CMN_LANE3 BIT(3)
137 139
140#define SPT_PMC_VRIC1_SLPS0LVEN BIT(13)
141#define SPT_PMC_VRIC1_XTALSDQDIS BIT(22)
142
138/* Cannonlake Power Management Controller register offsets */ 143/* Cannonlake Power Management Controller register offsets */
139#define CNP_PMC_SLPS0_DBG_OFFSET 0x10B4 144#define CNP_PMC_SLPS0_DBG_OFFSET 0x10B4
140#define CNP_PMC_PM_CFG_OFFSET 0x1818 145#define CNP_PMC_PM_CFG_OFFSET 0x1818
@@ -156,6 +161,7 @@ enum ppfear_regs {
156#define CNP_PMC_LTR_SATA 0x1B68 161#define CNP_PMC_LTR_SATA 0x1B68
157#define CNP_PMC_LTR_GBE 0x1B6C 162#define CNP_PMC_LTR_GBE 0x1B6C
158#define CNP_PMC_LTR_XHCI 0x1B70 163#define CNP_PMC_LTR_XHCI 0x1B70
164#define CNP_PMC_LTR_RESERVED 0x1B74
159#define CNP_PMC_LTR_ME 0x1B78 165#define CNP_PMC_LTR_ME 0x1B78
160#define CNP_PMC_LTR_EVA 0x1B7C 166#define CNP_PMC_LTR_EVA 0x1B7C
161#define CNP_PMC_LTR_SPC 0x1B80 167#define CNP_PMC_LTR_SPC 0x1B80
@@ -176,6 +182,10 @@ enum ppfear_regs {
176#define LTR_REQ_SNOOP BIT(15) 182#define LTR_REQ_SNOOP BIT(15)
177#define LTR_REQ_NONSNOOP BIT(31) 183#define LTR_REQ_NONSNOOP BIT(31)
178 184
185#define ICL_PPFEAR_NUM_ENTRIES 9
186#define ICL_NUM_IP_IGN_ALLOWED 20
187#define ICL_PMC_LTR_WIGIG 0x1BFC
188
179struct pmc_bit_map { 189struct pmc_bit_map {
180 const char *name; 190 const char *name;
181 u32 bit_mask; 191 u32 bit_mask;
@@ -208,6 +218,7 @@ struct pmc_reg_map {
208 const struct pmc_bit_map *pll_sts; 218 const struct pmc_bit_map *pll_sts;
209 const struct pmc_bit_map **slps0_dbg_maps; 219 const struct pmc_bit_map **slps0_dbg_maps;
210 const struct pmc_bit_map *ltr_show_sts; 220 const struct pmc_bit_map *ltr_show_sts;
221 const struct pmc_bit_map *msr_sts;
211 const u32 slp_s0_offset; 222 const u32 slp_s0_offset;
212 const u32 ltr_ignore_offset; 223 const u32 ltr_ignore_offset;
213 const int regmap_length; 224 const int regmap_length;
@@ -217,6 +228,7 @@ struct pmc_reg_map {
217 const int pm_read_disable_bit; 228 const int pm_read_disable_bit;
218 const u32 slps0_dbg_offset; 229 const u32 slps0_dbg_offset;
219 const u32 ltr_ignore_max; 230 const u32 ltr_ignore_max;
231 const u32 pm_vric1_offset;
220}; 232};
221 233
222/** 234/**
diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c
index df3fcd36776a..48fa7573e29b 100644
--- a/drivers/platform/x86/mlx-platform.c
+++ b/drivers/platform/x86/mlx-platform.c
@@ -25,6 +25,7 @@
25#define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00 25#define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00
26#define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01 26#define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01
27#define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02 27#define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02
28#define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET 0x03
28#define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d 29#define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d
29#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e 30#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e
30#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f 31#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f
@@ -33,6 +34,7 @@
33#define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22 34#define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22
34#define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23 35#define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23
35#define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24 36#define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24
37#define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a
36#define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30 38#define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30
37#define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31 39#define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31
38#define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32 40#define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32
@@ -67,6 +69,9 @@
67#define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee 69#define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee
68#define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef 70#define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef
69#define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0 71#define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0
72#define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0xf5
73#define MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET 0xf6
74#define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0xf7
70#define MLXPLAT_CPLD_LPC_IO_RANGE 0x100 75#define MLXPLAT_CPLD_LPC_IO_RANGE 0x100
71#define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb 76#define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb
72#define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda 77#define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda
@@ -584,36 +589,48 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_fan_items_data[] = {
584 .label = "fan1", 589 .label = "fan1",
585 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 590 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
586 .mask = BIT(0), 591 .mask = BIT(0),
592 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
593 .bit = BIT(0),
587 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 594 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
588 }, 595 },
589 { 596 {
590 .label = "fan2", 597 .label = "fan2",
591 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 598 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
592 .mask = BIT(1), 599 .mask = BIT(1),
600 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
601 .bit = BIT(1),
593 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 602 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
594 }, 603 },
595 { 604 {
596 .label = "fan3", 605 .label = "fan3",
597 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 606 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
598 .mask = BIT(2), 607 .mask = BIT(2),
608 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
609 .bit = BIT(2),
599 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 610 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
600 }, 611 },
601 { 612 {
602 .label = "fan4", 613 .label = "fan4",
603 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 614 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
604 .mask = BIT(3), 615 .mask = BIT(3),
616 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
617 .bit = BIT(3),
605 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 618 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
606 }, 619 },
607 { 620 {
608 .label = "fan5", 621 .label = "fan5",
609 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 622 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
610 .mask = BIT(4), 623 .mask = BIT(4),
624 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
625 .bit = BIT(4),
611 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 626 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
612 }, 627 },
613 { 628 {
614 .label = "fan6", 629 .label = "fan6",
615 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 630 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET,
616 .mask = BIT(5), 631 .mask = BIT(5),
632 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
633 .bit = BIT(5),
617 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 634 .hpdev.nr = MLXPLAT_CPLD_NR_NONE,
618 }, 635 },
619}; 636};
@@ -816,61 +833,90 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = {
816 .label = "fan1:green", 833 .label = "fan1:green",
817 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 834 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
818 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 835 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
836 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
837 .bit = BIT(0),
819 }, 838 },
820 { 839 {
821 .label = "fan1:orange", 840 .label = "fan1:orange",
822 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 841 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
823 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 842 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
843 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
844 .bit = BIT(0),
824 }, 845 },
825 { 846 {
826 .label = "fan2:green", 847 .label = "fan2:green",
827 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 848 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
828 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 849 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
850 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
851 .bit = BIT(1),
829 }, 852 },
830 { 853 {
831 .label = "fan2:orange", 854 .label = "fan2:orange",
832 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 855 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET,
833 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 856 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
857 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
858 .bit = BIT(1),
834 }, 859 },
835 { 860 {
836 .label = "fan3:green", 861 .label = "fan3:green",
837 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 862 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
838 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 863 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
864 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
865 .bit = BIT(2),
839 }, 866 },
840 { 867 {
841 .label = "fan3:orange", 868 .label = "fan3:orange",
842 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 869 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
843 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 870 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
871 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
872 .bit = BIT(2),
844 }, 873 },
845 { 874 {
846 .label = "fan4:green", 875 .label = "fan4:green",
847 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 876 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
848 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 877 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
878 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
879 .bit = BIT(3),
849 }, 880 },
850 { 881 {
851 .label = "fan4:orange", 882 .label = "fan4:orange",
852 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 883 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET,
853 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 884 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
885 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
886 .bit = BIT(3),
854 }, 887 },
855 { 888 {
856 .label = "fan5:green", 889 .label = "fan5:green",
857 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 890 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
858 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 891 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
892 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
893 .bit = BIT(4),
859 }, 894 },
860 { 895 {
861 .label = "fan5:orange", 896 .label = "fan5:orange",
862 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 897 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
863 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 898 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
899 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
900 .bit = BIT(4),
864 }, 901 },
865 { 902 {
866 .label = "fan6:green", 903 .label = "fan6:green",
867 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 904 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
868 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 905 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
906 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
907 .bit = BIT(5),
869 }, 908 },
870 { 909 {
871 .label = "fan6:orange", 910 .label = "fan6:orange",
872 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 911 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET,
873 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 912 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK,
913 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET,
914 .bit = BIT(5),
915 },
916 {
917 .label = "uid:blue",
918 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET,
919 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK,
874 }, 920 },
875}; 921};
876 922
@@ -1100,6 +1146,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
1100 .mode = 0444, 1146 .mode = 0444,
1101 }, 1147 },
1102 { 1148 {
1149 .label = "cpld4_version",
1150 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET,
1151 .bit = GENMASK(7, 0),
1152 .mode = 0444,
1153 },
1154 {
1103 .label = "reset_long_pb", 1155 .label = "reset_long_pb",
1104 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 1156 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET,
1105 .mask = GENMASK(7, 0) & ~BIT(0), 1157 .mask = GENMASK(7, 0) & ~BIT(0),
@@ -1184,6 +1236,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
1184 .bit = 1, 1236 .bit = 1,
1185 .mode = 0444, 1237 .mode = 0444,
1186 }, 1238 },
1239 {
1240 .label = "fan_dir",
1241 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION,
1242 .bit = GENMASK(7, 0),
1243 .mode = 0444,
1244 },
1187}; 1245};
1188 1246
1189static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = { 1247static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = {
@@ -1201,61 +1259,85 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = {
1201 .label = "tacho1", 1259 .label = "tacho1",
1202 .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET, 1260 .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET,
1203 .mask = GENMASK(7, 0), 1261 .mask = GENMASK(7, 0),
1262 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
1263 .bit = BIT(0),
1204 }, 1264 },
1205 { 1265 {
1206 .label = "tacho2", 1266 .label = "tacho2",
1207 .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET, 1267 .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET,
1208 .mask = GENMASK(7, 0), 1268 .mask = GENMASK(7, 0),
1269 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
1270 .bit = BIT(1),
1209 }, 1271 },
1210 { 1272 {
1211 .label = "tacho3", 1273 .label = "tacho3",
1212 .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET, 1274 .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET,
1213 .mask = GENMASK(7, 0), 1275 .mask = GENMASK(7, 0),
1276 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
1277 .bit = BIT(2),
1214 }, 1278 },
1215 { 1279 {
1216 .label = "tacho4", 1280 .label = "tacho4",
1217 .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET, 1281 .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET,
1218 .mask = GENMASK(7, 0), 1282 .mask = GENMASK(7, 0),
1283 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
1284 .bit = BIT(3),
1219 }, 1285 },
1220 { 1286 {
1221 .label = "tacho5", 1287 .label = "tacho5",
1222 .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET, 1288 .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET,
1223 .mask = GENMASK(7, 0), 1289 .mask = GENMASK(7, 0),
1290 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
1291 .bit = BIT(4),
1224 }, 1292 },
1225 { 1293 {
1226 .label = "tacho6", 1294 .label = "tacho6",
1227 .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET, 1295 .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET,
1228 .mask = GENMASK(7, 0), 1296 .mask = GENMASK(7, 0),
1297 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
1298 .bit = BIT(5),
1229 }, 1299 },
1230 { 1300 {
1231 .label = "tacho7", 1301 .label = "tacho7",
1232 .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET, 1302 .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET,
1233 .mask = GENMASK(7, 0), 1303 .mask = GENMASK(7, 0),
1304 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
1305 .bit = BIT(6),
1234 }, 1306 },
1235 { 1307 {
1236 .label = "tacho8", 1308 .label = "tacho8",
1237 .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET, 1309 .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET,
1238 .mask = GENMASK(7, 0), 1310 .mask = GENMASK(7, 0),
1311 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET,
1312 .bit = BIT(7),
1239 }, 1313 },
1240 { 1314 {
1241 .label = "tacho9", 1315 .label = "tacho9",
1242 .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET, 1316 .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET,
1243 .mask = GENMASK(7, 0), 1317 .mask = GENMASK(7, 0),
1318 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
1319 .bit = BIT(0),
1244 }, 1320 },
1245 { 1321 {
1246 .label = "tacho10", 1322 .label = "tacho10",
1247 .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET, 1323 .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET,
1248 .mask = GENMASK(7, 0), 1324 .mask = GENMASK(7, 0),
1325 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
1326 .bit = BIT(1),
1249 }, 1327 },
1250 { 1328 {
1251 .label = "tacho11", 1329 .label = "tacho11",
1252 .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET, 1330 .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET,
1253 .mask = GENMASK(7, 0), 1331 .mask = GENMASK(7, 0),
1332 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
1333 .bit = BIT(2),
1254 }, 1334 },
1255 { 1335 {
1256 .label = "tacho12", 1336 .label = "tacho12",
1257 .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET, 1337 .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET,
1258 .mask = GENMASK(7, 0), 1338 .mask = GENMASK(7, 0),
1339 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET,
1340 .bit = BIT(3),
1259 }, 1341 },
1260}; 1342};
1261 1343
@@ -1299,6 +1381,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
1299 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET: 1381 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
1300 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: 1382 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
1301 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: 1383 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
1384 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
1302 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: 1385 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
1303 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: 1386 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
1304 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: 1387 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
@@ -1307,6 +1390,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
1307 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 1390 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
1308 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 1391 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
1309 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 1392 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
1393 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:
1310 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 1394 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
1311 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: 1395 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET:
1312 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 1396 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
@@ -1341,6 +1425,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
1341 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET: 1425 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
1342 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: 1426 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
1343 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 1427 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
1428 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
1429 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
1430 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:
1344 return true; 1431 return true;
1345 } 1432 }
1346 return false; 1433 return false;
@@ -1352,6 +1439,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
1352 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET: 1439 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:
1353 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: 1440 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:
1354 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: 1441 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:
1442 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:
1355 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: 1443 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:
1356 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: 1444 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:
1357 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: 1445 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:
@@ -1360,6 +1448,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
1360 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 1448 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:
1361 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 1449 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:
1362 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 1450 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:
1451 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:
1363 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 1452 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:
1364 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 1453 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:
1365 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: 1454 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
@@ -1392,6 +1481,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
1392 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET: 1481 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:
1393 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: 1482 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:
1394 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 1483 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:
1484 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:
1485 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:
1486 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:
1395 return true; 1487 return true;
1396 } 1488 }
1397 return false; 1489 return false;
@@ -1614,6 +1706,13 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
1614 }, 1706 },
1615 }, 1707 },
1616 { 1708 {
1709 .callback = mlxplat_dmi_qmb7xx_matched,
1710 .matches = {
1711 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"),
1712 DMI_MATCH(DMI_PRODUCT_NAME, "MSN38"),
1713 },
1714 },
1715 {
1617 .callback = mlxplat_dmi_default_matched, 1716 .callback = mlxplat_dmi_default_matched,
1618 .matches = { 1717 .matches = {
1619 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"), 1718 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"),
@@ -1643,6 +1742,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {
1643 DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"), 1742 DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"),
1644 }, 1743 },
1645 }, 1744 },
1745 {
1746 .callback = mlxplat_dmi_qmb7xx_matched,
1747 .matches = {
1748 DMI_MATCH(DMI_BOARD_NAME, "VMOD0007"),
1749 },
1750 },
1646 { } 1751 { }
1647}; 1752};
1648 1753
diff --git a/drivers/platform/x86/touchscreen_dmi.c b/drivers/platform/x86/touchscreen_dmi.c
index 8c5d47c0aea6..2d56ff7c8230 100644
--- a/drivers/platform/x86/touchscreen_dmi.c
+++ b/drivers/platform/x86/touchscreen_dmi.c
@@ -41,6 +41,20 @@ static const struct ts_dmi_data chuwi_hi8_data = {
41 .properties = chuwi_hi8_props, 41 .properties = chuwi_hi8_props,
42}; 42};
43 43
44static const struct property_entry chuwi_hi8_air_props[] = {
45 PROPERTY_ENTRY_U32("touchscreen-size-x", 1728),
46 PROPERTY_ENTRY_U32("touchscreen-size-y", 1148),
47 PROPERTY_ENTRY_BOOL("touchscreen-swapped-x-y"),
48 PROPERTY_ENTRY_STRING("firmware-name", "gsl3676-chuwi-hi8-air.fw"),
49 PROPERTY_ENTRY_U32("silead,max-fingers", 10),
50 { }
51};
52
53static const struct ts_dmi_data chuwi_hi8_air_data = {
54 .acpi_name = "MSSL1680:00",
55 .properties = chuwi_hi8_air_props,
56};
57
44static const struct property_entry chuwi_hi8_pro_props[] = { 58static const struct property_entry chuwi_hi8_pro_props[] = {
45 PROPERTY_ENTRY_U32("touchscreen-min-x", 6), 59 PROPERTY_ENTRY_U32("touchscreen-min-x", 6),
46 PROPERTY_ENTRY_U32("touchscreen-min-y", 3), 60 PROPERTY_ENTRY_U32("touchscreen-min-y", 3),
@@ -58,6 +72,25 @@ static const struct ts_dmi_data chuwi_hi8_pro_data = {
58 .properties = chuwi_hi8_pro_props, 72 .properties = chuwi_hi8_pro_props,
59}; 73};
60 74
75static const struct property_entry chuwi_hi10_air_props[] = {
76 PROPERTY_ENTRY_U32("touchscreen-size-x", 1981),
77 PROPERTY_ENTRY_U32("touchscreen-size-y", 1271),
78 PROPERTY_ENTRY_U32("touchscreen-min-x", 99),
79 PROPERTY_ENTRY_U32("touchscreen-min-y", 9),
80 PROPERTY_ENTRY_BOOL("touchscreen-swapped-x-y"),
81 PROPERTY_ENTRY_U32("touchscreen-fuzz-x", 5),
82 PROPERTY_ENTRY_U32("touchscreen-fuzz-y", 4),
83 PROPERTY_ENTRY_STRING("firmware-name", "gsl1680-chuwi-hi10-air.fw"),
84 PROPERTY_ENTRY_U32("silead,max-fingers", 10),
85 PROPERTY_ENTRY_BOOL("silead,home-button"),
86 { }
87};
88
89static const struct ts_dmi_data chuwi_hi10_air_data = {
90 .acpi_name = "MSSL1680:00",
91 .properties = chuwi_hi10_air_props,
92};
93
61static const struct property_entry chuwi_vi8_props[] = { 94static const struct property_entry chuwi_vi8_props[] = {
62 PROPERTY_ENTRY_U32("touchscreen-min-x", 4), 95 PROPERTY_ENTRY_U32("touchscreen-min-x", 4),
63 PROPERTY_ENTRY_U32("touchscreen-min-y", 6), 96 PROPERTY_ENTRY_U32("touchscreen-min-y", 6),
@@ -369,6 +402,24 @@ static const struct ts_dmi_data pov_mobii_wintab_p800w_v21_data = {
369 .properties = pov_mobii_wintab_p800w_v21_props, 402 .properties = pov_mobii_wintab_p800w_v21_props,
370}; 403};
371 404
405static const struct property_entry pov_mobii_wintab_p1006w_v10_props[] = {
406 PROPERTY_ENTRY_U32("touchscreen-min-x", 1),
407 PROPERTY_ENTRY_U32("touchscreen-min-y", 3),
408 PROPERTY_ENTRY_U32("touchscreen-size-x", 1984),
409 PROPERTY_ENTRY_U32("touchscreen-size-y", 1520),
410 PROPERTY_ENTRY_BOOL("touchscreen-inverted-y"),
411 PROPERTY_ENTRY_STRING("firmware-name",
412 "gsl3692-pov-mobii-wintab-p1006w-v10.fw"),
413 PROPERTY_ENTRY_U32("silead,max-fingers", 10),
414 PROPERTY_ENTRY_BOOL("silead,home-button"),
415 { }
416};
417
418static const struct ts_dmi_data pov_mobii_wintab_p1006w_v10_data = {
419 .acpi_name = "MSSL1680:00",
420 .properties = pov_mobii_wintab_p1006w_v10_props,
421};
422
372static const struct property_entry teclast_x3_plus_props[] = { 423static const struct property_entry teclast_x3_plus_props[] = {
373 PROPERTY_ENTRY_U32("touchscreen-size-x", 1980), 424 PROPERTY_ENTRY_U32("touchscreen-size-x", 1980),
374 PROPERTY_ENTRY_U32("touchscreen-size-y", 1500), 425 PROPERTY_ENTRY_U32("touchscreen-size-y", 1500),
@@ -498,6 +549,15 @@ static const struct dmi_system_id touchscreen_dmi_table[] = {
498 }, 549 },
499 }, 550 },
500 { 551 {
552 /* Chuwi Hi8 Air (CWI543) */
553 .driver_data = (void *)&chuwi_hi8_air_data,
554 .matches = {
555 DMI_MATCH(DMI_BOARD_VENDOR, "Default string"),
556 DMI_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),
557 DMI_MATCH(DMI_PRODUCT_NAME, "Hi8 Air"),
558 },
559 },
560 {
501 /* Chuwi Hi8 Pro (CWI513) */ 561 /* Chuwi Hi8 Pro (CWI513) */
502 .driver_data = (void *)&chuwi_hi8_pro_data, 562 .driver_data = (void *)&chuwi_hi8_pro_data,
503 .matches = { 563 .matches = {
@@ -506,6 +566,14 @@ static const struct dmi_system_id touchscreen_dmi_table[] = {
506 }, 566 },
507 }, 567 },
508 { 568 {
569 /* Chuwi Hi10 Air */
570 .driver_data = (void *)&chuwi_hi10_air_data,
571 .matches = {
572 DMI_MATCH(DMI_BOARD_VENDOR, "Hampoo"),
573 DMI_MATCH(DMI_PRODUCT_SKU, "P1W6_C109D_B"),
574 },
575 },
576 {
509 /* Chuwi Vi8 (CWI506) */ 577 /* Chuwi Vi8 (CWI506) */
510 .driver_data = (void *)&chuwi_vi8_data, 578 .driver_data = (void *)&chuwi_vi8_data,
511 .matches = { 579 .matches = {
@@ -707,6 +775,17 @@ static const struct dmi_system_id touchscreen_dmi_table[] = {
707 }, 775 },
708 }, 776 },
709 { 777 {
778 /* Point of View mobii wintab p1006w (v1.0) */
779 .driver_data = (void *)&pov_mobii_wintab_p1006w_v10_data,
780 .matches = {
781 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Insyde"),
782 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "BayTrail"),
783 /* Note 105b is Foxcon's USB/PCI vendor id */
784 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "105B"),
785 DMI_EXACT_MATCH(DMI_BOARD_NAME, "0E57"),
786 },
787 },
788 {
710 /* Teclast X3 Plus */ 789 /* Teclast X3 Plus */
711 .driver_data = (void *)&teclast_x3_plus_data, 790 .driver_data = (void *)&teclast_x3_plus_data,
712 .matches = { 791 .matches = {
diff --git a/drivers/platform/x86/wmi-bmof.c b/drivers/platform/x86/wmi-bmof.c
index c4530ba715e8..8751a13134be 100644
--- a/drivers/platform/x86/wmi-bmof.c
+++ b/drivers/platform/x86/wmi-bmof.c
@@ -119,7 +119,7 @@ static struct wmi_driver wmi_bmof_driver = {
119 119
120module_wmi_driver(wmi_bmof_driver); 120module_wmi_driver(wmi_bmof_driver);
121 121
122MODULE_ALIAS("wmi:" WMI_BMOF_GUID); 122MODULE_DEVICE_TABLE(wmi, wmi_bmof_id_table);
123MODULE_AUTHOR("Andrew Lutomirski <luto@kernel.org>"); 123MODULE_AUTHOR("Andrew Lutomirski <luto@kernel.org>");
124MODULE_DESCRIPTION("WMI embedded Binary MOF driver"); 124MODULE_DESCRIPTION("WMI embedded Binary MOF driver");
125MODULE_LICENSE("GPL"); 125MODULE_LICENSE("GPL");
diff --git a/drivers/platform/x86/wmi.c b/drivers/platform/x86/wmi.c
index bea35be68706..7b26b6ccf1a0 100644
--- a/drivers/platform/x86/wmi.c
+++ b/drivers/platform/x86/wmi.c
@@ -768,7 +768,10 @@ static int wmi_dev_match(struct device *dev, struct device_driver *driver)
768 struct wmi_block *wblock = dev_to_wblock(dev); 768 struct wmi_block *wblock = dev_to_wblock(dev);
769 const struct wmi_device_id *id = wmi_driver->id_table; 769 const struct wmi_device_id *id = wmi_driver->id_table;
770 770
771 while (id->guid_string) { 771 if (id == NULL)
772 return 0;
773
774 while (*id->guid_string) {
772 uuid_le driver_guid; 775 uuid_le driver_guid;
773 776
774 if (WARN_ON(uuid_le_to_bin(id->guid_string, &driver_guid))) 777 if (WARN_ON(uuid_le_to_bin(id->guid_string, &driver_guid)))
diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
index 14eaeeb46f41..448621c32e4d 100644
--- a/include/linux/mod_devicetable.h
+++ b/include/linux/mod_devicetable.h
@@ -788,4 +788,16 @@ struct tee_client_device_id {
788 uuid_t uuid; 788 uuid_t uuid;
789}; 789};
790 790
791/* WMI */
792
793#define WMI_MODULE_PREFIX "wmi:"
794
795/**
796 * struct wmi_device_id - WMI device identifier
797 * @guid_string: 36 char string of the form fa50ff2b-f2e8-45de-83fa-65417f2f49ba
798 */
799struct wmi_device_id {
800 const char guid_string[UUID_STRING_LEN+1];
801};
802
791#endif /* LINUX_MOD_DEVICETABLE_H */ 803#endif /* LINUX_MOD_DEVICETABLE_H */
diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_data/mlxreg.h
index 19f5cb618c55..1b2f86f96743 100644
--- a/include/linux/platform_data/mlxreg.h
+++ b/include/linux/platform_data/mlxreg.h
@@ -61,6 +61,7 @@ struct mlxreg_hotplug_device {
61 * @reg: attribute register; 61 * @reg: attribute register;
62 * @mask: attribute access mask; 62 * @mask: attribute access mask;
63 * @bit: attribute effective bit; 63 * @bit: attribute effective bit;
64 * @capability: attribute capability register;
64 * @mode: access mode; 65 * @mode: access mode;
65 * @np - pointer to node platform associated with attribute; 66 * @np - pointer to node platform associated with attribute;
66 * @hpdev - hotplug device data; 67 * @hpdev - hotplug device data;
@@ -72,6 +73,7 @@ struct mlxreg_core_data {
72 u32 reg; 73 u32 reg;
73 u32 mask; 74 u32 mask;
74 u32 bit; 75 u32 bit;
76 u32 capability;
75 umode_t mode; 77 umode_t mode;
76 struct device_node *np; 78 struct device_node *np;
77 struct mlxreg_hotplug_device hpdev; 79 struct mlxreg_hotplug_device hpdev;
@@ -107,9 +109,9 @@ struct mlxreg_core_item {
107/** 109/**
108 * struct mlxreg_core_platform_data - platform data: 110 * struct mlxreg_core_platform_data - platform data:
109 * 111 *
110 * @led_data: led private data; 112 * @data: instance private data;
111 * @regmap: register map of parent device; 113 * @regmap: register map of parent device;
112 * @counter: number of led instances; 114 * @counter: number of instances;
113 */ 115 */
114struct mlxreg_core_platform_data { 116struct mlxreg_core_platform_data {
115 struct mlxreg_core_data *data; 117 struct mlxreg_core_data *data;
diff --git a/include/linux/wmi.h b/include/linux/wmi.h
index 4757cb5077e5..592f81afecbb 100644
--- a/include/linux/wmi.h
+++ b/include/linux/wmi.h
@@ -18,6 +18,7 @@
18 18
19#include <linux/device.h> 19#include <linux/device.h>
20#include <linux/acpi.h> 20#include <linux/acpi.h>
21#include <linux/mod_devicetable.h>
21#include <uapi/linux/wmi.h> 22#include <uapi/linux/wmi.h>
22 23
23struct wmi_device { 24struct wmi_device {
@@ -39,10 +40,6 @@ extern union acpi_object *wmidev_block_query(struct wmi_device *wdev,
39 40
40extern int set_required_buffer_size(struct wmi_device *wdev, u64 length); 41extern int set_required_buffer_size(struct wmi_device *wdev, u64 length);
41 42
42struct wmi_device_id {
43 const char *guid_string;
44};
45
46struct wmi_driver { 43struct wmi_driver {
47 struct device_driver driver; 44 struct device_driver driver;
48 const struct wmi_device_id *id_table; 45 const struct wmi_device_id *id_table;
diff --git a/scripts/mod/devicetable-offsets.c b/scripts/mod/devicetable-offsets.c
index 160718383a71..054405b90ba4 100644
--- a/scripts/mod/devicetable-offsets.c
+++ b/scripts/mod/devicetable-offsets.c
@@ -228,5 +228,8 @@ int main(void)
228 DEVID(tee_client_device_id); 228 DEVID(tee_client_device_id);
229 DEVID_FIELD(tee_client_device_id, uuid); 229 DEVID_FIELD(tee_client_device_id, uuid);
230 230
231 DEVID(wmi_device_id);
232 DEVID_FIELD(wmi_device_id, guid_string);
233
231 return 0; 234 return 0;
232} 235}
diff --git a/scripts/mod/file2alias.c b/scripts/mod/file2alias.c
index d0e41723627f..e17a29ae2e97 100644
--- a/scripts/mod/file2alias.c
+++ b/scripts/mod/file2alias.c
@@ -40,6 +40,7 @@ typedef struct {
40typedef struct { 40typedef struct {
41 __u8 b[16]; 41 __u8 b[16];
42} uuid_t; 42} uuid_t;
43#define UUID_STRING_LEN 36
43 44
44/* Big exception to the "don't include kernel headers into userspace, which 45/* Big exception to the "don't include kernel headers into userspace, which
45 * even potentially has different endianness and word sizes, since 46 * even potentially has different endianness and word sizes, since
@@ -53,6 +54,9 @@ struct devtable {
53 int (*do_entry)(const char *filename, void *symval, char *alias); 54 int (*do_entry)(const char *filename, void *symval, char *alias);
54}; 55};
55 56
57/* Size of alias provided to do_entry functions */
58#define ALIAS_SIZE 500
59
56/* Define a variable f that holds the value of field f of struct devid 60/* Define a variable f that holds the value of field f of struct devid
57 * based at address m. 61 * based at address m.
58 */ 62 */
@@ -1305,6 +1309,27 @@ static int do_tee_entry(const char *filename, void *symval, char *alias)
1305 return 1; 1309 return 1;
1306} 1310}
1307 1311
1312/* Looks like: wmi:guid */
1313static int do_wmi_entry(const char *filename, void *symval, char *alias)
1314{
1315 int len;
1316 DEF_FIELD_ADDR(symval, wmi_device_id, guid_string);
1317
1318 if (strlen(*guid_string) != UUID_STRING_LEN) {
1319 warn("Invalid WMI device id 'wmi:%s' in '%s'\n",
1320 *guid_string, filename);
1321 return 0;
1322 }
1323
1324 len = snprintf(alias, ALIAS_SIZE, WMI_MODULE_PREFIX "%s", *guid_string);
1325 if (len < 0 || len >= ALIAS_SIZE) {
1326 warn("Could not generate all MODULE_ALIAS's in '%s'\n",
1327 filename);
1328 return 0;
1329 }
1330 return 1;
1331}
1332
1308/* Does namelen bytes of name exactly match the symbol? */ 1333/* Does namelen bytes of name exactly match the symbol? */
1309static bool sym_is(const char *name, unsigned namelen, const char *symbol) 1334static bool sym_is(const char *name, unsigned namelen, const char *symbol)
1310{ 1335{
@@ -1321,7 +1346,7 @@ static void do_table(void *symval, unsigned long size,
1321 struct module *mod) 1346 struct module *mod)
1322{ 1347{
1323 unsigned int i; 1348 unsigned int i;
1324 char alias[500]; 1349 char alias[ALIAS_SIZE];
1325 1350
1326 device_id_check(mod->name, device_id, size, id_size, symval); 1351 device_id_check(mod->name, device_id, size, id_size, symval);
1327 /* Leave last one: it's the terminator. */ 1352 /* Leave last one: it's the terminator. */
@@ -1376,6 +1401,7 @@ static const struct devtable devtable[] = {
1376 {"tbsvc", SIZE_tb_service_id, do_tbsvc_entry}, 1401 {"tbsvc", SIZE_tb_service_id, do_tbsvc_entry},
1377 {"typec", SIZE_typec_device_id, do_typec_entry}, 1402 {"typec", SIZE_typec_device_id, do_typec_entry},
1378 {"tee", SIZE_tee_client_device_id, do_tee_entry}, 1403 {"tee", SIZE_tee_client_device_id, do_tee_entry},
1404 {"wmi", SIZE_wmi_device_id, do_wmi_entry},
1379}; 1405};
1380 1406
1381/* Create MODULE_ALIAS() statements. 1407/* Create MODULE_ALIAS() statements.
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-26 03:36:42 -0400