13 files changed, 40 insertions, 28 deletions

diff --git a/.mailmap b/.mailmap
index a32879a9f970..4757d361fd33 100644
--- a/.mailmap
+++ b/.mailmap
@@ -15,6 +15,7 @@ Adriana Reus <adi.reus@gmail.com> <adriana.reus@intel.com>
 Alan Cox <alan@lxorguk.ukuu.org.uk>
 Alan Cox <root@hraefn.swansea.linux.org.uk>
 Aleksey Gorelov <aleksey_gorelov@phoenix.com>
+Aleksandar Markovic <aleksandar.markovic@mips.com> <aleksandar.markovic@imgtec.com>
 Al Viro <viro@ftp.linux.org.uk>
 Al Viro <viro@zenIV.linux.org.uk>
 Andreas Herrmann <aherrman@de.ibm.com>
@@ -101,6 +102,7 @@ Leonid I Ananiev <leonid.i.ananiev@intel.com>
 Linas Vepstas <linas@austin.ibm.com>
 Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@web.de>
 Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@ascom.ch>
+Marcin Nowakowski <marcin.nowakowski@mips.com> <marcin.nowakowski@imgtec.com>
 Mark Brown <broonie@sirena.org.uk>
 Martin Kepplinger <martink@posteo.de> <martin.kepplinger@theobroma-systems.com>
 Martin Kepplinger <martink@posteo.de> <martin.kepplinger@ginzinger.com>
@@ -119,6 +121,7 @@ Matt Redfearn <matt.redfearn@mips.com> <matt.redfearn@imgtec.com>
 Mayuresh Janorkar <mayur@ti.com>
 Michael Buesch <m@bues.ch>
 Michel Dänzer <michel@tungstengraphics.com>
+Miodrag Dinic <miodrag.dinic@mips.com> <miodrag.dinic@imgtec.com>
 Mitesh shah <mshah@teja.com>
 Mohit Kumar <mohit.kumar@st.com> <mohit.kumar.dhaka@gmail.com>
 Morten Welinder <terra@gnome.org>
diff --git a/MAINTAINERS b/MAINTAINERS
index 00b0fda6c2e1..2f4e462aa4a2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -873,7 +873,7 @@ F:	drivers/android/
 F:      drivers/staging/android/
 
 ANDROID GOLDFISH RTC DRIVER
-M:      Miodrag Dinic <miodrag.dinic@imgtec.com>
+M:      Miodrag Dinic <miodrag.dinic@mips.com>
 S:      Supported
 F:      Documentation/devicetree/bindings/rtc/google,goldfish-rtc.txt
 F:      drivers/rtc/rtc-goldfish.c
@@ -9019,7 +9019,7 @@ F:	drivers/*/*loongson1*
 F:      drivers/*/*/*loongson1*
 
 MIPS RINT INSTRUCTION EMULATION
-M:      Aleksandar Markovic <aleksandar.markovic@imgtec.com>
+M:      Aleksandar Markovic <aleksandar.markovic@mips.com>
 L:      linux-mips@linux-mips.org
 S:      Supported
 F:      arch/mips/math-emu/sp_rint.c
@@ -10683,10 +10683,9 @@ S:	Maintained
 F:      drivers/pinctrl/spear/
 
 PISTACHIO SOC SUPPORT
-M:      James Hartley <james.hartley@imgtec.com>
-M:      Ionela Voinescu <ionela.voinescu@imgtec.com>
+M:      James Hartley <james.hartley@sondrel.com>
 L:      linux-mips@linux-mips.org
-S:      Maintained
+S:      Odd Fixes
 F:      arch/mips/pistachio/
 F:      arch/mips/include/asm/mach-pistachio/
 F:      arch/mips/boot/dts/img/pistachio*
diff --git a/arch/mips/generic/board-ni169445.its.S b/arch/mips/generic/board-ni169445.its.S
index d12e12fe90be..e4cb4f95a8cc 100644
--- a/arch/mips/generic/board-ni169445.its.S
+++ b/arch/mips/generic/board-ni169445.its.S
@@ -1,4 +1,4 @@
-{
+/ {
         images {
                 fdt@ni169445 {
                         description = "NI 169445 device tree";
diff --git a/arch/mips/generic/init.c b/arch/mips/generic/init.c
index cf409ba358a1..5ba6fcc26fa7 100644
--- a/arch/mips/generic/init.c
+++ b/arch/mips/generic/init.c
@@ -20,7 +20,7 @@
 #include <asm/fw/fw.h>
 #include <asm/irq_cpu.h>
 #include <asm/machine.h>
-#include <asm/mips-cpc.h>
+#include <asm/mips-cps.h>
 #include <asm/prom.h>
 #include <asm/smp-ops.h>
 #include <asm/time.h>
diff --git a/arch/mips/generic/kexec.c b/arch/mips/generic/kexec.c
index e9fb735299e3..1ca409f58929 100644
--- a/arch/mips/generic/kexec.c
+++ b/arch/mips/generic/kexec.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2016 Imagination Technologies
- * Author: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
+ * Author: Marcin Nowakowski <marcin.nowakowski@mips.com>
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
index 3708b8ccc0b4..8bc5df49b0e1 100644
--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@ -142,8 +142,8 @@ GCR_ACCESSOR_RO(64, 0x000, config)
 GCR_ACCESSOR_RW(64, 0x008, base)
 #define CM_GCR_BASE_GCRBASE                     GENMASK_ULL(47, 15)
 #define CM_GCR_BASE_CMDEFTGT                    GENMASK(1, 0)
-#define  CM_GCR_BASE_CMDEFTGT_DISABLED          0
-#define  CM_GCR_BASE_CMDEFTGT_MEM               1
+#define  CM_GCR_BASE_CMDEFTGT_MEM               0
+#define  CM_GCR_BASE_CMDEFTGT_RESERVED          1
 #define  CM_GCR_BASE_CMDEFTGT_IOCU0             2
 #define  CM_GCR_BASE_CMDEFTGT_IOCU1             3
 
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index 5d3563c55e0c..2161357cc68f 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -199,6 +199,10 @@
                 sll     k0, 3           /* extract cu0 bit */
                 .set    noreorder
                 bltz    k0, 8f
+                 move   k0, sp
+                .if \docfi
+                .cfi_register sp, k0
+                .endif
 #ifdef CONFIG_EVA
                 /*
                  * Flush interAptiv's Return Prediction Stack (RPS) by writing
@@ -225,10 +229,6 @@
                 MTC0    k0, CP0_ENTRYHI
 #endif
                 .set    reorder
-                 move   k0, sp
-                .if \docfi
-                .cfi_register sp, k0
-                .endif
                 /* Called from user mode, new stack. */
                 get_saved_sp docfi=\docfi tosp=1
 8:
diff --git a/arch/mips/kernel/probes-common.h b/arch/mips/kernel/probes-common.h
index dd08e41134b6..d2bf77b18822 100644
--- a/arch/mips/kernel/probes-common.h
+++ b/arch/mips/kernel/probes-common.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2016 Imagination Technologies
- * Author: Marcin Nowakowski <marcin.nowakowski@imgtec.com>
+ * Author: Marcin Nowakowski <marcin.nowakowski@mips.com>
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c
index 05295a4909f1..a2322009cac3 100644
--- a/arch/mips/kernel/smp-cmp.c
+++ b/arch/mips/kernel/smp-cmp.c
@@ -19,7 +19,7 @@
 #undef DEBUG
 
 #include <linux/kernel.h>
-#include <linux/sched.h>
+#include <linux/sched/task_stack.h>
 #include <linux/smp.h>
 #include <linux/cpumask.h>
 #include <linux/interrupt.h>
@@ -50,8 +50,8 @@ static void cmp_init_secondary(void)
 
 #ifdef CONFIG_MIPS_MT_SMP
         if (cpu_has_mipsmt)
-                c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
-                        TCBIND_CURVPE;
+                cpu_set_vpe_id(c, (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
+                                  TCBIND_CURVPE);
 #endif
 }
 
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index 7d6af41888e8..ecc1a853f48d 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -306,7 +306,7 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle)
         int err;
 
         /* We don't yet support booting CPUs in other clusters */
-        if (cpu_cluster(&cpu_data[cpu]) != cpu_cluster(&current_cpu_data))
+        if (cpu_cluster(&cpu_data[cpu]) != cpu_cluster(&raw_current_cpu_data))
                 return -ENOSYS;
 
         vpe_cfg->pc = (unsigned long)&smp_bootstrap;
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index bbe19b64def5..88be966d3e61 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -42,7 +42,7 @@
 #include <asm/processor.h>
 #include <asm/idle.h>
 #include <asm/r4k-timer.h>
-#include <asm/mips-cpc.h>
+#include <asm/mips-cps.h>
 #include <asm/mmu_context.h>
 #include <asm/time.h>
 #include <asm/setup.h>
@@ -66,6 +66,7 @@ EXPORT_SYMBOL(cpu_sibling_map);
 cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
 EXPORT_SYMBOL(cpu_core_map);
 
+static DECLARE_COMPLETION(cpu_starting);
 static DECLARE_COMPLETION(cpu_running);
 
 /*
@@ -374,6 +375,12 @@ asmlinkage void start_secondary(void)
         cpumask_set_cpu(cpu, &cpu_coherent_mask);
         notify_cpu_starting(cpu);
 
+        /* Notify boot CPU that we're starting & ready to sync counters */
+        complete(&cpu_starting);
+
+        synchronise_count_slave(cpu);
+
+        /* The CPU is running and counters synchronised, now mark it online */
         set_cpu_online(cpu, true);
 
         set_cpu_sibling_map(cpu);
@@ -381,8 +388,11 @@ asmlinkage void start_secondary(void)
 
         calculate_cpu_foreign_map();
 
+        /*
+         * Notify boot CPU that we're up & online and it can safely return
+         * from __cpu_up
+         */
         complete(&cpu_running);
-        synchronise_count_slave(cpu);
 
         /*
          * irq will be enabled in ->smp_finish(), enabling it too early
@@ -445,17 +455,17 @@ int __cpu_up(unsigned int cpu, struct task_struct *tidle)
         if (err)
                 return err;
 
-        /*
-         * We must check for timeout here, as the CPU will not be marked
-         * online until the counters are synchronised.
-         */
-        if (!wait_for_completion_timeout(&cpu_running,
+        /* Wait for CPU to start and be ready to sync counters */
+        if (!wait_for_completion_timeout(&cpu_starting,
                                          msecs_to_jiffies(1000))) {
                 pr_crit("CPU%u: failed to start\n", cpu);
                 return -EIO;
         }
 
         synchronise_count_master(cpu);
+
+        /* Wait for CPU to finish startup & mark itself online before return */
+        wait_for_completion(&cpu_running);
         return 0;
 }
 
diff --git a/arch/mips/mm/uasm-micromips.c b/arch/mips/mm/uasm-micromips.c
index c28ff53c8da0..cdb5a191b9d5 100644
--- a/arch/mips/mm/uasm-micromips.c
+++ b/arch/mips/mm/uasm-micromips.c
@@ -80,7 +80,7 @@ static const struct insn const insn_table_MM[insn_invalid] = {
         [insn_jr]       = {M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS},
         [insn_lb]       = {M(mm_lb32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
         [insn_ld]       = {0, 0},
-        [insn_lh]       = {M(mm_lh32_op, 0, 0, 0, 0, 0), RS | RS | SIMM},
+        [insn_lh]       = {M(mm_lh32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
         [insn_ll]       = {M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM},
         [insn_lld]      = {0, 0},
         [insn_lui]      = {M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM},
diff --git a/arch/mips/net/ebpf_jit.c b/arch/mips/net/ebpf_jit.c
index 01b7a87ea678..962b0259b4b6 100644
--- a/arch/mips/net/ebpf_jit.c
+++ b/arch/mips/net/ebpf_jit.c
@@ -1513,7 +1513,7 @@ ld_skb_common:
                 }
                 src = ebpf_to_mips_reg(ctx, insn, src_reg_no_fp);
                 if (src < 0)
-                        return dst;
+                        return src;
                 if (BPF_MODE(insn->code) == BPF_XADD) {
                         switch (BPF_SIZE(insn->code)) {
                         case BPF_W: