diff options
-rw-r--r-- | sound/soc/fsl/fsl_ssi.c | 57 |
1 files changed, 32 insertions, 25 deletions
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index 35e277379b86..fb8f52a0e7b7 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c | |||
@@ -321,6 +321,36 @@ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) | |||
321 | return ret; | 321 | return ret; |
322 | } | 322 | } |
323 | 323 | ||
324 | static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private) | ||
325 | { | ||
326 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | ||
327 | |||
328 | /* | ||
329 | * Setup the clock control register | ||
330 | */ | ||
331 | write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), | ||
332 | &ssi->stccr); | ||
333 | write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), | ||
334 | &ssi->srccr); | ||
335 | |||
336 | /* | ||
337 | * Enable AC97 mode and startup the SSI | ||
338 | */ | ||
339 | write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV, | ||
340 | &ssi->sacnt); | ||
341 | write_ssi(0xff, &ssi->saccdis); | ||
342 | write_ssi(0x300, &ssi->saccen); | ||
343 | |||
344 | /* | ||
345 | * Enable SSI, Transmit and Receive. AC97 has to communicate with the | ||
346 | * codec before a stream is started. | ||
347 | */ | ||
348 | write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN | | ||
349 | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE); | ||
350 | |||
351 | write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor); | ||
352 | } | ||
353 | |||
324 | static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private) | 354 | static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private) |
325 | { | 355 | { |
326 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; | 356 | struct ccsr_ssi __iomem *ssi = ssi_private->ssi; |
@@ -387,31 +417,8 @@ static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private) | |||
387 | * because it is also running without an active substream. Normally SSI | 417 | * because it is also running without an active substream. Normally SSI |
388 | * is only enabled when there is a substream. | 418 | * is only enabled when there is a substream. |
389 | */ | 419 | */ |
390 | if (ssi_private->imx_ac97) { | 420 | if (ssi_private->imx_ac97) |
391 | /* | 421 | fsl_ssi_setup_ac97(ssi_private); |
392 | * Setup the clock control register | ||
393 | */ | ||
394 | write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), | ||
395 | &ssi->stccr); | ||
396 | write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13), | ||
397 | &ssi->srccr); | ||
398 | |||
399 | /* | ||
400 | * Enable AC97 mode and startup the SSI | ||
401 | */ | ||
402 | write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV, | ||
403 | &ssi->sacnt); | ||
404 | write_ssi(0xff, &ssi->saccdis); | ||
405 | write_ssi(0x300, &ssi->saccen); | ||
406 | |||
407 | /* | ||
408 | * Enable SSI, Transmit and Receive | ||
409 | */ | ||
410 | write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN | | ||
411 | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE); | ||
412 | |||
413 | write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor); | ||
414 | } | ||
415 | 422 | ||
416 | return 0; | 423 | return 0; |
417 | } | 424 | } |