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-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt3
-rw-r--r--MAINTAINERS1
-rw-r--r--drivers/i2c/busses/i2c-i801.c7
-rw-r--r--drivers/i2c/busses/i2c-imx-lpi2c.c1
-rw-r--r--drivers/i2c/busses/i2c-uniphier-f.c7
-rw-r--r--drivers/i2c/busses/i2c-uniphier.c7
-rw-r--r--drivers/i2c/busses/i2c-xiic.c4
7 files changed, 16 insertions, 14 deletions
diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt
index 00e4365d7206..091c8dfd3229 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt
@@ -3,7 +3,6 @@
3Required properties: 3Required properties:
4- compatible : 4- compatible :
5 - "fsl,imx7ulp-lpi2c" for LPI2C compatible with the one integrated on i.MX7ULP soc 5 - "fsl,imx7ulp-lpi2c" for LPI2C compatible with the one integrated on i.MX7ULP soc
6 - "fsl,imx8dv-lpi2c" for LPI2C compatible with the one integrated on i.MX8DV soc
7- reg : address and length of the lpi2c master registers 6- reg : address and length of the lpi2c master registers
8- interrupts : lpi2c interrupt 7- interrupts : lpi2c interrupt
9- clocks : lpi2c clock specifier 8- clocks : lpi2c clock specifier
@@ -11,7 +10,7 @@ Required properties:
11Examples: 10Examples:
12 11
13lpi2c7: lpi2c7@40a50000 { 12lpi2c7: lpi2c7@40a50000 {
14 compatible = "fsl,imx8dv-lpi2c"; 13 compatible = "fsl,imx7ulp-lpi2c";
15 reg = <0x40A50000 0x10000>; 14 reg = <0x40A50000 0x10000>;
16 interrupt-parent = <&intc>; 15 interrupt-parent = <&intc>;
17 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 16 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/MAINTAINERS b/MAINTAINERS
index 9ad052aeac39..d870cb57c887 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2311,6 +2311,7 @@ F: drivers/clocksource/cadence_ttc_timer.c
2311F: drivers/i2c/busses/i2c-cadence.c 2311F: drivers/i2c/busses/i2c-cadence.c
2312F: drivers/mmc/host/sdhci-of-arasan.c 2312F: drivers/mmc/host/sdhci-of-arasan.c
2313F: drivers/edac/synopsys_edac.c 2313F: drivers/edac/synopsys_edac.c
2314F: drivers/i2c/busses/i2c-xiic.c
2314 2315
2315ARM64 PORT (AARCH64 ARCHITECTURE) 2316ARM64 PORT (AARCH64 ARCHITECTURE)
2316M: Catalin Marinas <catalin.marinas@arm.com> 2317M: Catalin Marinas <catalin.marinas@arm.com>
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index 04b60a349d7e..c91e145ef5a5 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -140,6 +140,7 @@
140 140
141#define SBREG_BAR 0x10 141#define SBREG_BAR 0x10
142#define SBREG_SMBCTRL 0xc6000c 142#define SBREG_SMBCTRL 0xc6000c
143#define SBREG_SMBCTRL_DNV 0xcf000c
143 144
144/* Host status bits for SMBPCISTS */ 145/* Host status bits for SMBPCISTS */
145#define SMBPCISTS_INTS BIT(3) 146#define SMBPCISTS_INTS BIT(3)
@@ -1399,7 +1400,11 @@ static void i801_add_tco(struct i801_priv *priv)
1399 spin_unlock(&p2sb_spinlock); 1400 spin_unlock(&p2sb_spinlock);
1400 1401
1401 res = &tco_res[ICH_RES_MEM_OFF]; 1402 res = &tco_res[ICH_RES_MEM_OFF];
1402 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; 1403 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1404 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1405 else
1406 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1407
1403 res->end = res->start + 3; 1408 res->end = res->start + 3;
1404 res->flags = IORESOURCE_MEM; 1409 res->flags = IORESOURCE_MEM;
1405 1410
diff --git a/drivers/i2c/busses/i2c-imx-lpi2c.c b/drivers/i2c/busses/i2c-imx-lpi2c.c
index 6d975f5221ca..06c4c767af32 100644
--- a/drivers/i2c/busses/i2c-imx-lpi2c.c
+++ b/drivers/i2c/busses/i2c-imx-lpi2c.c
@@ -538,7 +538,6 @@ static const struct i2c_algorithm lpi2c_imx_algo = {
538 538
539static const struct of_device_id lpi2c_imx_of_match[] = { 539static const struct of_device_id lpi2c_imx_of_match[] = {
540 { .compatible = "fsl,imx7ulp-lpi2c" }, 540 { .compatible = "fsl,imx7ulp-lpi2c" },
541 { .compatible = "fsl,imx8dv-lpi2c" },
542 { }, 541 { },
543}; 542};
544MODULE_DEVICE_TABLE(of, lpi2c_imx_of_match); 543MODULE_DEVICE_TABLE(of, lpi2c_imx_of_match);
diff --git a/drivers/i2c/busses/i2c-uniphier-f.c b/drivers/i2c/busses/i2c-uniphier-f.c
index 9918bdd81619..a403e8579b65 100644
--- a/drivers/i2c/busses/i2c-uniphier-f.c
+++ b/drivers/i2c/busses/i2c-uniphier-f.c
@@ -401,11 +401,8 @@ static int uniphier_fi2c_master_xfer(struct i2c_adapter *adap,
401 return ret; 401 return ret;
402 402
403 for (msg = msgs; msg < emsg; msg++) { 403 for (msg = msgs; msg < emsg; msg++) {
404 /* If next message is read, skip the stop condition */ 404 /* Emit STOP if it is the last message or I2C_M_STOP is set. */
405 bool stop = !(msg + 1 < emsg && msg[1].flags & I2C_M_RD); 405 bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP);
406 /* but, force it if I2C_M_STOP is set */
407 if (msg->flags & I2C_M_STOP)
408 stop = true;
409 406
410 ret = uniphier_fi2c_master_xfer_one(adap, msg, stop); 407 ret = uniphier_fi2c_master_xfer_one(adap, msg, stop);
411 if (ret) 408 if (ret)
diff --git a/drivers/i2c/busses/i2c-uniphier.c b/drivers/i2c/busses/i2c-uniphier.c
index bb181b088291..454f914ae66d 100644
--- a/drivers/i2c/busses/i2c-uniphier.c
+++ b/drivers/i2c/busses/i2c-uniphier.c
@@ -248,11 +248,8 @@ static int uniphier_i2c_master_xfer(struct i2c_adapter *adap,
248 return ret; 248 return ret;
249 249
250 for (msg = msgs; msg < emsg; msg++) { 250 for (msg = msgs; msg < emsg; msg++) {
251 /* If next message is read, skip the stop condition */ 251 /* Emit STOP if it is the last message or I2C_M_STOP is set. */
252 bool stop = !(msg + 1 < emsg && msg[1].flags & I2C_M_RD); 252 bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP);
253 /* but, force it if I2C_M_STOP is set */
254 if (msg->flags & I2C_M_STOP)
255 stop = true;
256 253
257 ret = uniphier_i2c_master_xfer_one(adap, msg, stop); 254 ret = uniphier_i2c_master_xfer_one(adap, msg, stop);
258 if (ret) 255 if (ret)
diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c
index 9a71e50d21f1..0c51c0ffdda9 100644
--- a/drivers/i2c/busses/i2c-xiic.c
+++ b/drivers/i2c/busses/i2c-xiic.c
@@ -532,6 +532,7 @@ static void xiic_start_recv(struct xiic_i2c *i2c)
532{ 532{
533 u8 rx_watermark; 533 u8 rx_watermark;
534 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; 534 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
535 unsigned long flags;
535 536
536 /* Clear and enable Rx full interrupt. */ 537 /* Clear and enable Rx full interrupt. */
537 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); 538 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
@@ -547,6 +548,7 @@ static void xiic_start_recv(struct xiic_i2c *i2c)
547 rx_watermark = IIC_RX_FIFO_DEPTH; 548 rx_watermark = IIC_RX_FIFO_DEPTH;
548 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1); 549 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);
549 550
551 local_irq_save(flags);
550 if (!(msg->flags & I2C_M_NOSTART)) 552 if (!(msg->flags & I2C_M_NOSTART))
551 /* write the address */ 553 /* write the address */
552 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 554 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
@@ -556,6 +558,8 @@ static void xiic_start_recv(struct xiic_i2c *i2c)
556 558
557 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 559 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
558 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); 560 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));
561 local_irq_restore(flags);
562
559 if (i2c->nmsgs == 1) 563 if (i2c->nmsgs == 1)
560 /* very last, enable bus not busy as well */ 564 /* very last, enable bus not busy as well */
561 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 565 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);