7 files changed, 206 insertions, 0 deletions

diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
index 5a781067a0e7..9f312a219510 100644
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@ -24,6 +24,7 @@ struct clk_omap_divider {
         u8                      flags;
         s8                      latch;
         const struct clk_div_table      *table;
+        u32             context;
 };
 
 #define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw)
@@ -36,6 +37,7 @@ struct clk_omap_mux {
         u8                      shift;
         s8                      latch;
         u8                      flags;
+        u8                      saved_parent;
 };
 
 #define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw)
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
index ccfb4d9a152a..373f620f49cb 100644
--- a/drivers/clk/ti/divider.c
+++ b/drivers/clk/ti/divider.c
@@ -268,10 +268,46 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
         return 0;
 }
 
+/**
+ * clk_divider_save_context - Save the divider value
+ * @hw: pointer  struct clk_hw
+ *
+ * Save the divider value
+ */
+static int clk_divider_save_context(struct clk_hw *hw)
+{
+        struct clk_omap_divider *divider = to_clk_omap_divider(hw);
+        u32 val;
+
+        val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift;
+        divider->context = val & div_mask(divider);
+
+        return 0;
+}
+
+/**
+ * clk_divider_restore_context - restore the saved the divider value
+ * @hw: pointer  struct clk_hw
+ *
+ * Restore the saved the divider value
+ */
+static void clk_divider_restore_context(struct clk_hw *hw)
+{
+        struct clk_omap_divider *divider = to_clk_omap_divider(hw);
+        u32 val;
+
+        val = ti_clk_ll_ops->clk_readl(&divider->reg);
+        val &= ~(div_mask(divider) << divider->shift);
+        val |= divider->context << divider->shift;
+        ti_clk_ll_ops->clk_writel(val, &divider->reg);
+}
+
 const struct clk_ops ti_clk_divider_ops = {
         .recalc_rate = ti_clk_divider_recalc_rate,
         .round_rate = ti_clk_divider_round_rate,
         .set_rate = ti_clk_divider_set_rate,
+        .save_context = clk_divider_save_context,
+        .restore_context = clk_divider_restore_context,
 };
 
 static struct clk *_register_divider(struct device *dev, const char *name,
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index dc86d07d0921..25d86d5ebb36 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -39,6 +39,8 @@ static const struct clk_ops dpll_m4xen_ck_ops = {
         .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
         .determine_rate = &omap4_dpll_regm4xen_determine_rate,
         .get_parent     = &omap2_init_dpll_parent,
+        .save_context   = &omap3_core_dpll_save_context,
+        .restore_context = &omap3_core_dpll_restore_context,
 };
 #else
 static const struct clk_ops dpll_m4xen_ck_ops = {};
@@ -62,6 +64,8 @@ static const struct clk_ops dpll_ck_ops = {
         .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
         .determine_rate = &omap3_noncore_dpll_determine_rate,
         .get_parent     = &omap2_init_dpll_parent,
+        .save_context   = &omap3_noncore_dpll_save_context,
+        .restore_context = &omap3_noncore_dpll_restore_context,
 };
 
 static const struct clk_ops dpll_no_gate_ck_ops = {
@@ -72,6 +76,8 @@ static const struct clk_ops dpll_no_gate_ck_ops = {
         .set_parent     = &omap3_noncore_dpll_set_parent,
         .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
         .determine_rate = &omap3_noncore_dpll_determine_rate,
+        .save_context   = &omap3_noncore_dpll_save_context,
+        .restore_context = &omap3_noncore_dpll_restore_context
 };
 #else
 static const struct clk_ops dpll_core_ck_ops = {};
diff --git a/drivers/clk/ti/dpll3xxx.c b/drivers/clk/ti/dpll3xxx.c
index 4534de2ef455..44b6b6403753 100644
--- a/drivers/clk/ti/dpll3xxx.c
+++ b/drivers/clk/ti/dpll3xxx.c
@@ -782,6 +782,130 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
         return rate;
 }
 
+/**
+ * omap3_core_dpll_save_context - Save the m and n values of the divider
+ * @hw: pointer  struct clk_hw
+ *
+ * Before the dpll registers are lost save the last rounded rate m and n
+ * and the enable mask.
+ */
+int omap3_core_dpll_save_context(struct clk_hw *hw)
+{
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+        struct dpll_data *dd;
+        u32 v;
+
+        dd = clk->dpll_data;
+
+        v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
+        clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
+
+        if (clk->context == DPLL_LOCKED) {
+                v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
+                dd->last_rounded_m = (v & dd->mult_mask) >>
+                                                __ffs(dd->mult_mask);
+                dd->last_rounded_n = ((v & dd->div1_mask) >>
+                                                __ffs(dd->div1_mask)) + 1;
+        }
+
+        return 0;
+}
+
+/**
+ * omap3_core_dpll_restore_context - restore the m and n values of the divider
+ * @hw: pointer  struct clk_hw
+ *
+ * Restore the last rounded rate m and n
+ * and the enable mask.
+ */
+void omap3_core_dpll_restore_context(struct clk_hw *hw)
+{
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+        const struct dpll_data *dd;
+        u32 v;
+
+        dd = clk->dpll_data;
+
+        if (clk->context == DPLL_LOCKED) {
+                _omap3_dpll_write_clken(clk, 0x4);
+                _omap3_wait_dpll_status(clk, 0);
+
+                v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
+                v &= ~(dd->mult_mask | dd->div1_mask);
+                v |= dd->last_rounded_m << __ffs(dd->mult_mask);
+                v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
+                ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);
+
+                _omap3_dpll_write_clken(clk, DPLL_LOCKED);
+                _omap3_wait_dpll_status(clk, 1);
+        } else {
+                _omap3_dpll_write_clken(clk, clk->context);
+        }
+}
+
+/**
+ * omap3_non_core_dpll_save_context - Save the m and n values of the divider
+ * @hw: pointer  struct clk_hw
+ *
+ * Before the dpll registers are lost save the last rounded rate m and n
+ * and the enable mask.
+ */
+int omap3_noncore_dpll_save_context(struct clk_hw *hw)
+{
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+        struct dpll_data *dd;
+        u32 v;
+
+        dd = clk->dpll_data;
+
+        v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
+        clk->context = (v & dd->enable_mask) >> __ffs(dd->enable_mask);
+
+        if (clk->context == DPLL_LOCKED) {
+                v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
+                dd->last_rounded_m = (v & dd->mult_mask) >>
+                                                __ffs(dd->mult_mask);
+                dd->last_rounded_n = ((v & dd->div1_mask) >>
+                                                __ffs(dd->div1_mask)) + 1;
+        }
+