81 files changed, 5770 insertions, 775 deletions

diff --git a/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
new file mode 100644
index 000000000000..d3058768b23d
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
@@ -0,0 +1,47 @@
+Applied Micro X-Gene SoC DMA nodes
+
+DMA nodes are defined to describe on-chip DMA interfaces in
+APM X-Gene SoC.
+
+Required properties for DMA interfaces:
+- compatible: Should be "apm,xgene-dma".
+- device_type: set to "dma".
+- reg: Address and length of the register set for the device.
+  It contains the information of registers in the following order:
+  1st - DMA control and status register address space.
+  2nd - Descriptor ring control and status register address space.
+  3rd - Descriptor ring command register address space.
+  4th - Soc efuse register address space.
+- interrupts: DMA has 5 interrupts sources. 1st interrupt is
+  DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts
+  are completion interrupts for each DMA channels.
+- clocks: Reference to the clock entry.
+
+Optional properties:
+- dma-coherent : Present if dma operations are coherent
+
+Example:
+        dmaclk: dmaclk@1f27c000 {
+                compatible = "apm,xgene-device-clock";
+                #clock-cells = <1>;
+                clocks = <&socplldiv2 0>;
+                reg = <0x0 0x1f27c000 0x0 0x1000>;
+                reg-names = "csr-reg";
+                clock-output-names = "dmaclk";
+        };
+
+        dma: dma@1f270000 {
+                        compatible = "apm,xgene-storm-dma";
+                        device_type = "dma";
+                        reg = <0x0 0x1f270000 0x0 0x10000>,
+                              <0x0 0x1f200000 0x0 0x10000>,
+                              <0x0 0x1b008000 0x0 0x2000>,
+                              <0x0 0x1054a000 0x0 0x100>;
+                        interrupts = <0x0 0x82 0x4>,
+                                     <0x0 0xb8 0x4>,
+                                     <0x0 0xb9 0x4>,
+                                     <0x0 0xba 0x4>,
+                                     <0x0 0xbb 0x4>;
+                        dma-coherent;
+                        clocks = <&dmaclk 0>;
+        };
diff --git a/Documentation/devicetree/bindings/dma/jz4780-dma.txt b/Documentation/devicetree/bindings/dma/jz4780-dma.txt
new file mode 100644
index 000000000000..f25feee62b15
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/jz4780-dma.txt
@@ -0,0 +1,56 @@
+* Ingenic JZ4780 DMA Controller
+
+Required properties:
+
+- compatible: Should be "ingenic,jz4780-dma"
+- reg: Should contain the DMA controller registers location and length.
+- interrupts: Should contain the interrupt specifier of the DMA controller.
+- interrupt-parent: Should be the phandle of the interrupt controller that
+- clocks: Should contain a clock specifier for the JZ4780 PDMA clock.
+- #dma-cells: Must be <2>. Number of integer cells in the dmas property of
+  DMA clients (see below).
+
+Optional properties:
+
+- ingenic,reserved-channels: Bitmask of channels to reserve for devices that
+  need a specific channel. These channels will only be assigned when explicitly
+  requested by a client. The primary use for this is channels 0 and 1, which
+  can be configured to have special behaviour for NAND/BCH when using
+  programmable firmware.
+
+Example:
+
+dma: dma@13420000 {
+        compatible = "ingenic,jz4780-dma";
+        reg = <0x13420000 0x10000>;
+
+        interrupt-parent = <&intc>;
+        interrupts = <10>;
+