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-rw-r--r--Documentation/devicetree/bindings/mfd/palmas.txt2
-rw-r--r--Documentation/devicetree/bindings/regulator/palmas-pmic.txt1
-rw-r--r--drivers/mfd/palmas.c233
-rw-r--r--drivers/regulator/lp8755.c23
-rw-r--r--drivers/regulator/ltc3589.c2
-rw-r--r--drivers/regulator/max8952.c34
-rw-r--r--drivers/regulator/mc13xxx-regulator-core.c37
-rw-r--r--drivers/regulator/mc13xxx.h1
-rw-r--r--drivers/regulator/palmas-regulator.c1104
-rw-r--r--include/linux/mfd/palmas.h837
10 files changed, 1837 insertions, 437 deletions
diff --git a/Documentation/devicetree/bindings/mfd/palmas.txt b/Documentation/devicetree/bindings/mfd/palmas.txt
index e5f0f8303461..eda898978d33 100644
--- a/Documentation/devicetree/bindings/mfd/palmas.txt
+++ b/Documentation/devicetree/bindings/mfd/palmas.txt
@@ -6,6 +6,7 @@ twl6037 (palmas)
6tps65913 (palmas) 6tps65913 (palmas)
7tps65914 (palmas) 7tps65914 (palmas)
8tps659038 8tps659038
9tps65917
9 10
10Required properties: 11Required properties:
11- compatible : Should be from the list 12- compatible : Should be from the list
@@ -16,6 +17,7 @@ Required properties:
16 ti,tps65914 17 ti,tps65914
17 ti,tps80036 18 ti,tps80036
18 ti,tps659038 19 ti,tps659038
20 ti,tps65917
19and also the generic series names 21and also the generic series names
20 ti,palmas 22 ti,palmas
21- interrupt-controller : palmas has its own internal IRQs 23- interrupt-controller : palmas has its own internal IRQs
diff --git a/Documentation/devicetree/bindings/regulator/palmas-pmic.txt b/Documentation/devicetree/bindings/regulator/palmas-pmic.txt
index 42e6b6bc48ff..725393c8a7f2 100644
--- a/Documentation/devicetree/bindings/regulator/palmas-pmic.txt
+++ b/Documentation/devicetree/bindings/regulator/palmas-pmic.txt
@@ -7,6 +7,7 @@ Required properties:
7 ti,twl6037-pmic 7 ti,twl6037-pmic
8 ti,tps65913-pmic 8 ti,tps65913-pmic
9 ti,tps65914-pmic 9 ti,tps65914-pmic
10 ti,tps65917-pmic
10and also the generic series names 11and also the generic series names
11 ti,palmas-pmic 12 ti,palmas-pmic
12- interrupt-parent : The parent interrupt controller which is palmas. 13- interrupt-parent : The parent interrupt controller which is palmas.
diff --git a/drivers/mfd/palmas.c b/drivers/mfd/palmas.c
index d280d789e55a..28cb048f4760 100644
--- a/drivers/mfd/palmas.c
+++ b/drivers/mfd/palmas.c
@@ -25,52 +25,6 @@
25#include <linux/mfd/palmas.h> 25#include <linux/mfd/palmas.h>
26#include <linux/of_device.h> 26#include <linux/of_device.h>
27 27
28#define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 | \
29 PALMAS_EXT_CONTROL_ENABLE2 | \
30 PALMAS_EXT_CONTROL_NSLEEP)
31
32struct palmas_sleep_requestor_info {
33 int id;
34 int reg_offset;
35 int bit_pos;
36};
37
38#define EXTERNAL_REQUESTOR(_id, _offset, _pos) \
39 [PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \
40 .id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \
41 .reg_offset = _offset, \
42 .bit_pos = _pos, \
43 }
44
45static struct palmas_sleep_requestor_info sleep_req_info[] = {
46 EXTERNAL_REQUESTOR(REGEN1, 0, 0),
47 EXTERNAL_REQUESTOR(REGEN2, 0, 1),
48 EXTERNAL_REQUESTOR(SYSEN1, 0, 2),
49 EXTERNAL_REQUESTOR(SYSEN2, 0, 3),
50 EXTERNAL_REQUESTOR(CLK32KG, 0, 4),
51 EXTERNAL_REQUESTOR(CLK32KGAUDIO, 0, 5),
52 EXTERNAL_REQUESTOR(REGEN3, 0, 6),
53 EXTERNAL_REQUESTOR(SMPS12, 1, 0),
54 EXTERNAL_REQUESTOR(SMPS3, 1, 1),
55 EXTERNAL_REQUESTOR(SMPS45, 1, 2),
56 EXTERNAL_REQUESTOR(SMPS6, 1, 3),
57 EXTERNAL_REQUESTOR(SMPS7, 1, 4),
58 EXTERNAL_REQUESTOR(SMPS8, 1, 5),
59 EXTERNAL_REQUESTOR(SMPS9, 1, 6),
60 EXTERNAL_REQUESTOR(SMPS10, 1, 7),
61 EXTERNAL_REQUESTOR(LDO1, 2, 0),
62 EXTERNAL_REQUESTOR(LDO2, 2, 1),
63 EXTERNAL_REQUESTOR(LDO3, 2, 2),
64 EXTERNAL_REQUESTOR(LDO4, 2, 3),
65 EXTERNAL_REQUESTOR(LDO5, 2, 4),
66 EXTERNAL_REQUESTOR(LDO6, 2, 5),
67 EXTERNAL_REQUESTOR(LDO7, 2, 6),
68 EXTERNAL_REQUESTOR(LDO8, 2, 7),
69 EXTERNAL_REQUESTOR(LDO9, 3, 0),
70 EXTERNAL_REQUESTOR(LDOLN, 3, 1),
71 EXTERNAL_REQUESTOR(LDOUSB, 3, 2),
72};
73
74static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = { 28static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
75 { 29 {
76 .reg_bits = 8, 30 .reg_bits = 8,
@@ -92,6 +46,133 @@ static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
92 }, 46 },
93}; 47};
94 48
49static const struct regmap_irq tps65917_irqs[] = {
50 /* INT1 IRQs */
51 [TPS65917_RESERVED1] = {
52 .mask = TPS65917_RESERVED,
53 },
54 [TPS65917_PWRON_IRQ] = {
55 .mask = TPS65917_INT1_STATUS_PWRON,
56 },
57 [TPS65917_LONG_PRESS_KEY_IRQ] = {
58 .mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY,
59 },
60 [TPS65917_RESERVED2] = {
61 .mask = TPS65917_RESERVED,
62 },
63 [TPS65917_PWRDOWN_IRQ] = {
64 .mask = TPS65917_INT1_STATUS_PWRDOWN,
65 },
66 [TPS65917_HOTDIE_IRQ] = {
67 .mask = TPS65917_INT1_STATUS_HOTDIE,
68 },
69 [TPS65917_VSYS_MON_IRQ] = {
70 .mask = TPS65917_INT1_STATUS_VSYS_MON,
71 },
72 [TPS65917_RESERVED3] = {
73 .mask = TPS65917_RESERVED,
74 },
75 /* INT2 IRQs*/
76 [TPS65917_RESERVED4] = {
77 .mask = TPS65917_RESERVED,
78 .reg_offset = 1,
79 },
80 [TPS65917_OTP_ERROR_IRQ] = {
81 .mask = TPS65917_INT2_STATUS_OTP_ERROR,
82 .reg_offset = 1,
83 },
84 [TPS65917_WDT_IRQ] = {
85 .mask = TPS65917_INT2_STATUS_WDT,
86 .reg_offset = 1,
87 },
88 [TPS65917_RESERVED5] = {
89 .mask = TPS65917_RESERVED,
90 .reg_offset = 1,
91 },
92 [TPS65917_RESET_IN_IRQ] = {
93 .mask = TPS65917_INT2_STATUS_RESET_IN,
94 .reg_offset = 1,
95 },
96 [TPS65917_FSD_IRQ] = {
97 .mask = TPS65917_INT2_STATUS_FSD,
98 .reg_offset = 1,
99 },
100 [TPS65917_SHORT_IRQ] = {
101 .mask = TPS65917_INT2_STATUS_SHORT,
102 .reg_offset = 1,
103 },
104 [TPS65917_RESERVED6] = {
105 .mask = TPS65917_RESERVED,
106 .reg_offset = 1,
107 },
108 /* INT3 IRQs */
109 [TPS65917_GPADC_AUTO_0_IRQ] = {
110 .mask = TPS65917_INT3_STATUS_GPADC_AUTO_0,
111 .reg_offset = 2,
112 },
113 [TPS65917_GPADC_AUTO_1_IRQ] = {
114 .mask = TPS65917_INT3_STATUS_GPADC_AUTO_1,
115 .reg_offset = 2,
116 },
117 [TPS65917_GPADC_EOC_SW_IRQ] = {
118 .mask = TPS65917_INT3_STATUS_GPADC_EOC_SW,
119 .reg_offset = 2,
120 },
121 [TPS65917_RESREVED6] = {
122 .mask = TPS65917_RESERVED6,
123 .reg_offset = 2,
124 },
125 [TPS65917_RESERVED7] = {
126 .mask = TPS65917_RESERVED,
127 .reg_offset = 2,
128 },
129 [TPS65917_RESERVED8] = {
130 .mask = TPS65917_RESERVED,
131 .reg_offset = 2,
132 },
133 [TPS65917_RESERVED9] = {
134 .mask = TPS65917_RESERVED,
135 .reg_offset = 2,
136 },
137 [TPS65917_VBUS_IRQ] = {
138 .mask = TPS65917_INT3_STATUS_VBUS,
139 .reg_offset = 2,
140 },
141 /* INT4 IRQs */
142 [TPS65917_GPIO_0_IRQ] = {
143 .mask = TPS65917_INT4_STATUS_GPIO_0,
144 .reg_offset = 3,
145 },
146 [TPS65917_GPIO_1_IRQ] = {
147 .mask = TPS65917_INT4_STATUS_GPIO_1,
148 .reg_offset = 3,
149 },
150 [TPS65917_GPIO_2_IRQ] = {
151 .mask = TPS65917_INT4_STATUS_GPIO_2,
152 .reg_offset = 3,
153 },
154 [TPS65917_GPIO_3_IRQ] = {
155 .mask = TPS65917_INT4_STATUS_GPIO_3,
156 .reg_offset = 3,
157 },
158 [TPS65917_GPIO_4_IRQ] = {
159 .mask = TPS65917_INT4_STATUS_GPIO_4,
160 .reg_offset = 3,
161 },
162 [TPS65917_GPIO_5_IRQ] = {
163 .mask = TPS65917_INT4_STATUS_GPIO_5,
164 .reg_offset = 3,
165 },
166 [TPS65917_GPIO_6_IRQ] = {
167 .mask = TPS65917_INT4_STATUS_GPIO_6,
168 .reg_offset = 3,
169 },
170 [TPS65917_RESERVED10] = {
171 .mask = TPS65917_RESERVED10,
172 .reg_offset = 3,
173 },
174};
175
95static const struct regmap_irq palmas_irqs[] = { 176static const struct regmap_irq palmas_irqs[] = {
96 /* INT1 IRQs */ 177 /* INT1 IRQs */
97 [PALMAS_CHARG_DET_N_VBUS_OVV_IRQ] = { 178 [PALMAS_CHARG_DET_N_VBUS_OVV_IRQ] = {
@@ -232,13 +313,26 @@ static struct regmap_irq_chip palmas_irq_chip = {
232 PALMAS_INT1_MASK), 313 PALMAS_INT1_MASK),
233}; 314};
234 315
316static struct regmap_irq_chip tps65917_irq_chip = {
317 .name = "tps65917",
318 .irqs = tps65917_irqs,
319 .num_irqs = ARRAY_SIZE(tps65917_irqs),
320
321 .num_regs = 4,
322 .irq_reg_stride = 5,
323 .status_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
324 PALMAS_INT1_STATUS),
325 .mask_base = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
326 PALMAS_INT1_MASK),
327};
328
235int palmas_ext_control_req_config(struct palmas *palmas, 329int palmas_ext_control_req_config(struct palmas *palmas,
236 enum palmas_external_requestor_id id, int ext_ctrl, bool enable) 330 enum palmas_external_requestor_id id, int ext_ctrl, bool enable)
237{ 331{
332 struct palmas_pmic_driver_data *pmic_ddata = palmas->pmic_ddata;
238 int preq_mask_bit = 0; 333 int preq_mask_bit = 0;
239 int reg_add = 0; 334 int reg_add = 0;
240 int bit_pos; 335 int bit_pos, ret;
241 int ret;
242 336
243 if (!(ext_ctrl & PALMAS_EXT_REQ)) 337 if (!(ext_ctrl & PALMAS_EXT_REQ))
244 return 0; 338 return 0;
@@ -257,8 +351,8 @@ int palmas_ext_control_req_config(struct palmas *palmas,
257 preq_mask_bit = 2; 351 preq_mask_bit = 2;
258 } 352 }
259 353
260 bit_pos = sleep_req_info[id].bit_pos; 354 bit_pos = pmic_ddata->sleep_req_info[id].bit_pos;
261 reg_add += sleep_req_info[id].reg_offset; 355 reg_add += pmic_ddata->sleep_req_info[id].reg_offset;
262 if (enable) 356 if (enable)
263 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE, 357 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
264 reg_add, BIT(bit_pos), BIT(bit_pos)); 358 reg_add, BIT(bit_pos), BIT(bit_pos));
@@ -357,14 +451,38 @@ static void palmas_power_off(void)
357static unsigned int palmas_features = PALMAS_PMIC_FEATURE_SMPS10_BOOST; 451static unsigned int palmas_features = PALMAS_PMIC_FEATURE_SMPS10_BOOST;
358static unsigned int tps659038_features; 452static unsigned int tps659038_features;
359 453
454struct palmas_driver_data {
455 unsigned int *features;
456 struct regmap_irq_chip *irq_chip;
457};
458
459static struct palmas_driver_data palmas_data = {
460 .features = &palmas_features,
461 .irq_chip = &palmas_irq_chip,
462};
463
464static struct palmas_driver_data tps659038_data = {
465 .features = &tps659038_features,
466 .irq_chip = &palmas_irq_chip,
467};
468
469static struct palmas_driver_data tps65917_data = {
470 .features = &tps659038_features,
471 .irq_chip = &tps65917_irq_chip,
472};
473
360static const struct of_device_id of_palmas_match_tbl[] = { 474static const struct of_device_id of_palmas_match_tbl[] = {
361 { 475 {
362 .compatible = "ti,palmas", 476 .compatible = "ti,palmas",
363 .data = &palmas_features, 477 .data = &palmas_data,
364 }, 478 },
365 { 479 {
366 .compatible = "ti,tps659038", 480 .compatible = "ti,tps659038",
367 .data = &tps659038_features, 481 .data = &tps659038_data,
482 },
483 {
484 .compatible = "ti,tps65917",
485 .data = &tps65917_data,
368 }, 486 },
369 { }, 487 { },
370}; 488};
@@ -375,9 +493,10 @@ static int palmas_i2c_probe(struct i2c_client *i2c,
375{ 493{
376 struct palmas *palmas; 494 struct palmas *palmas;
377 struct palmas_platform_data *pdata; 495 struct palmas_platform_data *pdata;
496 struct palmas_driver_data *driver_data;
378 struct device_node *node = i2c->dev.of_node; 497 struct device_node *node = i2c->dev.of_node;
379 int ret = 0, i; 498 int ret = 0, i;
380 unsigned int reg, addr, *features; 499 unsigned int reg, addr;
381 int slave; 500 int slave;
382 const struct of_device_id *match; 501 const struct of_device_id *match;
383 502
@@ -408,8 +527,8 @@ static int palmas_i2c_probe(struct i2c_client *i2c,
408 if (!match) 527 if (!match)
409 return -ENODATA; 528 return -ENODATA;
410 529
411 features = (unsigned int *)match->data; 530 driver_data = (struct palmas_driver_data *)match->data;
412 palmas->features = *features; 531 palmas->features = *driver_data->features;
413 532
414 for (i = 0; i < PALMAS_NUM_CLIENTS; i++) { 533 for (i = 0; i < PALMAS_NUM_CLIENTS; i++) {
415 if (i == 0) 534 if (i == 0)
@@ -463,8 +582,8 @@ static int palmas_i2c_probe(struct i2c_client *i2c,
463 regmap_write(palmas->regmap[slave], addr, reg); 582 regmap_write(palmas->regmap[slave], addr, reg);
464 583
465 ret = regmap_add_irq_chip(palmas->regmap[slave], palmas->irq, 584 ret = regmap_add_irq_chip(palmas->regmap[slave], palmas->irq,
466 IRQF_ONESHOT | pdata->irq_flags, 0, &palmas_irq_chip, 585 IRQF_ONESHOT | pdata->irq_flags, 0,
467 &palmas->irq_data); 586 driver_data->irq_chip, &palmas->irq_data);
468 if (ret < 0) 587 if (ret < 0)
469 goto err_i2c; 588 goto err_i2c;
470 589
diff --git a/drivers/regulator/lp8755.c b/drivers/regulator/lp8755.c
index 785a25e9a437..4a415d4ee463 100644
--- a/drivers/regulator/lp8755.c
+++ b/drivers/regulator/lp8755.c
@@ -339,22 +339,18 @@ static int lp8755_regulator_init(struct lp8755_chip *pchip)
339 rconfig.init_data = pdata->buck_data[buck_num]; 339 rconfig.init_data = pdata->buck_data[buck_num];
340 rconfig.of_node = pchip->dev->of_node; 340 rconfig.of_node = pchip->dev->of_node;
341 pchip->rdev[buck_num] = 341 pchip->rdev[buck_num] =
342 regulator_register(&lp8755_regulators[buck_num], &rconfig); 342 devm_regulator_register(pchip->dev,
343 &lp8755_regulators[buck_num], &rconfig);
343 if (IS_ERR(pchip->rdev[buck_num])) { 344 if (IS_ERR(pchip->rdev[buck_num])) {
344 ret = PTR_ERR(pchip->rdev[buck_num]); 345 ret = PTR_ERR(pchip->rdev[buck_num]);
345 pchip->rdev[buck_num] = NULL; 346 pchip->rdev[buck_num] = NULL;
346 dev_err(pchip->dev, "regulator init failed: buck %d\n", 347 dev_err(pchip->dev, "regulator init failed: buck %d\n",
347 buck_num); 348 buck_num);
348 goto err_buck; 349 return ret;
349 } 350 }
350 } 351 }
351 352
352 return 0; 353 return 0;
353
354err_buck:
355 for (icnt = 0; icnt < LP8755_BUCK_MAX; icnt++)
356 regulator_unregister(pchip->rdev[icnt]);
357 return ret;
358} 354}
359 355
360static irqreturn_t lp8755_irq_handler(int irq, void *data) 356static irqreturn_t lp8755_irq_handler(int irq, void *data)
@@ -490,23 +486,19 @@ static int lp8755_probe(struct i2c_client *client,
490 ret = lp8755_regulator_init(pchip); 486 ret = lp8755_regulator_init(pchip);
491 if (ret < 0) { 487 if (ret < 0) {
492 dev_err(&client->dev, "fail to initialize regulators\n"); 488 dev_err(&client->dev, "fail to initialize regulators\n");
493 goto err_regulator; 489 goto err;
494 } 490 }
495 491
496 pchip->irq = client->irq; 492 pchip->irq = client->irq;
497 ret = lp8755_int_config(pchip); 493 ret = lp8755_int_config(pchip);
498 if (ret < 0) { 494 if (ret < 0) {
499 dev_err(&client->dev, "fail to irq config\n"); 495 dev_err(&client->dev, "fail to irq config\n");
500 goto err_irq; 496 goto err;
501 } 497 }
502 498
503 return ret; 499 return ret;
504 500
505err_irq: 501err:
506 for (icnt = 0; icnt < mphase_buck[pchip->mphase].nreg; icnt++)
507 regulator_unregister(pchip->rdev[icnt]);
508
509err_regulator:
510 /* output disable */ 502 /* output disable */
511 for (icnt = 0; icnt < LP8755_BUCK_MAX; icnt++) 503 for (icnt = 0; icnt < LP8755_BUCK_MAX; icnt++)
512 lp8755_write(pchip, icnt, 0x00); 504 lp8755_write(pchip, icnt, 0x00);
@@ -519,9 +511,6 @@ static int lp8755_remove(struct i2c_client *client)
519 int icnt; 511 int icnt;
520 struct lp8755_chip *pchip = i2c_get_clientdata(client); 512 struct lp8755_chip *pchip = i2c_get_clientdata(client);
521 513
522 for (icnt = 0; icnt < mphase_buck[pchip->mphase].nreg; icnt++)
523 regulator_unregister(pchip->rdev[icnt]);
524
525 for (icnt = 0; icnt < LP8755_BUCK_MAX; icnt++) 514 for (icnt = 0; icnt < LP8755_BUCK_MAX; icnt++)
526 lp8755_write(pchip, icnt, 0x00); 515 lp8755_write(pchip, icnt, 0x00);
527 516
diff --git a/drivers/regulator/ltc3589.c b/drivers/regulator/ltc3589.c
index c8105182b8b8..c756955bfcc5 100644
--- a/drivers/regulator/ltc3589.c
+++ b/drivers/regulator/ltc3589.c
@@ -377,7 +377,7 @@ static bool ltc3589_volatile_reg(struct device *dev, unsigned int reg)
377 return false; 377 return false;
378} 378}
379 379
380struct reg_default ltc3589_reg_defaults[] = { 380static struct reg_default ltc3589_reg_defaults[] = {
381 { LTC3589_SCR1, 0x00 }, 381 { LTC3589_SCR1, 0x00 },
382 { LTC3589_OVEN, 0x00 }, 382 { LTC3589_OVEN, 0x00 },
383 { LTC3589_SCR2, 0x00 }, 383 { LTC3589_SCR2, 0x00 },
diff --git a/drivers/regulator/max8952.c b/drivers/regulator/max8952.c
index c2792f0271ab..f7f9efcfedb7 100644
--- a/drivers/regulator/max8952.c
+++ b/drivers/regulator/max8952.c
@@ -229,7 +229,6 @@ static int max8952_pmic_probe(struct i2c_client *client,
229 config.ena_gpio_flags |= GPIOF_OUT_INIT_HIGH; 229 config.ena_gpio_flags |= GPIOF_OUT_INIT_HIGH;
230 230
231 rdev = devm_regulator_register(&client->dev, &regulator, &config); 231 rdev = devm_regulator_register(&client->dev, &regulator, &config);
232
233 if (IS_ERR(rdev)) { 232 if (IS_ERR(rdev)) {
234 ret = PTR_ERR(rdev); 233 ret = PTR_ERR(rdev);
235 dev_err(&client->dev, "regulator init failed (%d)\n", ret); 234 dev_err(&client->dev, "regulator init failed (%d)\n", ret);
@@ -241,21 +240,19 @@ static int max8952_pmic_probe(struct i2c_client *client,
241 240
242 if (gpio_is_valid(pdata->gpio_vid0) && 241 if (gpio_is_valid(pdata->gpio_vid0) &&
243 gpio_is_valid(pdata->gpio_vid1)) { 242 gpio_is_valid(pdata->gpio_vid1)) {
244 if (!gpio_request(pdata->gpio_vid0, "MAX8952 VID0")) 243 unsigned long gpio_flags;
245 gpio_direction_output(pdata->gpio_vid0, 244
246 (pdata->default_mode) & 0x1); 245 gpio_flags = max8952->vid0 ?
247 else 246 GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
247 if (devm_gpio_request_one(&client->dev, pdata->gpio_vid0,
248 gpio_flags, "MAX8952 VID0"))
248 err = 1; 249 err = 1;
249 250
250 if (!gpio_request(pdata->gpio_vid1, "MAX8952 VID1")) 251 gpio_flags = max8952->vid1 ?
251 gpio_direction_output(pdata->gpio_vid1, 252 GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
252 (pdata->default_mode >> 1) & 0x1); 253 if (devm_gpio_request_one(&client->dev, pdata->gpio_vid1,
253 else { 254 gpio_flags, "MAX8952 VID1"))
254 if (!err)
255 gpio_free(pdata->gpio_vid0);
256 err = 2; 255 err = 2;
257 }
258
259 } else 256 } else
260 err = 3; 257 err = 3;
261 258
@@ -314,16 +311,6 @@ static int max8952_pmic_probe(struct i2c_client *client,
314 return 0; 311 return 0;
315} 312}
316 313
317static int max8952_pmic_remove(struct i2c_client *client)
318{
319 struct max8952_data *max8952 = i2c_get_clientdata(client);
320 struct max8952_platform_data *pdata = max8952->pdata;
321
322 gpio_free(pdata->gpio_vid0);
323 gpio_free(pdata->gpio_vid1);
324 return 0;
325}
326
327static const struct i2c_device_id max8952_ids[] = { 314static const struct i2c_device_id max8952_ids[] = {
328 { "max8952", 0 }, 315 { "max8952", 0 },
329 { }, 316 { },
@@ -332,7 +319,6 @@ MODULE_DEVICE_TABLE(i2c, max8952_ids);
332 319
333static struct i2c_driver max8952_pmic_driver = { 320static struct i2c_driver max8952_pmic_driver = {
334 .probe = max8952_pmic_probe, 321 .probe = max8952_pmic_probe,
335 .remove = max8952_pmic_remove,
336 .driver = { 322 .driver = {
337 .name = "max8952", 323 .name = "max8952",
338 .of_match_table = of_match_ptr(max8952_dt_match), 324 .of_match_table = of_match_ptr(max8952_dt_match),
diff --git a/drivers/regulator/mc13xxx-regulator-core.c b/drivers/regulator/mc13xxx-regulator-core.c
index 05b971726ffa..afba024953e1 100644
--- a/drivers/regulator/mc13xxx-regulator-core.c
+++ b/drivers/regulator/mc13xxx-regulator-core.c
@@ -33,17 +33,12 @@ static int mc13xxx_regulator_enable(struct regulator_dev *rdev)
33 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev); 33 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
34 struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators; 34 struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
35 int id = rdev_get_id(rdev); 35 int id = rdev_get_id(rdev);
36 int ret;
37 36
38 dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id); 37 dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
39 38
40 mc13xxx_lock(priv->mc13xxx); 39 return mc13xxx_reg_rmw(priv->mc13xxx, mc13xxx_regulators[id].reg,
41 ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13xxx_regulators[id].reg, 40 mc13xxx_regulators[id].enable_bit,
42 mc13xxx_regulators[id].enable_bit, 41 mc13xxx_regulators[id].enable_bit);
43 mc13xxx_regulators[id].enable_bit);
44 mc13xxx_unlock(priv->mc13xxx);
45
46 return ret;
47} 42}
48 43
49static int mc13xxx_regulator_disable(struct regulator_dev *rdev) 44static int mc13xxx_regulator_disable(struct regulator_dev *rdev)
@@ -51,16 +46,11 @@ static int mc13xxx_regulator_disable(struct regulator_dev *rdev)
51 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev); 46 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
52 struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators; 47 struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
53 int id = rdev_get_id(rdev); 48 int id = rdev_get_id(rdev);
54 int ret;
55 49
56 dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id); 50 dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
57 51
58 mc13xxx_lock(priv->mc13xxx); 52 return mc13xxx_reg_rmw(priv->mc13xxx, mc13xxx_regulators[id].reg,
59 ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13xxx_regulators[id].reg, 53 mc13xxx_regulators[id].enable_bit, 0);
60 mc13xxx_regulators[id].enable_bit, 0);
61 mc13xxx_unlock(priv->mc13xxx);
62
63 return ret;
64} 54}
65 55
66static int mc13xxx_regulator_is_enabled(struct regulator_dev *rdev) 56static int mc13xxx_regulator_is_enabled(struct regulator_dev *rdev)
@@ -70,10 +60,7 @@ static int mc13xxx_regulator_is_enabled(struct regulator_dev *rdev)
70 int ret, id = rdev_get_id(rdev); 60 int ret, id = rdev_get_id(rdev);
71 unsigned int val; 61 unsigned int val;
72 62
73 mc13xxx_lock(priv->mc13xxx);
74 ret = mc13xxx_reg_read(priv->mc13xxx, mc13xxx_regulators[id].reg, &val); 63 ret = mc13xxx_reg_read(priv->mc13xxx, mc13xxx_regulators[id].reg, &val);
75 mc13xxx_unlock(priv->mc13xxx);
76
77 if (ret) 64 if (ret)
78 return ret; 65 return ret;
79 66
@@ -86,15 +73,10 @@ static int mc13xxx_regulator_set_voltage_sel(struct regulator_dev *rdev,
86 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev); 73 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
87 struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators; 74 struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
88 int id = rdev_get_id(rdev); 75 int id = rdev_get_id(rdev);
89 int ret;
90 76
91 mc13xxx_lock(priv->mc13xxx); 77 return mc13xxx_reg_rmw(priv->mc13xxx, mc13xxx_regulators[id].vsel_reg,
92 ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13xxx_regulators[id].vsel_reg, 78 mc13xxx_regulators[id].vsel_mask,
93 mc13xxx_regulators[id].vsel_mask, 79 selector << mc13xxx_regulators[id].vsel_shift);
94 selector << mc13xxx_regulators[id].vsel_shift);
95 mc13xxx_unlock(priv->mc13xxx);
96
97 return ret;
98} 80}
99 81
100static int mc13xxx_regulator_get_voltage(struct regulator_dev *rdev) 82static int mc13xxx_regulator_get_voltage(struct regulator_dev *rdev)
@@ -106,11 +88,8 @@ static int mc13xxx_regulator_get_voltage(struct regulator_dev *rdev)
106 88
107 dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id); 89 dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
108 90
109 mc13xxx_lock(priv->mc13xxx);
110 ret = mc13xxx_reg_read(priv->mc13xxx, 91 ret = mc13xxx_reg_read(priv->mc13xxx,
111 mc13xxx_regulators[id].vsel_reg, &val); 92 mc13xxx_regulators[id].vsel_reg, &val);
112 mc13xxx_unlock(priv->mc13xxx);
113
114 if (ret) 93 if (ret)
115 return ret; 94 return ret;
116 95
diff --git a/drivers/regulator/mc13xxx.h b/drivers/regulator/mc13xxx.h
index 06c8903f182a..2ab9bfd93b4e 100644
--- a/drivers/regulator/mc13xxx.h
+++ b/drivers/regulator/mc13xxx.h
@@ -21,7 +21,6 @@ struct mc13xxx_regulator {
21 int vsel_reg; 21 int vsel_reg;
22 int vsel_shift; 22 int vsel_shift;
23 int vsel_mask; 23 int vsel_mask;
24 int hi_bit;
25}; 24};
26 25
27struct mc13xxx_regulator_priv { 26struct mc13xxx_regulator_priv {
diff --git a/drivers/regulator/palmas-regulator.c b/drivers/regulator/palmas-regulator.c
index 93b4ad842901..a7ce34d1b5f2 100644
--- a/drivers/regulator/palmas-regulator.c
+++ b/drivers/regulator/palmas-regulator.c
@@ -27,15 +27,6 @@
27#include <linux/of_platform.h> 27#include <linux/of_platform.h>
28#include <linux/regulator/of_regulator.h> 28#include <linux/regulator/of_regulator.h>
29 29
30struct regs_info {
31 char *name;
32 char *sname;
33 u8 vsel_addr;
34 u8 ctrl_addr;
35 u8 tstep_addr;
36 int sleep_id;
37};
38
39static const struct regulator_linear_range smps_low_ranges[] = { 30static const struct regulator_linear_range smps_low_ranges[] = {
40 REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0), 31 REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0),
41 REGULATOR_LINEAR_RANGE(500000, 0x1, 0x6, 0), 32 REGULATOR_LINEAR_RANGE(500000, 0x1, 0x6, 0),
@@ -50,7 +41,7 @@ static const struct regulator_linear_range smps_high_ranges[] = {
50 REGULATOR_LINEAR_RANGE(3300000, 0x7A, 0x7f, 0), 41 REGULATOR_LINEAR_RANGE(3300000, 0x7A, 0x7f, 0),
51}; 42};
52 43
53static const struct regs_info palmas_regs_info[] = { 44static struct palmas_regs_info palmas_generic_regs_info[] = {
54 { 45 {
55 .name = "SMPS12", 46 .name = "SMPS12",
56 .sname = "smps1-in", 47 .sname = "smps1-in",
@@ -236,6 +227,153 @@ static const struct regs_info palmas_regs_info[] = {
236 }, 227 },
237}; 228};
238 229
230static struct palmas_regs_info tps65917_regs_info[] = {
231 {
232 .name = "SMPS1",
233 .sname = "smps1-in",
234 .vsel_addr = TPS65917_SMPS1_VOLTAGE,
235 .ctrl_addr = TPS65917_SMPS1_CTRL,
236 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
237 },
238 {
239 .name = "SMPS2",
240 .sname = "smps2-in",
241 .vsel_addr = TPS65917_SMPS2_VOLTAGE,
242 .ctrl_addr = TPS65917_SMPS2_CTRL,
243 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
244 },
245 {
246 .name = "SMPS3",
247 .sname = "smps3-in",
248 .vsel_addr = TPS65917_SMPS3_VOLTAGE,
249 .ctrl_addr = TPS65917_SMPS3_CTRL,
250 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
251 },
252 {
253 .name = "SMPS4",
254 .sname = "smps4-in",
255 .vsel_addr = TPS65917_SMPS4_VOLTAGE,
256 .ctrl_addr = TPS65917_SMPS4_CTRL,
257 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
258 },
259 {
260 .name = "SMPS5",
261 .sname = "smps5-in",
262 .vsel_addr = TPS65917_SMPS5_VOLTAGE,
263 .ctrl_addr = TPS65917_SMPS5_CTRL,
264 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
265 },
266 {
267 .name = "LDO1",
268 .sname = "ldo1-in",
269 .vsel_addr = TPS65917_LDO1_VOLTAGE,
270 .ctrl_addr = TPS65917_LDO1_CTRL,
271 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO1,
272 },
273 {
274 .name = "LDO2",
275 .sname = "ldo2-in",
276 .vsel_addr = TPS65917_LDO2_VOLTAGE,
277 .ctrl_addr = TPS65917_LDO2_CTRL,
278 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO2,
279 },
280 {
281 .name = "LDO3",
282 .sname = "ldo3-in",
283 .vsel_addr = TPS65917_LDO3_VOLTAGE,
284 .ctrl_addr = TPS65917_LDO3_CTRL,
285 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO3,
286 },
287 {
288 .name = "LDO4",
289 .sname = "ldo4-in",
290 .vsel_addr = TPS65917_LDO4_VOLTAGE,
291 .ctrl_addr = TPS65917_LDO4_CTRL,
292 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO4,
293 },
294 {
295 .name = "LDO5",
296 .sname = "ldo5-in",
297 .vsel_addr = TPS65917_LDO5_VOLTAGE,
298 .ctrl_addr = TPS65917_LDO5_CTRL,
299 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO5,
300 },
301 {
302 .name = "REGEN1",
303 .ctrl_addr = TPS65917_REGEN1_CTRL,
304 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
305 },
306 {
307 .name = "REGEN2",
308 .ctrl_addr = TPS65917_REGEN2_CTRL,
309 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
310 },
311 {
312 .name = "REGEN3",
313 .ctrl_addr = TPS65917_REGEN3_CTRL,
314 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
315 },
316};
317
318#define EXTERNAL_REQUESTOR(_id, _offset, _pos) \
319 [PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \
320 .id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \
321 .reg_offset = _offset, \
322 .bit_pos = _pos, \
323 }
324
325static struct palmas_sleep_requestor_info palma_sleep_req_info[] = {
326 EXTERNAL_REQUESTOR(REGEN1, 0, 0),
327 EXTERNAL_REQUESTOR(REGEN2, 0, 1),
328 EXTERNAL_REQUESTOR(SYSEN1, 0, 2),
329 EXTERNAL_REQUESTOR(SYSEN2, 0, 3),
330 EXTERNAL_REQUESTOR(CLK32KG, 0, 4),
331 EXTERNAL_REQUESTOR(CLK32KGAUDIO, 0, 5),
332 EXTERNAL_REQUESTOR(REGEN3, 0, 6),
333 EXTERNAL_REQUESTOR(SMPS12, 1, 0),
334 EXTERNAL_REQUESTOR(SMPS3, 1, 1),
335 EXTERNAL_REQUESTOR(SMPS45, 1, 2),
336 EXTERNAL_REQUESTOR(SMPS6, 1, 3),
337 EXTERNAL_REQUESTOR(SMPS7, 1, 4),
338 EXTERNAL_REQUESTOR(SMPS8, 1, 5),
339 EXTERNAL_REQUESTOR(SMPS9, 1, 6),
340 EXTERNAL_REQUESTOR(SMPS10, 1, 7),
341 EXTERNAL_REQUESTOR(LDO1, 2, 0),
342 EXTERNAL_REQUESTOR(LDO2, 2, 1),
343 EXTERNAL_REQUESTOR(LDO3, 2, 2),
344 EXTERNAL_REQUESTOR(LDO4, 2, 3),
345 EXTERNAL_REQUESTOR(LDO5, 2, 4),
346 EXTERNAL_REQUESTOR(LDO6, 2, 5),
347 EXTERNAL_REQUESTOR(LDO7, 2, 6),
348 EXTERNAL_REQUESTOR(LDO8, 2, 7),
349 EXTERNAL_REQUESTOR(LDO9, 3, 0),
350 EXTERNAL_REQUESTOR(LDOLN, 3, 1),
351 EXTERNAL_REQUESTOR(LDOUSB, 3, 2),
352};
353
354#define EXTERNAL_REQUESTOR_TPS65917(_id, _offset, _pos) \
355 [TPS65917_EXTERNAL_REQSTR_ID_##_id] = { \
356 .id = TPS65917_EXTERNAL_REQSTR_ID_##_id, \
357 .reg_offset = _offset, \
358 .bit_pos = _pos, \
359 }
360
361static struct palmas_sleep_requestor_info tps65917_sleep_req_info[] = {
362 EXTERNAL_REQUESTOR_TPS65917(REGEN1, 0, 0),
363 EXTERNAL_REQUESTOR_TPS65917(REGEN2, 0, 1),
364 EXTERNAL_REQUESTOR_TPS65917(REGEN3, 0, 6),
365 EXTERNAL_REQUESTOR_TPS65917(SMPS1, 1, 0),
366 EXTERNAL_REQUESTOR_TPS65917(SMPS2, 1, 1),
367 EXTERNAL_REQUESTOR_TPS65917(SMPS3, 1, 2),
368 EXTERNAL_REQUESTOR_TPS65917(SMPS4, 1, 3),
369 EXTERNAL_REQUESTOR_TPS65917(SMPS5, 1, 4),
370 EXTERNAL_REQUESTOR_TPS65917(LDO1, 2, 0),
371 EXTERNAL_REQUESTOR_TPS65917(LDO2, 2, 1),
372 EXTERNAL_REQUESTOR_TPS65917(LDO3, 2, 2),
373 EXTERNAL_REQUESTOR_TPS65917(LDO4, 2, 3),
374 EXTERNAL_REQUESTOR_TPS65917(LDO5, 2, 4),
375};
376
239static unsigned int palmas_smps_ramp_delay[4] = {0, 10000, 5000, 2500}; 377static unsigned int palmas_smps_ramp_delay[4] = {0, 10000, 5000, 2500};
240 378
241#define SMPS_CTRL_MODE_OFF 0x00 379#define SMPS_CTRL_MODE_OFF 0x00
@@ -296,12 +434,15 @@ static int palmas_ldo_write(struct palmas *palmas, unsigned int reg,
296 434
297static int palmas_set_mode_smps(struct regulator_dev *dev, unsigned int mode) 435static int palmas_set_mode_smps(struct regulator_dev *dev, unsigned int mode)
298{ 436{
299 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
300 int id = rdev_get_id(dev); 437 int id = rdev_get_id(dev);
438 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
439 struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
440 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
301 unsigned int reg; 441 unsigned int reg;
302 bool rail_enable = true; 442 bool rail_enable = true;
303 443
304 palmas_smps_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, &reg); 444 palmas_smps_read(pmic->palmas, rinfo->ctrl_addr, &reg);
445
305 reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; 446 reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
306 447
307 if (reg == SMPS_CTRL_MODE_OFF) 448 if (reg == SMPS_CTRL_MODE_OFF)
@@ -323,8 +464,7 @@ static int palmas_set_mode_smps(struct regulator_dev *dev, unsigned int mode)
323 464
324 pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; 465 pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
325 if (rail_enable) 466 if (rail_enable)
326 palmas_smps_write(pmic->palmas, 467 palmas_smps_write(pmic->palmas, rinfo->ctrl_addr, reg);
327 palmas_regs_info[id].ctrl_addr, reg);
328 468
329 /* Switch the enable value to ensure this is used for enable */ 469 /* Switch the enable value to ensure this is used for enable */
330 pmic->desc[id].enable_val = pmic->current_reg_mode[id]; 470 pmic->desc[id].enable_val = pmic->current_reg_mode[id];
@@ -355,10 +495,11 @@ static unsigned int palmas_get_mode_smps(struct regulator_dev *dev)
355static int palmas_smps_set_ramp_delay(struct regulator_dev *rdev, 495static int palmas_smps_set_ramp_delay(struct regulator_dev *rdev,
356 int ramp_delay) 496 int ramp_delay)
357{ 497{
358 struct palmas_pmic *pmic = rdev_get_drvdata(rdev);
359 int id = rdev_get_id(rdev); 498 int id = rdev_get_id(rdev);
499 struct palmas_pmic *pmic = rdev_get_drvdata(rdev);
500 struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
501 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
360 unsigned int reg = 0; 502 unsigned int reg = 0;
361 unsigned int addr = palmas_regs_info[id].tstep_addr;
362 int ret; 503 int ret;
363 504
364 /* SMPS3 and SMPS7 do not have tstep_addr setting */ 505 /* SMPS3 and SMPS7 do not have tstep_addr setting */
@@ -377,7 +518,7 @@ static int palmas_smps_set_ramp_delay(struct regulator_dev *rdev,
377 else 518 else
378 reg = 1; 519 reg = 1;
379 520
380 ret = palmas_smps_write(pmic->palmas, addr, reg); 521 ret = palmas_smps_write(pmic->palmas, rinfo->tstep_addr, reg);
381 if (ret < 0) { 522 if (ret < 0) {
382 dev_err(pmic->palmas->dev, "TSTEP write failed: %d\n", ret); 523 dev_err(pmic->palmas->dev, "TSTEP write failed: %d\n", ret);
383 return ret; 524 return ret;
@@ -424,13 +565,37 @@ static struct regulator_ops palmas_ops_smps10 = {
424 .get_bypass = regulator_get_bypass_regmap, 565 .get_bypass = regulator_get_bypass_regmap,
425}; 566};
426 567
568static struct regulator_ops tps65917_ops_smps = {
569 .is_enabled = regulator_is_enabled_regmap,
570 .enable = regulator_enable_regmap,
571 .disable = regulator_disable_regmap,
572 .set_mode = palmas_set_mode_smps,
573 .get_mode = palmas_get_mode_smps,
574 .get_voltage_sel = regulator_get_voltage_sel_regmap,
575 .set_voltage_sel = regulator_set_voltage_sel_regmap,
576 .list_voltage = regulator_list_voltage_linear_range,
577 .map_voltage = regulator_map_voltage_linear_range,
578 .set_voltage_time_sel = regulator_set_voltage_time_sel,
579};
580
581static struct regulator_ops tps65917_ops_ext_control_smps = {
582 .set_mode = palmas_set_mode_smps,
583 .get_mode = palmas_get_mode_smps,
584 .get_voltage_sel = regulator_get_voltage_sel_regmap,
585 .set_voltage_sel = regulator_set_voltage_sel_regmap,
586 .list_voltage = regulator_list_voltage_linear_range,
587 .map_voltage = regulator_map_voltage_linear_range,
588};
589
427static int palmas_is_enabled_ldo(struct regulator_dev *dev) 590static int palmas_is_enabled_ldo(struct regulator_dev *dev)
428{ 591{
429 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
430 int id = rdev_get_id(dev); 592 int id = rdev_get_id(dev);
593 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
594 struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
595 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
431 unsigned int reg; 596 unsigned int reg;
432 597
433 palmas_ldo_read(pmic->palmas, palmas_regs_info[id].ctrl_addr, &reg); 598 palmas_ldo_read(pmic->palmas, rinfo->ctrl_addr, &reg);
434 599
435 reg &= PALMAS_LDO1_CTRL_STATUS; 600 reg &= PALMAS_LDO1_CTRL_STATUS;
436 601
@@ -463,14 +628,26 @@ static struct regulator_ops palmas_ops_extreg = {
463static struct regulator_ops palmas_ops_ext_control_extreg = { 628static struct regulator_ops palmas_ops_ext_control_extreg = {
464}; 629};
465 630
631static struct regulator_ops tps65917_ops_ldo = {
632 .is_enabled = palmas_is_enabled_ldo,
633 .enable = regulator_enable_regmap,
634 .disable = regulator_disable_regmap,
635 .get_voltage_sel = regulator_get_voltage_sel_regmap,
636 .set_voltage_sel = regulator_set_voltage_sel_regmap,
637 .list_voltage = regulator_list_voltage_linear,
638 .map_voltage = regulator_map_voltage_linear,
639 .set_voltage_time_sel = regulator_set_voltage_time_sel,
640};
641
466static int palmas_regulator_config_external(struct palmas *palmas, int id, 642static int palmas_regulator_config_external(struct palmas *palmas, int id,
467 struct palmas_reg_init *reg_init) 643 struct palmas_reg_init *reg_init)
468{ 644{
469 int sleep_id = palmas_regs_info[id].sleep_id; 645 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
646 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
470 int ret; 647 int ret;
471 648
472 ret = palmas_ext_control_req_config(palmas, sleep_id, 649 ret = palmas_ext_control_req_config(palmas, rinfo->sleep_id,
473 reg_init->roof_floor, true); 650 reg_init->roof_floor, true);
474 if (ret < 0) 651 if (ret < 0)
475 dev_err(palmas->dev, 652 dev_err(palmas->dev,
476 "Ext control config for regulator %d failed %d\n", 653 "Ext control config for regulator %d failed %d\n",
@@ -488,10 +665,10 @@ static int palmas_smps_init(struct palmas *palmas, int id,
488 struct palmas_reg_init *reg_init) 665 struct palmas_reg_init *reg_init)
489{ 666{
490 unsigned int reg; 667 unsigned int reg;
491 unsigned int addr;
492 int ret; 668 int ret;
493 669 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
494 addr = palmas_regs_info[id].ctrl_addr; 670 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
671 unsigned int addr = rinfo->ctrl_addr;
495 672
496 ret = palmas_smps_read(palmas, addr, &reg); 673 ret = palmas_smps_read(palmas, addr, &reg);
497 if (ret) 674 if (ret)
@@ -526,12 +703,11 @@ static int palmas_smps_init(struct palmas *palmas, int id,
526 if (ret) 703 if (ret)
527 return ret; 704 return ret;
528 705
529 if (palmas_regs_info[id].vsel_addr && reg_init->vsel) { 706 if (rinfo->vsel_addr && reg_init->vsel) {
530 addr = palmas_regs_info[id].vsel_addr;
531 707
532 reg = reg_init->vsel; 708 reg = reg_init->vsel;
533 709
534 ret = palmas_smps_write(palmas, addr, reg); 710 ret = palmas_smps_write(palmas, rinfo->vsel_addr, reg);
535 if (ret) 711 if (ret)
536 return ret; 712 return ret;
537 } 713 }
@@ -539,7 +715,6 @@ static int palmas_smps_init(struct palmas *palmas, int id,
539 if (reg_init->roof_floor && (id != PALMAS_REG_SMPS10_OUT1) && 715 if (reg_init->roof_floor && (id != PALMAS_REG_SMPS10_OUT1) &&
540 (id != PALMAS_REG_SMPS10_OUT2)) { 716 (id != PALMAS_REG_SMPS10_OUT2)) {
541 /* Enable externally controlled regulator */ 717 /* Enable externally controlled regulator */
542 addr = palmas_regs_info[id].ctrl_addr;
543 ret = palmas_smps_read(palmas, addr, &reg); 718 ret = palmas_smps_read(palmas, addr, &reg);
544 if (ret < 0) 719 if (ret < 0)
545 return ret; 720 return ret;
@@ -561,8 +736,10 @@ static int palmas_ldo_init(struct palmas *palmas, int id,
561 unsigned int reg; 736 unsigned int reg;
562 unsigned int addr; 737 unsigned int addr;
563 int ret; 738 int ret;
739 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
740 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
564 741
565 addr = palmas_regs_info[id].ctrl_addr; 742 addr = rinfo->ctrl_addr;
566 743
567 ret = palmas_ldo_read(palmas, addr, &reg); 744 ret = palmas_ldo_read(palmas, addr, &reg);
568 if (ret) 745 if (ret)
@@ -584,7 +761,6 @@ static int palmas_ldo_init(struct palmas *palmas, int id,
584 761
585 if (reg_init->roof_floor) { 762 if (reg_init->roof_floor) {
586 /* Enable externally controlled regulator */ 763 /* Enable externally controlled regulator */
587 addr = palmas_regs_info[id].ctrl_addr;
588 ret = palmas_update_bits(palmas, PALMAS_LDO_BASE, 764 ret = palmas_update_bits(palmas, PALMAS_LDO_BASE,
589 addr, PALMAS_LDO1_CTRL_MODE_ACTIVE, 765 addr, PALMAS_LDO1_CTRL_MODE_ACTIVE,
590 PALMAS_LDO1_CTRL_MODE_ACTIVE); 766 PALMAS_LDO1_CTRL_MODE_ACTIVE);
@@ -605,8 +781,10 @@ static int palmas_extreg_init(struct palmas *palmas, int id,
605 unsigned int addr; 781 unsigned int addr;
606 int ret; 782 int ret;
607 unsigned int val = 0; 783 unsigned int val = 0;
784 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
785 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
608 786
609 addr = palmas_regs_info[id].ctrl_addr; 787 addr = rinfo->ctrl_addr;
610 788
611 if (reg_init->mode_sleep) 789 if (reg_init->mode_sleep)
612 val = PALMAS_REGEN1_CTRL_MODE_SLEEP; 790 val = PALMAS_REGEN1_CTRL_MODE_SLEEP;
@@ -621,7 +799,6 @@ static int palmas_extreg_init(struct palmas *palmas, int id,
621 799
622 if (reg_init->roof_floor) { 800 if (reg_init->roof_floor) {
623 /* Enable externally controlled regulator */ 801 /* Enable externally controlled regulator */
624 addr = palmas_regs_info[id].ctrl_addr;
625 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE, 802 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
626 addr, PALMAS_REGEN1_CTRL_MODE_ACTIVE, 803 addr, PALMAS_REGEN1_CTRL_MODE_ACTIVE,
627 PALMAS_REGEN1_CTRL_MODE_ACTIVE); 804 PALMAS_REGEN1_CTRL_MODE_ACTIVE);
@@ -641,8 +818,11 @@ static void palmas_enable_ldo8_track(struct palmas *palmas)
641 unsigned int reg; 818 unsigned int reg;
642 unsigned int addr; 819 unsigned int addr;
643 int ret; 820 int ret;
821 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
822 struct palmas_regs_info *rinfo;
644 823
645 addr = palmas_regs_info[PALMAS_REG_LDO8].ctrl_addr; 824 rinfo = &ddata->palmas_regs_info[PALMAS_REG_LDO8];
825 addr = rinfo->ctrl_addr;
646 826
647 ret = palmas_ldo_read(palmas, addr, &reg); 827 ret = palmas_ldo_read(palmas, addr, &reg);
648 if (ret) { 828 if (ret) {
@@ -661,7 +841,7 @@ static void palmas_enable_ldo8_track(struct palmas *palmas)
661 * output is defined by the LDO8_VOLTAGE.VSEL register divided by two, 841 * output is defined by the LDO8_VOLTAGE.VSEL register divided by two,
662 * and can be set from 0.45 to 1.65 V. 842 * and can be set from 0.45 to 1.65 V.
663 */ 843 */
664 addr = palmas_regs_info[PALMAS_REG_LDO8].vsel_addr; 844 addr = rinfo->vsel_addr;
665 ret = palmas_ldo_read(palmas, addr, &reg); 845 ret = palmas_ldo_read(palmas, addr, &reg);
666 if (ret) { 846 if (ret) {
667 dev_err(palmas->dev, "Error in reading ldo8 voltage reg\n"); 847 dev_err(palmas->dev, "Error in reading ldo8 voltage reg\n");
@@ -676,169 +856,230 @@ static void palmas_enable_ldo8_track(struct palmas *palmas)
676 return; 856 return;
677} 857}
678 858
679static struct of_regulator_match palmas_matches[] = { 859static int palmas_ldo_registration(struct palmas_pmic *pmic,
680 { .name = "smps12", }, 860 struct palmas_pmic_driver_data *ddata,
681 { .name = "smps123", }, 861 struct palmas_pmic_platform_data *pdata,
682 { .name = "smps3", }, 862 const char *pdev_name,
683 { .name = "smps45", }, 863 struct regulator_config config)
684 { .name = "smps457", },
685 { .name = "smps6", },
686 { .name = "smps7", },
687 { .name = "smps8", },
688 { .name = "smps9", },
689 { .name = "smps10_out2", },
690 { .name = "smps10_out1", },
691 { .name = "ldo1", },
692 { .name = "ldo2", },
693 { .name = "ldo3", },
694 { .name = "ldo4", },
695 { .name = "ldo5", },
696 { .name = "ldo6", },
697 { .name = "ldo7", },
698 { .name = "ldo8", },
699 { .name = "ldo9", },
700 { .name = "ldoln", },
701 { .name = "ldousb", },
702 { .name = "regen1", },
703 { .name = "regen2", },
704 { .name = "regen3", },
705 { .name = "sysen1", },
706 { .name = "sysen2", },
707};
708
709static void palmas_dt_to_pdata(struct device *dev,
710 struct device_node *node,
711 struct palmas_pmic_platform_data *pdata)
712{ 864{
713 struct device_node *regulators; 865 int id, ret;
714 u32 prop; 866 struct regulator_dev *rdev;
715 int idx, ret; 867 struct palmas_reg_init *reg_init;
868 struct palmas_regs_info *rinfo;
869 struct regulator_desc *desc;
716 870
717 node = of_node_get(node); 871 for (id = ddata->ldo_begin; id < ddata->max_reg; id++) {
718 regulators = of_get_child_by_name(node, "regulators"); 872 if (pdata && pdata->reg_init[id])
719 if (!regulators) { 873 reg_init = pdata->reg_init[id];
720 dev_info(dev, "regulator node not found\n"); 874 else
721 return; 875 reg_init = NULL;
722 }
723 876
724 ret = of_regulator_match(dev, regulators, palmas_matches, 877 rinfo = &ddata->palmas_regs_info[id];
725 PALMAS_NUM_REGS); 878 /* Miss out regulators which are not available due
726 of_node_put(regulators); 879 * to alternate functions.
727 if (ret < 0) { 880 */
728 dev_err(dev, "Error parsing regulator init data: %d\n", ret);
729 return;
730 }
731 881
732 for (idx = 0; idx < PALMAS_NUM_REGS; idx++) { 882 /* Register the regulators */
733 if (!palmas_matches[idx].init_data || 883 desc = &pmic->desc[id];
734 !palmas_matches[idx].of_node) 884 desc->name = rinfo->name;
735 continue; 885 desc->id = id;
886 desc->type = REGULATOR_VOLTAGE;
887 desc->owner = THIS_MODULE;
736 888
737 pdata->reg_data[idx] = palmas_matches[idx].init_data; 889 if (id < PALMAS_REG_REGEN1) {
890 desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES;
891 if (reg_init && reg_init->roof_floor)
892 desc->ops = &palmas_ops_ext_control_ldo;
893 else
894 desc->ops = &palmas_ops_ldo;
895 desc->min_uV = 900000;
896 desc->uV_step = 50000;
897 desc->linear_min_sel = 1;
898 desc->enable_time = 500;
899 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
900 rinfo->vsel_addr);
901 desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK;
902 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
903 rinfo->ctrl_addr);
904 desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE;
738 905
739 pdata->reg_init[idx] = devm_kzalloc(dev, 906 /* Check if LDO8 is in tracking mode or not */
740 sizeof(struct palmas_reg_init), GFP_KERNEL); 907 if (pdata && (id == PALMAS_REG_LDO8) &&
908 pdata->enable_ldo8_tracking) {
909 palmas_enable_ldo8_track(pmic->palmas);
910 desc->min_uV = 450000;
911 desc->uV_step = 25000;
912 }
741 913
742 pdata->reg_init[idx]->warm_reset = 914 /* LOD6 in vibrator mode will have enable time 2000us */
743 of_property_read_bool(palmas_matches[idx].of_node, 915 if (pdata && pdata->ldo6_vibrator &&
744 "ti,warm-reset"); 916 (id == PALMAS_REG_LDO6))
917 desc->enable_time = 2000;
918 } else {
919 desc->n_voltages = 1;
920 if (reg_init && reg_init->roof_floor)
921 desc->ops = &palmas_ops_ext_control_extreg;
922 else
923 desc->ops = &palmas_ops_extreg;
924 desc->enable_reg =
925 PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
926 rinfo->ctrl_addr);
927 desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE;
928 }
745 929
746 ret = of_property_read_u32(palmas_matches[idx].of_node, 930 if (pdata)
747 "ti,roof-floor", &prop); 931 config.init_data = pdata->reg_data[id];
748 /* EINVAL: Property not found */ 932 else
749 if (ret != -EINVAL) { 933 config.init_data = NULL;
750 int econtrol;
751 934
752 /* use default value, when no value is specified */ 935 desc->supply_name = rinfo->sname;
753 econtrol = PALMAS_EXT_CONTROL_NSLEEP; 936 config.of_node = ddata->palmas_matches[id].of_node;
754 if (!ret) {
755 switch (prop) {
756 case 1:
757 econtrol = PALMAS_EXT_CONTROL_ENABLE1;
758 break;
759 case 2:
760 econtrol = PALMAS_EXT_CONTROL_ENABLE2;
761 break;
762 case 3:
763 econtrol = PALMAS_EXT_CONTROL_NSLEEP;
764 break;
765 default:
766 WARN_ON(1);
767 dev_warn(dev,
768 "%s: Invalid roof-floor option: %u\n",
769 palmas_matches[idx].name, prop);
770 break;
771 }
772 }
773 pdata->reg_init[idx]->roof_floor = econtrol;
774 }
775 937
776 ret = of_property_read_u32(palmas_matches[idx].of_node, 938 rdev = devm_regulator_register(pmic->dev, desc, &config);
777 "ti,mode-sleep", &prop); 939 if (IS_ERR(rdev)) {
778 if (!ret) 940 dev_err(pmic->dev,
779 pdata->reg_init[idx]->mode_sleep = prop; 941 "failed to register %s regulator\n",
942 pdev_name);
943 return PTR_ERR(rdev);
944 }
780 945
781 ret = of_property_read_bool(palmas_matches[idx].of_node, 946 /* Save regulator for cleanup */
782 "ti,smps-range"); 947 pmic->rdev[id] = rdev;
783 if (ret)
784 pdata->reg_init[idx]->vsel =
785 PALMAS_SMPS12_VOLTAGE_RANGE;
786 948
787 if (idx == PALMAS_REG_LDO8) 949 /* Initialise sleep/init values from platform data */
788 pdata->enable_ldo8_tracking = of_property_read_bool( 950 if (pdata) {
789 palmas_matches[idx].of_node, 951 reg_init = pdata->reg_init[id];
790 "ti,enable-ldo8-tracking"); 952 if (reg_init) {
953 if (id <= ddata->ldo_end)
954 ret = palmas_ldo_init(pmic->palmas, id,
955 reg_init);
956 else
957 ret = palmas_extreg_init(pmic->palmas,
958 id, reg_init);
959 if (ret)
960 return ret;
961 }
962 }
791 } 963 }
792 964
793 pdata->ldo6_vibrator = of_property_read_bool(node, "ti,ldo6-vibrator"); 965 return 0;
794} 966}
795 967
796 968static int tps65917_ldo_registration(struct palmas_pmic *pmic,
797static int palmas_regulators_probe(struct platform_device *pdev) 969 struct palmas_pmic_driver_data *ddata,
970 struct palmas_pmic_platform_data *pdata,
971 const char *pdev_name,
972 struct regulator_config config)
798{ 973{
799 struct palmas *palmas = dev_get_drvdata(pdev->dev.parent); 974 int id, ret;
800 struct palmas_pmic_platform_data *pdata = dev_get_platdata(&pdev->dev);
801 struct device_node *node = pdev->dev.of_node;
802 struct regulator_dev *rdev; 975 struct regulator_dev *rdev;
803 struct regulator_config config = { };
804 struct palmas_pmic *pmic;
805 struct palmas_reg_init *reg_init; 976 struct palmas_reg_init *reg_init;
806 int id = 0, ret; 977 struct palmas_regs_info *rinfo;
807 unsigned int addr, reg; 978 struct regulator_desc *desc;
808 979
809 if (node && !pdata) { 980 for (id = ddata->ldo_begin; id < ddata->max_reg; id++) {
810 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 981 if (pdata && pdata->reg_init[id])
982 reg_init = pdata->reg_init[id];
983 else
984 reg_init = NULL;
811 985
812 if (!pdata) 986 /* Miss out regulators which are not available due
813 return -ENOMEM; 987 * to alternate functions.
988 */
989 rinfo = &ddata->palmas_regs_info[id];
814 990
815 palmas_dt_to_pdata(&pdev->dev, node, pdata); 991 /* Register the regulators */
816 } 992 desc = &pmic->desc[id];
993 desc->name = rinfo->name;
994 desc->id = id;
995 desc->type = REGULATOR_VOLTAGE;
996 desc->owner = THIS_MODULE;
997
998 if (id < TPS65917_REG_REGEN1) {
999 desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES;
1000 if (reg_init && reg_init->roof_floor)
1001 desc->ops = &palmas_ops_ext_control_ldo;
1002 else
1003 desc->ops = &tps65917_ops_ldo;
1004 desc->min_uV = 900000;
1005 desc->uV_step = 50000;
1006 desc->linear_min_sel = 1;
1007 desc->enable_time = 500;
1008 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
1009 rinfo->vsel_addr);
1010 desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK;
1011 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
1012 rinfo->ctrl_addr);
1013 desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE;
1014 /*
1015 * To be confirmed. Discussion on going with PMIC Team.
1016 * It is of the order of ~60mV/uS.
1017 */
1018 desc->ramp_delay = 2500;
1019 } else {
1020 desc->n_voltages = 1;
1021 if (reg_init && reg_init->roof_floor)
1022 desc->ops = &palmas_ops_ext_control_extreg;
1023 else
1024 desc->ops = &palmas_ops_extreg;
1025 desc->enable_reg =
1026 PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
1027 rinfo->ctrl_addr);
1028 desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE;
1029 }
817 1030
818 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL); 1031 if (pdata)
819 if (!pmic) 1032 config.init_data = pdata->reg_data[id];
820 return -ENOMEM; 1033 else
1034 config.init_data = NULL;
821 1035
822 pmic->dev = &pdev->dev; 1036 desc->supply_name = rinfo->sname;
823 pmic->palmas = palmas; 1037 config.of_node = ddata->palmas_matches[id].of_node;
824 palmas->pmic = pmic;
825 platform_set_drvdata(pdev, pmic);
826 1038
827 ret = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, &reg); 1039 rdev = devm_regulator_register(pmic->dev, desc, &config);
828 if (ret) 1040 if (IS_ERR(rdev)) {
829 return ret; 1041 dev_err(pmic->dev,
1042 "failed to register %s regulator\n",
1043 pdev_name);
1044 return PTR_ERR(rdev);
1045 }
830 1046
831 if (reg & PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN) 1047 /* Save regulator for cleanup */
832 pmic->smps123 = 1; 1048 pmic->rdev[id] = rdev;
833 1049
834 if (reg & PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN) 1050 /* Initialise sleep/init values from platform data */
835 pmic->smps457 = 1; 1051 if (pdata) {
1052 reg_init = pdata->reg_init[id];
1053 if (reg_init) {
1054 if (id < TPS65917_REG_REGEN1)
1055 ret = palmas_ldo_init(pmic->palmas,
1056 id, reg_init);
1057 else
1058 ret = palmas_extreg_init(pmic->palmas,
1059 id, reg_init);
1060 if (ret)
1061 return ret;
1062 }
1063 }
1064 }
836 1065
837 config.regmap = palmas->regmap[REGULATOR_SLAVE]; 1066 return 0;
838 config.dev = &pdev->dev; 1067}
839 config.driver_data = pmic; 1068
1069static int palmas_smps_registration(struct palmas_pmic *pmic,
1070 struct palmas_pmic_driver_data *ddata,
1071 struct palmas_pmic_platform_data *pdata,
1072 const char *pdev_name,
1073 struct regulator_config config)
1074{
1075 int id, ret;
1076 unsigned int addr, reg;
1077 struct regulator_dev *rdev;
1078 struct palmas_reg_init *reg_init;
1079 struct palmas_regs_info *rinfo;
1080 struct regulator_desc *desc;
840 1081
841 for (id = 0; id < PALMAS_REG_LDO1; id++) { 1082 for (id = ddata->smps_start; id <= ddata->smps_end; id++) {
842 bool ramp_delay_support = false; 1083 bool ramp_delay_support = false;
843 1084
844 /* 1085 /*
@@ -872,30 +1113,31 @@ static int palmas_regulators_probe(struct platform_device *pdev)
872 break; 1113 break;
873 case PALMAS_REG_SMPS10_OUT1: 1114 case PALMAS_REG_SMPS10_OUT1:
874 case PALMAS_REG_SMPS10_OUT2: 1115 case PALMAS_REG_SMPS10_OUT2:
875 if (!PALMAS_PMIC_HAS(palmas, SMPS10_BOOST)) 1116 if (!PALMAS_PMIC_HAS(pmic->palmas, SMPS10_BOOST))
876 continue; 1117 continue;
877 } 1118 }
1119 rinfo = &ddata->palmas_regs_info[id];
1120 desc = &pmic->desc[id];
878 1121
879 if ((id == PALMAS_REG_SMPS6) || (id == PALMAS_REG_SMPS8)) 1122 if ((id == PALMAS_REG_SMPS6) || (id == PALMAS_REG_SMPS8))
880 ramp_delay_support = true; 1123 ramp_delay_support = true;
881 1124
882 if (ramp_delay_support) { 1125 if (ramp_delay_support) {
883 addr = palmas_regs_info[id].tstep_addr; 1126 addr = rinfo->tstep_addr;
884 ret = palmas_smps_read(pmic->palmas, addr, &reg); 1127 ret = palmas_smps_read(pmic->palmas, addr, &reg);
885 if (ret < 0) { 1128 if (ret < 0) {
886 dev_err(&pdev->dev, 1129 dev_err(pmic->dev,
887 "reading TSTEP reg failed: %d\n", ret); 1130 "reading TSTEP reg failed: %d\n", ret);
888 return ret; 1131 return ret;
889 } 1132 }
890 pmic->desc[id].ramp_delay = 1133 desc->ramp_delay = palmas_smps_ramp_delay[reg & 0x3];
891 palmas_smps_ramp_delay[reg & 0x3]; 1134 pmic->ramp_delay[id] = desc->ramp_delay;
892 pmic->ramp_delay[id] = pmic->desc[id].ramp_delay;
893 } 1135 }
894 1136
895 /* Initialise sleep/init values from platform data */ 1137 /* Initialise sleep/init values from platform data */
896 if (pdata && pdata->reg_init[id]) { 1138 if (pdata && pdata->reg_init[id]) {
897 reg_init = pdata->reg_init[id]; 1139 reg_init = pdata->reg_init[id];
898 ret = palmas_smps_init(palmas, id, reg_init); 1140 ret = palmas_smps_init(pmic->palmas, id, reg_init);
899 if (ret) 1141 if (ret)
900 return ret; 1142 return ret;
901 } else { 1143 } else {
@@ -903,31 +1145,28 @@ static int palmas_regulators_probe(struct platform_device *pdev)
903 } 1145 }
904 1146
905 /* Register the regulators */ 1147 /* Register the regulators */
906 pmic->desc[id].name = palmas_regs_info[id].name; 1148 desc->name = rinfo->name;
907 pmic->desc[id].id = id; 1149 desc->id = id;
908 1150
909 switch (id) { 1151 switch (id) {
910 case PALMAS_REG_SMPS10_OUT1: 1152 case PALMAS_REG_SMPS10_OUT1:
911 case PALMAS_REG_SMPS10_OUT2: 1153 case PALMAS_REG_SMPS10_OUT2:
912 pmic->desc[id].n_voltages = PALMAS_SMPS10_NUM_VOLTAGES; 1154 desc->n_voltages = PALMAS_SMPS10_NUM_VOLTAGES;
913 pmic->desc[id].ops = &palmas_ops_smps10; 1155 desc->ops = &palmas_ops_smps10;
914 pmic->desc[id].vsel_reg = 1156 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
915 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, 1157 PALMAS_SMPS10_CTRL);
916 PALMAS_SMPS10_CTRL); 1158 desc->vsel_mask = SMPS10_VSEL;
917 pmic->desc[id].vsel_mask = SMPS10_VSEL; 1159 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
918 pmic->desc[id].enable_reg = 1160 PALMAS_SMPS10_CTRL);
919 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
920 PALMAS_SMPS10_CTRL);
921 if (id == PALMAS_REG_SMPS10_OUT1) 1161 if (id == PALMAS_REG_SMPS10_OUT1)
922 pmic->desc[id].enable_mask = SMPS10_SWITCH_EN; 1162 desc->enable_mask = SMPS10_SWITCH_EN;
923 else 1163 else
924 pmic->desc[id].enable_mask = SMPS10_BOOST_EN; 1164 desc->enable_mask = SMPS10_BOOST_EN;
925 pmic->desc[id].bypass_reg = 1165 desc->bypass_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
926 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, 1166 PALMAS_SMPS10_CTRL);
927 PALMAS_SMPS10_CTRL); 1167 desc->bypass_mask = SMPS10_BYPASS_EN;
928 pmic->desc[id].bypass_mask = SMPS10_BYPASS_EN; 1168 desc->min_uV = 3750000;
929 pmic->desc[id].min_uV = 3750000; 1169 desc->uV_step = 1250000;
930 pmic->desc[id].uV_step = 1250000;
931 break; 1170 break;
932 default: 1171 default:
933 /* 1172 /*
@@ -936,8 +1175,8 @@ static int palmas_regulators_probe(struct platform_device *pdev)
936 * otherwise we error in probe with unsupportable 1175 * otherwise we error in probe with unsupportable
937 * ranges. Read the current smps mode for later use. 1176 * ranges. Read the current smps mode for later use.
938 */ 1177 */
939 addr = palmas_regs_info[id].vsel_addr; 1178 addr = rinfo->vsel_addr;
940 pmic->desc[id].n_linear_ranges = 3; 1179 desc->n_linear_ranges = 3;
941 1180
942 ret = palmas_smps_read(pmic->palmas, addr, &reg); 1181 ret = palmas_smps_read(pmic->palmas, addr, &reg);
943 if (ret) 1182 if (ret)
@@ -945,56 +1184,50 @@ static int palmas_regulators_probe(struct platform_device *pdev)
945 if (reg & PALMAS_SMPS12_VOLTAGE_RANGE) 1184 if (reg & PALMAS_SMPS12_VOLTAGE_RANGE)
946 pmic->range[id] = 1; 1185 pmic->range[id] = 1;
947 if (pmic->range[id]) 1186 if (pmic->range[id])
948 pmic->desc[id].linear_ranges = smps_high_ranges; 1187 desc->linear_ranges = smps_high_ranges;
949 else 1188 else
950 pmic->desc[id].linear_ranges = smps_low_ranges; 1189 desc->linear_ranges = smps_low_ranges;
951 1190
952 if (reg_init && reg_init->roof_floor) 1191 if (reg_init && reg_init->roof_floor)
953 pmic->desc[id].ops = 1192 desc->ops = &palmas_ops_ext_control_smps;
954 &palmas_ops_ext_control_smps;
955 else 1193 else
956 pmic->desc[id].ops = &palmas_ops_smps; 1194 desc->ops = &palmas_ops_smps;
957 pmic->desc[id].n_voltages = PALMAS_SMPS_NUM_VOLTAGES; 1195 desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
958 pmic->desc[id].vsel_reg = 1196 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
959 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, 1197 rinfo->vsel_addr);
960 palmas_regs_info[id].vsel_addr); 1198 desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
961 pmic->desc[id].vsel_mask =
962 PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
963 1199
964 /* Read the smps mode for later use. */ 1200 /* Read the smps mode for later use. */
965 addr = palmas_regs_info[id].ctrl_addr; 1201 addr = rinfo->ctrl_addr;
966 ret = palmas_smps_read(pmic->palmas, addr, &reg); 1202 ret = palmas_smps_read(pmic->palmas, addr, &reg);
967 if (ret) 1203 if (ret)
968 return ret; 1204 return ret;
969 pmic->current_reg_mode[id] = reg & 1205 pmic->current_reg_mode[id] = reg &
970 PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; 1206 PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
971 1207
972 pmic->desc[id].enable_reg = 1208 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
973 PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, 1209 rinfo->ctrl_addr);
974 palmas_regs_info[id].ctrl_addr); 1210 desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
975 pmic->desc[id].enable_mask =
976 PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
977 /* set_mode overrides this value */ 1211 /* set_mode overrides this value */
978 pmic->desc[id].enable_val = SMPS_CTRL_MODE_ON; 1212 desc->enable_val = SMPS_CTRL_MODE_ON;
979 } 1213 }
980 1214
981 pmic->desc[id].type = REGULATOR_VOLTAGE; 1215 desc->type = REGULATOR_VOLTAGE;
982 pmic->desc[id].owner = THIS_MODULE; 1216 desc->owner = THIS_MODULE;
983 1217
984 if (pdata) 1218 if (pdata)
985 config.init_data = pdata->reg_data[id]; 1219 config.init_data = pdata->reg_data[id];
986 else 1220 else
987 config.init_data = NULL; 1221 config.init_data = NULL;
988 1222
989 pmic->desc[id].supply_name = palmas_regs_info[id].sname; 1223 desc->supply_name = rinfo->sname;
990 config.of_node = palmas_matches[id].of_node; 1224 config.of_node = ddata->palmas_matches[id].of_node;
991 1225
992 rdev = devm_regulator_register(&pdev->dev, &pmic->desc[id], 1226 rdev = devm_regulator_register(pmic->dev, desc, &config);
993 &config);
994 if (IS_ERR(rdev)) { 1227 if (IS_ERR(rdev)) {
995 dev_err(&pdev->dev, 1228 dev_err(pmic->dev,
996 "failed to register %s regulator\n", 1229 "failed to register %s regulator\n",
997 pdev->name); 1230 pdev_name);
998 return PTR_ERR(rdev); 1231 return PTR_ERR(rdev);
999 } 1232 }
1000 1233
@@ -1002,123 +1235,378 @@ static int palmas_regulators_probe(struct platform_device *pdev)
1002 pmic->rdev[id] = rdev; 1235 pmic->rdev[id] = rdev;
1003 } 1236 }
1004 1237
1005 /* Start this loop from the id left from previous loop */ 1238 return 0;
1006 for (; id < PALMAS_NUM_REGS; id++) { 1239}
1007 if (pdata && pdata->reg_init[id]) 1240
1241static int tps65917_smps_registration(struct palmas_pmic *pmic,
1242 struct palmas_pmic_driver_data *ddata,
1243 struct palmas_pmic_platform_data *pdata,
1244 const char *pdev_name,
1245 struct regulator_config config)
1246{
1247 int id, ret;
1248 unsigned int addr, reg;
1249 struct regulator_dev *rdev;
1250 struct palmas_reg_init *reg_init;
1251 struct palmas_regs_info *rinfo;
1252 struct regulator_desc *desc;
1253
1254 for (id = ddata->smps_start; id <= ddata->smps_end; id++) {
1255 /*
1256 * Miss out regulators which are not available due
1257 * to slaving configurations.
1258 */
1259 desc = &pmic->desc[id];
1260 desc->n_linear_ranges = 3;
1261 if ((id == TPS65917_REG_SMPS2) && pmic->smps12)
1262 continue;
1263
1264 /* Initialise sleep/init values from platform data */
1265 if (pdata && pdata->reg_init[id]) {
1008 reg_init = pdata->reg_init[id]; 1266 reg_init = pdata->reg_init[id];
1009 else 1267 ret = palmas_smps_init(pmic->palmas, id, reg_init);
1268 if (ret)
1269 return ret;
1270 } else {
1010 reg_init = NULL; 1271 reg_init = NULL;
1272 }
1273 rinfo = &ddata->palmas_regs_info[id];
1011 1274
1012 /* Miss out regulators which are not available due 1275 /* Register the regulators */
1013 * to alternate functions. 1276 desc->name = rinfo->name;
1277 desc->id = id;
1278
1279 /*
1280 * Read and store the RANGE bit for later use
1281 * This must be done before regulator is probed,
1282 * otherwise we error in probe with unsupportable
1283 * ranges. Read the current smps mode for later use.
1014 */ 1284 */
1285 addr = rinfo->vsel_addr;
1015 1286
1016 /* Register the regulators */ 1287 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1017 pmic->desc[id].name = palmas_regs_info[id].name; 1288 if (ret)
1018 pmic->desc[id].id = id; 1289 return ret;
1019 pmic->desc[id].type = REGULATOR_VOLTAGE; 1290 if (reg & TPS65917_SMPS1_VOLTAGE_RANGE)
1020 pmic->desc[id].owner = THIS_MODULE; 1291 pmic->range[id] = 1;
1021 1292
1022 if (id < PALMAS_REG_REGEN1) { 1293 if (pmic->range[id])
1023 pmic->desc[id].n_voltages = PALMAS_LDO_NUM_VOLTAGES; 1294 desc->linear_ranges = smps_high_ranges;
1024 if (reg_init && reg_init->roof_floor) 1295 else
1025 pmic->desc[id].ops = 1296 desc->linear_ranges = smps_low_ranges;
1026 &palmas_ops_ext_control_ldo;
1027 else
1028 pmic->desc[id].ops = &palmas_ops_ldo;
1029 pmic->desc[id].min_uV = 900000;
1030 pmic->desc[id].uV_step = 50000;
1031 pmic->desc[id].linear_min_sel = 1;
1032 pmic->desc[id].enable_time = 500;
1033 pmic->desc[id].vsel_reg =
1034 PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
1035 palmas_regs_info[id].vsel_addr);
1036 pmic->desc[id].vsel_mask =
1037 PALMAS_LDO1_VOLTAGE_VSEL_MASK;
1038 pmic->desc[id].enable_reg =
1039 PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
1040 palmas_regs_info[id].ctrl_addr);
1041 pmic->desc[id].enable_mask =
1042 PALMAS_LDO1_CTRL_MODE_ACTIVE;
1043 1297
1044 /* Check if LDO8 is in tracking mode or not */ 1298 if (reg_init && reg_init->roof_floor)
1045 if (pdata && (id == PALMAS_REG_LDO8) && 1299 desc->ops = &tps65917_ops_ext_control_smps;
1046 pdata->enable_ldo8_tracking) { 1300 else
1047 palmas_enable_ldo8_track(palmas); 1301 desc->ops = &tps65917_ops_smps;
1048 pmic->desc[id].min_uV = 450000; 1302 desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
1049 pmic->desc[id].uV_step = 25000; 1303 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1050 } 1304 rinfo->vsel_addr);
1305 desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
1306 desc->ramp_delay = 2500;
1307
1308 /* Read the smps mode for later use. */
1309 addr = rinfo->ctrl_addr;
1310 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1311 if (ret)
1312 return ret;
1313 pmic->current_reg_mode[id] = reg &
1314 PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
1315 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1316 rinfo->ctrl_addr);
1317 desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
1318 /* set_mode overrides this value */
1319 desc->enable_val = SMPS_CTRL_MODE_ON;
1051 1320
1052 /* LOD6 in vibrator mode will have enable time 2000us */ 1321 desc->type = REGULATOR_VOLTAGE;
1053 if (pdata && pdata->ldo6_vibrator && 1322 desc->owner = THIS_MODULE;
1054 (id == PALMAS_REG_LDO6))
1055 pmic->desc[id].enable_time = 2000;
1056 } else {
1057 pmic->desc[id].n_voltages = 1;
1058 if (reg_init && reg_init->roof_floor)
1059 pmic->desc[id].ops =
1060 &palmas_ops_ext_control_extreg;
1061 else
1062 pmic->desc[id].ops = &palmas_ops_extreg;
1063 pmic->desc[id].enable_reg =
1064 PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
1065 palmas_regs_info[id].ctrl_addr);
1066 pmic->desc[id].enable_mask =
1067 PALMAS_REGEN1_CTRL_MODE_ACTIVE;
1068 }
1069 1323
1070 if (pdata) 1324 if (pdata)
1071 config.init_data = pdata->reg_data[id]; 1325 config.init_data = pdata->reg_data[id];
1072 else 1326 else
1073 config.init_data = NULL; 1327 config.init_data = NULL;
1074 1328
1075 pmic->desc[id].supply_name = palmas_regs_info[id].sname; 1329 desc->supply_name = rinfo->sname;
1076 config.of_node = palmas_matches[id].of_node; 1330 config.of_node = ddata->palmas_matches[id].of_node;
1077 1331
1078 rdev = devm_regulator_register(&pdev->dev, &pmic->desc[id], 1332 rdev = devm_regulator_register(pmic->dev, desc, &config);
1079 &config);
1080 if (IS_ERR(rdev)) { 1333 if (IS_ERR(rdev)) {
1081 dev_err(&pdev->dev, 1334 dev_err(pmic->dev,
1082 "failed to register %s regulator\n", 1335 "failed to register %s regulator\n",
1083 pdev->name); 1336 pdev_name);
1084 return PTR_ERR(rdev); 1337 return PTR_ERR(rdev);
1085 } 1338 }
1086 1339
1087 /* Save regulator for cleanup */ 1340 /* Save regulator for cleanup */
1088 pmic->rdev[id] = rdev; 1341 pmic->rdev[id] = rdev;
1342 }
1089 1343
1090 /* Initialise sleep/init values from platform data */ 1344 return 0;
1091 if (pdata) { 1345}
1092 reg_init = pdata->reg_init[id]; 1346
1093 if (reg_init) { 1347static struct of_regulator_match palmas_matches[] = {
1094 if (id < PALMAS_REG_REGEN1) 1348 { .name = "smps12", },
1095 ret = palmas_ldo_init(palmas, 1349 { .name = "smps123", },
1096 id, reg_init); 1350 { .name = "smps3", },
1097 else 1351 { .name = "smps45", },
1098 ret = palmas_extreg_init(palmas, 1352 { .name = "smps457", },
1099 id, reg_init); 1353 { .name = "smps6", },
1100 if (ret) 1354 { .name = "smps7", },
1101 return ret; 1355 { .name = "smps8", },
1356 { .name = "smps9", },
1357 { .name = "smps10_out2", },
1358 { .name = "smps10_out1", },
1359 { .name = "ldo1", },
1360 { .name = "ldo2", },
1361 { .name = "ldo3", },
1362 { .name = "ldo4", },
1363 { .name = "ldo5", },
1364 { .name = "ldo6", },
1365 { .name = "ldo7", },
1366 { .name = "ldo8", },
1367 { .name = "ldo9", },
1368 { .name = "ldoln", },
1369 { .name = "ldousb", },
1370 { .name = "regen1", },
1371 { .name = "regen2", },
1372 { .name = "regen3", },
1373 { .name = "sysen1", },
1374 { .name = "sysen2", },
1375};
1376
1377static struct of_regulator_match tps65917_matches[] = {
1378 { .name = "smps1", },
1379 { .name = "smps2", },
1380 { .name = "smps3", },
1381 { .name = "smps4", },
1382 { .name = "smps5", },
1383 { .name = "ldo1", },
1384 { .name = "ldo2", },
1385 { .name = "ldo3", },
1386 { .name = "ldo4", },
1387 { .name = "ldo5", },
1388 { .name = "regen1", },
1389 { .name = "regen2", },
1390 { .name = "regen3", },
1391 { .name = "sysen1", },
1392 { .name = "sysen2", },
1393};
1394
1395static struct palmas_pmic_driver_data palmas_ddata = {
1396 .smps_start = PALMAS_REG_SMPS12,
1397 .smps_end = PALMAS_REG_SMPS10_OUT1,
1398 .ldo_begin = PALMAS_REG_LDO1,
1399 .ldo_end = PALMAS_REG_LDOUSB,
1400 .max_reg = PALMAS_NUM_REGS,
1401 .palmas_regs_info = palmas_generic_regs_info,
1402 .palmas_matches = palmas_matches,
1403 .sleep_req_info = palma_sleep_req_info,
1404 .smps_register = palmas_smps_registration,
1405 .ldo_register = palmas_ldo_registration,
1406};
1407
1408static struct palmas_pmic_driver_data tps65917_ddata = {
1409 .smps_start = TPS65917_REG_SMPS1,
1410 .smps_end = TPS65917_REG_SMPS5,
1411 .ldo_begin = TPS65917_REG_LDO1,
1412 .ldo_end = TPS65917_REG_LDO5,
1413 .max_reg = TPS65917_NUM_REGS,
1414 .palmas_regs_info = tps65917_regs_info,
1415 .palmas_matches = tps65917_matches,
1416 .sleep_req_info = tps65917_sleep_req_info,
1417 .smps_register = tps65917_smps_registration,
1418 .ldo_register = tps65917_ldo_registration,
1419};
1420
1421static void palmas_dt_to_pdata(struct device *dev,
1422 struct device_node *node,
1423 struct palmas_pmic_platform_data *pdata,
1424 struct palmas_pmic_driver_data *ddata)
1425{
1426 struct device_node *regulators;
1427 u32 prop;
1428 int idx, ret;
1429
1430 node = of_node_get(node);
1431 regulators = of_get_child_by_name(node, "regulators");
1432 if (!regulators) {
1433 dev_info(dev, "regulator node not found\n");
1434 return;
1435 }
1436
1437 ret = of_regulator_match(dev, regulators, ddata->palmas_matches,
1438 ddata->max_reg);
1439 of_node_put(regulators);
1440 if (ret < 0) {
1441 dev_err(dev, "Error parsing regulator init data: %d\n", ret);
1442 return;
1443 }
1444
1445 for (idx = 0; idx < ddata->max_reg; idx++) {
1446 if (!ddata->palmas_matches[idx].init_data ||
1447 !ddata->palmas_matches[idx].of_node)
1448 continue;
1449
1450 pdata->reg_data[idx] = ddata->palmas_matches[idx].init_data;
1451
1452 pdata->reg_init[idx] = devm_kzalloc(dev,
1453 sizeof(struct palmas_reg_init), GFP_KERNEL);
1454
1455 pdata->reg_init[idx]->warm_reset =
1456 of_property_read_bool(ddata->palmas_matches[idx].of_node,
1457 "ti,warm-reset");
1458
1459 ret = of_property_read_u32(ddata->palmas_matches[idx].of_node,
1460 "ti,roof-floor", &prop);
1461 /* EINVAL: Property not found */
1462 if (ret != -EINVAL) {
1463 int econtrol;
1464
1465 /* use default value, when no value is specified */
1466 econtrol = PALMAS_EXT_CONTROL_NSLEEP;
1467 if (!ret) {
1468 switch (prop) {
1469 case 1:
1470 econtrol = PALMAS_EXT_CONTROL_ENABLE1;
1471 break;
1472 case 2:
1473 econtrol = PALMAS_EXT_CONTROL_ENABLE2;
1474 break;
1475 case 3:
1476 econtrol = PALMAS_EXT_CONTROL_NSLEEP;
1477 break;
1478 default:
1479 WARN_ON(1);
1480 dev_warn(dev,
1481 "%s: Invalid roof-floor option: %u\n",
1482 palmas_matches[idx].name, prop);
1483 break;
1484 }
1102 } 1485 }
1486 pdata->reg_init[idx]->roof_floor = econtrol;
1103 } 1487 }
1104 }
1105 1488
1489 ret = of_property_read_u32(ddata->palmas_matches[idx].of_node,
1490 "ti,mode-sleep", &prop);
1491 if (!ret)
1492 pdata->reg_init[idx]->mode_sleep = prop;
1493
1494 ret = of_property_read_bool(ddata->palmas_matches[idx].of_node,
1495 "ti,smps-range");
1496 if (ret)
1497 pdata->reg_init[idx]->vsel =
1498 PALMAS_SMPS12_VOLTAGE_RANGE;
1106 1499
1107 return 0; 1500 if (idx == PALMAS_REG_LDO8)
1501 pdata->enable_ldo8_tracking = of_property_read_bool(
1502 ddata->palmas_matches[idx].of_node,
1503 "ti,enable-ldo8-tracking");
1504 }
1505
1506 pdata->ldo6_vibrator = of_property_read_bool(node, "ti,ldo6-vibrator");
1108} 1507}
1109 1508
1110static const struct of_device_id of_palmas_match_tbl[] = { 1509static struct of_device_id of_palmas_match_tbl[] = {
1111 { .compatible = "ti,palmas-pmic", }, 1510 {
1112 { .compatible = "ti,twl6035-pmic", }, 1511 .compatible = "ti,palmas-pmic",
1113 { .compatible = "ti,twl6036-pmic", }, 1512 .data = &palmas_ddata,
1114 { .compatible = "ti,twl6037-pmic", }, 1513 },
1115 { .compatible = "ti,tps65913-pmic", }, 1514 {
1116 { .compatible = "ti,tps65914-pmic", }, 1515 .compatible = "ti,twl6035-pmic",
1117 { .compatible = "ti,tps80036-pmic", }, 1516 .data = &palmas_ddata,
1118 { .compatible = "ti,tps659038-pmic", }, 1517 },
1518 {
1519 .compatible = "ti,twl6036-pmic",
1520 .data = &palmas_ddata,
1521 },
1522 {
1523 .compatible = "ti,twl6037-pmic",
1524 .data = &palmas_ddata,
1525 },
1526 {
1527 .compatible = "ti,tps65913-pmic",
1528 .data = &palmas_ddata,
1529 },
1530 {
1531 .compatible = "ti,tps65914-pmic",
1532 .data = &palmas_ddata,
1533 },
1534 {
1535 .compatible = "ti,tps80036-pmic",
1536 .data = &palmas_ddata,
1537 },
1538 {
1539 .compatible = "ti,tps659038-pmic",
1540 .data = &palmas_ddata,
1541 },
1542 {
1543 .compatible = "ti,tps65917-pmic",
1544 .data = &tps65917_ddata,
1545 },
1119 { /* end */ } 1546 { /* end */ }
1120}; 1547};
1121 1548
1549static int palmas_regulators_probe(struct platform_device *pdev)
1550{
1551 struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
1552 struct palmas_pmic_platform_data *pdata = dev_get_platdata(&pdev->dev);
1553 struct device_node *node = pdev->dev.of_node;
1554 struct palmas_pmic_driver_data *driver_data;
1555 struct regulator_config config = { };
1556 struct palmas_pmic *pmic;
1557 const char *pdev_name;
1558 const struct of_device_id *match;
1559 int ret = 0;
1560 unsigned int reg;
1561
1562 match = of_match_device(of_match_ptr(of_palmas_match_tbl), &pdev->dev);
1563
1564 if (!match)
1565 return -ENODATA;
1566
1567 driver_data = (struct palmas_pmic_driver_data *)match->data;
1568 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1569 if (!pdata)
1570 return -ENOMEM;
1571
1572 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
1573 if (!pmic)
1574 return -ENOMEM;
1575
1576 pmic->dev = &pdev->dev;
1577 pmic->palmas = palmas;
1578 palmas->pmic = pmic;
1579 platform_set_drvdata(pdev, pmic);
1580 pmic->palmas->pmic_ddata = driver_data;
1581
1582 palmas_dt_to_pdata(&pdev->dev, node, pdata, driver_data);
1583
1584 ret = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, &reg);
1585 if (ret)
1586 return ret;
1587
1588 if (reg & PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN)
1589 pmic->smps123 = 1;
1590
1591 if (reg & PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN)
1592 pmic->smps457 = 1;
1593
1594 config.regmap = palmas->regmap[REGULATOR_SLAVE];
1595 config.dev = &pdev->dev;
1596 config.driver_data = pmic;
1597 pdev_name = pdev->name;
1598
1599 ret = driver_data->smps_register(pmic, driver_data, pdata, pdev_name,
1600 config);
1601 if (ret)
1602 return ret;
1603
1604 ret = driver_data->ldo_register(pmic, driver_data, pdata, pdev_name,
1605 config);
1606
1607 return ret;
1608}
1609
1122static struct platform_driver palmas_driver = { 1610static struct platform_driver palmas_driver = {
1123 .driver = { 1611 .driver = {
1124 .name = "palmas-pmic", 1612 .name = "palmas-pmic",
diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h
index 3420e09e2e20..fb0390a1a498 100644
--- a/include/linux/mfd/palmas.h
+++ b/include/linux/mfd/palmas.h
@@ -30,6 +30,8 @@
30#define PALMAS_CHIP_ID 0xC035 30#define PALMAS_CHIP_ID 0xC035
31#define PALMAS_CHIP_CHARGER_ID 0xC036 31#define PALMAS_CHIP_CHARGER_ID 0xC036
32 32
33#define TPS65917_RESERVED -1
34
33#define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \ 35#define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \
34 ((a) == PALMAS_CHIP_ID)) 36 ((a) == PALMAS_CHIP_ID))
35#define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID) 37#define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
@@ -51,6 +53,8 @@ struct palmas_pmic;
51struct palmas_gpadc; 53struct palmas_gpadc;
52struct palmas_resource; 54struct palmas_resource;
53struct palmas_usb; 55struct palmas_usb;
56struct palmas_pmic_driver_data;
57struct palmas_pmic_platform_data;
54 58
55enum palmas_usb_state { 59enum palmas_usb_state {
56 PALMAS_USB_STATE_DISCONNECT, 60 PALMAS_USB_STATE_DISCONNECT,
@@ -74,6 +78,8 @@ struct palmas {
74 struct mutex irq_lock; 78 struct mutex irq_lock;
75 struct regmap_irq_chip_data *irq_data; 79 struct regmap_irq_chip_data *irq_data;
76 80
81 struct palmas_pmic_driver_data *pmic_ddata;
82
77 /* Child Devices */ 83 /* Child Devices */
78 struct palmas_pmic *pmic; 84 struct palmas_pmic *pmic;
79 struct palmas_gpadc *gpadc; 85 struct palmas_gpadc *gpadc;
@@ -86,6 +92,46 @@ struct palmas {
86 u8 pwm_muxed; 92 u8 pwm_muxed;
87}; 93};
88 94
95#define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 | \
96 PALMAS_EXT_CONTROL_ENABLE2 | \
97 PALMAS_EXT_CONTROL_NSLEEP)
98
99struct palmas_sleep_requestor_info {
100 int id;
101 int reg_offset;
102 int bit_pos;
103};
104
105struct palmas_regs_info {
106 char *name;
107 char *sname;
108 u8 vsel_addr;
109 u8 ctrl_addr;
110 u8 tstep_addr;
111 int sleep_id;
112};
113
114struct palmas_pmic_driver_data {
115 int smps_start;
116 int smps_end;
117 int ldo_begin;
118 int ldo_end;
119 int max_reg;
120 struct palmas_regs_info *palmas_regs_info;
121 struct of_regulator_match *palmas_matches;
122 struct palmas_sleep_requestor_info *sleep_req_info;
123 int (*smps_register)(struct palmas_pmic *pmic,
124 struct palmas_pmic_driver_data *ddata,
125 struct palmas_pmic_platform_data *pdata,
126 const char *pdev_name,
127 struct regulator_config config);
128 int (*ldo_register)(struct palmas_pmic *pmic,
129 struct palmas_pmic_driver_data *ddata,
130 struct palmas_pmic_platform_data *pdata,
131 const char *pdev_name,
132 struct regulator_config config);
133};
134
89struct palmas_gpadc_platform_data { 135struct palmas_gpadc_platform_data {
90 /* Channel 3 current source is only enabled during conversion */ 136 /* Channel 3 current source is only enabled during conversion */
91 int ch3_current; 137 int ch3_current;
@@ -184,6 +230,27 @@ enum palmas_regulators {
184 PALMAS_NUM_REGS, 230 PALMAS_NUM_REGS,
185}; 231};
186 232
233enum tps65917_regulators {
234 /* SMPS regulators */
235 TPS65917_REG_SMPS1,
236 TPS65917_REG_SMPS2,
237 TPS65917_REG_SMPS3,
238 TPS65917_REG_SMPS4,
239 TPS65917_REG_SMPS5,
240 /* LDO regulators */
241 TPS65917_REG_LDO1,
242 TPS65917_REG_LDO2,
243 TPS65917_REG_LDO3,
244 TPS65917_REG_LDO4,
245 TPS65917_REG_LDO5,
246 TPS65917_REG_REGEN1,
247 TPS65917_REG_REGEN2,
248 TPS65917_REG_REGEN3,
249
250 /* Total number of regulators */
251 TPS65917_NUM_REGS,
252};
253
187/* External controll signal name */ 254/* External controll signal name */
188enum { 255enum {
189 PALMAS_EXT_CONTROL_ENABLE1 = 0x1, 256 PALMAS_EXT_CONTROL_ENABLE1 = 0x1,
@@ -228,6 +295,24 @@ enum palmas_external_requestor_id {
228 PALMAS_EXTERNAL_REQSTR_ID_MAX, 295 PALMAS_EXTERNAL_REQSTR_ID_MAX,
229}; 296};
230 297
298enum tps65917_external_requestor_id {
299 TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
300 TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
301 TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
302 TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
303 TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
304 TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
305 TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
306 TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
307 TPS65917_EXTERNAL_REQSTR_ID_LDO1,
308 TPS65917_EXTERNAL_REQSTR_ID_LDO2,
309 TPS65917_EXTERNAL_REQSTR_ID_LDO3,
310 TPS65917_EXTERNAL_REQSTR_ID_LDO4,
311 TPS65917_EXTERNAL_REQSTR_ID_LDO5,
312 /* Last entry */
313 TPS65917_EXTERNAL_REQSTR_ID_MAX,
314};
315
231struct palmas_pmic_platform_data { 316struct palmas_pmic_platform_data {
232 /* An array of pointers to regulator init data indexed by regulator 317 /* An array of pointers to regulator init data indexed by regulator
233 * ID 318 * ID
@@ -349,6 +434,48 @@ struct palmas_gpadc_result {
349 434
350#define PALMAS_MAX_CHANNELS 16 435#define PALMAS_MAX_CHANNELS 16
351 436
437/* Define the tps65917 IRQ numbers */
438enum tps65917_irqs {
439 /* INT1 registers */
440 TPS65917_RESERVED1,
441 TPS65917_PWRON_IRQ,
442 TPS65917_LONG_PRESS_KEY_IRQ,
443 TPS65917_RESERVED2,
444 TPS65917_PWRDOWN_IRQ,
445 TPS65917_HOTDIE_IRQ,
446 TPS65917_VSYS_MON_IRQ,
447 TPS65917_RESERVED3,
448 /* INT2 registers */
449 TPS65917_RESERVED4,
450 TPS65917_OTP_ERROR_IRQ,
451 TPS65917_WDT_IRQ,
452 TPS65917_RESERVED5,
453 TPS65917_RESET_IN_IRQ,
454 TPS65917_FSD_IRQ,
455 TPS65917_SHORT_IRQ,
456 TPS65917_RESERVED6,
457 /* INT3 registers */
458 TPS65917_GPADC_AUTO_0_IRQ,
459 TPS65917_GPADC_AUTO_1_IRQ,
460 TPS65917_GPADC_EOC_SW_IRQ,
461 TPS65917_RESREVED6,
462 TPS65917_RESERVED7,
463 TPS65917_RESERVED8,
464 TPS65917_RESERVED9,
465 TPS65917_VBUS_IRQ,
466 /* INT4 registers */
467 TPS65917_GPIO_0_IRQ,
468 TPS65917_GPIO_1_IRQ,
469 TPS65917_GPIO_2_IRQ,
470 TPS65917_GPIO_3_IRQ,
471 TPS65917_GPIO_4_IRQ,
472 TPS65917_GPIO_5_IRQ,
473 TPS65917_GPIO_6_IRQ,
474 TPS65917_RESERVED10,
475 /* Total Number IRQs */
476 TPS65917_NUM_IRQ,
477};
478
352/* Define the palmas IRQ numbers */ 479/* Define the palmas IRQ numbers */
353enum palmas_irqs { 480enum palmas_irqs {
354 /* INT1 registers */ 481 /* INT1 registers */
@@ -400,6 +527,7 @@ struct palmas_pmic {
400 527
401 int smps123; 528 int smps123;
402 int smps457; 529 int smps457;
530 int smps12;
403 531
404 int range[PALMAS_REG_SMPS10_OUT1]; 532 int range[PALMAS_REG_SMPS10_OUT1];
405 unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1]; 533 unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1];
@@ -2871,6 +2999,715 @@ enum usb_irq_events {
2871#define PALMAS_GPADC_TRIM15 0x0E 2999#define PALMAS_GPADC_TRIM15 0x0E
2872#define PALMAS_GPADC_TRIM16 0x0F 3000#define PALMAS_GPADC_TRIM16 0x0F
2873 3001
3002/* TPS65917 Interrupt registers */
3003
3004/* Registers for function INTERRUPT */
3005#define TPS65917_INT1_STATUS 0x00
3006#define TPS65917_INT1_MASK 0x01
3007#define TPS65917_INT1_LINE_STATE 0x02
3008#define TPS65917_INT2_STATUS 0x05
3009#define TPS65917_INT2_MASK 0x06
3010#define TPS65917_INT2_LINE_STATE 0x07
3011#define TPS65917_INT3_STATUS 0x0A
3012#define TPS65917_INT3_MASK 0x0B
3013#define TPS65917_INT3_LINE_STATE 0x0C
3014#define TPS65917_INT4_STATUS 0x0F
3015#define TPS65917_INT4_MASK 0x10
3016#define TPS65917_INT4_LINE_STATE 0x11
3017#define TPS65917_INT4_EDGE_DETECT1 0x12
3018#define TPS65917_INT4_EDGE_DETECT2 0x13
3019#define TPS65917_INT_CTRL 0x14
3020
3021/* Bit definitions for INT1_STATUS */
3022#define TPS65917_INT1_STATUS_VSYS_MON 0x40
3023#define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06
3024#define TPS65917_INT1_STATUS_HOTDIE 0x20
3025#define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05
3026#define TPS65917_INT1_STATUS_PWRDOWN 0x10
3027#define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04
3028#define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04
3029#define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
3030#define TPS65917_INT1_STATUS_PWRON 0x02
3031#define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01
3032
3033/* Bit definitions for INT1_MASK */
3034#define TPS65917_INT1_MASK_VSYS_MON 0x40
3035#define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06
3036#define TPS65917_INT1_MASK_HOTDIE 0x20
3037#define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05
3038#define TPS65917_INT1_MASK_PWRDOWN 0x10
3039#define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04
3040#define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04
3041#define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
3042#define TPS65917_INT1_MASK_PWRON 0x02
3043#define TPS65917_INT1_MASK_PWRON_SHIFT 0x01
3044
3045/* Bit definitions for INT1_LINE_STATE */
3046#define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40
3047#define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
3048#define TPS65917_INT1_LINE_STATE_HOTDIE 0x20
3049#define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
3050#define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10
3051#define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
3052#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
3053#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
3054#define TPS65917_INT1_LINE_STATE_PWRON 0x02
3055#define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01
3056
3057/* Bit definitions for INT2_STATUS */
3058#define TPS65917_INT2_STATUS_SHORT 0x40
3059#define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06
3060#define TPS65917_INT2_STATUS_FSD 0x20
3061#define TPS65917_INT2_STATUS_FSD_SHIFT 0x05
3062#define TPS65917_INT2_STATUS_RESET_IN 0x10
3063#define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04
3064#define TPS65917_INT2_STATUS_WDT 0x04
3065#define TPS65917_INT2_STATUS_WDT_SHIFT 0x02
3066#define TPS65917_INT2_STATUS_OTP_ERROR 0x02
3067#define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01
3068
3069/* Bit definitions for INT2_MASK */
3070#define TPS65917_INT2_MASK_SHORT 0x40
3071#define TPS65917_INT2_MASK_SHORT_SHIFT 0x06
3072#define TPS65917_INT2_MASK_FSD 0x20
3073#define TPS65917_INT2_MASK_FSD_SHIFT 0x05
3074#define TPS65917_INT2_MASK_RESET_IN 0x10
3075#define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04
3076#define TPS65917_INT2_MASK_WDT 0x04
3077#define TPS65917_INT2_MASK_WDT_SHIFT 0x02
3078#define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02
3079#define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01
3080
3081/* Bit definitions for INT2_LINE_STATE */
3082#define TPS65917_INT2_LINE_STATE_SHORT 0x40
3083#define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06
3084#define TPS65917_INT2_LINE_STATE_FSD 0x20
3085#define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05
3086#define TPS65917_INT2_LINE_STATE_RESET_IN 0x10
3087#define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
3088#define TPS65917_INT2_LINE_STATE_WDT 0x04
3089#define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02
3090#define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02
3091#define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01
3092
3093/* Bit definitions for INT3_STATUS */
3094#define TPS65917_INT3_STATUS_VBUS 0x80
3095#define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07
3096#define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04
3097#define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
3098#define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02
3099#define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
3100#define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01
3101#define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
3102
3103/* Bit definitions for INT3_MASK */
3104#define TPS65917_INT3_MASK_VBUS 0x80
3105#define TPS65917_INT3_MASK_VBUS_SHIFT 0x07
3106#define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04
3107#define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
3108#define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02
3109#define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
3110#define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01
3111#define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
3112
3113/* Bit definitions for INT3_LINE_STATE */
3114#define TPS65917_INT3_LINE_STATE_VBUS 0x80
3115#define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07
3116#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04
3117#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
3118#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02
3119#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
3120#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01
3121#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
3122
3123/* Bit definitions for INT4_STATUS */
3124#define TPS65917_INT4_STATUS_GPIO_6 0x40
3125#define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06
3126#define TPS65917_INT4_STATUS_GPIO_5 0x20
3127#define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05
3128#define TPS65917_INT4_STATUS_GPIO_4 0x10
3129#define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04
3130#define TPS65917_INT4_STATUS_GPIO_3 0x08
3131#define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03
3132#define TPS65917_INT4_STATUS_GPIO_2 0x04
3133#define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02
3134#define TPS65917_INT4_STATUS_GPIO_1 0x02
3135#define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01
3136#define TPS65917_INT4_STATUS_GPIO_0 0x01
3137#define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00
3138
3139/* Bit definitions for INT4_MASK */
3140#define TPS65917_INT4_MASK_GPIO_6 0x40
3141#define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06
3142#define TPS65917_INT4_MASK_GPIO_5 0x20
3143#define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05
3144#define TPS65917_INT4_MASK_GPIO_4 0x10
3145#define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04
3146#define TPS65917_INT4_MASK_GPIO_3 0x08
3147#define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03
3148#define TPS65917_INT4_MASK_GPIO_2 0x04
3149#define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02
3150#define TPS65917_INT4_MASK_GPIO_1 0x02
3151#define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01
3152#define TPS65917_INT4_MASK_GPIO_0 0x01
3153#define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00
3154
3155/* Bit definitions for INT4_LINE_STATE */
3156#define TPS65917_INT4_LINE_STATE_GPIO_6 0x40
3157#define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
3158#define TPS65917_INT4_LINE_STATE_GPIO_5 0x20
3159#define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
3160#define TPS65917_INT4_LINE_STATE_GPIO_4 0x10
3161#define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
3162#define TPS65917_INT4_LINE_STATE_GPIO_3 0x08
3163#define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
3164#define TPS65917_INT4_LINE_STATE_GPIO_2 0x04
3165#define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
3166#define TPS65917_INT4_LINE_STATE_GPIO_1 0x02
3167#define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
3168#define TPS65917_INT4_LINE_STATE_GPIO_0 0x01
3169#define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
3170
3171/* Bit definitions for INT4_EDGE_DETECT1 */
3172#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
3173#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
3174#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
3175#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
3176#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
3177#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
3178#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
3179#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
3180#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
3181#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
3182#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
3183#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
3184#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
3185#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
3186#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
3187#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
3188
3189/* Bit definitions for INT4_EDGE_DETECT2 */
3190#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
3191#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
3192#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
3193#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
3194#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
3195#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
3196#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
3197#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
3198#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
3199#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
3200#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
3201#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
3202
3203/* Bit definitions for INT_CTRL */
3204#define TPS65917_INT_CTRL_INT_PENDING 0x04
3205#define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02
3206#define TPS65917_INT_CTRL_INT_CLEAR 0x01
3207#define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00
3208
3209/* TPS65917 SMPS Registers */
3210
3211/* Registers for function SMPS */
3212#define TPS65917_SMPS1_CTRL 0x00
3213#define TPS65917_SMPS1_FORCE 0x02
3214#define TPS65917_SMPS1_VOLTAGE 0x03
3215#define TPS65917_SMPS2_CTRL 0x04
3216#define TPS65917_SMPS2_FORCE 0x06
3217#define TPS65917_SMPS2_VOLTAGE 0x07
3218#define TPS65917_SMPS3_CTRL 0x0C
3219#define TPS65917_SMPS3_FORCE 0x0E
3220#define TPS65917_SMPS3_VOLTAGE 0x0F
3221#define TPS65917_SMPS4_CTRL 0x10
3222#define TPS65917_SMPS4_VOLTAGE 0x13
3223#define TPS65917_SMPS5_CTRL 0x18
3224#define TPS65917_SMPS5_VOLTAGE 0x1B
3225#define TPS65917_SMPS_CTRL 0x24
3226#define TPS65917_SMPS_PD_CTRL 0x25
3227#define TPS65917_SMPS_THERMAL_EN 0x27
3228#define TPS65917_SMPS_THERMAL_STATUS 0x28
3229#define TPS65917_SMPS_SHORT_STATUS 0x29
3230#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
3231#define TPS65917_SMPS_POWERGOOD_MASK1 0x2B
3232#define TPS65917_SMPS_POWERGOOD_MASK2 0x2C
3233
3234/* Bit definitions for SMPS1_CTRL */
3235#define TPS65917_SMPS1_CTRL_WR_S 0x80
3236#define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07
3237#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40
3238#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3239#define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30
3240#define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04
3241#define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C
3242#define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02
3243#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03
3244#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00
3245
3246/* Bit definitions for SMPS1_FORCE */
3247#define TPS65917_SMPS1_FORCE_CMD 0x80
3248#define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07
3249#define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F
3250#define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00
3251
3252/* Bit definitions for SMPS1_VOLTAGE */
3253#define TPS65917_SMPS1_VOLTAGE_RANGE 0x80
3254#define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07
3255#define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F
3256#define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00
3257
3258/* Bit definitions for SMPS2_CTRL */
3259#define TPS65917_SMPS2_CTRL_WR_S 0x80
3260#define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07
3261#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40
3262#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3263#define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30
3264#define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04
3265#define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C
3266#define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02
3267#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03
3268#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00
3269
3270/* Bit definitions for SMPS2_FORCE */
3271#define TPS65917_SMPS2_FORCE_CMD 0x80
3272#define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07
3273#define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F
3274#define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00
3275
3276/* Bit definitions for SMPS2_VOLTAGE */
3277#define TPS65917_SMPS2_VOLTAGE_RANGE 0x80
3278#define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07
3279#define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F
3280#define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00
3281
3282/* Bit definitions for SMPS3_CTRL */
3283#define TPS65917_SMPS3_CTRL_WR_S 0x80
3284#define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07
3285#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40
3286#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3287#define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30
3288#define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04
3289#define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C
3290#define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
3291#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
3292#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
3293
3294/* Bit definitions for SMPS3_FORCE */
3295#define TPS65917_SMPS3_FORCE_CMD 0x80
3296#define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07
3297#define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F
3298#define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00
3299
3300/* Bit definitions for SMPS3_VOLTAGE */
3301#define TPS65917_SMPS3_VOLTAGE_RANGE 0x80
3302#define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
3303#define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F
3304#define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
3305
3306/* Bit definitions for SMPS4_CTRL */
3307#define TPS65917_SMPS4_CTRL_WR_S 0x80
3308#define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07
3309#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40
3310#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3311#define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30
3312#define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04
3313#define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C
3314#define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02
3315#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03
3316#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00
3317
3318/* Bit definitions for SMPS4_VOLTAGE */
3319#define TPS65917_SMPS4_VOLTAGE_RANGE 0x80
3320#define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07
3321#define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F
3322#define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00
3323
3324/* Bit definitions for SMPS5_CTRL */
3325#define TPS65917_SMPS5_CTRL_WR_S 0x80
3326#define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07
3327#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40
3328#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3329#define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30
3330#define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04
3331#define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C
3332#define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02
3333#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03
3334#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00
3335
3336/* Bit definitions for SMPS5_VOLTAGE */
3337#define TPS65917_SMPS5_VOLTAGE_RANGE 0x80
3338#define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07
3339#define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F
3340#define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00
3341
3342/* Bit definitions for SMPS_CTRL */
3343#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10
3344#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04
3345#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03
3346#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00
3347
3348/* Bit definitions for SMPS_PD_CTRL */
3349#define TPS65917_SMPS_PD_CTRL_SMPS5 0x40
3350#define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06
3351#define TPS65917_SMPS_PD_CTRL_SMPS4 0x10
3352#define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04
3353#define TPS65917_SMPS_PD_CTRL_SMPS3 0x08
3354#define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03
3355#define TPS65917_SMPS_PD_CTRL_SMPS2 0x02
3356#define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01
3357#define TPS65917_SMPS_PD_CTRL_SMPS1 0x01
3358#define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00
3359
3360/* Bit definitions for SMPS_THERMAL_EN */
3361#define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40
3362#define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06
3363#define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08
3364#define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03
3365#define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01
3366#define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00
3367
3368/* Bit definitions for SMPS_THERMAL_STATUS */
3369#define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40
3370#define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06
3371#define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08
3372#define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03
3373#define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01
3374#define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00
3375
3376/* Bit definitions for SMPS_SHORT_STATUS */
3377#define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40
3378#define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06
3379#define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10
3380#define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04
3381#define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08
3382#define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03
3383#define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02
3384#define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01
3385#define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01
3386#define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00
3387
3388/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
3389#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40
3390#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06
3391#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10
3392#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04
3393#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08
3394#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03
3395#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02
3396#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01
3397#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01
3398#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00
3399
3400/* Bit definitions for SMPS_POWERGOOD_MASK1 */
3401#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40
3402#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06
3403#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10
3404#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04
3405#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08
3406#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03
3407#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02
3408#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01
3409#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01
3410#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00
3411
3412/* Bit definitions for SMPS_POWERGOOD_MASK2 */
3413#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
3414#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
3415#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10
3416#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04
3417
3418/* Bit definitions for SMPS_PLL_CTRL */
3419
3420#define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08
3421#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03
3422#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04
3423#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02
3424
3425/* Registers for function LDO */
3426#define TPS65917_LDO1_CTRL 0x00
3427#define TPS65917_LDO1_VOLTAGE 0x01
3428#define TPS65917_LDO2_CTRL 0x02
3429#define TPS65917_LDO2_VOLTAGE 0x03
3430#define TPS65917_LDO3_CTRL 0x04
3431#define TPS65917_LDO3_VOLTAGE 0x05
3432#define TPS65917_LDO4_CTRL 0x0E
3433#define TPS65917_LDO4_VOLTAGE 0x0F
3434#define TPS65917_LDO5_CTRL 0x12
3435#define TPS65917_LDO5_VOLTAGE 0x13
3436#define TPS65917_LDO_PD_CTRL1 0x1B
3437#define TPS65917_LDO_PD_CTRL2 0x1C
3438#define TPS65917_LDO_SHORT_STATUS1 0x1D
3439#define TPS65917_LDO_SHORT_STATUS2 0x1E
3440#define TPS65917_LDO_PD_CTRL3 0x2D
3441#define TPS65917_LDO_SHORT_STATUS3 0x2E
3442
3443/* Bit definitions for LDO1_CTRL */
3444#define TPS65917_LDO1_CTRL_WR_S 0x80
3445#define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07
3446#define TPS65917_LDO1_CTRL_BYPASS_EN 0x40
3447#define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06
3448#define TPS65917_LDO1_CTRL_STATUS 0x10
3449#define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04
3450#define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04
3451#define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
3452#define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01
3453#define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
3454
3455/* Bit definitions for LDO1_VOLTAGE */
3456#define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F
3457#define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00
3458
3459/* Bit definitions for LDO2_CTRL */
3460#define TPS65917_LDO2_CTRL_WR_S 0x80
3461#define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07
3462#define TPS65917_LDO2_CTRL_BYPASS_EN 0x40
3463#define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06
3464#define TPS65917_LDO2_CTRL_STATUS 0x10
3465#define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04
3466#define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04
3467#define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
3468#define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01
3469#define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
3470
3471/* Bit definitions for LDO2_VOLTAGE */
3472#define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F
3473#define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00
3474
3475/* Bit definitions for LDO3_CTRL */
3476#define TPS65917_LDO3_CTRL_WR_S 0x80
3477#define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07
3478#define TPS65917_LDO3_CTRL_STATUS 0x10
3479#define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04
3480#define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04
3481#define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
3482#define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01
3483#define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
3484
3485/* Bit definitions for LDO3_VOLTAGE */
3486#define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F
3487#define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00
3488
3489/* Bit definitions for LDO4_CTRL */
3490#define TPS65917_LDO4_CTRL_WR_S 0x80
3491#define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07
3492#define TPS65917_LDO4_CTRL_STATUS 0x10
3493#define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04
3494#define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04
3495#define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
3496#define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01
3497#define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
3498
3499/* Bit definitions for LDO4_VOLTAGE */
3500#define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F
3501#define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00
3502
3503/* Bit definitions for LDO5_CTRL */
3504#define TPS65917_LDO5_CTRL_WR_S 0x80
3505#define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07
3506#define TPS65917_LDO5_CTRL_STATUS 0x10
3507#define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04
3508#define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04
3509#define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
3510#define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01
3511#define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
3512
3513/* Bit definitions for LDO5_VOLTAGE */
3514#define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F
3515#define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00
3516
3517/* Bit definitions for LDO_PD_CTRL1 */
3518#define TPS65917_LDO_PD_CTRL1_LDO4 0x80
3519#define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07
3520#define TPS65917_LDO_PD_CTRL1_LDO2 0x02
3521#define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01
3522#define TPS65917_LDO_PD_CTRL1_LDO1 0x01
3523#define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00
3524
3525/* Bit definitions for LDO_PD_CTRL2 */
3526#define TPS65917_LDO_PD_CTRL2_LDO3 0x04
3527#define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02
3528#define TPS65917_LDO_PD_CTRL2_LDO5 0x02
3529#define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01
3530
3531/* Bit definitions for LDO_PD_CTRL3 */
3532#define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80
3533#define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07
3534
3535/* Bit definitions for LDO_SHORT_STATUS1 */
3536#define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80
3537#define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07
3538#define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02
3539#define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
3540#define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01
3541#define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
3542
3543/* Bit definitions for LDO_SHORT_STATUS2 */
3544#define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04
3545#define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02
3546#define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02
3547#define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01
3548
3549/* Bit definitions for LDO_SHORT_STATUS2 */
3550#define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80
3551#define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07
3552
3553/* Bit definitions for REGEN1_CTRL */
3554#define TPS65917_REGEN1_CTRL_STATUS 0x10
3555#define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04
3556#define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04
3557#define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
3558#define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01
3559#define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
3560
3561/* Bit definitions for PLLEN_CTRL */
3562#define TPS65917_PLLEN_CTRL_STATUS 0x10
3563#define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04
3564#define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04
3565#define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02
3566#define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01
3567#define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00
3568
3569/* Bit definitions for REGEN2_CTRL */
3570#define TPS65917_REGEN2_CTRL_STATUS 0x10
3571#define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04
3572#define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04
3573#define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
3574#define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01
3575#define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
3576
3577/* Bit definitions for NSLEEP_RES_ASSIGN */
3578#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08
3579#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03
3580#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04
3581#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02
3582#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02
3583#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
3584#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01
3585#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
3586
3587/* Bit definitions for NSLEEP_SMPS_ASSIGN */
3588#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40
3589#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3590#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10
3591#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3592#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08
3593#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3594#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02
3595#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3596#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01
3597#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3598
3599/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
3600#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80
3601#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07
3602#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02
3603#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
3604#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01
3605#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
3606
3607/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
3608#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04
3609#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02
3610#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02
3611#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01
3612
3613/* Bit definitions for ENABLE1_RES_ASSIGN */
3614#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08
3615#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03
3616#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04
3617#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02
3618#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02
3619#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
3620#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01
3621#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
3622
3623/* Bit definitions for ENABLE1_SMPS_ASSIGN */
3624#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40
3625#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3626#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10
3627#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3628#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08
3629#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3630#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02
3631#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3632#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01
3633#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3634
3635/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
3636#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80
3637#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07
3638#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02
3639#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
3640#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01
3641#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
3642
3643/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
3644#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04
3645#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02
3646#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02
3647#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01
3648
3649/* Bit definitions for ENABLE2_RES_ASSIGN */
3650#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08
3651#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03
3652#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04
3653#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02
3654#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02
3655#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
3656#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01
3657#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
3658
3659/* Bit definitions for ENABLE2_SMPS_ASSIGN */
3660#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40
3661#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3662#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10
3663#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3664#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08
3665#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3666#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02
3667#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3668#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01
3669#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3670
3671/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
3672#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80
3673#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07
3674#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02
3675#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
3676#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01
3677#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
3678
3679/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
3680#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04
3681#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02
3682#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02
3683#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01
3684
3685/* Bit definitions for REGEN3_CTRL */
3686#define TPS65917_REGEN3_CTRL_STATUS 0x10
3687#define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04
3688#define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04
3689#define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
3690#define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01
3691#define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
3692
3693/* Registers for function RESOURCE */
3694#define TPS65917_REGEN1_CTRL 0x2
3695#define TPS65917_PLLEN_CTRL 0x3
3696#define TPS65917_NSLEEP_RES_ASSIGN 0x6
3697#define TPS65917_NSLEEP_SMPS_ASSIGN 0x7
3698#define TPS65917_NSLEEP_LDO_ASSIGN1 0x8
3699#define TPS65917_NSLEEP_LDO_ASSIGN2 0x9
3700#define TPS65917_ENABLE1_RES_ASSIGN 0xA
3701#define TPS65917_ENABLE1_SMPS_ASSIGN 0xB
3702#define TPS65917_ENABLE1_LDO_ASSIGN1 0xC
3703#define TPS65917_ENABLE1_LDO_ASSIGN2 0xD
3704#define TPS65917_ENABLE2_RES_ASSIGN 0xE
3705#define TPS65917_ENABLE2_SMPS_ASSIGN 0xF
3706#define TPS65917_ENABLE2_LDO_ASSIGN1 0x10
3707#define TPS65917_ENABLE2_LDO_ASSIGN2 0x11
3708#define TPS65917_REGEN2_CTRL 0x12
3709#define TPS65917_REGEN3_CTRL 0x13
3710
2874static inline int palmas_read(struct palmas *palmas, unsigned int base, 3711static inline int palmas_read(struct palmas *palmas, unsigned int base,
2875 unsigned int reg, unsigned int *val) 3712 unsigned int reg, unsigned int *val)
2876{ 3713{
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-31 22:57:24 -0500