diff options
| -rw-r--r-- | Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt | 4 | ||||
| -rw-r--r-- | drivers/clk/renesas/clk-rz.c | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt index bb5d942075fb..8ff3e2774ed8 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | * Renesas RZ Clock Pulse Generator (CPG) | 1 | * Renesas RZ/A1 Clock Pulse Generator (CPG) |
| 2 | 2 | ||
| 3 | The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable | 3 | The CPG generates core clocks for the RZ/A1 SoCs. It includes the PLL, variable |
| 4 | CPU and GPU clocks, and several fixed ratio dividers. | 4 | CPU and GPU clocks, and several fixed ratio dividers. |
| 5 | The CPG also provides a Clock Domain for SoC devices, in combination with the | 5 | The CPG also provides a Clock Domain for SoC devices, in combination with the |
| 6 | CPG Module Stop (MSTP) Clocks. | 6 | CPG Module Stop (MSTP) Clocks. |
diff --git a/drivers/clk/renesas/clk-rz.c b/drivers/clk/renesas/clk-rz.c index 5adb934326d1..127c58135c8f 100644 --- a/drivers/clk/renesas/clk-rz.c +++ b/drivers/clk/renesas/clk-rz.c | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * rz Core CPG Clocks | 2 | * RZ/A1 Core CPG Clocks |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2013 Ideas On Board SPRL | 4 | * Copyright (C) 2013 Ideas On Board SPRL |
| 5 | * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> | 5 | * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> |