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-rw-r--r--tools/perf/pmu-events/arch/arm64/ampere/emag/branch.json23
-rw-r--r--tools/perf/pmu-events/arch/arm64/ampere/emag/bus.json26
-rw-r--r--tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json191
-rw-r--r--tools/perf/pmu-events/arch/arm64/ampere/emag/clock.json20
-rw-r--r--tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json32
-rw-r--r--tools/perf/pmu-events/arch/arm64/ampere/emag/exception.json50
-rw-r--r--tools/perf/pmu-events/arch/arm64/ampere/emag/instruction.json89
-rw-r--r--tools/perf/pmu-events/arch/arm64/ampere/emag/intrinsic.json14
-rw-r--r--tools/perf/pmu-events/arch/arm64/ampere/emag/memory.json29
-rw-r--r--tools/perf/pmu-events/arch/arm64/ampere/emag/pipeline.json50
10 files changed, 492 insertions, 32 deletions
diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/branch.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/branch.json
new file mode 100644
index 000000000000..abc98b018446
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/branch.json
@@ -0,0 +1,23 @@
1[
2 {
3 "ArchStdEvent": "BR_IMMED_SPEC",
4 },
5 {
6 "ArchStdEvent": "BR_RETURN_SPEC",
7 },
8 {
9 "ArchStdEvent": "BR_INDIRECT_SPEC",
10 },
11 {
12 "PublicDescription": "Mispredicted or not predicted branch speculatively executed",
13 "EventCode": "0x10",
14 "EventName": "BR_MIS_PRED",
15 "BriefDescription": "Branch mispredicted"
16 },
17 {
18 "PublicDescription": "Predictable branch speculatively executed",
19 "EventCode": "0x12",
20 "EventName": "BR_PRED",
21 "BriefDescription": "Predictable branch"
22 },
23]
diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/bus.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/bus.json
new file mode 100644
index 000000000000..687b2629e1d1
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/bus.json
@@ -0,0 +1,26 @@
1[
2 {
3 "ArchStdEvent": "BUS_ACCESS_RD",
4 },
5 {
6 "ArchStdEvent": "BUS_ACCESS_WR",
7 },
8 {
9 "ArchStdEvent": "BUS_ACCESS_SHARED",
10 },
11 {
12 "ArchStdEvent": "BUS_ACCESS_NOT_SHARED",
13 },
14 {
15 "ArchStdEvent": "BUS_ACCESS_NORMAL",
16 },
17 {
18 "ArchStdEvent": "BUS_ACCESS_PERIPH",
19 },
20 {
21 "PublicDescription": "Bus access",
22 "EventCode": "0x19",
23 "EventName": "BUS_ACCESS",
24 "BriefDescription": "Bus access"
25 },
26]
diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json
new file mode 100644
index 000000000000..df9201434cb6
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/cache.json
@@ -0,0 +1,191 @@
1[
2 {
3 "ArchStdEvent": "L1D_CACHE_RD",
4 },
5 {
6 "ArchStdEvent": "L1D_CACHE_WR",
7 },
8 {
9 "ArchStdEvent": "L1D_CACHE_REFILL_RD",
10 },
11 {
12 "ArchStdEvent": "L1D_CACHE_INVAL",
13 },
14 {
15 "ArchStdEvent": "L1D_TLB_REFILL_RD",
16 },
17 {
18 "ArchStdEvent": "L1D_TLB_REFILL_WR",
19 },
20 {
21 "ArchStdEvent": "L2D_CACHE_RD",
22 },
23 {
24 "ArchStdEvent": "L2D_CACHE_WR",
25 },
26 {
27 "ArchStdEvent": "L2D_CACHE_REFILL_RD",
28 },
29 {
30 "ArchStdEvent": "L2D_CACHE_REFILL_WR",
31 },
32 {
33 "ArchStdEvent": "L2D_CACHE_WB_VICTIM",
34 },
35 {
36 "ArchStdEvent": "L2D_CACHE_WB_CLEAN",
37 },
38 {
39 "ArchStdEvent": "L2D_CACHE_INVAL",
40 },
41 {
42 "PublicDescription": "Level 1 instruction cache refill",
43 "EventCode": "0x01",
44 "EventName": "L1I_CACHE_REFILL",
45 "BriefDescription": "L1I cache refill"
46 },
47 {
48 "PublicDescription": "Level 1 instruction TLB refill",
49 "EventCode": "0x02",
50 "EventName": "L1I_TLB_REFILL",
51 "BriefDescription": "L1I TLB refill"
52 },
53 {
54 "PublicDescription": "Level 1 data cache refill",
55 "EventCode": "0x03",
56 "EventName": "L1D_CACHE_REFILL",
57 "BriefDescription": "L1D cache refill"
58 },
59 {
60 "PublicDescription": "Level 1 data cache access",
61 "EventCode": "0x04",
62 "EventName": "L1D_CACHE_ACCESS",
63 "BriefDescription": "L1D cache access"
64 },
65 {
66 "PublicDescription": "Level 1 data TLB refill",
67 "EventCode": "0x05",
68 "EventName": "L1D_TLB_REFILL",
69 "BriefDescription": "L1D TLB refill"
70 },
71 {
72 "PublicDescription": "Level 1 instruction cache access",
73 "EventCode": "0x14",
74 "EventName": "L1I_CACHE_ACCESS",
75 "BriefDescription": "L1I cache access"
76 },
77 {
78 "PublicDescription": "Level 2 data cache access",
79 "EventCode": "0x16",
80 "EventName": "L2D_CACHE_ACCESS",
81 "BriefDescription": "L2D cache access"
82 },
83 {
84 "PublicDescription": "Level 2 data refill",
85 "EventCode": "0x17",
86 "EventName": "L2D_CACHE_REFILL",
87 "BriefDescription": "L2D cache refill"
88 },
89 {
90 "PublicDescription": "Level 2 data cache, Write-Back",
91 "EventCode": "0x18",
92 "EventName": "L2D_CACHE_WB",
93 "BriefDescription": "L2D cache Write-Back"
94 },
95 {
96 "PublicDescription": "Level 1 data TLB access. This event counts any load or store operation which accesses the data L1 TLB",
97 "EventCode": "0x25",
98 "EventName": "L1D_TLB_ACCESS",
99 "BriefDescription": "L1D TLB access"
100 },
101 {
102 "PublicDescription": "Level 1 instruction TLB access. This event counts any instruction fetch which accesses the instruction L1 TLB",
103 "EventCode": "0x26",
104 "EventName": "L1I_TLB_ACCESS",
105 "BriefDescription": "L1I TLB access"
106 },
107 {
108 "PublicDescription": "Level 2 access to data TLB that caused a page table walk. This event counts on any data access which causes L2D_TLB_REFILL to count",
109 "EventCode": "0x34",
110 "EventName": "L2D_TLB_ACCESS",
111 "BriefDescription": "L2D TLB access"
112 },
113 {
114 "PublicDescription": "Level 2 access to instruciton TLB that caused a page table walk. This event counts on any instruciton access which causes L2I_TLB_REFILL to count",
115 "EventCode": "0x35",
116 "EventName": "L2I_TLB_ACCESS",
117 "BriefDescription": "L2D TLB access"
118 },
119 {
120 "PublicDescription": "Branch target buffer misprediction",
121 "EventCode": "0x102",
122 "EventName": "BTB_MIS_PRED",
123 "BriefDescription": "BTB misprediction"
124 },
125 {
126 "PublicDescription": "ITB miss",
127 "EventCode": "0x103",
128 "EventName": "ITB_MISS",
129 "BriefDescription": "ITB miss"
130 },
131 {
132 "PublicDescription": "DTB miss",
133 "EventCode": "0x104",
134 "EventName": "DTB_MISS",
135 "BriefDescription": "DTB miss"
136 },
137 {
138 "PublicDescription": "Level 1 data cache late miss",
139 "EventCode": "0x105",
140 "EventName": "L1D_CACHE_LATE_MISS",
141 "BriefDescription": "L1D cache late miss"
142 },
143 {
144 "PublicDescription": "Level 1 data cache prefetch request",
145 "EventCode": "0x106",
146 "EventName": "L1D_CACHE_PREFETCH",
147 "BriefDescription": "L1D cache prefetch"
148 },
149 {
150 "PublicDescription": "Level 2 data cache prefetch request",
151 "EventCode": "0x107",
152 "EventName": "L2D_CACHE_PREFETCH",
153 "BriefDescription": "L2D cache prefetch"
154 },
155 {
156 "PublicDescription": "Level 1 stage 2 TLB refill",
157 "EventCode": "0x111",
158 "EventName": "L1_STAGE2_TLB_REFILL",
159 "BriefDescription": "L1 stage 2 TLB refill"
160 },
161 {
162 "PublicDescription": "Page walk cache level-0 stage-1 hit",
163 "EventCode": "0x112",
164 "EventName": "PAGE_WALK_L0_STAGE1_HIT",
165 "BriefDescription": "Page walk, L0 stage-1 hit"
166 },
167 {
168 "PublicDescription": "Page walk cache level-1 stage-1 hit",
169 "EventCode": "0x113",
170 "EventName": "PAGE_WALK_L1_STAGE1_HIT",
171 "BriefDescription": "Page walk, L1 stage-1 hit"
172 },
173 {
174 "PublicDescription": "Page walk cache level-2 stage-1 hit",
175 "EventCode": "0x114",
176 "EventName": "PAGE_WALK_L2_STAGE1_HIT",
177 "BriefDescription": "Page walk, L2 stage-1 hit"
178 },
179 {
180 "PublicDescription": "Page walk cache level-1 stage-2 hit",
181 "EventCode": "0x115",
182 "EventName": "PAGE_WALK_L1_STAGE2_HIT",
183 "BriefDescription": "Page walk, L1 stage-2 hit"
184 },
185 {
186 "PublicDescription": "Page walk cache level-2 stage-2 hit",
187 "EventCode": "0x116",
188 "EventName": "PAGE_WALK_L2_STAGE2_HIT",
189 "BriefDescription": "Page walk, L2 stage-2 hit"
190 },
191]
diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/clock.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/clock.json
new file mode 100644
index 000000000000..38cd1f1a70dc
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/clock.json
@@ -0,0 +1,20 @@
1[
2 {
3 "PublicDescription": "The number of core clock cycles",
4 "EventCode": "0x11",
5 "EventName": "CPU_CYCLES",
6 "BriefDescription": "Clock cycles"
7 },
8 {
9 "PublicDescription": "FSU clocking gated off cycle",
10 "EventCode": "0x101",
11 "EventName": "FSU_CLOCK_OFF_CYCLES",
12 "BriefDescription": "FSU clocking gated off cycle"
13 },
14 {
15 "PublicDescription": "Wait state cycle",
16 "EventCode": "0x110",
17 "EventName": "Wait_CYCLES",
18 "BriefDescription": "Wait state cycle"
19 },
20]
diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json
deleted file mode 100644
index bc03c06c3918..000000000000
--- a/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json
+++ /dev/null
@@ -1,32 +0,0 @@
1[
2 {
3 "ArchStdEvent": "L1D_CACHE_RD",
4 },
5 {
6 "ArchStdEvent": "L1D_CACHE_WR",
7 },
8 {
9 "ArchStdEvent": "L1D_CACHE_REFILL_RD",
10 },
11 {
12 "ArchStdEvent": "L1D_CACHE_REFILL_WR",
13 },
14 {
15 "ArchStdEvent": "L1D_TLB_REFILL_RD",
16 },
17 {
18 "ArchStdEvent": "L1D_TLB_REFILL_WR",
19 },
20 {
21 "ArchStdEvent": "L1D_TLB_RD",
22 },
23 {
24 "ArchStdEvent": "L1D_TLB_WR",
25 },
26 {
27 "ArchStdEvent": "BUS_ACCESS_RD",
28 },
29 {
30 "ArchStdEvent": "BUS_ACCESS_WR",
31 }
32]
diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/exception.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/exception.json
new file mode 100644
index 000000000000..3720dc28a15f
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/exception.json
@@ -0,0 +1,50 @@
1[
2 {
3 "ArchStdEvent": "EXC_UNDEF",
4 },
5 {
6 "ArchStdEvent": "EXC_SVC",
7 },
8 {
9 "ArchStdEvent": "EXC_PABORT",
10 },
11 {
12 "ArchStdEvent": "EXC_DABORT",
13 },
14 {
15 "ArchStdEvent": "EXC_IRQ",
16 },
17 {
18 "ArchStdEvent": "EXC_FIQ",
19 },
20 {
21 "ArchStdEvent": "EXC_HVC",
22 },
23 {
24 "ArchStdEvent": "EXC_TRAP_PABORT",
25 },
26 {
27 "ArchStdEvent": "EXC_TRAP_DABORT",
28 },
29 {
30 "ArchStdEvent": "EXC_TRAP_OTHER",
31 },
32 {
33 "ArchStdEvent": "EXC_TRAP_IRQ",
34 },
35 {
36 "ArchStdEvent": "EXC_TRAP_FIQ",
37 },
38 {
39 "PublicDescription": "Exception taken",
40 "EventCode": "0x09",
41 "EventName": "EXC_TAKEN",
42 "BriefDescription": "Exception taken"
43 },
44 {
45 "PublicDescription": "Instruction architecturally executed, condition check pass, exception return",
46 "EventCode": "0x0a",
47 "EventName": "EXC_RETURN",
48 "BriefDescription": "Exception return"
49 },
50]
diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/instruction.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/instruction.json
new file mode 100644
index 000000000000..82cf753e6472
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/instruction.json
@@ -0,0 +1,89 @@
1[
2 {
3 "ArchStdEvent": "LD_SPEC",
4 },
5 {
6 "ArchStdEvent": "ST_SPEC",
7 },
8 {
9 "ArchStdEvent": "LDST_SPEC",
10 },
11 {
12 "ArchStdEvent": "DP_SPEC",
13 },
14 {
15 "ArchStdEvent": "ASE_SPEC",
16 },
17 {
18 "ArchStdEvent": "VFP_SPEC",
19 },
20 {
21 "ArchStdEvent": "PC_WRITE_SPEC",
22 },
23 {
24 "ArchStdEvent": "CRYPTO_SPEC",
25 },
26 {
27 "ArchStdEvent": "ISB_SPEC",
28 },
29 {
30 "ArchStdEvent": "DSB_SPEC",
31 },
32 {
33 "ArchStdEvent": "DMB_SPEC",
34 },
35 {
36 "ArchStdEvent": "RC_LD_SPEC",
37 },
38 {
39 "ArchStdEvent": "RC_ST_SPEC",
40 },
41 {
42 "PublicDescription": "Instruction architecturally executed, software increment",
43 "EventCode": "0x00",
44 "EventName": "SW_INCR",
45 "BriefDescription": "Software increment"
46 },
47 {
48 "PublicDescription": "Instruction architecturally executed",
49 "EventCode": "0x08",
50 "EventName": "INST_RETIRED",
51 "BriefDescription": "Instruction retired"
52 },
53 {
54 "PublicDescription": "Instruction architecturally executed, condition code check pass, write to CONTEXTIDR",
55 "EventCode": "0x0b",
56 "EventName": "CID_WRITE_RETIRED",
57 "BriefDescription": "Write to CONTEXTIDR"
58 },
59 {
60 "PublicDescription": "Operation speculatively executed",
61 "EventCode": "0x1b",
62 "EventName": "INST_SPEC",
63 "BriefDescription": "Speculatively executed"
64 },
65 {
66 "PublicDescription": "Instruction architecturally executed (condition check pass), write to TTBR",
67 "EventCode": "0x1c",
68 "EventName": "TTBR_WRITE_RETIRED",
69 "BriefDescription": "Instruction executed, TTBR write"
70 },
71 {
72 "PublicDescription": "Instruction architecturally executed, branch. This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches",
73 "EventCode": "0x21",
74 "EventName": "BR_RETIRED",
75 "BriefDescription": "Branch retired"
76 },
77 {
78 "PublicDescription": "Instruction architecturally executed, mispredicted branch. This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush",
79 "EventCode": "0x22",
80 "EventName": "BR_MISPRED_RETIRED",
81 "BriefDescription": "Mispredicted branch retired"
82 },
83 {
84 "PublicDescription": "Operation speculatively executed, NOP",
85 "EventCode": "0x100",
86 "EventName": "NOP_SPEC",
87 "BriefDescription": "Speculatively executed, NOP"
88 },
89]
diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/intrinsic.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/intrinsic.json
new file mode 100644
index 000000000000..2aecc5c2347d
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/intrinsic.json
@@ -0,0 +1,14 @@
1[
2 {
3 "ArchStdEvent": "LDREX_SPEC",
4 },
5 {
6 "ArchStdEvent": "STREX_PASS_SPEC",
7 },
8 {
9 "ArchStdEvent": "STREX_FAIL_SPEC",
10 },
11 {
12 "ArchStdEvent": "STREX_SPEC",
13 },
14]
diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/memory.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/memory.json
new file mode 100644
index 000000000000..08508697b318
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/memory.json
@@ -0,0 +1,29 @@
1[
2 {
3 "ArchStdEvent": "MEM_ACCESS_RD",
4 },
5 {
6 "ArchStdEvent": "MEM_ACCESS_WR",
7 },
8 {
9 "ArchStdEvent": "UNALIGNED_LD_SPEC",
10 },
11 {
12 "ArchStdEvent": "UNALIGNED_ST_SPEC",
13 },
14 {
15 "ArchStdEvent": "UNALIGNED_LDST_SPEC",
16 },
17 {
18 "PublicDescription": "Data memory access",
19 "EventCode": "0x13",
20 "EventName": "MEM_ACCESS",
21 "BriefDescription": "Memory access"
22 },
23 {
24 "PublicDescription": "Local memory error. This event counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
25 "EventCode": "0x1a",
26 "EventName": "MEM_ERROR",
27 "BriefDescription": "Memory error"
28 },
29]
diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/pipeline.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/pipeline.json
new file mode 100644
index 000000000000..e2087de586bf
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/pipeline.json
@@ -0,0 +1,50 @@
1[
2 {
3 "PublicDescription": "Decode starved for instruction cycle",
4 "EventCode": "0x108",
5 "EventName": "DECODE_STALL",
6 "BriefDescription": "Decode starved"
7 },
8 {
9 "PublicDescription": "Op dispatch stalled cycle",
10 "EventCode": "0x109",
11 "EventName": "DISPATCH_STALL",
12 "BriefDescription": "Dispatch stalled"
13 },
14 {
15 "PublicDescription": "IXA Op non-issue",
16 "EventCode": "0x10a",
17 "EventName": "IXA_STALL",
18 "BriefDescription": "IXA stalled"
19 },
20 {
21 "PublicDescription": "IXB Op non-issue",
22 "EventCode": "0x10b",
23 "EventName": "IXB_STALL",
24 "BriefDescription": "IXB stalled"
25 },
26 {
27 "PublicDescription": "BX Op non-issue",
28 "EventCode": "0x10c",
29 "EventName": "BX_STALL",
30 "BriefDescription": "BX stalled"
31 },
32 {
33 "PublicDescription": "LX Op non-issue",
34 "EventCode": "0x10d",
35 "EventName": "LX_STALL",
36 "BriefDescription": "LX stalled"
37 },
38 {
39 "PublicDescription": "SX Op non-issue",
40 "EventCode": "0x10e",
41 "EventName": "SX_STALL",
42 "BriefDescription": "SX stalled"
43 },
44 {
45 "PublicDescription": "FX Op non-issue",
46 "EventCode": "0x10f",
47 "EventName": "FX_STALL",
48 "BriefDescription": "FX stalled"
49 },
50]
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-01 06:15:25 -0500