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-rw-r--r--drivers/irqchip/irq-atmel-aic5.c24
1 files changed, 16 insertions, 8 deletions
diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c
index 9da9942ac83c..f6d680485bee 100644
--- a/drivers/irqchip/irq-atmel-aic5.c
+++ b/drivers/irqchip/irq-atmel-aic5.c
@@ -88,28 +88,36 @@ static void aic5_mask(struct irq_data *d)
88{ 88{
89 struct irq_domain *domain = d->domain; 89 struct irq_domain *domain = d->domain;
90 struct irq_domain_chip_generic *dgc = domain->gc; 90 struct irq_domain_chip_generic *dgc = domain->gc;
91 struct irq_chip_generic *gc = dgc->gc[0]; 91 struct irq_chip_generic *bgc = dgc->gc[0];
92 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
92 93
93 /* Disable interrupt on AIC5 */ 94 /*
94 irq_gc_lock(gc); 95 * Disable interrupt on AIC5. We always take the lock of the
96 * first irq chip as all chips share the same registers.
97 */
98 irq_gc_lock(bgc);
95 irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR); 99 irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);
96 irq_reg_writel(gc, 1, AT91_AIC5_IDCR); 100 irq_reg_writel(gc, 1, AT91_AIC5_IDCR);
97 gc->mask_cache &= ~d->mask; 101 gc->mask_cache &= ~d->mask;
98 irq_gc_unlock(gc); 102 irq_gc_unlock(bgc);
99} 103}
100 104
101static void aic5_unmask(struct irq_data *d) 105static void aic5_unmask(struct irq_data *d)
102{ 106{
103 struct irq_domain *domain = d->domain; 107 struct irq_domain *domain = d->domain;
104 struct irq_domain_chip_generic *dgc = domain->gc; 108 struct irq_domain_chip_generic *dgc = domain->gc;
105 struct irq_chip_generic *gc = dgc->gc[0]; 109 struct irq_chip_generic *bgc = dgc->gc[0];
110 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
106 111
107 /* Enable interrupt on AIC5 */ 112 /*
108 irq_gc_lock(gc); 113 * Enable interrupt on AIC5. We always take the lock of the
114 * first irq chip as all chips share the same registers.
115 */
116 irq_gc_lock(bgc);
109 irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR); 117 irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);
110 irq_reg_writel(gc, 1, AT91_AIC5_IECR); 118 irq_reg_writel(gc, 1, AT91_AIC5_IECR);
111 gc->mask_cache |= d->mask; 119 gc->mask_cache |= d->mask;
112 irq_gc_unlock(gc); 120 irq_gc_unlock(bgc);
113} 121}
114 122
115static int aic5_retrigger(struct irq_data *d) 123static int aic5_retrigger(struct irq_data *d)