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-rw-r--r--Documentation/devicetree/bindings/sound/rt5616.txt26
-rw-r--r--Documentation/devicetree/bindings/sound/rt5659.txt75
-rw-r--r--Documentation/devicetree/bindings/sound/rt5677.txt2
-rw-r--r--include/sound/rt5659.h49
-rw-r--r--sound/soc/codecs/Kconfig12
-rw-r--r--sound/soc/codecs/Makefile4
-rw-r--r--sound/soc/codecs/rt286.c6
-rw-r--r--sound/soc/codecs/rt298.c2
-rw-r--r--sound/soc/codecs/rt5616.c1381
-rw-r--r--sound/soc/codecs/rt5616.h1819
-rw-r--r--sound/soc/codecs/rt5659.c4223
-rw-r--r--sound/soc/codecs/rt5659.h1819
-rw-r--r--sound/soc/codecs/rt5677.c11
13 files changed, 9422 insertions, 7 deletions
diff --git a/Documentation/devicetree/bindings/sound/rt5616.txt b/Documentation/devicetree/bindings/sound/rt5616.txt
new file mode 100644
index 000000000000..efc48c65198d
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/rt5616.txt
@@ -0,0 +1,26 @@
1RT5616 audio CODEC
2
3This device supports I2C only.
4
5Required properties:
6
7- compatible : "realtek,rt5616".
8
9- reg : The I2C address of the device.
10
11Pins on the device (for linking into audio routes) for RT5616:
12
13 * IN1P
14 * IN2P
15 * IN2N
16 * LOUTL
17 * LOUTR
18 * HPOL
19 * HPOR
20
21Example:
22
23codec: rt5616@1b {
24 compatible = "realtek,rt5616";
25 reg = <0x1b>;
26};
diff --git a/Documentation/devicetree/bindings/sound/rt5659.txt b/Documentation/devicetree/bindings/sound/rt5659.txt
new file mode 100644
index 000000000000..5f79e7fde032
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/rt5659.txt
@@ -0,0 +1,75 @@
1RT5659/RT5658 audio CODEC
2
3This device supports I2C only.
4
5Required properties:
6
7- compatible : One of "realtek,rt5659" or "realtek,rt5658".
8
9- reg : The I2C address of the device.
10
11- interrupts : The CODEC's interrupt output.
12
13Optional properties:
14
15- realtek,in1-differential
16- realtek,in3-differential
17- realtek,in4-differential
18 Boolean. Indicate MIC1/3/4 input are differential, rather than single-ended.
19
20- realtek,dmic1-data-pin
21 0: dmic1 is not used
22 1: using IN2N pin as dmic1 data pin
23 2: using GPIO5 pin as dmic1 data pin
24 3: using GPIO9 pin as dmic1 data pin
25 4: using GPIO11 pin as dmic1 data pin
26
27- realtek,dmic2-data-pin
28 0: dmic2 is not used
29 1: using IN2P pin as dmic2 data pin
30 2: using GPIO6 pin as dmic2 data pin
31 3: using GPIO10 pin as dmic2 data pin
32 4: using GPIO12 pin as dmic2 data pin
33
34- realtek,jd-src
35 0: No JD is used
36 1: using JD3 as JD source
37
38- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
39- realtek,reset-gpios : The GPIO that controls the CODEC's RESET pin.
40
41Pins on the device (for linking into audio routes) for RT5659/RT5658:
42
43 * DMIC L1
44 * DMIC R1
45 * DMIC L2
46 * DMIC R2
47 * IN1P
48 * IN1N
49 * IN2P
50 * IN2N
51 * IN3P
52 * IN3N
53 * IN4P
54 * IN4N
55 * HPOL
56 * HPOR
57 * SPOL
58 * SPOR
59 * LOUTL
60 * LOUTR
61 * MONOOUT
62 * PDML
63 * PDMR
64 * SPDIF
65
66Example:
67
68rt5659 {
69 compatible = "realtek,rt5659";
70 reg = <0x1b>;
71 interrupt-parent = <&gpio>;
72 interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
73 realtek,ldo1-en-gpios =
74 <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
75};
diff --git a/Documentation/devicetree/bindings/sound/rt5677.txt b/Documentation/devicetree/bindings/sound/rt5677.txt
index f07078997f87..1b3c13d206ff 100644
--- a/Documentation/devicetree/bindings/sound/rt5677.txt
+++ b/Documentation/devicetree/bindings/sound/rt5677.txt
@@ -18,7 +18,7 @@ Required properties:
18Optional properties: 18Optional properties:
19 19
20- realtek,pow-ldo2-gpio : The GPIO that controls the CODEC's POW_LDO2 pin. 20- realtek,pow-ldo2-gpio : The GPIO that controls the CODEC's POW_LDO2 pin.
21- realtek,reset-gpio : The GPIO that controls the CODEC's RESET pin. 21- realtek,reset-gpio : The GPIO that controls the CODEC's RESET pin. Active low.
22 22
23- realtek,in1-differential 23- realtek,in1-differential
24- realtek,in2-differential 24- realtek,in2-differential
diff --git a/include/sound/rt5659.h b/include/sound/rt5659.h
new file mode 100644
index 000000000000..656c4d58948d
--- /dev/null
+++ b/include/sound/rt5659.h
@@ -0,0 +1,49 @@
1/*
2 * linux/sound/rt5659.h -- Platform data for RT5659
3 *
4 * Copyright 2013 Realtek Microelectronics
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __LINUX_SND_RT5659_H
12#define __LINUX_SND_RT5659_H
13
14enum rt5659_dmic1_data_pin {
15 RT5659_DMIC1_NULL,
16 RT5659_DMIC1_DATA_IN2N,
17 RT5659_DMIC1_DATA_GPIO5,
18 RT5659_DMIC1_DATA_GPIO9,
19 RT5659_DMIC1_DATA_GPIO11,
20};
21
22enum rt5659_dmic2_data_pin {
23 RT5659_DMIC2_NULL,
24 RT5659_DMIC2_DATA_IN2P,
25 RT5659_DMIC2_DATA_GPIO6,
26 RT5659_DMIC2_DATA_GPIO10,
27 RT5659_DMIC2_DATA_GPIO12,
28};
29
30enum rt5659_jd_src {
31 RT5659_JD_NULL,
32 RT5659_JD3,
33};
34
35struct rt5659_platform_data {
36 bool in1_diff;
37 bool in3_diff;
38 bool in4_diff;
39
40 int ldo1_en; /* GPIO for LDO1_EN */
41 int reset; /* GPIO for RESET */
42
43 enum rt5659_dmic1_data_pin dmic1_data_pin;
44 enum rt5659_dmic2_data_pin dmic2_data_pin;
45 enum rt5659_jd_src jd_src;
46};
47
48#endif
49
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 784468e1cbad..ac0291ca6163 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -95,10 +95,12 @@ config SND_SOC_ALL_CODECS
95 select SND_SOC_PCM512x_SPI if SPI_MASTER 95 select SND_SOC_PCM512x_SPI if SPI_MASTER
96 select SND_SOC_RT286 if I2C 96 select SND_SOC_RT286 if I2C
97 select SND_SOC_RT298 if I2C 97 select SND_SOC_RT298 if I2C
98 select SND_SOC_RT5616 if I2C
98 select SND_SOC_RT5631 if I2C 99 select SND_SOC_RT5631 if I2C
99 select SND_SOC_RT5640 if I2C 100 select SND_SOC_RT5640 if I2C
100 select SND_SOC_RT5645 if I2C 101 select SND_SOC_RT5645 if I2C
101 select SND_SOC_RT5651 if I2C 102 select SND_SOC_RT5651 if I2C
103 select SND_SOC_RT5659 if I2C
102 select SND_SOC_RT5670 if I2C 104 select SND_SOC_RT5670 if I2C
103 select SND_SOC_RT5677 if I2C && SPI_MASTER 105 select SND_SOC_RT5677 if I2C && SPI_MASTER
104 select SND_SOC_SGTL5000 if I2C 106 select SND_SOC_SGTL5000 if I2C
@@ -563,14 +565,18 @@ config SND_SOC_PCM512x_SPI
563 565
564config SND_SOC_RL6231 566config SND_SOC_RL6231
565 tristate 567 tristate
568 default y if SND_SOC_RT5616=y
566 default y if SND_SOC_RT5640=y 569 default y if SND_SOC_RT5640=y
567 default y if SND_SOC_RT5645=y 570 default y if SND_SOC_RT5645=y
568 default y if SND_SOC_RT5651=y 571 default y if SND_SOC_RT5651=y
572 default y if SND_SOC_RT5659=y
569 default y if SND_SOC_RT5670=y 573 default y if SND_SOC_RT5670=y
570 default y if SND_SOC_RT5677=y 574 default y if SND_SOC_RT5677=y
575 default m if SND_SOC_RT5616=m
571 default m if SND_SOC_RT5640=m 576 default m if SND_SOC_RT5640=m
572 default m if SND_SOC_RT5645=m 577 default m if SND_SOC_RT5645=m
573 default m if SND_SOC_RT5651=m 578 default m if SND_SOC_RT5651=m
579 default m if SND_SOC_RT5659=m
574 default m if SND_SOC_RT5670=m 580 default m if SND_SOC_RT5670=m
575 default m if SND_SOC_RT5677=m 581 default m if SND_SOC_RT5677=m
576 582
@@ -589,6 +595,9 @@ config SND_SOC_RT298
589 tristate 595 tristate
590 depends on I2C 596 depends on I2C
591 597
598config SND_SOC_RT5616
599 tristate
600
592config SND_SOC_RT5631 601config SND_SOC_RT5631
593 tristate "Realtek ALC5631/RT5631 CODEC" 602 tristate "Realtek ALC5631/RT5631 CODEC"
594 depends on I2C 603 depends on I2C
@@ -602,6 +611,9 @@ config SND_SOC_RT5645
602config SND_SOC_RT5651 611config SND_SOC_RT5651
603 tristate 612 tristate
604 613
614config SND_SOC_RT5659
615 tristate
616
605config SND_SOC_RT5670 617config SND_SOC_RT5670
606 tristate 618 tristate
607 619
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 44d8958bd032..fb846e2ad33b 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -92,10 +92,12 @@ snd-soc-rl6231-objs := rl6231.o
92snd-soc-rl6347a-objs := rl6347a.o 92snd-soc-rl6347a-objs := rl6347a.o
93snd-soc-rt286-objs := rt286.o 93snd-soc-rt286-objs := rt286.o
94snd-soc-rt298-objs := rt298.o 94snd-soc-rt298-objs := rt298.o
95snd-soc-rt5616-objs := rt5616.o
95snd-soc-rt5631-objs := rt5631.o 96snd-soc-rt5631-objs := rt5631.o
96snd-soc-rt5640-objs := rt5640.o 97snd-soc-rt5640-objs := rt5640.o
97snd-soc-rt5645-objs := rt5645.o 98snd-soc-rt5645-objs := rt5645.o
98snd-soc-rt5651-objs := rt5651.o 99snd-soc-rt5651-objs := rt5651.o
100snd-soc-rt5659-objs := rt5659.o
99snd-soc-rt5670-objs := rt5670.o 101snd-soc-rt5670-objs := rt5670.o
100snd-soc-rt5677-objs := rt5677.o 102snd-soc-rt5677-objs := rt5677.o
101snd-soc-rt5677-spi-objs := rt5677-spi.o 103snd-soc-rt5677-spi-objs := rt5677-spi.o
@@ -294,10 +296,12 @@ obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o
294obj-$(CONFIG_SND_SOC_RL6347A) += snd-soc-rl6347a.o 296obj-$(CONFIG_SND_SOC_RL6347A) += snd-soc-rl6347a.o
295obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o 297obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o
296obj-$(CONFIG_SND_SOC_RT298) += snd-soc-rt298.o 298obj-$(CONFIG_SND_SOC_RT298) += snd-soc-rt298.o
299obj-$(CONFIG_SND_SOC_RT5616) += snd-soc-rt5616.o
297obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o 300obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o
298obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o 301obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o
299obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o 302obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o
300obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o 303obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o
304obj-$(CONFIG_SND_SOC_RT5659) += snd-soc-rt5659.o
301obj-$(CONFIG_SND_SOC_RT5670) += snd-soc-rt5670.o 305obj-$(CONFIG_SND_SOC_RT5670) += snd-soc-rt5670.o
302obj-$(CONFIG_SND_SOC_RT5677) += snd-soc-rt5677.o 306obj-$(CONFIG_SND_SOC_RT5677) += snd-soc-rt5677.o
303obj-$(CONFIG_SND_SOC_RT5677_SPI) += snd-soc-rt5677-spi.o 307obj-$(CONFIG_SND_SOC_RT5677_SPI) += snd-soc-rt5677-spi.o
diff --git a/sound/soc/codecs/rt286.c b/sound/soc/codecs/rt286.c
index af2ed774b552..bc08f0c5a5f6 100644
--- a/sound/soc/codecs/rt286.c
+++ b/sound/soc/codecs/rt286.c
@@ -1114,6 +1114,12 @@ static const struct dmi_system_id force_combo_jack_table[] = {
1114 DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS") 1114 DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS")
1115 } 1115 }
1116 }, 1116 },
1117 {
1118 .ident = "Intel Skylake RVP",
1119 .matches = {
1120 DMI_MATCH(DMI_PRODUCT_NAME, "Skylake Client platform")
1121 }
1122 },
1117 { } 1123 { }
1118}; 1124};
1119 1125
diff --git a/sound/soc/codecs/rt298.c b/sound/soc/codecs/rt298.c
index b3f795c60749..30c6de62ae6c 100644
--- a/sound/soc/codecs/rt298.c
+++ b/sound/soc/codecs/rt298.c
@@ -855,8 +855,6 @@ static int rt298_set_dai_sysclk(struct snd_soc_dai *dai,
855 snd_soc_update_bits(codec, 855 snd_soc_update_bits(codec,
856 RT298_I2S_CTRL2, 0x0100, 0x0100); 856 RT298_I2S_CTRL2, 0x0100, 0x0100);
857 snd_soc_update_bits(codec, 857 snd_soc_update_bits(codec,
858 RT298_PLL_CTRL, 0x4, 0x4);
859 snd_soc_update_bits(codec,
860 RT298_PLL_CTRL1, 0x20, 0x0); 858 RT298_PLL_CTRL1, 0x20, 0x0);
861 } 859 }
862 860
diff --git a/sound/soc/codecs/rt5616.c b/sound/soc/codecs/rt5616.c
new file mode 100644
index 000000000000..1c10d8ed39d2
--- /dev/null
+++ b/sound/soc/codecs/rt5616.c
@@ -0,0 +1,1381 @@
1/*
2 * rt5616.c -- RT5616 ALSA SoC audio codec driver
3 *
4 * Copyright 2015 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
20#include <sound/core.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/soc.h>
24#include <sound/soc-dapm.h>
25#include <sound/initval.h>
26#include <sound/tlv.h>
27
28#include "rl6231.h"
29#include "rt5616.h"
30
31#define RT5616_PR_RANGE_BASE (0xff + 1)
32#define RT5616_PR_SPACING 0x100
33
34#define RT5616_PR_BASE (RT5616_PR_RANGE_BASE + (0 * RT5616_PR_SPACING))
35
36static const struct regmap_range_cfg rt5616_ranges[] = {
37 {
38 .name = "PR",
39 .range_min = RT5616_PR_BASE,
40 .range_max = RT5616_PR_BASE + 0xf8,
41 .selector_reg = RT5616_PRIV_INDEX,
42 .selector_mask = 0xff,
43 .selector_shift = 0x0,
44 .window_start = RT5616_PRIV_DATA,
45 .window_len = 0x1,
46 },
47};
48
49static const struct reg_sequence init_list[] = {
50 {RT5616_PR_BASE + 0x3d, 0x3e00},
51 {RT5616_PR_BASE + 0x25, 0x6110},
52 {RT5616_PR_BASE + 0x20, 0x611f},
53 {RT5616_PR_BASE + 0x21, 0x4040},
54 {RT5616_PR_BASE + 0x23, 0x0004},
55};
56#define RT5616_INIT_REG_LEN ARRAY_SIZE(init_list)
57
58static const struct reg_default rt5616_reg[] = {
59 { 0x00, 0x0021 },
60 { 0x02, 0xc8c8 },
61 { 0x03, 0xc8c8 },
62 { 0x05, 0x0000 },
63 { 0x0d, 0x0000 },
64 { 0x0f, 0x0808 },
65 { 0x19, 0xafaf },
66 { 0x1c, 0x2f2f },
67 { 0x1e, 0x0000 },
68 { 0x27, 0x7860 },
69 { 0x29, 0x8080 },
70 { 0x2a, 0x5252 },
71 { 0x3b, 0x0000 },
72 { 0x3c, 0x006f },
73 { 0x3d, 0x0000 },
74 { 0x3e, 0x006f },
75 { 0x45, 0x6000 },
76 { 0x4d, 0x0000 },
77 { 0x4e, 0x0000 },
78 { 0x4f, 0x0279 },
79 { 0x50, 0x0000 },
80 { 0x51, 0x0000 },
81 { 0x52, 0x0279 },
82 { 0x53, 0xf000 },
83 { 0x61, 0x0000 },
84 { 0x62, 0x0000 },
85 { 0x63, 0x00c0 },
86 { 0x64, 0x0000 },
87 { 0x65, 0x0000 },
88 { 0x66, 0x0000 },
89 { 0x70, 0x8000 },
90 { 0x73, 0x1104 },
91 { 0x74, 0x0c00 },
92 { 0x80, 0x0000 },
93 { 0x81, 0x0000 },
94 { 0x82, 0x0000 },
95 { 0x8b, 0x0600 },
96 { 0x8e, 0x0004 },
97 { 0x8f, 0x1100 },
98 { 0x90, 0x0000 },
99 { 0x91, 0x0000 },
100 { 0x92, 0x0000 },
101 { 0x93, 0x2000 },
102 { 0x94, 0x0200 },
103 { 0x95, 0x0000 },
104 { 0xb0, 0x2080 },
105 { 0xb1, 0x0000 },
106 { 0xb2, 0x0000 },
107 { 0xb4, 0x2206 },
108 { 0xb5, 0x1f00 },
109 { 0xb6, 0x0000 },
110 { 0xb7, 0x0000 },
111 { 0xbb, 0x0000 },
112 { 0xbc, 0x0000 },
113 { 0xbd, 0x0000 },
114 { 0xbe, 0x0000 },
115 { 0xbf, 0x0000 },
116 { 0xc0, 0x0100 },
117 { 0xc1, 0x0000 },
118 { 0xc2, 0x0000 },
119 { 0xc8, 0x0000 },
120 { 0xc9, 0x0000 },
121 { 0xca, 0x0000 },
122 { 0xcb, 0x0000 },
123 { 0xcc, 0x0000 },
124 { 0xcd, 0x0000 },
125 { 0xce, 0x0000 },
126 { 0xcf, 0x0013 },
127 { 0xd0, 0x0680 },
128 { 0xd1, 0x1c17 },
129 { 0xd3, 0xb320 },
130 { 0xd4, 0x0000 },
131 { 0xd6, 0x0000 },
132 { 0xd7, 0x0000 },
133 { 0xd9, 0x0809 },
134 { 0xda, 0x0000 },
135 { 0xfa, 0x0010 },
136 { 0xfb, 0x0000 },
137 { 0xfc, 0x0000 },
138 { 0xfe, 0x10ec },
139 { 0xff, 0x6281 },
140};
141
142struct rt5616_priv {
143 struct snd_soc_codec *codec;
144 struct delayed_work patch_work;
145 struct regmap *regmap;
146
147 int sysclk;
148 int sysclk_src;
149 int lrck[RT5616_AIFS];
150 int bclk[RT5616_AIFS];
151 int master[RT5616_AIFS];
152
153 int pll_src;
154 int pll_in;
155 int pll_out;
156
157};
158
159static bool rt5616_volatile_register(struct device *dev, unsigned int reg)
160{
161 int i;
162
163 for (i = 0; i < ARRAY_SIZE(rt5616_ranges); i++) {
164 if (reg >= rt5616_ranges[i].range_min &&
165 reg <= rt5616_ranges[i].range_max) {
166 return true;
167 }
168 }
169
170 switch (reg) {
171 case RT5616_RESET:
172 case RT5616_PRIV_DATA:
173 case RT5616_EQ_CTRL1:
174 case RT5616_DRC_AGC_1:
175 case RT5616_IRQ_CTRL2:
176 case RT5616_INT_IRQ_ST:
177 case RT5616_PGM_REG_ARR1:
178 case RT5616_PGM_REG_ARR3:
179 case RT5616_VENDOR_ID:
180 case RT5616_DEVICE_ID:
181 return true;
182 default:
183 return false;
184 }
185}
186
187static bool rt5616_readable_register(struct device *dev, unsigned int reg)
188{
189 int i;
190
191 for (i = 0; i < ARRAY_SIZE(rt5616_ranges); i++) {
192 if (reg >= rt5616_ranges[i].range_min &&
193 reg <= rt5616_ranges[i].range_max) {
194 return true;
195 }
196 }
197
198 switch (reg) {
199 case RT5616_RESET:
200 case RT5616_VERSION_ID:
201 case RT5616_VENDOR_ID:
202 case RT5616_DEVICE_ID:
203 case RT5616_HP_VOL:
204 case RT5616_LOUT_CTRL1:
205 case RT5616_LOUT_CTRL2:
206 case RT5616_IN1_IN2:
207 case RT5616_INL1_INR1_VOL:
208 case RT5616_DAC1_DIG_VOL:
209 case RT5616_ADC_DIG_VOL:
210 case RT5616_ADC_BST_VOL:
211 case RT5616_STO1_ADC_MIXER:
212 case RT5616_AD_DA_MIXER:
213 case RT5616_STO_DAC_MIXER:
214 case RT5616_REC_L1_MIXER:
215 case RT5616_REC_L2_MIXER:
216 case RT5616_REC_R1_MIXER:
217 case RT5616_REC_R2_MIXER:
218 case RT5616_HPO_MIXER:
219 case RT5616_OUT_L1_MIXER:
220 case RT5616_OUT_L2_MIXER:
221 case RT5616_OUT_L3_MIXER:
222 case RT5616_OUT_R1_MIXER:
223 case RT5616_OUT_R2_MIXER:
224 case RT5616_OUT_R3_MIXER:
225 case RT5616_LOUT_MIXER:
226 case RT5616_PWR_DIG1:
227 case RT5616_PWR_DIG2:
228 case RT5616_PWR_ANLG1:
229 case RT5616_PWR_ANLG2:
230 case RT5616_PWR_MIXER:
231 case RT5616_PWR_VOL:
232 case RT5616_PRIV_INDEX:
233 case RT5616_PRIV_DATA:
234 case RT5616_I2S1_SDP:
235 case RT5616_ADDA_CLK1:
236 case RT5616_ADDA_CLK2:
237 case RT5616_GLB_CLK:
238 case RT5616_PLL_CTRL1:
239 case RT5616_PLL_CTRL2:
240 case RT5616_HP_OVCD:
241 case RT5616_DEPOP_M1:
242 case RT5616_DEPOP_M2:
243 case RT5616_DEPOP_M3:
244 case RT5616_CHARGE_PUMP:
245 case RT5616_PV_DET_SPK_G:
246 case RT5616_MICBIAS:
247 case RT5616_A_JD_CTL1:
248 case RT5616_A_JD_CTL2:
249 case RT5616_EQ_CTRL1:
250 case RT5616_EQ_CTRL2:
251 case RT5616_WIND_FILTER:
252 case RT5616_DRC_AGC_1:
253 case RT5616_DRC_AGC_2:
254 case RT5616_DRC_AGC_3:
255 case RT5616_SVOL_ZC:
256 case RT5616_JD_CTRL1:
257 case RT5616_JD_CTRL2:
258 case RT5616_IRQ_CTRL1:
259 case RT5616_IRQ_CTRL2:
260 case RT5616_INT_IRQ_ST:
261 case RT5616_GPIO_CTRL1:
262 case RT5616_GPIO_CTRL2:
263 case RT5616_GPIO_CTRL3:
264 case RT5616_PGM_REG_ARR1:
265 case RT5616_PGM_REG_ARR2:
266 case RT5616_PGM_REG_ARR3:
267 case RT5616_PGM_REG_ARR4:
268 case RT5616_PGM_REG_ARR5:
269 case RT5616_SCB_FUNC:
270 case RT5616_SCB_CTRL:
271 case RT5616_BASE_BACK:
272 case RT5616_MP3_PLUS1:
273 case RT5616_MP3_PLUS2:
274 case RT5616_ADJ_HPF_CTRL1:
275 case RT5616_ADJ_HPF_CTRL2:
276 case RT5616_HP_CALIB_AMP_DET:
277 case RT5616_HP_CALIB2:
278 case RT5616_SV_ZCD1:
279 case RT5616_SV_ZCD2:
280 case RT5616_D_MISC:
281 case RT5616_DUMMY2:
282 case RT5616_DUMMY3:
283 return true;
284 default:
285 return false;
286 }
287}
288
289static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
290static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
291static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
292static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
293static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
294
295/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
296static unsigned int bst_tlv[] = {
297 TLV_DB_RANGE_HEAD(7),
298 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
299 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
300 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
301 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
302 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
303 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
304 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
305};
306
307static const struct snd_kcontrol_new rt5616_snd_controls[] = {
308 /* Headphone Output Volume */
309 SOC_DOUBLE("HP Playback Switch", RT5616_HP_VOL,
310 RT5616_L_MUTE_SFT, RT5616_R_MUTE_SFT, 1, 1),
311 SOC_DOUBLE_TLV("HP Playback Volume", RT5616_HP_VOL,
312 RT5616_L_VOL_SFT, RT5616_R_VOL_SFT, 39, 1, out_vol_tlv),
313 /* OUTPUT Control */
314 SOC_DOUBLE("OUT Playback Switch", RT5616_LOUT_CTRL1,
315 RT5616_L_MUTE_SFT, RT5616_R_MUTE_SFT, 1, 1),
316 SOC_DOUBLE("OUT Channel Switch", RT5616_LOUT_CTRL1,
317 RT5616_VOL_L_SFT, RT5616_VOL_R_SFT, 1, 1),
318 SOC_DOUBLE_TLV("OUT Playback Volume", RT5616_LOUT_CTRL1,
319 RT5616_L_VOL_SFT, RT5616_R_VOL_SFT, 39, 1, out_vol_tlv),
320
321 /* DAC Digital Volume */
322 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5616_DAC1_DIG_VOL,
323 RT5616_L_VOL_SFT, RT5616_R_VOL_SFT,
324 175, 0, dac_vol_tlv),
325 /* IN1/IN2 Control */
326 SOC_SINGLE_TLV("IN1 Boost Volume", RT5616_IN1_IN2,
327 RT5616_BST_SFT1, 8, 0, bst_tlv),
328 SOC_SINGLE_TLV("IN2 Boost Volume", RT5616_IN1_IN2,
329 RT5616_BST_SFT2, 8, 0, bst_tlv),
330 /* INL/INR Volume Control */
331 SOC_DOUBLE_TLV("IN Capture Volume", RT5616_INL1_INR1_VOL,
332 RT5616_INL_VOL_SFT, RT5616_INR_VOL_SFT,
333 31, 1, in_vol_tlv),
334 /* ADC Digital Volume Control */
335 SOC_DOUBLE("ADC Capture Switch", RT5616_ADC_DIG_VOL,
336 RT5616_L_MUTE_SFT, RT5616_R_MUTE_SFT, 1, 1),
337 SOC_DOUBLE_TLV("ADC Capture Volume", RT5616_ADC_DIG_VOL,
338 RT5616_L_VOL_SFT, RT5616_R_VOL_SFT,
339 127, 0, adc_vol_tlv),
340
341 /* ADC Boost Volume Control */
342 SOC_DOUBLE_TLV("ADC Boost Volume", RT5616_ADC_BST_VOL,
343 RT5616_ADC_L_BST_SFT, RT5616_ADC_R_BST_SFT,
344 3, 0, adc_bst_tlv),
345};
346
347static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
348 struct snd_soc_dapm_widget *sink)
349{
350 unsigned int val;
351
352 val = snd_soc_read(snd_soc_dapm_to_codec(source->dapm), RT5616_GLB_CLK);
353 val &= RT5616_SCLK_SRC_MASK;
354 if (val == RT5616_SCLK_SRC_PLL1)
355 return 1;
356 else
357 return 0;
358}
359
360/* Digital Mixer */
361static const struct snd_kcontrol_new rt5616_sto1_adc_l_mix[] = {
362 SOC_DAPM_SINGLE("ADC1 Switch", RT5616_STO1_ADC_MIXER,
363 RT5616_M_STO1_ADC_L1_SFT, 1, 1),
364};
365
366static const struct snd_kcontrol_new rt5616_sto1_adc_r_mix[] = {
367 SOC_DAPM_SINGLE("ADC1 Switch", RT5616_STO1_ADC_MIXER,
368 RT5616_M_STO1_ADC_R1_SFT, 1, 1),
369};
370
371static const struct snd_kcontrol_new rt5616_dac_l_mix[] = {
372 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5616_AD_DA_MIXER,
373 RT5616_M_ADCMIX_L_SFT, 1, 1),
374 SOC_DAPM_SINGLE("INF1 Switch", RT5616_AD_DA_MIXER,
375 RT5616_M_IF1_DAC_L_SFT, 1, 1),
376};
377
378static const struct snd_kcontrol_new rt5616_dac_r_mix[] = {
379 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5616_AD_DA_MIXER,
380 RT5616_M_ADCMIX_R_SFT, 1, 1),
381 SOC_DAPM_SINGLE("INF1 Switch", RT5616_AD_DA_MIXER,
382 RT5616_M_IF1_DAC_R_SFT, 1, 1),
383};
384
385static const struct snd_kcontrol_new rt5616_sto_dac_l_mix[] = {
386 SOC_DAPM_SINGLE("DAC L1 Switch", RT5616_STO_DAC_MIXER,
387 RT5616_M_DAC_L1_MIXL_SFT, 1, 1),
388 SOC_DAPM_SINGLE("DAC R1 Switch", RT5616_STO_DAC_MIXER,
389 RT5616_M_DAC_R1_MIXL_SFT, 1, 1),
390};
391
392static const struct snd_kcontrol_new rt5616_sto_dac_r_mix[] = {
393 SOC_DAPM_SINGLE("DAC R1 Switch", RT5616_STO_DAC_MIXER,
394 RT5616_M_DAC_R1_MIXR_SFT, 1, 1),
395 SOC_DAPM_SINGLE("DAC L1 Switch", RT5616_STO_DAC_MIXER,
396 RT5616_M_DAC_L1_MIXR_SFT, 1, 1),
397};
398
399/* Analog Input Mixer */
400static const struct snd_kcontrol_new rt5616_rec_l_mix[] = {
401 SOC_DAPM_SINGLE("INL1 Switch", RT5616_REC_L2_MIXER,
402 RT5616_M_IN1_L_RM_L_SFT, 1, 1),
403 SOC_DAPM_SINGLE("BST2 Switch", RT5616_REC_L2_MIXER,
404 RT5616_M_BST2_RM_L_SFT, 1, 1),
405 SOC_DAPM_SINGLE("BST1 Switch", RT5616_REC_L2_MIXER,
406 RT5616_M_BST1_RM_L_SFT, 1, 1),
407};
408
409static const struct snd_kcontrol_new rt5616_rec_r_mix[] = {
410 SOC_DAPM_SINGLE("INR1 Switch", RT5616_REC_R2_MIXER,
411 RT5616_M_IN1_R_RM_R_SFT, 1, 1),
412 SOC_DAPM_SINGLE("BST2 Switch", RT5616_REC_R2_MIXER,
413 RT5616_M_BST2_RM_R_SFT, 1, 1),
414 SOC_DAPM_SINGLE("BST1 Switch", RT5616_REC_R2_MIXER,
415 RT5616_M_BST1_RM_R_SFT, 1, 1),
416};
417
418/* Analog Output Mixer */
419
420static const struct snd_kcontrol_new rt5616_out_l_mix[] = {
421 SOC_DAPM_SINGLE("BST1 Switch", RT5616_OUT_L3_MIXER,
422 RT5616_M_BST1_OM_L_SFT, 1, 1),
423 SOC_DAPM_SINGLE("BST2 Switch", RT5616_OUT_L3_MIXER,
424 RT5616_M_BST2_OM_L_SFT, 1, 1),
425 SOC_DAPM_SINGLE("INL1 Switch", RT5616_OUT_L3_MIXER,
426 RT5616_M_IN1_L_OM_L_SFT, 1, 1),
427 SOC_DAPM_SINGLE("REC MIXL Switch", RT5616_OUT_L3_MIXER,
428 RT5616_M_RM_L_OM_L_SFT, 1, 1),
429 SOC_DAPM_SINGLE("DAC L1 Switch", RT5616_OUT_L3_MIXER,
430 RT5616_M_DAC_L1_OM_L_SFT, 1, 1),
431};
432
433static const struct snd_kcontrol_new rt5616_out_r_mix[] = {
434 SOC_DAPM_SINGLE("BST2 Switch", RT5616_OUT_R3_MIXER,
435 RT5616_M_BST2_OM_R_SFT, 1, 1),
436 SOC_DAPM_SINGLE("BST1 Switch", RT5616_OUT_R3_MIXER,
437 RT5616_M_BST1_OM_R_SFT, 1, 1),
438 SOC_DAPM_SINGLE("INR1 Switch", RT5616_OUT_R3_MIXER,
439 RT5616_M_IN1_R_OM_R_SFT, 1, 1),
440 SOC_DAPM_SINGLE("REC MIXR Switch", RT5616_OUT_R3_MIXER,
441 RT5616_M_RM_R_OM_R_SFT, 1, 1),
442 SOC_DAPM_SINGLE("DAC R1 Switch", RT5616_OUT_R3_MIXER,
443 RT5616_M_DAC_R1_OM_R_SFT, 1, 1),
444};
445
446static const struct snd_kcontrol_new rt5616_hpo_mix[] = {
447 SOC_DAPM_SINGLE("DAC1 Switch", RT5616_HPO_MIXER,
448 RT5616_M_DAC1_HM_SFT, 1, 1),
449 SOC_DAPM_SINGLE("HPVOL Switch", RT5616_HPO_MIXER,
450 RT5616_M_HPVOL_HM_SFT, 1, 1),
451};
452
453static const struct snd_kcontrol_new rt5616_lout_mix[] = {
454 SOC_DAPM_SINGLE("DAC L1 Switch", RT5616_LOUT_MIXER,
455 RT5616_M_DAC_L1_LM_SFT, 1, 1),
456 SOC_DAPM_SINGLE("DAC R1 Switch", RT5616_LOUT_MIXER,
457 RT5616_M_DAC_R1_LM_SFT, 1, 1),
458 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5616_LOUT_MIXER,
459 RT5616_M_OV_L_LM_SFT, 1, 1),
460 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5616_LOUT_MIXER,
461 RT5616_M_OV_R_LM_SFT, 1, 1),
462};
463
464static int rt5616_adc_event(struct snd_soc_dapm_widget *w,
465 struct snd_kcontrol *kcontrol, int event)
466{
467 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
468
469 switch (event) {
470 case SND_SOC_DAPM_POST_PMU:
471 snd_soc_update_bits(codec, RT5616_ADC_DIG_VOL,
472 RT5616_L_MUTE | RT5616_R_MUTE, 0);
473 break;
474
475 case SND_SOC_DAPM_POST_PMD:
476 snd_soc_update_bits(codec, RT5616_ADC_DIG_VOL,
477 RT5616_L_MUTE | RT5616_R_MUTE,
478 RT5616_L_MUTE | RT5616_R_MUTE);
479 break;
480
481 default:
482 return 0;
483 }
484
485 return 0;
486}
487
488static int rt5616_charge_pump_event(struct snd_soc_dapm_widget *w,
489 struct snd_kcontrol *kcontrol, int event)
490{
491 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
492
493 switch (event) {
494 case SND_SOC_DAPM_POST_PMU:
495 /* depop parameters */
496 snd_soc_update_bits(codec, RT5616_DEPOP_M2,
497 RT5616_DEPOP_MASK, RT5616_DEPOP_MAN);
498 snd_soc_update_bits(codec, RT5616_DEPOP_M1,
499 RT5616_HP_CP_MASK | RT5616_HP_SG_MASK |
500 RT5616_HP_CB_MASK, RT5616_HP_CP_PU |
501 RT5616_HP_SG_DIS | RT5616_HP_CB_PU);
502 snd_soc_write(codec, RT5616_PR_BASE +
503 RT5616_HP_DCC_INT1, 0x9f00);
504 /* headphone amp power on */
505 snd_soc_update_bits(codec, RT5616_PWR_ANLG1,
506 RT5616_PWR_FV1 | RT5616_PWR_FV2, 0);
507 snd_soc_update_bits(codec, RT5616_PWR_VOL,
508 RT5616_PWR_HV_L | RT5616_PWR_HV_R,
509 RT5616_PWR_HV_L | RT5616_PWR_HV_R);
510 snd_soc_update_bits(codec, RT5616_PWR_ANLG1,
511 RT5616_PWR_HP_L | RT5616_PWR_HP_R |
512 RT5616_PWR_HA, RT5616_PWR_HP_L |
513 RT5616_PWR_HP_R | RT5616_PWR_HA);
514 msleep(50);
515 snd_soc_update_bits(codec, RT5616_PWR_ANLG1,
516 RT5616_PWR_FV1 | RT5616_PWR_FV2,
517 RT5616_PWR_FV1 | RT5616_PWR_FV2);
518
519 snd_soc_update_bits(codec, RT5616_CHARGE_PUMP,
520 RT5616_PM_HP_MASK, RT5616_PM_HP_HV);
521 snd_soc_update_bits(codec, RT5616_PR_BASE +
522 RT5616_CHOP_DAC_ADC, 0x0200, 0x0200);
523 snd_soc_update_bits(codec, RT5616_DEPOP_M1,
524 RT5616_HP_CO_MASK | RT5616_HP_SG_MASK,
525 RT5616_HP_CO_EN | RT5616_HP_SG_EN);
526 break;
527 case SND_SOC_DAPM_PRE_PMD:
528 snd_soc_update_bits(codec, RT5616_PR_BASE +
529 RT5616_CHOP_DAC_ADC, 0x0200, 0x0);
530 snd_soc_update_bits(codec, RT5616_DEPOP_M1,
531 RT5616_HP_SG_MASK | RT5616_HP_L_SMT_MASK |
532 RT5616_HP_R_SMT_MASK, RT5616_HP_SG_DIS |
533 RT5616_HP_L_SMT_DIS | RT5616_HP_R_SMT_DIS);
534 /* headphone amp power down */
535 snd_soc_update_bits(codec, RT5616_DEPOP_M1,
536 RT5616_SMT_TRIG_MASK | RT5616_HP_CD_PD_MASK |
537 RT5616_HP_CO_MASK | RT5616_HP_CP_MASK |
538 RT5616_HP_SG_MASK | RT5616_HP_CB_MASK,
539 RT5616_SMT_TRIG_DIS | RT5616_HP_CD_PD_EN |
540 RT5616_HP_CO_DIS | RT5616_HP_CP_PD |
541 RT5616_HP_SG_EN | RT5616_HP_CB_PD);
542 snd_soc_update_bits(codec, RT5616_PWR_ANLG1,
543 RT5616_PWR_HP_L | RT5616_PWR_HP_R |
544 RT5616_PWR_HA, 0);
545 break;
546 default:
547 return 0;
548 }
549
550 return 0;
551}
552
553static int rt5616_hp_event(struct snd_soc_dapm_widget *w,
554 struct snd_kcontrol *kcontrol, int event)
555{
556 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
557
558 switch (event) {
559 case SND_SOC_DAPM_POST_PMU:
560 /* headphone unmute sequence */
561 snd_soc_update_bits(codec, RT5616_DEPOP_M3,
562 RT5616_CP_FQ1_MASK | RT5616_CP_FQ2_MASK |
563 RT5616_CP_FQ3_MASK,
564 (RT5616_CP_FQ_192_KHZ << RT5616_CP_FQ1_SFT) |
565 (RT5616_CP_FQ_12_KHZ << RT5616_CP_FQ2_SFT) |
566 (RT5616_CP_FQ_192_KHZ << RT5616_CP_FQ3_SFT));
567 snd_soc_write(codec, RT5616_PR_BASE +
568 RT5616_MAMP_INT_REG2, 0xfc00);
569 snd_soc_update_bits(codec, RT5616_DEPOP_M1,
570 RT5616_SMT_TRIG_MASK, RT5616_SMT_TRIG_EN);
571 snd_soc_update_bits(codec, RT5616_DEPOP_M1,
572 RT5616_RSTN_MASK, RT5616_RSTN_EN);
573 snd_soc_update_bits(codec, RT5616_DEPOP_M1,
574 RT5616_RSTN_MASK | RT5616_HP_L_SMT_MASK |
575 RT5616_HP_R_SMT_MASK, RT5616_RSTN_DIS |
576 RT5616_HP_L_SMT_EN | RT5616_HP_R_SMT_EN);
577 snd_soc_update_bits(codec, RT5616_HP_VOL,
578 RT5616_L_MUTE | RT5616_R_MUTE, 0);
579 msleep(100);
580 snd_soc_update_bits(codec, RT5616_DEPOP_M1,
581 RT5616_HP_SG_MASK | RT5616_HP_L_SMT_MASK |
582 RT5616_HP_R_SMT_MASK, RT5616_HP_SG_DIS |
583 RT5616_HP_L_SMT_DIS | RT5616_HP_R_SMT_DIS);
584 msleep(20);
585 snd_soc_update_bits(codec, RT5616_HP_CALIB_AMP_DET,
586 RT5616_HPD_PS_MASK, RT5616_HPD_PS_EN);
587 break;
588
589 case SND_SOC_DAPM_PRE_PMD:
590 /* headphone mute sequence */
591 snd_soc_update_bits(codec, RT5616_DEPOP_M3,
592 RT5616_CP_FQ1_MASK | RT5616_CP_FQ2_MASK |
593 RT5616_CP_FQ3_MASK,
594 (RT5616_CP_FQ_96_KHZ << RT5616_CP_FQ1_SFT) |
595 (RT5616_CP_FQ_12_KHZ << RT5616_CP_FQ2_SFT) |
596 (RT5616_CP_FQ_96_KHZ << RT5616_CP_FQ3_SFT));
597 snd_soc_write(codec, RT5616_PR_BASE +
598 RT5616_MAMP_INT_REG2, 0xfc00);
599 snd_soc_update_bits(codec, RT5616_DEPOP_M1,
600 RT5616_HP_SG_MASK, RT5616_HP_SG_EN);
601 snd_soc_update_bits(codec, RT5616_DEPOP_M1,
602 RT5616_RSTP_MASK, RT5616_RSTP_EN);
603 snd_soc_update_bits(codec, RT5616_DEPOP_M1,
604 RT5616_RSTP_MASK | RT5616_HP_L_SMT_MASK |
605 RT5616_HP_R_SMT_MASK, RT5616_RSTP_DIS |
606 RT5616_HP_L_SMT_EN | RT5616_HP_R_SMT_EN);
607 snd_soc_update_bits(codec, RT5616_HP_CALIB_AMP_DET,
608 RT5616_HPD_PS_MASK, RT5616_HPD_PS_DIS);
609 msleep(90);
610 snd_soc_update_bits(codec, RT5616_HP_VOL,
611 RT5616_L_MUTE | RT5616_R_MUTE,
612 RT5616_L_MUTE | RT5616_R_MUTE);
613 msleep(30);
614 break;
615
616 default:
617 return 0;
618 }
619
620 return 0;
621}
622
623static int rt5616_lout_event(struct snd_soc_dapm_widget *w,
624 struct snd_kcontrol *kcontrol, int event)
625{
626 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
627
628 switch (event) {
629 case SND_SOC_DAPM_POST_PMU:
630 snd_soc_update_bits(codec, RT5616_PWR_ANLG1,
631 RT5616_PWR_LM, RT5616_PWR_LM);
632 snd_soc_update_bits(codec, RT5616_LOUT_CTRL1,
633 RT5616_L_MUTE | RT5616_R_MUTE, 0);
634 break;
635
636 case SND_SOC_DAPM_PRE_PMD:
637 snd_soc_update_bits(codec, RT5616_LOUT_CTRL1,
638 RT5616_L_MUTE | RT5616_R_MUTE,
639 RT5616_L_MUTE | RT5616_R_MUTE);
640 snd_soc_update_bits(codec, RT5616_PWR_ANLG1,
641 RT5616_PWR_LM, 0);
642 break;
643
644 default:
645 return 0;
646 }
647
648 return 0;
649}
650
651static int rt5616_bst1_event(struct snd_soc_dapm_widget *w,
652 struct snd_kcontrol *kcontrol, int event)
653{
654 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
655
656 switch (event) {
657 case SND_SOC_DAPM_POST_PMU:
658 snd_soc_update_bits(codec, RT5616_PWR_ANLG2,
659 RT5616_PWR_BST1_OP2, RT5616_PWR_BST1_OP2);
660 break;
661
662 case SND_SOC_DAPM_PRE_PMD:
663 snd_soc_update_bits(codec, RT5616_PWR_ANLG2,
664 RT5616_PWR_BST1_OP2, 0);
665 break;
666
667 default:
668 return 0;
669 }
670
671 return 0;
672}
673
674static int rt5616_bst2_event(struct snd_soc_dapm_widget *w,
675 struct snd_kcontrol *kcontrol, int event)
676{
677 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
678
679 switch (event) {
680 case SND_SOC_DAPM_POST_PMU:
681 snd_soc_update_bits(codec, RT5616_PWR_ANLG2,
682 RT5616_PWR_BST2_OP2, RT5616_PWR_BST2_OP2);
683 break;
684
685 case SND_SOC_DAPM_PRE_PMD:
686 snd_soc_update_bits(codec, RT5616_PWR_ANLG2,
687 RT5616_PWR_BST2_OP2, 0);
688 break;
689
690 default:
691 return 0;
692 }
693
694 return 0;
695}
696
697static const struct snd_soc_dapm_widget rt5616_dapm_widgets[] = {
698 SND_SOC_DAPM_SUPPLY("PLL1", RT5616_PWR_ANLG2,
699 RT5616_PWR_PLL_BIT, 0, NULL, 0),
700 /* Input Side */
701 /* micbias */
702 SND_SOC_DAPM_SUPPLY("LDO", RT5616_PWR_ANLG1,
703 RT5616_PWR_LDO_BIT, 0, NULL, 0),
704 SND_SOC_DAPM_SUPPLY("micbias1", RT5616_PWR_ANLG2,
705 RT5616_PWR_MB1_BIT, 0, NULL, 0),
706
707 /* Input Lines */
708 SND_SOC_DAPM_INPUT("MIC1"),
709 SND_SOC_DAPM_INPUT("MIC2"),
710
711 SND_SOC_DAPM_INPUT("IN1P"),
712 SND_SOC_DAPM_INPUT("IN2P"),
713 SND_SOC_DAPM_INPUT("IN2N"),
714
715 /* Boost */
716 SND_SOC_DAPM_PGA_E("BST1", RT5616_PWR_ANLG2,
717 RT5616_PWR_BST1_BIT, 0, NULL, 0, rt5616_bst1_event,
718 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
719 SND_SOC_DAPM_PGA_E("BST2", RT5616_PWR_ANLG2,
720 RT5616_PWR_BST2_BIT, 0, NULL, 0, rt5616_bst2_event,
721 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
722 /* Input Volume */
723 SND_SOC_DAPM_PGA("INL1 VOL", RT5616_PWR_VOL,
724 RT5616_PWR_IN1_L_BIT, 0, NULL, 0),
725 SND_SOC_DAPM_PGA("INR1 VOL", RT5616_PWR_VOL,
726 RT5616_PWR_IN1_R_BIT, 0, NULL, 0),
727 SND_SOC_DAPM_PGA("INL2 VOL", RT5616_PWR_VOL,
728 RT5616_PWR_IN2_L_BIT, 0, NULL, 0),
729 SND_SOC_DAPM_PGA("INR2 VOL", RT5616_PWR_VOL,
730 RT5616_PWR_IN2_R_BIT, 0, NULL, 0),
731
732 /* REC Mixer */
733 SND_SOC_DAPM_MIXER("RECMIXL", RT5616_PWR_MIXER, RT5616_PWR_RM_L_BIT, 0,
734 rt5616_rec_l_mix, ARRAY_SIZE(rt5616_rec_l_mix)),
735 SND_SOC_DAPM_MIXER("RECMIXR", RT5616_PWR_MIXER, RT5616_PWR_RM_R_BIT, 0,
736 rt5616_rec_r_mix, ARRAY_SIZE(rt5616_rec_r_mix)),
737 /* ADCs */
738 SND_SOC_DAPM_ADC_E("ADC L", NULL, RT5616_PWR_DIG1,
739 RT5616_PWR_ADC_L_BIT, 0, rt5616_adc_event,
740 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
741 SND_SOC_DAPM_ADC_E("ADC R", NULL, RT5616_PWR_DIG1,
742 RT5616_PWR_ADC_R_BIT, 0, rt5616_adc_event,
743 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
744
745 /* ADC Mixer */
746 SND_SOC_DAPM_SUPPLY("stereo1 filter", RT5616_PWR_DIG2,
747 RT5616_PWR_ADC_STO1_F_BIT, 0, NULL, 0),
748 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0,
749 rt5616_sto1_adc_l_mix, ARRAY_SIZE(rt5616_sto1_adc_l_mix)),
750 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0,
751 rt5616_sto1_adc_r_mix, ARRAY_SIZE(rt5616_sto1_adc_r_mix)),
752
753 /* Digital Interface */
754 SND_SOC_DAPM_SUPPLY("I2S1", RT5616_PWR_DIG1,
755 RT5616_PWR_I2S1_BIT, 0, NULL, 0),
756 SND_SOC_DAPM_PGA("IF1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
757 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
758 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
759 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
760
761 /* Digital Interface Select */
762
763 /* Audio Interface */
764 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
765 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
766
767 /* Audio DSP */
768 SND_SOC_DAPM_PGA("Audio DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
769
770 /* Output Side */
771 /* DAC mixer before sound effect */
772 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
773 rt5616_dac_l_mix, ARRAY_SIZE(rt5616_dac_l_mix)),
774 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
775 rt5616_dac_r_mix, ARRAY_SIZE(rt5616_dac_r_mix)),
776
777 SND_SOC_DAPM_SUPPLY("Stero1 DAC Power", RT5616_PWR_DIG2,
778 RT5616_PWR_DAC_STO1_F_BIT, 0, NULL, 0),
779
780 /* DAC Mixer */
781 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
782 rt5616_sto_dac_l_mix, ARRAY_SIZE(rt5616_sto_dac_l_mix)),
783 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
784 rt5616_sto_dac_r_mix, ARRAY_SIZE(rt5616_sto_dac_r_mix)),
785
786 /* DACs */
787 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5616_PWR_DIG1,
788 RT5616_PWR_DAC_L1_BIT, 0),
789 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5616_PWR_DIG1,
790 RT5616_PWR_DAC_R1_BIT, 0),
791 /* OUT Mixer */
792 SND_SOC_DAPM_MIXER("OUT MIXL", RT5616_PWR_MIXER, RT5616_PWR_OM_L_BIT,
793 0, rt5616_out_l_mix, ARRAY_SIZE(rt5616_out_l_mix)),
794 SND_SOC_DAPM_MIXER("OUT MIXR", RT5616_PWR_MIXER, RT5616_PWR_OM_R_BIT,
795 0, rt5616_out_r_mix, ARRAY_SIZE(rt5616_out_r_mix)),
796 /* Output Volume */
797 SND_SOC_DAPM_PGA("OUTVOL L", RT5616_PWR_VOL,
798 RT5616_PWR_OV_L_BIT, 0, NULL, 0),
799 SND_SOC_DAPM_PGA("OUTVOL R", RT5616_PWR_VOL,
800 RT5616_PWR_OV_R_BIT, 0, NULL, 0),
801 SND_SOC_DAPM_PGA("HPOVOL L", RT5616_PWR_VOL,
802 RT5616_PWR_HV_L_BIT, 0, NULL, 0),
803 SND_SOC_DAPM_PGA("HPOVOL R", RT5616_PWR_VOL,
804 RT5616_PWR_HV_R_BIT, 0, NULL, 0),
805 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM,
806 0, 0, NULL, 0),
807 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM,
808 0, 0, NULL, 0),
809 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM,
810 0, 0, NULL, 0),
811 SND_SOC_DAPM_PGA("INL1", RT5616_PWR_VOL,
812 RT5616_PWR_IN1_L_BIT, 0, NULL, 0),
813 SND_SOC_DAPM_PGA("INR1", RT5616_PWR_VOL,
814 RT5616_PWR_IN1_R_BIT, 0, NULL, 0),
815 SND_SOC_DAPM_PGA("INL2", RT5616_PWR_VOL,
816 RT5616_PWR_IN2_L_BIT, 0, NULL, 0),
817 SND_SOC_DAPM_PGA("INR2", RT5616_PWR_VOL,
818 RT5616_PWR_IN2_R_BIT, 0, NULL, 0),
819 /* HPO/LOUT/Mono Mixer */
820 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0,
821 rt5616_hpo_mix, ARRAY_SIZE(rt5616_hpo_mix)),
822 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0,
823 rt5616_lout_mix, ARRAY_SIZE(rt5616_lout_mix)),
824
825 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0,
826 rt5616_hp_event, SND_SOC_DAPM_PRE_PMD |
827 SND_SOC_DAPM_POST_PMU),
828 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0,
829 rt5616_lout_event, SND_SOC_DAPM_PRE_PMD |
830 SND_SOC_DAPM_POST_PMU),
831
832 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, SND_SOC_NOPM, 0, 0,
833 rt5616_charge_pump_event, SND_SOC_DAPM_POST_PMU |
834 SND_SOC_DAPM_PRE_PMD),
835
836 /* Output Lines */
837 SND_SOC_DAPM_OUTPUT("HPOL"),
838 SND_SOC_DAPM_OUTPUT("HPOR"),
839 SND_SOC_DAPM_OUTPUT("LOUTL"),
840 SND_SOC_DAPM_OUTPUT("LOUTR"),
841};
842
843static const struct snd_soc_dapm_route rt5616_dapm_routes[] = {
844 {"IN1P", NULL, "LDO"},
845 {"IN2P", NULL, "LDO"},
846
847 {"IN1P", NULL, "MIC1"},
848 {"IN2P", NULL, "MIC2"},
849 {"IN2N", NULL, "MIC2"},
850
851 {"BST1", NULL, "IN1P"},
852 {"BST2", NULL, "IN2P"},
853 {"BST2", NULL, "IN2N"},
854 {"BST1", NULL, "micbias1"},
855 {"BST2", NULL, "micbias1"},
856
857 {"INL1 VOL", NULL, "IN2P"},
858 {"INR1 VOL", NULL, "IN2N"},
859
860 {"RECMIXL", "INL1 Switch", "INL1 VOL"},
861 {"RECMIXL", "BST2 Switch", "BST2"},
862 {"RECMIXL", "BST1 Switch", "BST1"},
863
864 {"RECMIXR", "INR1 Switch", "INR1 VOL"},
865 {"RECMIXR", "BST2 Switch", "BST2"},
866 {"RECMIXR", "BST1 Switch", "BST1"},
867
868 {"ADC L", NULL, "RECMIXL"},
869 {"ADC R", NULL, "RECMIXR"},
870
871 {"Stereo1 ADC MIXL", "ADC1 Switch", "ADC L"},
872 {"Stereo1 ADC MIXL", NULL, "stereo1 filter"},
873 {"stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll},
874
875 {"Stereo1 ADC MIXR", "ADC1 Switch", "ADC R"},
876 {"Stereo1 ADC MIXR", NULL, "stereo1 filter"},
877 {"stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll},
878
879 {"IF1 ADC1", NULL, "Stereo1 ADC MIXL"},
880 {"IF1 ADC1", NULL, "Stereo1 ADC MIXR"},
881 {"IF1 ADC1", NULL, "I2S1"},
882
883 {"AIF1TX", NULL, "IF1 ADC1"},
884
885 {"IF1 DAC", NULL, "AIF1RX"},
886 {"IF1 DAC", NULL, "I2S1"},
887
888 {"IF1 DAC1 L", NULL, "IF1 DAC"},
889 {"IF1 DAC1 R", NULL, "IF1 DAC"},
890
891 {"DAC MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
892 {"DAC MIXL", "INF1 Switch", "IF1 DAC1 L"},
893 {"DAC MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
894 {"DAC MIXR", "INF1 Switch", "IF1 DAC1 R"},
895
896 {"Audio DSP", NULL, "DAC MIXL"},
897 {"Audio DSP", NULL, "DAC MIXR"},
898
899 {"Stereo DAC MIXL", "DAC L1 Switch", "Audio DSP"},
900 {"Stereo DAC MIXL", "DAC R1 Switch", "DAC MIXR"},
901 {"Stereo DAC MIXL", NULL, "Stero1 DAC Power"},
902 {"Stereo DAC MIXR", "DAC R1 Switch", "Audio DSP"},
903 {"Stereo DAC MIXR", "DAC L1 Switch", "DAC MIXL"},
904 {"Stereo DAC MIXR", NULL, "Stero1 DAC Power"},
905
906 {"DAC L1", NULL, "Stereo DAC MIXL"},
907 {"DAC L1", NULL, "PLL1", is_sys_clk_from_pll},
908 {"DAC R1", NULL, "Stereo DAC MIXR"},
909 {"DAC R1", NULL, "PLL1", is_sys_clk_from_pll},
910
911 {"OUT MIXL", "BST1 Switch", "BST1"},
912 {"OUT MIXL", "BST2 Switch", "BST2"},
913 {"OUT MIXL", "INL1 Switch", "INL1 VOL"},
914 {"OUT MIXL", "REC MIXL Switch", "RECMIXL"},
915 {"OUT MIXL", "DAC L1 Switch", "DAC L1"},
916
917 {"OUT MIXR", "BST2 Switch", "BST2"},
918 {"OUT MIXR", "BST1 Switch", "BST1"},
919 {"OUT MIXR", "INR1 Switch", "INR1 VOL"},
920 {"OUT MIXR", "REC MIXR Switch", "RECMIXR"},
921 {"OUT MIXR", "DAC R1 Switch", "DAC R1"},
922
923 {"HPOVOL L", NULL, "OUT MIXL"},
924 {"HPOVOL R", NULL, "OUT MIXR"},
925 {"OUTVOL L", NULL, "OUT MIXL"},
926 {"OUTVOL R", NULL, "OUT MIXR"},
927
928 {"DAC 1", NULL, "DAC L1"},
929 {"DAC 1", NULL, "DAC R1"},
930 {"HPOVOL", NULL, "HPOVOL L"},
931 {"HPOVOL", NULL, "HPOVOL R"},
932 {"HPO MIX", "DAC1 Switch", "DAC 1"},
933 {"HPO MIX", "HPVOL Switch", "HPOVOL"},
934
935 {"LOUT MIX", "DAC L1 Switch", "DAC L1"},
936 {"LOUT MIX", "DAC R1 Switch", "DAC R1"},
937 {"LOUT MIX", "OUTVOL L Switch", "OUTVOL L"},
938 {"LOUT MIX", "OUTVOL R Switch", "OUTVOL R"},
939
940 {"HP amp", NULL, "HPO MIX"},
941 {"HP amp", NULL, "Charge Pump"},
942 {"HPOL", NULL, "HP amp"},
943 {"HPOR", NULL, "HP amp"},
944
945 {"LOUT amp", NULL, "LOUT MIX"},
946 {"LOUT amp", NULL, "Charge Pump"},
947 {"LOUTL", NULL, "LOUT amp"},
948 {"LOUTR", NULL, "LOUT amp"},
949
950};
951
952static int rt5616_hw_params(struct snd_pcm_substream *substream,
953 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
954{
955 struct snd_soc_pcm_runtime *rtd = substream->private_data;
956 struct snd_soc_codec *codec = rtd->codec;
957 struct rt5616_priv *rt5616 = snd_soc_codec_get_drvdata(codec);
958 unsigned int val_len = 0, val_clk, mask_clk;
959 int pre_div, bclk_ms, frame_size;
960
961 rt5616->lrck[dai->id] = params_rate(params);
962
963 pre_div = rl6231_get_clk_info(rt5616->sysclk, rt5616->lrck[dai->id]);
964
965 if (pre_div < 0) {
966 dev_err(codec->dev, "Unsupported clock setting\n");
967 return -EINVAL;
968 }
969 frame_size = snd_soc_params_to_frame_size(params);
970 if (frame_size < 0) {
971 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
972 return -EINVAL;
973 }
974 bclk_ms = frame_size > 32 ? 1 : 0;
975 rt5616->bclk[dai->id] = rt5616->lrck[dai->id] * (32 << bclk_ms);
976
977 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
978 rt5616->bclk[dai->id], rt5616->lrck[dai->id]);
979 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
980 bclk_ms, pre_div, dai->id);
981
982 switch (params_format(params)) {
983 case SNDRV_PCM_FORMAT_S16_LE:
984 break;
985 case SNDRV_PCM_FORMAT_S20_3LE:
986 val_len |= RT5616_I2S_DL_20;
987 break;
988 case SNDRV_PCM_FORMAT_S24_LE:
989 val_len |= RT5616_I2S_DL_24;
990 break;
991 case SNDRV_PCM_FORMAT_S8:
992 val_len |= RT5616_I2S_DL_8;
993 break;
994 default:
995 return -EINVAL;
996 }
997
998 mask_clk = RT5616_I2S_PD1_MASK;
999 val_clk = pre_div << RT5616_I2S_PD1_SFT;
1000 snd_soc_update_bits(codec, RT5616_I2S1_SDP,
1001 RT5616_I2S_DL_MASK, val_len);
1002 snd_soc_update_bits(codec, RT5616_ADDA_CLK1, mask_clk, val_clk);
1003
1004
1005 return 0;
1006}
1007
1008static int rt5616_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1009{
1010 struct snd_soc_codec *codec = dai->codec;
1011 struct rt5616_priv *rt5616 = snd_soc_codec_get_drvdata(codec);
1012 unsigned int reg_val = 0;
1013
1014 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1015 case SND_SOC_DAIFMT_CBM_CFM:
1016 rt5616->master[dai->id] = 1;
1017 break;
1018 case SND_SOC_DAIFMT_CBS_CFS:
1019 reg_val |= RT5616_I2S_MS_S;
1020 rt5616->master[dai->id] = 0;
1021 break;
1022 default:
1023 return -EINVAL;
1024 }
1025
1026 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1027 case SND_SOC_DAIFMT_NB_NF:
1028 break;
1029 case SND_SOC_DAIFMT_IB_NF:
1030 reg_val |= RT5616_I2S_BP_INV;
1031 break;
1032 default:
1033 return -EINVAL;
1034 }
1035
1036 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1037 case SND_SOC_DAIFMT_I2S:
1038 break;
1039 case SND_SOC_DAIFMT_LEFT_J:
1040 reg_val |= RT5616_I2S_DF_LEFT;
1041 break;
1042 case SND_SOC_DAIFMT_DSP_A:
1043 reg_val |= RT5616_I2S_DF_PCM_A;
1044 break;
1045 case SND_SOC_DAIFMT_DSP_B:
1046 reg_val |= RT5616_I2S_DF_PCM_B;
1047 break;
1048 default:
1049 return -EINVAL;
1050 }
1051
1052 snd_soc_update_bits(codec, RT5616_I2S1_SDP,
1053 RT5616_I2S_MS_MASK | RT5616_I2S_BP_MASK |
1054 RT5616_I2S_DF_MASK, reg_val);
1055
1056
1057 return 0;
1058}
1059
1060static int rt5616_set_dai_sysclk(struct snd_soc_dai *dai,
1061 int clk_id, unsigned int freq, int dir)
1062{
1063 struct snd_soc_codec *codec = dai->codec;
1064 struct rt5616_priv *rt5616 = snd_soc_codec_get_drvdata(codec);
1065 unsigned int reg_val = 0;
1066
1067 if (freq == rt5616->sysclk && clk_id == rt5616->sysclk_src)
1068 return 0;
1069
1070 switch (clk_id) {
1071 case RT5616_SCLK_S_MCLK:
1072 reg_val |= RT5616_SCLK_SRC_MCLK;
1073 break;
1074 case RT5616_SCLK_S_PLL1:
1075 reg_val |= RT5616_SCLK_SRC_PLL1;
1076 break;
1077 default:
1078 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
1079 return -EINVAL;
1080 }
1081 snd_soc_update_bits(codec, RT5616_GLB_CLK,
1082 RT5616_SCLK_SRC_MASK, reg_val);
1083 rt5616->sysclk = freq;
1084 rt5616->sysclk_src = clk_id;
1085
1086 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
1087
1088 return 0;
1089}
1090
1091static int rt5616_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
1092 unsigned int freq_in, unsigned int freq_out)
1093{
1094 struct snd_soc_codec *codec = dai->codec;
1095 struct rt5616_priv *rt5616 = snd_soc_codec_get_drvdata(codec);
1096 struct rl6231_pll_code pll_code;
1097 int ret;
1098
1099 if (source == rt5616->pll_src && freq_in == rt5616->pll_in &&
1100 freq_out == rt5616->pll_out)
1101 return 0;
1102
1103 if (!freq_in || !freq_out) {
1104 dev_dbg(codec->dev, "PLL disabled\n");
1105
1106 rt5616->pll_in = 0;
1107 rt5616->pll_out = 0;
1108 snd_soc_update_bits(codec, RT5616_GLB_CLK,
1109 RT5616_SCLK_SRC_MASK, RT5616_SCLK_SRC_MCLK);
1110 return 0;
1111 }
1112
1113 switch (source) {
1114 case RT5616_PLL1_S_MCLK:
1115 snd_soc_update_bits(codec, RT5616_GLB_CLK,
1116 RT5616_PLL1_SRC_MASK, RT5616_PLL1_SRC_MCLK);
1117 break;
1118 case RT5616_PLL1_S_BCLK1:
1119 case RT5616_PLL1_S_BCLK2:
1120 snd_soc_update_bits(codec, RT5616_GLB_CLK,
1121 RT5616_PLL1_SRC_MASK, RT5616_PLL1_SRC_BCLK1);
1122 break;
1123 default:
1124 dev_err(codec->dev, "Unknown PLL source %d\n", source);
1125 return -EINVAL;
1126 }
1127
1128 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1129 if (ret < 0) {
1130 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
1131 return ret;
1132 }
1133
1134 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
1135 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
1136 pll_code.n_code, pll_code.k_code);
1137
1138 snd_soc_write(codec, RT5616_PLL_CTRL1,
1139 pll_code.n_code << RT5616_PLL_N_SFT | pll_code.k_code);
1140 snd_soc_write(codec, RT5616_PLL_CTRL2,
1141 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5616_PLL_M_SFT |
1142 pll_code.m_bp << RT5616_PLL_M_BP_SFT);
1143
1144 rt5616->pll_in = freq_in;
1145 rt5616->pll_out = freq_out;
1146 rt5616->pll_src = source;
1147
1148 return 0;
1149}
1150
1151static int rt5616_set_bias_level(struct snd_soc_codec *codec,
1152 enum snd_soc_bias_level level)
1153{
1154 switch (level) {
1155 case SND_SOC_BIAS_STANDBY:
1156 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
1157 snd_soc_update_bits(codec, RT5616_PWR_ANLG1,
1158 RT5616_PWR_VREF1 | RT5616_PWR_MB |
1159 RT5616_PWR_BG | RT5616_PWR_VREF2,
1160 RT5616_PWR_VREF1 | RT5616_PWR_MB |
1161 RT5616_PWR_BG | RT5616_PWR_VREF2);
1162 mdelay(10);
1163 snd_soc_update_bits(codec, RT5616_PWR_ANLG1,
1164 RT5616_PWR_FV1 | RT5616_PWR_FV2,
1165 RT5616_PWR_FV1 | RT5616_PWR_FV2);
1166 snd_soc_update_bits(codec, RT5616_D_MISC,
1167 RT5616_D_GATE_EN, RT5616_D_GATE_EN);
1168 }
1169 break;
1170
1171 case SND_SOC_BIAS_OFF:
1172 snd_soc_update_bits(codec, RT5616_D_MISC, RT5616_D_GATE_EN, 0);
1173 snd_soc_write(codec, RT5616_PWR_DIG1, 0x0000);
1174 snd_soc_write(codec, RT5616_PWR_DIG2, 0x0000);
1175 snd_soc_write(codec, RT5616_PWR_VOL, 0x0000);
1176 snd_soc_write(codec, RT5616_PWR_MIXER, 0x0000);
1177 snd_soc_write(codec, RT5616_PWR_ANLG1, 0x0000);
1178 snd_soc_write(codec, RT5616_PWR_ANLG2, 0x0000);
1179 break;
1180
1181 default:
1182 break;
1183 }
1184
1185 return 0;
1186}
1187
1188static int rt5616_probe(struct snd_soc_codec *codec)
1189{
1190 struct rt5616_priv *rt5616 = snd_soc_codec_get_drvdata(codec);
1191
1192 rt5616->codec = codec;
1193
1194 return 0;
1195}
1196
1197#ifdef CONFIG_PM
1198static int rt5616_suspend(struct snd_soc_codec *codec)
1199{
1200 struct rt5616_priv *rt5616 = snd_soc_codec_get_drvdata(codec);
1201
1202 regcache_cache_only(rt5616->regmap, true);
1203 regcache_mark_dirty(rt5616->regmap);
1204
1205 return 0;
1206}
1207
1208static int rt5616_resume(struct snd_soc_codec *codec)
1209{
1210 struct rt5616_priv *rt5616 = snd_soc_codec_get_drvdata(codec);
1211
1212 regcache_cache_only(rt5616->regmap, false);
1213 regcache_sync(rt5616->regmap);
1214 return 0;
1215}
1216#else
1217#define rt5616_suspend NULL
1218#define rt5616_resume NULL
1219#endif
1220
1221#define RT5616_STEREO_RATES SNDRV_PCM_RATE_8000_96000
1222#define RT5616_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1223 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1224
1225
1226struct snd_soc_dai_ops rt5616_aif_dai_ops = {
1227 .hw_params = rt5616_hw_params,
1228 .set_fmt = rt5616_set_dai_fmt,
1229 .set_sysclk = rt5616_set_dai_sysclk,
1230 .set_pll = rt5616_set_dai_pll,
1231};
1232
1233struct snd_soc_dai_driver rt5616_dai[] = {
1234 {
1235 .name = "rt5616-aif1",
1236 .id = RT5616_AIF1,
1237 .playback = {
1238 .stream_name = "AIF1 Playback",
1239 .channels_min = 1,
1240 .channels_max = 2,
1241 .rates = RT5616_STEREO_RATES,
1242 .formats = RT5616_FORMATS,
1243 },
1244 .capture = {
1245 .stream_name = "AIF1 Capture",
1246 .channels_min = 1,
1247 .channels_max = 2,
1248 .rates = RT5616_STEREO_RATES,
1249 .formats = RT5616_FORMATS,
1250 },
1251 .ops = &rt5616_aif_dai_ops,
1252 },
1253};
1254
1255static struct snd_soc_codec_driver soc_codec_dev_rt5616 = {
1256 .probe = rt5616_probe,
1257 .suspend = rt5616_suspend,
1258 .resume = rt5616_resume,
1259 .set_bias_level = rt5616_set_bias_level,
1260 .idle_bias_off = true,
1261 .controls = rt5616_snd_controls,
1262 .num_controls = ARRAY_SIZE(rt5616_snd_controls),
1263 .dapm_widgets = rt5616_dapm_widgets,
1264 .num_dapm_widgets = ARRAY_SIZE(rt5616_dapm_widgets),
1265 .dapm_routes = rt5616_dapm_routes,
1266 .num_dapm_routes = ARRAY_SIZE(rt5616_dapm_routes),
1267};
1268
1269static const struct regmap_config rt5616_regmap = {
1270 .reg_bits = 8,
1271 .val_bits = 16,
1272 .use_single_rw = true,
1273 .max_register = RT5616_DEVICE_ID + 1 + (ARRAY_SIZE(rt5616_ranges) *
1274 RT5616_PR_SPACING),
1275 .volatile_reg = rt5616_volatile_register,
1276 .readable_reg = rt5616_readable_register,
1277 .cache_type = REGCACHE_RBTREE,
1278 .reg_defaults = rt5616_reg,
1279 .num_reg_defaults = ARRAY_SIZE(rt5616_reg),
1280 .ranges = rt5616_ranges,
1281 .num_ranges = ARRAY_SIZE(rt5616_ranges),
1282};
1283
1284static const struct i2c_device_id rt5616_i2c_id[] = {
1285 { "rt5616", 0 },
1286 { }
1287};
1288MODULE_DEVICE_TABLE(i2c, rt5616_i2c_id);
1289
1290#if defined(CONFIG_OF)
1291static const struct of_device_id rt5616_of_match[] = {
1292 { .compatible = "realtek,rt5616", },
1293 {},
1294};
1295MODULE_DEVICE_TABLE(of, rt5616_of_match);
1296#endif
1297
1298static int rt5616_i2c_probe(struct i2c_client *i2c,
1299 const struct i2c_device_id *id)
1300{
1301 struct rt5616_priv *rt5616;
1302 unsigned int val;
1303 int ret;
1304
1305 rt5616 = devm_kzalloc(&i2c->dev, sizeof(struct rt5616_priv),
1306 GFP_KERNEL);
1307 if (rt5616 == NULL)
1308 return -ENOMEM;
1309
1310 i2c_set_clientdata(i2c, rt5616);
1311
1312 rt5616->regmap = devm_regmap_init_i2c(i2c, &rt5616_regmap);
1313 if (IS_ERR(rt5616->regmap)) {
1314 ret = PTR_ERR(rt5616->regmap);
1315 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1316 ret);
1317 return ret;
1318 }
1319
1320 regmap_read(rt5616->regmap, RT5616_DEVICE_ID, &val);
1321 if (val != 0x6281) {
1322 dev_err(&i2c->dev,
1323 "Device with ID register %#x is not rt5616\n",
1324 val);
1325 return -ENODEV;
1326 }
1327 regmap_write(rt5616->regmap, RT5616_RESET, 0);
1328 regmap_update_bits(rt5616->regmap, RT5616_PWR_ANLG1,
1329 RT5616_PWR_VREF1 | RT5616_PWR_MB |
1330 RT5616_PWR_BG | RT5616_PWR_VREF2,
1331 RT5616_PWR_VREF1 | RT5616_PWR_MB |
1332 RT5616_PWR_BG | RT5616_PWR_VREF2);
1333 mdelay(10);
1334 regmap_update_bits(rt5616->regmap, RT5616_PWR_ANLG1,
1335 RT5616_PWR_FV1 | RT5616_PWR_FV2,
1336 RT5616_PWR_FV1 | RT5616_PWR_FV2);
1337
1338 ret = regmap_register_patch(rt5616->regmap, init_list,
1339 ARRAY_SIZE(init_list));
1340 if (ret != 0)
1341 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
1342
1343 regmap_update_bits(rt5616->regmap, RT5616_PWR_ANLG1,
1344 RT5616_PWR_LDO_DVO_MASK, RT5616_PWR_LDO_DVO_1_2V);
1345
1346 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5616,
1347 rt5616_dai, ARRAY_SIZE(rt5616_dai));
1348
1349}
1350
1351static int rt5616_i2c_remove(struct i2c_client *i2c)
1352{
1353 snd_soc_unregister_codec(&i2c->dev);
1354
1355 return 0;
1356}
1357
1358static void rt5616_i2c_shutdown(struct i2c_client *client)
1359{
1360 struct rt5616_priv *rt5616 = i2c_get_clientdata(client);
1361
1362 regmap_write(rt5616->regmap, RT5616_HP_VOL, 0xc8c8);
1363 regmap_write(rt5616->regmap, RT5616_LOUT_CTRL1, 0xc8c8);
1364
1365}
1366
1367static struct i2c_driver rt5616_i2c_driver = {
1368 .driver = {
1369 .name = "rt5616",
1370 .of_match_table = of_match_ptr(rt5616_of_match),
1371 },
1372 .probe = rt5616_i2c_probe,
1373 .remove = rt5616_i2c_remove,
1374 .shutdown = rt5616_i2c_shutdown,
1375 .id_table = rt5616_i2c_id,
1376};
1377module_i2c_driver(rt5616_i2c_driver);
1378
1379MODULE_DESCRIPTION("ASoC RT5616 driver");
1380MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
1381MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/rt5616.h b/sound/soc/codecs/rt5616.h
new file mode 100644
index 000000000000..f88cdddbc34a
--- /dev/null
+++ b/sound/soc/codecs/rt5616.h
@@ -0,0 +1,1819 @@
1/*
2 * rt5616.h -- RT5616 ALSA SoC audio driver
3 *
4 * Copyright 2011 Realtek Microelectronics
5 * Author: Johnny Hsu <johnnyhsu@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __RT5616_H__
13#define __RT5616_H__
14
15/* Info */
16#define RT5616_RESET 0x00
17#define RT5616_VERSION_ID 0xfd
18#define RT5616_VENDOR_ID 0xfe
19#define RT5616_DEVICE_ID 0xff
20/* I/O - Output */
21#define RT5616_HP_VOL 0x02
22#define RT5616_LOUT_CTRL1 0x03
23#define RT5616_LOUT_CTRL2 0x05
24/* I/O - Input */
25#define RT5616_IN1_IN2 0x0d
26#define RT5616_INL1_INR1_VOL 0x0f
27/* I/O - ADC/DAC/DMIC */
28#define RT5616_DAC1_DIG_VOL 0x19
29#define RT5616_ADC_DIG_VOL 0x1c
30#define RT5616_ADC_BST_VOL 0x1e
31/* Mixer - D-D */
32#define RT5616_STO1_ADC_MIXER 0x27
33#define RT5616_AD_DA_MIXER 0x29
34#define RT5616_STO_DAC_MIXER 0x2a
35
36/* Mixer - ADC */
37#define RT5616_REC_L1_MIXER 0x3b
38#define RT5616_REC_L2_MIXER 0x3c
39#define RT5616_REC_R1_MIXER 0x3d
40#define RT5616_REC_R2_MIXER 0x3e
41/* Mixer - DAC */
42#define RT5616_HPO_MIXER 0x45
43#define RT5616_OUT_L1_MIXER 0x4d
44#define RT5616_OUT_L2_MIXER 0x4e
45#define RT5616_OUT_L3_MIXER 0x4f
46#define RT5616_OUT_R1_MIXER 0x50
47#define RT5616_OUT_R2_MIXER 0x51
48#define RT5616_OUT_R3_MIXER 0x52
49#define RT5616_LOUT_MIXER 0x53
50/* Power */
51#define RT5616_PWR_DIG1 0x61
52#define RT5616_PWR_DIG2 0x62
53#define RT5616_PWR_ANLG1 0x63
54#define RT5616_PWR_ANLG2 0x64
55#define RT5616_PWR_MIXER 0x65
56#define RT5616_PWR_VOL 0x66
57/* Private Register Control */
58#define RT5616_PRIV_INDEX 0x6a
59#define RT5616_PRIV_DATA 0x6c
60/* Format - ADC/DAC */
61#define RT5616_I2S1_SDP 0x70
62#define RT5616_ADDA_CLK1 0x73
63#define RT5616_ADDA_CLK2 0x74
64
65/* Function - Analog */
66#define RT5616_GLB_CLK 0x80
67#define RT5616_PLL_CTRL1 0x81
68#define RT5616_PLL_CTRL2 0x82
69#define RT5616_HP_OVCD 0x8b
70#define RT5616_DEPOP_M1 0x8e
71#define RT5616_DEPOP_M2 0x8f
72#define RT5616_DEPOP_M3 0x90
73#define RT5616_CHARGE_PUMP 0x91
74#define RT5616_PV_DET_SPK_G 0x92
75#define RT5616_MICBIAS 0x93
76#define RT5616_A_JD_CTL1 0x94
77#define RT5616_A_JD_CTL2 0x95
78/* Function - Digital */
79#define RT5616_EQ_CTRL1 0xb0
80#define RT5616_EQ_CTRL2 0xb1
81#define RT5616_WIND_FILTER 0xb2
82#define RT5616_DRC_AGC_1 0xb4
83#define RT5616_DRC_AGC_2 0xb5
84#define RT5616_DRC_AGC_3 0xb6
85#define RT5616_SVOL_ZC 0xb7
86#define RT5616_JD_CTRL1 0xbb
87#define RT5616_JD_CTRL2 0xbc
88#define RT5616_IRQ_CTRL1 0xbd
89#define RT5616_IRQ_CTRL2 0xbe
90#define RT5616_INT_IRQ_ST 0xbf
91#define RT5616_GPIO_CTRL1 0xc0
92#define RT5616_GPIO_CTRL2 0xc1
93#define RT5616_GPIO_CTRL3 0xc2
94#define RT5616_PGM_REG_ARR1 0xc8
95#define RT5616_PGM_REG_ARR2 0xc9
96#define RT5616_PGM_REG_ARR3 0xca
97#define RT5616_PGM_REG_ARR4 0xcb
98#define RT5616_PGM_REG_ARR5 0xcc
99#define RT5616_SCB_FUNC 0xcd
100#define RT5616_SCB_CTRL 0xce
101#define RT5616_BASE_BACK 0xcf
102#define RT5616_MP3_PLUS1 0xd0
103#define RT5616_MP3_PLUS2 0xd1
104#define RT5616_ADJ_HPF_CTRL1 0xd3
105#define RT5616_ADJ_HPF_CTRL2 0xd4
106#define RT5616_HP_CALIB_AMP_DET 0xd6
107#define RT5616_HP_CALIB2 0xd7
108#define RT5616_SV_ZCD1 0xd9
109#define RT5616_SV_ZCD2 0xda
110#define RT5616_D_MISC 0xfa
111/* Dummy Register */
112#define RT5616_DUMMY2 0xfb
113#define RT5616_DUMMY3 0xfc
114
115
116/* Index of Codec Private Register definition */
117#define RT5616_BIAS_CUR1 0x12
118#define RT5616_BIAS_CUR3 0x14
119#define RT5616_CLSD_INT_REG1 0x1c
120#define RT5616_MAMP_INT_REG2 0x37
121#define RT5616_CHOP_DAC_ADC 0x3d
122#define RT5616_3D_SPK 0x63
123#define RT5616_WND_1 0x6c
124#define RT5616_WND_2 0x6d
125#define RT5616_WND_3 0x6e
126#define RT5616_WND_4 0x6f
127#define RT5616_WND_5 0x70
128#define RT5616_WND_8 0x73
129#define RT5616_DIP_SPK_INF 0x75
130#define RT5616_HP_DCC_INT1 0x77
131#define RT5616_EQ_BW_LOP 0xa0
132#define RT5616_EQ_GN_LOP 0xa1
133#define RT5616_EQ_FC_BP1 0xa2
134#define RT5616_EQ_BW_BP1 0xa3
135#define RT5616_EQ_GN_BP1 0xa4
136#define RT5616_EQ_FC_BP2 0xa5
137#define RT5616_EQ_BW_BP2 0xa6
138#define RT5616_EQ_GN_BP2 0xa7
139#define RT5616_EQ_FC_BP3 0xa8
140#define RT5616_EQ_BW_BP3 0xa9
141#define RT5616_EQ_GN_BP3 0xaa
142#define RT5616_EQ_FC_BP4 0xab
143#define RT5616_EQ_BW_BP4 0xac
144#define RT5616_EQ_GN_BP4 0xad
145#define RT5616_EQ_FC_HIP1 0xae
146#define RT5616_EQ_GN_HIP1 0xaf
147#define RT5616_EQ_FC_HIP2 0xb0
148#define RT5616_EQ_BW_HIP2 0xb1
149#define RT5616_EQ_GN_HIP2 0xb2
150#define RT5616_EQ_PRE_VOL 0xb3
151#define RT5616_EQ_PST_VOL 0xb4
152
153
154/* global definition */
155#define RT5616_L_MUTE (0x1 << 15)
156#define RT5616_L_MUTE_SFT 15
157#define RT5616_VOL_L_MUTE (0x1 << 14)
158#define RT5616_VOL_L_SFT 14
159#define RT5616_R_MUTE (0x1 << 7)
160#define RT5616_R_MUTE_SFT 7
161#define RT5616_VOL_R_MUTE (0x1 << 6)
162#define RT5616_VOL_R_SFT 6
163#define RT5616_L_VOL_MASK (0x3f << 8)
164#define RT5616_L_VOL_SFT 8
165#define RT5616_R_VOL_MASK (0x3f)
166#define RT5616_R_VOL_SFT 0
167
168/* LOUT Control 2(0x05) */
169#define RT5616_EN_DFO (0x1 << 15)
170
171/* IN1 and IN2 Control (0x0d) */
172/* IN3 and IN4 Control (0x0e) */
173#define RT5616_BST_MASK1 (0xf<<12)
174#define RT5616_BST_SFT1 12
175#define RT5616_BST_MASK2 (0xf<<8)
176#define RT5616_BST_SFT2 8
177#define RT5616_IN_DF1 (0x1 << 7)
178#define RT5616_IN_SFT1 7
179#define RT5616_IN_DF2 (0x1 << 6)
180#define RT5616_IN_SFT2 6
181
182/* INL1 and INR1 Volume Control (0x0f) */
183#define RT5616_INL_VOL_MASK (0x1f << 8)
184#define RT5616_INL_VOL_SFT 8
185#define RT5616_INR_SEL_MASK (0x1 << 7)
186#define RT5616_INR_SEL_SFT 7
187#define RT5616_INR_SEL_IN4N (0x0 << 7)
188#define RT5616_INR_SEL_MONON (0x1 << 7)
189#define RT5616_INR_VOL_MASK (0x1f)
190#define RT5616_INR_VOL_SFT 0
191
192/* DAC1 Digital Volume (0x19) */
193#define RT5616_DAC_L1_VOL_MASK (0xff << 8)
194#define RT5616_DAC_L1_VOL_SFT 8
195#define RT5616_DAC_R1_VOL_MASK (0xff)
196#define RT5616_DAC_R1_VOL_SFT 0
197
198/* DAC2 Digital Volume (0x1a) */
199#define RT5616_DAC_L2_VOL_MASK (0xff << 8)
200#define RT5616_DAC_L2_VOL_SFT 8
201#define RT5616_DAC_R2_VOL_MASK (0xff)
202#define RT5616_DAC_R2_VOL_SFT 0
203
204/* ADC Digital Volume Control (0x1c) */
205#define RT5616_ADC_L_VOL_MASK (0x7f << 8)
206#define RT5616_ADC_L_VOL_SFT 8
207#define RT5616_ADC_R_VOL_MASK (0x7f)
208#define RT5616_ADC_R_VOL_SFT 0
209
210/* Mono ADC Digital Volume Control (0x1d) */
211#define RT5616_M_MONO_ADC_L (0x1 << 15)
212#define RT5616_M_MONO_ADC_L_SFT 15
213#define RT5616_MONO_ADC_L_VOL_MASK (0x7f << 8)
214#define RT5616_MONO_ADC_L_VOL_SFT 8
215#define RT5616_M_MONO_ADC_R (0x1 << 7)
216#define RT5616_M_MONO_ADC_R_SFT 7
217#define RT5616_MONO_ADC_R_VOL_MASK (0x7f)
218#define RT5616_MONO_ADC_R_VOL_SFT 0
219
220/* ADC Boost Volume Control (0x1e) */
221#define RT5616_ADC_L_BST_MASK (0x3 << 14)
222#define RT5616_ADC_L_BST_SFT 14
223#define RT5616_ADC_R_BST_MASK (0x3 << 12)
224#define RT5616_ADC_R_BST_SFT 12
225#define RT5616_ADC_COMP_MASK (0x3 << 10)
226#define RT5616_ADC_COMP_SFT 10
227
228/* Stereo ADC1 Mixer Control (0x27) */
229#define RT5616_M_STO1_ADC_L1 (0x1 << 14)
230#define RT5616_M_STO1_ADC_L1_SFT 14
231#define RT5616_M_STO1_ADC_R1 (0x1 << 6)
232#define RT5616_M_STO1_ADC_R1_SFT 6
233
234/* ADC Mixer to DAC Mixer Control (0x29) */
235#define RT5616_M_ADCMIX_L (0x1 << 15)
236#define RT5616_M_ADCMIX_L_SFT 15
237#define RT5616_M_IF1_DAC_L (0x1 << 14)
238#define RT5616_M_IF1_DAC_L_SFT 14
239#define RT5616_M_ADCMIX_R (0x1 << 7)
240#define RT5616_M_ADCMIX_R_SFT 7
241#define RT5616_M_IF1_DAC_R (0x1 << 6)
242#define RT5616_M_IF1_DAC_R_SFT 6
243
244/* Stereo DAC Mixer Control (0x2a) */
245#define RT5616_M_DAC_L1_MIXL (0x1 << 14)
246#define RT5616_M_DAC_L1_MIXL_SFT 14
247#define RT5616_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
248#define RT5616_DAC_L1_STO_L_VOL_SFT 13
249#define RT5616_M_DAC_R1_MIXL (0x1 << 9)
250#define RT5616_M_DAC_R1_MIXL_SFT 9
251#define RT5616_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
252#define RT5616_DAC_R1_STO_L_VOL_SFT 8
253#define RT5616_M_DAC_R1_MIXR (0x1 << 6)
254#define RT5616_M_DAC_R1_MIXR_SFT 6
255#define RT5616_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
256#define RT5616_DAC_R1_STO_R_VOL_SFT 5
257#define RT5616_M_DAC_L1_MIXR (0x1 << 1)
258#define RT5616_M_DAC_L1_MIXR_SFT 1
259#define RT5616_DAC_L1_STO_R_VOL_MASK (0x1)
260#define RT5616_DAC_L1_STO_R_VOL_SFT 0
261
262/* DD Mixer Control (0x2b) */
263#define RT5616_M_STO_DD_L1 (0x1 << 14)
264#define RT5616_M_STO_DD_L1_SFT 14
265#define RT5616_STO_DD_L1_VOL_MASK (0x1 << 13)
266#define RT5616_DAC_DD_L1_VOL_SFT 13
267#define RT5616_M_STO_DD_L2 (0x1 << 12)
268#define RT5616_M_STO_DD_L2_SFT 12
269#define RT5616_STO_DD_L2_VOL_MASK (0x1 << 11)
270#define RT5616_STO_DD_L2_VOL_SFT 11
271#define RT5616_M_STO_DD_R2_L (0x1 << 10)
272#define RT5616_M_STO_DD_R2_L_SFT 10
273#define RT5616_STO_DD_R2_L_VOL_MASK (0x1 << 9)
274#define RT5616_STO_DD_R2_L_VOL_SFT 9
275#define RT5616_M_STO_DD_R1 (0x1 << 6)
276#define RT5616_M_STO_DD_R1_SFT 6
277#define RT5616_STO_DD_R1_VOL_MASK (0x1 << 5)
278#define RT5616_STO_DD_R1_VOL_SFT 5
279#define RT5616_M_STO_DD_R2 (0x1 << 4)
280#define RT5616_M_STO_DD_R2_SFT 4
281#define RT5616_STO_DD_R2_VOL_MASK (0x1 << 3)
282#define RT5616_STO_DD_R2_VOL_SFT 3
283#define RT5616_M_STO_DD_L2_R (0x1 << 2)
284#define RT5616_M_STO_DD_L2_R_SFT 2
285#define RT5616_STO_DD_L2_R_VOL_MASK (0x1 << 1)
286#define RT5616_STO_DD_L2_R_VOL_SFT 1
287
288/* Digital Mixer Control (0x2c) */
289#define RT5616_M_STO_L_DAC_L (0x1 << 15)
290#define RT5616_M_STO_L_DAC_L_SFT 15
291#define RT5616_STO_L_DAC_L_VOL_MASK (0x1 << 14)
292#define RT5616_STO_L_DAC_L_VOL_SFT 14
293#define RT5616_M_DAC_L2_DAC_L (0x1 << 13)
294#define RT5616_M_DAC_L2_DAC_L_SFT 13
295#define RT5616_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
296#define RT5616_DAC_L2_DAC_L_VOL_SFT 12
297#define RT5616_M_STO_R_DAC_R (0x1 << 11)
298#define RT5616_M_STO_R_DAC_R_SFT 11
299#define RT5616_STO_R_DAC_R_VOL_MASK (0x1 << 10)
300#define RT5616_STO_R_DAC_R_VOL_SFT 10
301#define RT5616_M_DAC_R2_DAC_R (0x1 << 9)
302#define RT5616_M_DAC_R2_DAC_R_SFT 9
303#define RT5616_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
304#define RT5616_DAC_R2_DAC_R_VOL_SFT 8
305
306/* DSP Path Control 1 (0x2d) */
307#define RT5616_RXDP_SRC_MASK (0x1 << 15)
308#define RT5616_RXDP_SRC_SFT 15
309#define RT5616_RXDP_SRC_NOR (0x0 << 15)
310#define RT5616_RXDP_SRC_DIV3 (0x1 << 15)
311#define RT5616_TXDP_SRC_MASK (0x1 << 14)
312#define RT5616_TXDP_SRC_SFT 14
313#define RT5616_TXDP_SRC_NOR (0x0 << 14)
314#define RT5616_TXDP_SRC_DIV3 (0x1 << 14)
315
316/* DSP Path Control 2 (0x2e) */
317#define RT5616_DAC_L2_SEL_MASK (0x3 << 14)
318#define RT5616_DAC_L2_SEL_SFT 14
319#define RT5616_DAC_L2_SEL_IF2 (0x0 << 14)
320#define RT5616_DAC_L2_SEL_IF3 (0x1 << 14)
321#define RT5616_DAC_L2_SEL_TXDC (0x2 << 14)
322#define RT5616_DAC_L2_SEL_BASS (0x3 << 14)
323#define RT5616_DAC_R2_SEL_MASK (0x3 << 12)
324#define RT5616_DAC_R2_SEL_SFT 12
325#define RT5616_DAC_R2_SEL_IF2 (0x0 << 12)
326#define RT5616_DAC_R2_SEL_IF3 (0x1 << 12)
327#define RT5616_DAC_R2_SEL_TXDC (0x2 << 12)
328#define RT5616_IF2_ADC_L_SEL_MASK (0x1 << 11)
329#define RT5616_IF2_ADC_L_SEL_SFT 11
330#define RT5616_IF2_ADC_L_SEL_TXDP (0x0 << 11)
331#define RT5616_IF2_ADC_L_SEL_PASS (0x1 << 11)
332#define RT5616_IF2_ADC_R_SEL_MASK (0x1 << 10)
333#define RT5616_IF2_ADC_R_SEL_SFT 10
334#define RT5616_IF2_ADC_R_SEL_TXDP (0x0 << 10)
335#define RT5616_IF2_ADC_R_SEL_PASS (0x1 << 10)
336#define RT5616_RXDC_SEL_MASK (0x3 << 8)
337#define RT5616_RXDC_SEL_SFT 8
338#define RT5616_RXDC_SEL_NOR (0x0 << 8)
339#define RT5616_RXDC_SEL_L2R (0x1 << 8)
340#define RT5616_RXDC_SEL_R2L (0x2 << 8)
341#define RT5616_RXDC_SEL_SWAP (0x3 << 8)
342#define RT5616_RXDP_SEL_MASK (0x3 << 6)
343#define RT5616_RXDP_SEL_SFT 6
344#define RT5616_RXDP_SEL_NOR (0x0 << 6)
345#define RT5616_RXDP_SEL_L2R (0x1 << 6)
346#define RT5616_RXDP_SEL_R2L (0x2 << 6)
347#define RT5616_RXDP_SEL_SWAP (0x3 << 6)
348#define RT5616_TXDC_SEL_MASK (0x3 << 4)
349#define RT5616_TXDC_SEL_SFT 4
350#define RT5616_TXDC_SEL_NOR (0x0 << 4)
351#define RT5616_TXDC_SEL_L2R (0x1 << 4)
352#define RT5616_TXDC_SEL_R2L (0x2 << 4)
353#define RT5616_TXDC_SEL_SWAP (0x3 << 4)
354#define RT5616_TXDP_SEL_MASK (0x3 << 2)
355#define RT5616_TXDP_SEL_SFT 2
356#define RT5616_TXDP_SEL_NOR (0x0 << 2)
357#define RT5616_TXDP_SEL_L2R (0x1 << 2)
358#define RT5616_TXDP_SEL_R2L (0x2 << 2)
359#define RT5616_TRXDP_SEL_SWAP (0x3 << 2)
360
361/* REC Left Mixer Control 1 (0x3b) */
362#define RT5616_G_LN_L2_RM_L_MASK (0x7 << 13)
363#define RT5616_G_IN_L2_RM_L_SFT 13
364#define RT5616_G_LN_L1_RM_L_MASK (0x7 << 10)
365#define RT5616_G_IN_L1_RM_L_SFT 10
366#define RT5616_G_BST3_RM_L_MASK (0x7 << 4)
367#define RT5616_G_BST3_RM_L_SFT 4
368#define RT5616_G_BST2_RM_L_MASK (0x7 << 1)
369#define RT5616_G_BST2_RM_L_SFT 1
370
371/* REC Left Mixer Control 2 (0x3c) */
372#define RT5616_G_BST1_RM_L_MASK (0x7 << 13)
373#define RT5616_G_BST1_RM_L_SFT 13
374#define RT5616_G_OM_L_RM_L_MASK (0x7 << 10)
375#define RT5616_G_OM_L_RM_L_SFT 10
376#define RT5616_M_IN2_L_RM_L (0x1 << 6)
377#define RT5616_M_IN2_L_RM_L_SFT 6
378#define RT5616_M_IN1_L_RM_L (0x1 << 5)
379#define RT5616_M_IN1_L_RM_L_SFT 5
380#define RT5616_M_BST3_RM_L (0x1 << 3)
381#define RT5616_M_BST3_RM_L_SFT 3
382#define RT5616_M_BST2_RM_L (0x1 << 2)
383#define RT5616_M_BST2_RM_L_SFT 2
384#define RT5616_M_BST1_RM_L (0x1 << 1)
385#define RT5616_M_BST1_RM_L_SFT 1
386#define RT5616_M_OM_L_RM_L (0x1)
387#define RT5616_M_OM_L_RM_L_SFT 0
388
389/* REC Right Mixer Control 1 (0x3d) */
390#define RT5616_G_IN2_R_RM_R_MASK (0x7 << 13)
391#define RT5616_G_IN2_R_RM_R_SFT 13
392#define RT5616_G_IN1_R_RM_R_MASK (0x7 << 10)
393#define RT5616_G_IN1_R_RM_R_SFT 10
394#define RT5616_G_BST3_RM_R_MASK (0x7 << 4)
395#define RT5616_G_BST3_RM_R_SFT 4
396#define RT5616_G_BST2_RM_R_MASK (0x7 << 1)
397#define RT5616_G_BST2_RM_R_SFT 1
398
399/* REC Right Mixer Control 2 (0x3e) */
400#define RT5616_G_BST1_RM_R_MASK (0x7 << 13)
401#define RT5616_G_BST1_RM_R_SFT 13
402#define RT5616_G_OM_R_RM_R_MASK (0x7 << 10)
403#define RT5616_G_OM_R_RM_R_SFT 10
404#define RT5616_M_IN2_R_RM_R (0x1 << 6)
405#define RT5616_M_IN2_R_RM_R_SFT 6
406#define RT5616_M_IN1_R_RM_R (0x1 << 5)
407#define RT5616_M_IN1_R_RM_R_SFT 5
408#define RT5616_M_BST3_RM_R (0x1 << 3)
409#define RT5616_M_BST3_RM_R_SFT 3
410#define RT5616_M_BST2_RM_R (0x1 << 2)
411#define RT5616_M_BST2_RM_R_SFT 2
412#define RT5616_M_BST1_RM_R (0x1 << 1)
413#define RT5616_M_BST1_RM_R_SFT 1
414#define RT5616_M_OM_R_RM_R (0x1)
415#define RT5616_M_OM_R_RM_R_SFT 0
416
417/* HPMIX Control (0x45) */
418#define RT5616_M_DAC1_HM (0x1 << 14)
419#define RT5616_M_DAC1_HM_SFT 14
420#define RT5616_M_HPVOL_HM (0x1 << 13)
421#define RT5616_M_HPVOL_HM_SFT 13
422#define RT5616_G_HPOMIX_MASK (0x1 << 12)
423#define RT5616_G_HPOMIX_SFT 12
424
425/* SPK Left Mixer Control (0x46) */
426#define RT5616_G_RM_L_SM_L_MASK (0x3 << 14)
427#define RT5616_G_RM_L_SM_L_SFT 14
428#define RT5616_G_IN_L_SM_L_MASK (0x3 << 12)
429#define RT5616_G_IN_L_SM_L_SFT 12
430#define RT5616_G_DAC_L1_SM_L_MASK (0x3 << 10)
431#define RT5616_G_DAC_L1_SM_L_SFT 10
432#define RT5616_G_DAC_L2_SM_L_MASK (0x3 << 8)
433#define RT5616_G_DAC_L2_SM_L_SFT 8
434#define RT5616_G_OM_L_SM_L_MASK (0x3 << 6)
435#define RT5616_G_OM_L_SM_L_SFT 6
436#define RT5616_M_RM_L_SM_L (0x1 << 5)
437#define RT5616_M_RM_L_SM_L_SFT 5
438#define RT5616_M_IN_L_SM_L (0x1 << 4)
439#define RT5616_M_IN_L_SM_L_SFT 4
440#define RT5616_M_DAC_L1_SM_L (0x1 << 3)
441#define RT5616_M_DAC_L1_SM_L_SFT 3
442#define RT5616_M_DAC_L2_SM_L (0x1 << 2)
443#define RT5616_M_DAC_L2_SM_L_SFT 2
444#define RT5616_M_OM_L_SM_L (0x1 << 1)
445#define RT5616_M_OM_L_SM_L_SFT 1
446
447/* SPK Right Mixer Control (0x47) */
448#define RT5616_G_RM_R_SM_R_MASK (0x3 << 14)
449#define RT5616_G_RM_R_SM_R_SFT 14
450#define RT5616_G_IN_R_SM_R_MASK (0x3 << 12)
451#define RT5616_G_IN_R_SM_R_SFT 12
452#define RT5616_G_DAC_R1_SM_R_MASK (0x3 << 10)
453#define RT5616_G_DAC_R1_SM_R_SFT 10
454#define RT5616_G_DAC_R2_SM_R_MASK (0x3 << 8)
455#define RT5616_G_DAC_R2_SM_R_SFT 8
456#define RT5616_G_OM_R_SM_R_MASK (0x3 << 6)
457#define RT5616_G_OM_R_SM_R_SFT 6
458#define RT5616_M_RM_R_SM_R (0x1 << 5)
459#define RT5616_M_RM_R_SM_R_SFT 5
460#define RT5616_M_IN_R_SM_R (0x1 << 4)
461#define RT5616_M_IN_R_SM_R_SFT 4
462#define RT5616_M_DAC_R1_SM_R (0x1 << 3)
463#define RT5616_M_DAC_R1_SM_R_SFT 3
464#define RT5616_M_DAC_R2_SM_R (0x1 << 2)
465#define RT5616_M_DAC_R2_SM_R_SFT 2
466#define RT5616_M_OM_R_SM_R (0x1 << 1)
467#define RT5616_M_OM_R_SM_R_SFT 1
468
469/* SPOLMIX Control (0x48) */
470#define RT5616_M_DAC_R1_SPM_L (0x1 << 15)
471#define RT5616_M_DAC_R1_SPM_L_SFT 15
472#define RT5616_M_DAC_L1_SPM_L (0x1 << 14)
473#define RT5616_M_DAC_L1_SPM_L_SFT 14
474#define RT5616_M_SV_R_SPM_L (0x1 << 13)
475#define RT5616_M_SV_R_SPM_L_SFT 13
476#define RT5616_M_SV_L_SPM_L (0x1 << 12)
477#define RT5616_M_SV_L_SPM_L_SFT 12
478#define RT5616_M_BST1_SPM_L (0x1 << 11)
479#define RT5616_M_BST1_SPM_L_SFT 11
480
481/* SPORMIX Control (0x49) */
482#define RT5616_M_DAC_R1_SPM_R (0x1 << 13)
483#define RT5616_M_DAC_R1_SPM_R_SFT 13
484#define RT5616_M_SV_R_SPM_R (0x1 << 12)
485#define RT5616_M_SV_R_SPM_R_SFT 12
486#define RT5616_M_BST1_SPM_R (0x1 << 11)
487#define RT5616_M_BST1_SPM_R_SFT 11
488
489/* SPOLMIX / SPORMIX Ratio Control (0x4a) */
490#define RT5616_SPO_CLSD_RATIO_MASK (0x7)
491#define RT5616_SPO_CLSD_RATIO_SFT 0
492
493/* Mono Output Mixer Control (0x4c) */
494#define RT5616_M_DAC_R2_MM (0x1 << 15)
495#define RT5616_M_DAC_R2_MM_SFT 15
496#define RT5616_M_DAC_L2_MM (0x1 << 14)
497#define RT5616_M_DAC_L2_MM_SFT 14
498#define RT5616_M_OV_R_MM (0x1 << 13)
499#define RT5616_M_OV_R_MM_SFT 13
500#define RT5616_M_OV_L_MM (0x1 << 12)
501#define RT5616_M_OV_L_MM_SFT 12
502#define RT5616_M_BST1_MM (0x1 << 11)
503#define RT5616_M_BST1_MM_SFT 11
504#define RT5616_G_MONOMIX_MASK (0x1 << 10)
505#define RT5616_G_MONOMIX_SFT 10
506
507/* Output Left Mixer Control 1 (0x4d) */
508#define RT5616_G_BST2_OM_L_MASK (0x7 << 10)
509#define RT5616_G_BST2_OM_L_SFT 10
510#define RT5616_G_BST1_OM_L_MASK (0x7 << 7)
511#define RT5616_G_BST1_OM_L_SFT 7
512#define RT5616_G_IN1_L_OM_L_MASK (0x7 << 4)
513#define RT5616_G_IN1_L_OM_L_SFT 4
514#define RT5616_G_RM_L_OM_L_MASK (0x7 << 1)
515#define RT5616_G_RM_L_OM_L_SFT 1
516
517/* Output Left Mixer Control 2 (0x4e) */
518#define RT5616_G_DAC_L1_OM_L_MASK (0x7 << 7)
519#define RT5616_G_DAC_L1_OM_L_SFT 7
520#define RT5616_G_IN2_L_OM_L_MASK (0x7 << 4)
521#define RT5616_G_IN2_L_OM_L_SFT 4
522
523/* Output Left Mixer Control 3 (0x4f) */
524#define RT5616_M_IN2_L_OM_L (0x1 << 9)
525#define RT5616_M_IN2_L_OM_L_SFT 9
526#define RT5616_M_BST2_OM_L (0x1 << 6)
527#define RT5616_M_BST2_OM_L_SFT 6
528#define RT5616_M_BST1_OM_L (0x1 << 5)
529#define RT5616_M_BST1_OM_L_SFT 5
530#define RT5616_M_IN1_L_OM_L (0x1 << 4)
531#define RT5616_M_IN1_L_OM_L_SFT 4
532#define RT5616_M_RM_L_OM_L (0x1 << 3)
533#define RT5616_M_RM_L_OM_L_SFT 3
534#define RT5616_M_DAC_L1_OM_L (0x1)
535#define RT5616_M_DAC_L1_OM_L_SFT 0
536
537/* Output Right Mixer Control 1 (0x50) */
538#define RT5616_G_BST2_OM_R_MASK (0x7 << 10)
539#define RT5616_G_BST2_OM_R_SFT 10
540#define RT5616_G_BST1_OM_R_MASK (0x7 << 7)
541#define RT5616_G_BST1_OM_R_SFT 7
542#define RT5616_G_IN1_R_OM_R_MASK (0x7 << 4)
543#define RT5616_G_IN1_R_OM_R_SFT 4
544#define RT5616_G_RM_R_OM_R_MASK (0x7 << 1)
545#define RT5616_G_RM_R_OM_R_SFT 1
546
547/* Output Right Mixer Control 2 (0x51) */
548#define RT5616_G_DAC_R1_OM_R_MASK (0x7 << 7)
549#define RT5616_G_DAC_R1_OM_R_SFT 7
550#define RT5616_G_IN2_R_OM_R_MASK (0x7 << 4)
551#define RT5616_G_IN2_R_OM_R_SFT 4
552
553/* Output Right Mixer Control 3 (0x52) */
554#define RT5616_M_IN2_R_OM_R (0x1 << 9)
555#define RT5616_M_IN2_R_OM_R_SFT 9
556#define RT5616_M_BST2_OM_R (0x1 << 6)
557#define RT5616_M_BST2_OM_R_SFT 6
558#define RT5616_M_BST1_OM_R (0x1 << 5)
559#define RT5616_M_BST1_OM_R_SFT 5
560#define RT5616_M_IN1_R_OM_R (0x1 << 4)
561#define RT5616_M_IN1_R_OM_R_SFT 4
562#define RT5616_M_RM_R_OM_R (0x1 << 3)
563#define RT5616_M_RM_R_OM_R_SFT 3
564#define RT5616_M_DAC_R1_OM_R (0x1)
565#define RT5616_M_DAC_R1_OM_R_SFT 0
566
567/* LOUT Mixer Control (0x53) */
568#define RT5616_M_DAC_L1_LM (0x1 << 15)
569#define RT5616_M_DAC_L1_LM_SFT 15
570#define RT5616_M_DAC_R1_LM (0x1 << 14)
571#define RT5616_M_DAC_R1_LM_SFT 14
572#define RT5616_M_OV_L_LM (0x1 << 13)
573#define RT5616_M_OV_L_LM_SFT 13
574#define RT5616_M_OV_R_LM (0x1 << 12)
575#define RT5616_M_OV_R_LM_SFT 12
576#define RT5616_G_LOUTMIX_MASK (0x1 << 11)
577#define RT5616_G_LOUTMIX_SFT 11
578
579/* Power Management for Digital 1 (0x61) */
580#define RT5616_PWR_I2S1 (0x1 << 15)
581#define RT5616_PWR_I2S1_BIT 15
582#define RT5616_PWR_I2S2 (0x1 << 14)
583#define RT5616_PWR_I2S2_BIT 14
584#define RT5616_PWR_DAC_L1 (0x1 << 12)
585#define RT5616_PWR_DAC_L1_BIT 12
586#define RT5616_PWR_DAC_R1 (0x1 << 11)
587#define RT5616_PWR_DAC_R1_BIT 11
588#define RT5616_PWR_ADC_L (0x1 << 2)
589#define RT5616_PWR_ADC_L_BIT 2
590#define RT5616_PWR_ADC_R (0x1 << 1)
591#define RT5616_PWR_ADC_R_BIT 1
592
593/* Power Management for Digital 2 (0x62) */
594#define RT5616_PWR_ADC_STO1_F (0x1 << 15)
595#define RT5616_PWR_ADC_STO1_F_BIT 15
596#define RT5616_PWR_DAC_STO1_F (0x1 << 11)
597#define RT5616_PWR_DAC_STO1_F_BIT 11
598
599/* Power Management for Analog 1 (0x63) */
600#define RT5616_PWR_VREF1 (0x1 << 15)
601#define RT5616_PWR_VREF1_BIT 15
602#define RT5616_PWR_FV1 (0x1 << 14)
603#define RT5616_PWR_FV1_BIT 14
604#define RT5616_PWR_MB (0x1 << 13)
605#define RT5616_PWR_MB_BIT 13
606#define RT5616_PWR_LM (0x1 << 12)
607#define RT5616_PWR_LM_BIT 12
608#define RT5616_PWR_BG (0x1 << 11)
609#define RT5616_PWR_BG_BIT 11
610#define RT5616_PWR_HP_L (0x1 << 7)
611#define RT5616_PWR_HP_L_BIT 7
612#define RT5616_PWR_HP_R (0x1 << 6)
613#define RT5616_PWR_HP_R_BIT 6
614#define RT5616_PWR_HA (0x1 << 5)
615#define RT5616_PWR_HA_BIT 5
616#define RT5616_PWR_VREF2 (0x1 << 4)
617#define RT5616_PWR_VREF2_BIT 4
618#define RT5616_PWR_FV2 (0x1 << 3)
619#define RT5616_PWR_FV2_BIT 3
620#define RT5616_PWR_LDO (0x1 << 2)
621#define RT5616_PWR_LDO_BIT 2
622#define RT5616_PWR_LDO_DVO_MASK (0x3)
623#define RT5616_PWR_LDO_DVO_1_0V 0
624#define RT5616_PWR_LDO_DVO_1_1V 1
625#define RT5616_PWR_LDO_DVO_1_2V 2
626#define RT5616_PWR_LDO_DVO_1_3V 3
627
628/* Power Management for Analog 2 (0x64) */
629#define RT5616_PWR_BST1 (0x1 << 15)
630#define RT5616_PWR_BST1_BIT 15
631#define RT5616_PWR_BST2 (0x1 << 14)
632#define RT5616_PWR_BST2_BIT 14
633#define RT5616_PWR_MB1 (0x1 << 11)
634#define RT5616_PWR_MB1_BIT 11
635#define RT5616_PWR_PLL (0x1 << 9)
636#define RT5616_PWR_PLL_BIT 9
637#define RT5616_PWR_BST1_OP2 (0x1 << 5)
638#define RT5616_PWR_BST1_OP2_BIT 5
639#define RT5616_PWR_BST2_OP2 (0x1 << 4)
640#define RT5616_PWR_BST2_OP2_BIT 4
641#define RT5616_PWR_BST3_OP2 (0x1 << 3)
642#define RT5616_PWR_BST3_OP2_BIT 3
643#define RT5616_PWR_JD_M (0x1 << 2)
644#define RT5616_PWM_JD_M_BIT 2
645#define RT5616_PWR_JD2 (0x1 << 1)
646#define RT5616_PWM_JD2_BIT 1
647#define RT5616_PWR_JD3 (0x1)
648#define RT5616_PWM_JD3_BIT 0
649
650/* Power Management for Mixer (0x65) */
651#define RT5616_PWR_OM_L (0x1 << 15)
652#define RT5616_PWR_OM_L_BIT 15
653#define RT5616_PWR_OM_R (0x1 << 14)
654#define RT5616_PWR_OM_R_BIT 14
655#define RT5616_PWR_RM_L (0x1 << 11)
656#define RT5616_PWR_RM_L_BIT 11
657#define RT5616_PWR_RM_R (0x1 << 10)
658#define RT5616_PWR_RM_R_BIT 10
659
660/* Power Management for Volume (0x66) */
661#define RT5616_PWR_OV_L (0x1 << 13)
662#define RT5616_PWR_OV_L_BIT 13
663#define RT5616_PWR_OV_R (0x1 << 12)
664#define RT5616_PWR_OV_R_BIT 12
665#define RT5616_PWR_HV_L (0x1 << 11)
666#define RT5616_PWR_HV_L_BIT 11
667#define RT5616_PWR_HV_R (0x1 << 10)
668#define RT5616_PWR_HV_R_BIT 10
669#define RT5616_PWR_IN1_L (0x1 << 9)
670#define RT5616_PWR_IN1_L_BIT 9
671#define RT5616_PWR_IN1_R (0x1 << 8)
672#define RT5616_PWR_IN1_R_BIT 8
673#define RT5616_PWR_IN2_L (0x1 << 7)
674#define RT5616_PWR_IN2_L_BIT 7
675#define RT5616_PWR_IN2_R (0x1 << 6)
676#define RT5616_PWR_IN2_R_BIT 6
677
678/* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71) */
679#define RT5616_I2S_MS_MASK (0x1 << 15)
680#define RT5616_I2S_MS_SFT 15
681#define RT5616_I2S_MS_M (0x0 << 15)
682#define RT5616_I2S_MS_S (0x1 << 15)
683#define RT5616_I2S_O_CP_MASK (0x3 << 10)
684#define RT5616_I2S_O_CP_SFT 10
685#define RT5616_I2S_O_CP_OFF (0x0 << 10)
686#define RT5616_I2S_O_CP_U_LAW (0x1 << 10)
687#define RT5616_I2S_O_CP_A_LAW (0x2 << 10)
688#define RT5616_I2S_I_CP_MASK (0x3 << 8)
689#define RT5616_I2S_I_CP_SFT 8
690#define RT5616_I2S_I_CP_OFF (0x0 << 8)
691#define RT5616_I2S_I_CP_U_LAW (0x1 << 8)
692#define RT5616_I2S_I_CP_A_LAW (0x2 << 8)
693#define RT5616_I2S_BP_MASK (0x1 << 7)
694#define RT5616_I2S_BP_SFT 7
695#define RT5616_I2S_BP_NOR (0x0 << 7)
696#define RT5616_I2S_BP_INV (0x1 << 7)
697#define RT5616_I2S_DL_MASK (0x3 << 2)
698#define RT5616_I2S_DL_SFT 2
699#define RT5616_I2S_DL_16 (0x0 << 2)
700#define RT5616_I2S_DL_20 (0x1 << 2)
701#define RT5616_I2S_DL_24 (0x2 << 2)
702#define RT5616_I2S_DL_8 (0x3 << 2)
703#define RT5616_I2S_DF_MASK (0x3)
704#define RT5616_I2S_DF_SFT 0
705#define RT5616_I2S_DF_I2S (0x0)
706#define RT5616_I2S_DF_LEFT (0x1)
707#define RT5616_I2S_DF_PCM_A (0x2)
708#define RT5616_I2S_DF_PCM_B (0x3)
709
710/* ADC/DAC Clock Control 1 (0x73) */
711#define RT5616_I2S_PD1_MASK (0x7 << 12)
712#define RT5616_I2S_PD1_SFT 12
713#define RT5616_I2S_PD1_1 (0x0 << 12)
714#define RT5616_I2S_PD1_2 (0x1 << 12)
715#define RT5616_I2S_PD1_3 (0x2 << 12)
716#define RT5616_I2S_PD1_4 (0x3 << 12)
717#define RT5616_I2S_PD1_6 (0x4 << 12)
718#define RT5616_I2S_PD1_8 (0x5 << 12)
719#define RT5616_I2S_PD1_12 (0x6 << 12)
720#define RT5616_I2S_PD1_16 (0x7 << 12)
721#define RT5616_I2S_BCLK_MS2_MASK (0x1 << 11)
722#define RT5616_DAC_OSR_MASK (0x3 << 2)
723#define RT5616_DAC_OSR_SFT 2
724#define RT5616_DAC_OSR_128 (0x0 << 2)
725#define RT5616_DAC_OSR_64 (0x1 << 2)
726#define RT5616_DAC_OSR_32 (0x2 << 2)
727#define RT5616_DAC_OSR_128_3 (0x3 << 2)
728#define RT5616_ADC_OSR_MASK (0x3)
729#define RT5616_ADC_OSR_SFT 0
730#define RT5616_ADC_OSR_128 (0x0)
731#define RT5616_ADC_OSR_64 (0x1)
732#define RT5616_ADC_OSR_32 (0x2)
733#define RT5616_ADC_OSR_128_3 (0x3)
734
735/* ADC/DAC Clock Control 2 (0x74) */
736#define RT5616_DAHPF_EN (0x1 << 11)
737#define RT5616_DAHPF_EN_SFT 11
738#define RT5616_ADHPF_EN (0x1 << 10)
739#define RT5616_ADHPF_EN_SFT 10
740
741/* TDM Control 1 (0x77) */
742#define RT5616_TDM_INTEL_SEL_MASK (0x1 << 15)
743#define RT5616_TDM_INTEL_SEL_SFT 15
744#define RT5616_TDM_INTEL_SEL_64 (0x0 << 15)
745#define RT5616_TDM_INTEL_SEL_50 (0x1 << 15)
746#define RT5616_TDM_MODE_SEL_MASK (0x1 << 14)
747#define RT5616_TDM_MODE_SEL_SFT 14
748#define RT5616_TDM_MODE_SEL_NOR (0x0 << 14)
749#define RT5616_TDM_MODE_SEL_TDM (0x1 << 14)
750#define RT5616_TDM_CH_NUM_SEL_MASK (0x3 << 12)
751#define RT5616_TDM_CH_NUM_SEL_SFT 12
752#define RT5616_TDM_CH_NUM_SEL_2 (0x0 << 12)
753#define RT5616_TDM_CH_NUM_SEL_4 (0x1 << 12)
754#define RT5616_TDM_CH_NUM_SEL_6 (0x2 << 12)
755#define RT5616_TDM_CH_NUM_SEL_8 (0x3 << 12)
756#define RT5616_TDM_CH_LEN_SEL_MASK (0x3 << 10)
757#define RT5616_TDM_CH_LEN_SEL_SFT 10
758#define RT5616_TDM_CH_LEN_SEL_16 (0x0 << 10)
759#define RT5616_TDM_CH_LEN_SEL_20 (0x1 << 10)
760#define RT5616_TDM_CH_LEN_SEL_24 (0x2 << 10)
761#define RT5616_TDM_CH_LEN_SEL_32 (0x3 << 10)
762#define RT5616_TDM_ADC_SEL_MASK (0x1 << 9)
763#define RT5616_TDM_ADC_SEL_SFT 9
764#define RT5616_TDM_ADC_SEL_NOR (0x0 << 9)
765#define RT5616_TDM_ADC_SEL_SWAP (0x1 << 9)
766#define RT5616_TDM_ADC_START_SEL_MASK (0x1 << 8)
767#define RT5616_TDM_ADC_START_SEL_SFT 8
768#define RT5616_TDM_ADC_START_SEL_SL0 (0x0 << 8)
769#define RT5616_TDM_ADC_START_SEL_SL4 (0x1 << 8)
770#define RT5616_TDM_I2S_CH2_SEL_MASK (0x3 << 6)
771#define RT5616_TDM_I2S_CH2_SEL_SFT 6
772#define RT5616_TDM_I2S_CH2_SEL_LR (0x0 << 6)
773#define RT5616_TDM_I2S_CH2_SEL_RL (0x1 << 6)
774#define RT5616_TDM_I2S_CH2_SEL_LL (0x2 << 6)
775#define RT5616_TDM_I2S_CH2_SEL_RR (0x3 << 6)
776#define RT5616_TDM_I2S_CH4_SEL_MASK (0x3 << 4)
777#define RT5616_TDM_I2S_CH4_SEL_SFT 4
778#define RT5616_TDM_I2S_CH4_SEL_LR (0x0 << 4)
779#define RT5616_TDM_I2S_CH4_SEL_RL (0x1 << 4)
780#define RT5616_TDM_I2S_CH4_SEL_LL (0x2 << 4)
781#define RT5616_TDM_I2S_CH4_SEL_RR (0x3 << 4)
782#define RT5616_TDM_I2S_CH6_SEL_MASK (0x3 << 2)
783#define RT5616_TDM_I2S_CH6_SEL_SFT 2
784#define RT5616_TDM_I2S_CH6_SEL_LR (0x0 << 2)
785#define RT5616_TDM_I2S_CH6_SEL_RL (0x1 << 2)
786#define RT5616_TDM_I2S_CH6_SEL_LL (0x2 << 2)
787#define RT5616_TDM_I2S_CH6_SEL_RR (0x3 << 2)
788#define RT5616_TDM_I2S_CH8_SEL_MASK (0x3)
789#define RT5616_TDM_I2S_CH8_SEL_SFT 0
790#define RT5616_TDM_I2S_CH8_SEL_LR (0x0)
791#define RT5616_TDM_I2S_CH8_SEL_RL (0x1)
792#define RT5616_TDM_I2S_CH8_SEL_LL (0x2)
793#define RT5616_TDM_I2S_CH8_SEL_RR (0x3)
794
795/* TDM Control 2 (0x78) */
796#define RT5616_TDM_LRCK_POL_SEL_MASK (0x1 << 15)
797#define RT5616_TDM_LRCK_POL_SEL_SFT 15
798#define RT5616_TDM_LRCK_POL_SEL_NOR (0x0 << 15)
799#define RT5616_TDM_LRCK_POL_SEL_INV (0x1 << 15)
800#define RT5616_TDM_CH_VAL_SEL_MASK (0x1 << 14)
801#define RT5616_TDM_CH_VAL_SEL_SFT 14
802#define RT5616_TDM_CH_VAL_SEL_CH01 (0x0 << 14)
803#define RT5616_TDM_CH_VAL_SEL_CH0123 (0x1 << 14)
804#define RT5616_TDM_CH_VAL_EN (0x1 << 13)
805#define RT5616_TDM_CH_VAL_SFT 13
806#define RT5616_TDM_LPBK_EN (0x1 << 12)
807#define RT5616_TDM_LPBK_SFT 12
808#define RT5616_TDM_LRCK_PULSE_SEL_MASK (0x1 << 11)
809#define RT5616_TDM_LRCK_PULSE_SEL_SFT 11
810#define RT5616_TDM_LRCK_PULSE_SEL_BCLK (0x0 << 11)
811#define RT5616_TDM_LRCK_PULSE_SEL_CH (0x1 << 11)
812#define RT5616_TDM_END_EDGE_SEL_MASK (0x1 << 10)
813#define RT5616_TDM_END_EDGE_SEL_SFT 10
814#define RT5616_TDM_END_EDGE_SEL_POS (0x0 << 10)
815#define RT5616_TDM_END_EDGE_SEL_NEG (0x1 << 10)
816#define RT5616_TDM_END_EDGE_EN (0x1 << 9)
817#define RT5616_TDM_END_EDGE_EN_SFT 9
818#define RT5616_TDM_TRAN_EDGE_SEL_MASK (0x1 << 8)
819#define RT5616_TDM_TRAN_EDGE_SEL_SFT 8
820#define RT5616_TDM_TRAN_EDGE_SEL_POS (0x0 << 8)
821#define RT5616_TDM_TRAN_EDGE_SEL_NEG (0x1 << 8)
822#define RT5616_M_TDM2_L (0x1 << 7)
823#define RT5616_M_TDM2_L_SFT 7
824#define RT5616_M_TDM2_R (0x1 << 6)
825#define RT5616_M_TDM2_R_SFT 6
826#define RT5616_M_TDM4_L (0x1 << 5)
827#define RT5616_M_TDM4_L_SFT 5
828#define RT5616_M_TDM4_R (0x1 << 4)
829#define RT5616_M_TDM4_R_SFT 4
830
831/* Global Clock Control (0x80) */
832#define RT5616_SCLK_SRC_MASK (0x3 << 14)
833#define RT5616_SCLK_SRC_SFT 14
834#define RT5616_SCLK_SRC_MCLK (0x0 << 14)
835#define RT5616_SCLK_SRC_PLL1 (0x1 << 14)
836#define RT5616_PLL1_SRC_MASK (0x3 << 12)
837#define RT5616_PLL1_SRC_SFT 12
838#define RT5616_PLL1_SRC_MCLK (0x0 << 12)
839#define RT5616_PLL1_SRC_BCLK1 (0x1 << 12)
840#define RT5616_PLL1_SRC_BCLK2 (0x2 << 12)
841#define RT5616_PLL1_PD_MASK (0x1 << 3)
842#define RT5616_PLL1_PD_SFT 3
843#define RT5616_PLL1_PD_1 (0x0 << 3)
844#define RT5616_PLL1_PD_2 (0x1 << 3)
845
846#define RT5616_PLL_INP_MAX 40000000
847#define RT5616_PLL_INP_MIN 256000
848/* PLL M/N/K Code Control 1 (0x81) */
849#define RT5616_PLL_N_MAX 0x1ff
850#define RT5616_PLL_N_MASK (RT5616_PLL_N_MAX << 7)
851#define RT5616_PLL_N_SFT 7
852#define RT5616_PLL_K_MAX 0x1f
853#define RT5616_PLL_K_MASK (RT5616_PLL_K_MAX)
854#define RT5616_PLL_K_SFT 0
855
856/* PLL M/N/K Code Control 2 (0x82) */
857#define RT5616_PLL_M_MAX 0xf
858#define RT5616_PLL_M_MASK (RT5616_PLL_M_MAX << 12)
859#define RT5616_PLL_M_SFT 12
860#define RT5616_PLL_M_BP (0x1 << 11)
861#define RT5616_PLL_M_BP_SFT 11
862
863/* PLL tracking mode 1 (0x83) */
864#define RT5616_STO1_T_MASK (0x1 << 15)
865#define RT5616_STO1_T_SFT 15
866#define RT5616_STO1_T_SCLK (0x0 << 15)
867#define RT5616_STO1_T_LRCK1 (0x1 << 15)
868#define RT5616_STO2_T_MASK (0x1 << 12)
869#define RT5616_STO2_T_SFT 12
870#define RT5616_STO2_T_I2S2 (0x0 << 12)
871#define RT5616_STO2_T_LRCK2 (0x1 << 12)
872#define RT5616_ASRC2_REF_MASK (0x1 << 11)
873#define RT5616_ASRC2_REF_SFT 11
874#define RT5616_ASRC2_REF_LRCK2 (0x0 << 11)
875#define RT5616_ASRC2_REF_LRCK1 (0x1 << 11)
876#define RT5616_DMIC_1_M_MASK (0x1 << 9)
877#define RT5616_DMIC_1_M_SFT 9
878#define RT5616_DMIC_1_M_NOR (0x0 << 9)
879#define RT5616_DMIC_1_M_ASYN (0x1 << 9)
880
881/* PLL tracking mode 2 (0x84) */
882#define RT5616_STO1_ASRC_EN (0x1 << 15)
883#define RT5616_STO1_ASRC_EN_SFT 15
884#define RT5616_STO2_ASRC_EN (0x1 << 14)
885#define RT5616_STO2_ASRC_EN_SFT 14
886#define RT5616_STO1_DAC_M_MASK (0x1 << 13)
887#define RT5616_STO1_DAC_M_SFT 13
888#define RT5616_STO1_DAC_M_NOR (0x0 << 13)
889#define RT5616_STO1_DAC_M_ASRC (0x1 << 13)
890#define RT5616_STO2_DAC_M_MASK (0x1 << 12)
891#define RT5616_STO2_DAC_M_SFT 12
892#define RT5616_STO2_DAC_M_NOR (0x0 << 12)
893#define RT5616_STO2_DAC_M_ASRC (0x1 << 12)
894#define RT5616_ADC_M_MASK (0x1 << 11)
895#define RT5616_ADC_M_SFT 11
896#define RT5616_ADC_M_NOR (0x0 << 11)
897#define RT5616_ADC_M_ASRC (0x1 << 11)
898#define RT5616_I2S1_R_D_MASK (0x1 << 4)
899#define RT5616_I2S1_R_D_SFT 4
900#define RT5616_I2S1_R_D_DIS (0x0 << 4)
901#define RT5616_I2S1_R_D_EN (0x1 << 4)
902#define RT5616_I2S2_R_D_MASK (0x1 << 3)
903#define RT5616_I2S2_R_D_SFT 3
904#define RT5616_I2S2_R_D_DIS (0x0 << 3)
905#define RT5616_I2S2_R_D_EN (0x1 << 3)
906#define RT5616_PRE_SCLK_MASK (0x3)
907#define RT5616_PRE_SCLK_SFT 0
908#define RT5616_PRE_SCLK_512 (0x0)
909#define RT5616_PRE_SCLK_1024 (0x1)
910#define RT5616_PRE_SCLK_2048 (0x2)
911
912/* PLL tracking mode 3 (0x85) */
913#define RT5616_I2S1_RATE_MASK (0xf << 12)
914#define RT5616_I2S1_RATE_SFT 12
915#define RT5616_I2S2_RATE_MASK (0xf << 8)
916#define RT5616_I2S2_RATE_SFT 8
917#define RT5616_G_ASRC_LP_MASK (0x1 << 3)
918#define RT5616_G_ASRC_LP_SFT 3
919#define RT5616_ASRC_LP_F_M (0x1 << 2)
920#define RT5616_ASRC_LP_F_SFT 2
921#define RT5616_ASRC_LP_F_NOR (0x0 << 2)
922#define RT5616_ASRC_LP_F_SB (0x1 << 2)
923#define RT5616_FTK_PH_DET_MASK (0x3)
924#define RT5616_FTK_PH_DET_SFT 0
925#define RT5616_FTK_PH_DET_DIV1 (0x0)
926#define RT5616_FTK_PH_DET_DIV2 (0x1)
927#define RT5616_FTK_PH_DET_DIV4 (0x2)
928#define RT5616_FTK_PH_DET_DIV8 (0x3)
929
930/*PLL tracking mode 6 (0x89) */
931#define RT5616_I2S1_PD_MASK (0x7 << 12)
932#define RT5616_I2S1_PD_SFT 12
933#define RT5616_I2S2_PD_MASK (0x7 << 8)
934#define RT5616_I2S2_PD_SFT 8
935
936/*PLL tracking mode 7 (0x8a) */
937#define RT5616_FSI1_RATE_MASK (0xf << 12)
938#define RT5616_FSI1_RATE_SFT 12
939#define RT5616_FSI2_RATE_MASK (0xf << 8)
940#define RT5616_FSI2_RATE_SFT 8
941
942/* HPOUT Over Current Detection (0x8b) */
943#define RT5616_HP_OVCD_MASK (0x1 << 10)
944#define RT5616_HP_OVCD_SFT 10
945#define RT5616_HP_OVCD_DIS (0x0 << 10)
946#define RT5616_HP_OVCD_EN (0x1 << 10)
947#define RT5616_HP_OC_TH_MASK (0x3 << 8)
948#define RT5616_HP_OC_TH_SFT 8
949#define RT5616_HP_OC_TH_90 (0x0 << 8)
950#define RT5616_HP_OC_TH_105 (0x1 << 8)
951#define RT5616_HP_OC_TH_120 (0x2 << 8)
952#define RT5616_HP_OC_TH_135 (0x3 << 8)
953
954/* Depop Mode Control 1 (0x8e) */
955#define RT5616_SMT_TRIG_MASK (0x1 << 15)
956#define RT5616_SMT_TRIG_SFT 15
957#define RT5616_SMT_TRIG_DIS (0x0 << 15)
958#define RT5616_SMT_TRIG_EN (0x1 << 15)
959#define RT5616_HP_L_SMT_MASK (0x1 << 9)
960#define RT5616_HP_L_SMT_SFT 9
961#define RT5616_HP_L_SMT_DIS (0x0 << 9)
962#define RT5616_HP_L_SMT_EN (0x1 << 9)
963#define RT5616_HP_R_SMT_MASK (0x1 << 8)
964#define RT5616_HP_R_SMT_SFT 8
965#define RT5616_HP_R_SMT_DIS (0x0 << 8)
966#define RT5616_HP_R_SMT_EN (0x1 << 8)
967#define RT5616_HP_CD_PD_MASK (0x1 << 7)
968#define RT5616_HP_CD_PD_SFT 7
969#define RT5616_HP_CD_PD_DIS (0x0 << 7)
970#define RT5616_HP_CD_PD_EN (0x1 << 7)
971#define RT5616_RSTN_MASK (0x1 << 6)
972#define RT5616_RSTN_SFT 6
973#define RT5616_RSTN_DIS (0x0 << 6)
974#define RT5616_RSTN_EN (0x1 << 6)
975#define RT5616_RSTP_MASK (0x1 << 5)
976#define RT5616_RSTP_SFT 5
977#define RT5616_RSTP_DIS (0x0 << 5)
978#define RT5616_RSTP_EN (0x1 << 5)
979#define RT5616_HP_CO_MASK (0x1 << 4)
980#define RT5616_HP_CO_SFT 4
981#define RT5616_HP_CO_DIS (0x0 << 4)
982#define RT5616_HP_CO_EN (0x1 << 4)
983#define RT5616_HP_CP_MASK (0x1 << 3)
984#define RT5616_HP_CP_SFT 3
985#define RT5616_HP_CP_PD (0x0 << 3)
986#define RT5616_HP_CP_PU (0x1 << 3)
987#define RT5616_HP_SG_MASK (0x1 << 2)
988#define RT5616_HP_SG_SFT 2
989#define RT5616_HP_SG_DIS (0x0 << 2)
990#define RT5616_HP_SG_EN (0x1 << 2)
991#define RT5616_HP_DP_MASK (0x1 << 1)
992#define RT5616_HP_DP_SFT 1
993#define RT5616_HP_DP_PD (0x0 << 1)
994#define RT5616_HP_DP_PU (0x1 << 1)
995#define RT5616_HP_CB_MASK (0x1)
996#define RT5616_HP_CB_SFT 0
997#define RT5616_HP_CB_PD (0x0)
998#define RT5616_HP_CB_PU (0x1)
999
1000/* Depop Mode Control 2 (0x8f) */
1001#define RT5616_DEPOP_MASK (0x1 << 13)
1002#define RT5616_DEPOP_SFT 13
1003#define RT5616_DEPOP_AUTO (0x0 << 13)
1004#define RT5616_DEPOP_MAN (0x1 << 13)
1005#define RT5616_RAMP_MASK (0x1 << 12)
1006#define RT5616_RAMP_SFT 12
1007#define RT5616_RAMP_DIS (0x0 << 12)
1008#define RT5616_RAMP_EN (0x1 << 12)
1009#define RT5616_BPS_MASK (0x1 << 11)
1010#define RT5616_BPS_SFT 11
1011#define RT5616_BPS_DIS (0x0 << 11)
1012#define RT5616_BPS_EN (0x1 << 11)
1013#define RT5616_FAST_UPDN_MASK (0x1 << 10)
1014#define RT5616_FAST_UPDN_SFT 10
1015#define RT5616_FAST_UPDN_DIS (0x0 << 10)
1016#define RT5616_FAST_UPDN_EN (0x1 << 10)
1017#define RT5616_MRES_MASK (0x3 << 8)
1018#define RT5616_MRES_SFT 8
1019#define RT5616_MRES_15MO (0x0 << 8)
1020#define RT5616_MRES_25MO (0x1 << 8)
1021#define RT5616_MRES_35MO (0x2 << 8)
1022#define RT5616_MRES_45MO (0x3 << 8)
1023#define RT5616_VLO_MASK (0x1 << 7)
1024#define RT5616_VLO_SFT 7
1025#define RT5616_VLO_3V (0x0 << 7)
1026#define RT5616_VLO_32V (0x1 << 7)
1027#define RT5616_DIG_DP_MASK (0x1 << 6)
1028#define RT5616_DIG_DP_SFT 6
1029#define RT5616_DIG_DP_DIS (0x0 << 6)
1030#define RT5616_DIG_DP_EN (0x1 << 6)
1031#define RT5616_DP_TH_MASK (0x3 << 4)
1032#define RT5616_DP_TH_SFT 4
1033
1034/* Depop Mode Control 3 (0x90) */
1035#define RT5616_CP_SYS_MASK (0x7 << 12)
1036#define RT5616_CP_SYS_SFT 12
1037#define RT5616_CP_FQ1_MASK (0x7 << 8)
1038#define RT5616_CP_FQ1_SFT 8
1039#define RT5616_CP_FQ2_MASK (0x7 << 4)
1040#define RT5616_CP_FQ2_SFT 4
1041#define RT5616_CP_FQ3_MASK (0x7)
1042#define RT5616_CP_FQ3_SFT 0
1043#define RT5616_CP_FQ_1_5_KHZ 0
1044#define RT5616_CP_FQ_3_KHZ 1
1045#define RT5616_CP_FQ_6_KHZ 2
1046#define RT5616_CP_FQ_12_KHZ 3
1047#define RT5616_CP_FQ_24_KHZ 4
1048#define RT5616_CP_FQ_48_KHZ 5
1049#define RT5616_CP_FQ_96_KHZ 6
1050#define RT5616_CP_FQ_192_KHZ 7
1051
1052/* HPOUT charge pump (0x91) */
1053#define RT5616_OSW_L_MASK (0x1 << 11)
1054#define RT5616_OSW_L_SFT 11
1055#define RT5616_OSW_L_DIS (0x0 << 11)
1056#define RT5616_OSW_L_EN (0x1 << 11)
1057#define RT5616_OSW_R_MASK (0x1 << 10)
1058#define RT5616_OSW_R_SFT 10
1059#define RT5616_OSW_R_DIS (0x0 << 10)
1060#define RT5616_OSW_R_EN (0x1 << 10)
1061#define RT5616_PM_HP_MASK (0x3 << 8)
1062#define RT5616_PM_HP_SFT 8
1063#define RT5616_PM_HP_LV (0x0 << 8)
1064#define RT5616_PM_HP_MV (0x1 << 8)
1065#define RT5616_PM_HP_HV (0x2 << 8)
1066#define RT5616_IB_HP_MASK (0x3 << 6)
1067#define RT5616_IB_HP_SFT 6
1068#define RT5616_IB_HP_125IL (0x0 << 6)
1069#define RT5616_IB_HP_25IL (0x1 << 6)
1070#define RT5616_IB_HP_5IL (0x2 << 6)
1071#define RT5616_IB_HP_1IL (0x3 << 6)
1072
1073/* Micbias Control (0x93) */
1074#define RT5616_MIC1_BS_MASK (0x1 << 15)
1075#define RT5616_MIC1_BS_SFT 15
1076#define RT5616_MIC1_BS_9AV (0x0 << 15)
1077#define RT5616_MIC1_BS_75AV (0x1 << 15)
1078#define RT5616_MIC1_CLK_MASK (0x1 << 13)
1079#define RT5616_MIC1_CLK_SFT 13
1080#define RT5616_MIC1_CLK_DIS (0x0 << 13)
1081#define RT5616_MIC1_CLK_EN (0x1 << 13)
1082#define RT5616_MIC1_OVCD_MASK (0x1 << 11)
1083#define RT5616_MIC1_OVCD_SFT 11
1084#define RT5616_MIC1_OVCD_DIS (0x0 << 11)
1085#define RT5616_MIC1_OVCD_EN (0x1 << 11)
1086#define RT5616_MIC1_OVTH_MASK (0x3 << 9)
1087#define RT5616_MIC1_OVTH_SFT 9
1088#define RT5616_MIC1_OVTH_600UA (0x0 << 9)
1089#define RT5616_MIC1_OVTH_1500UA (0x1 << 9)
1090#define RT5616_MIC1_OVTH_2000UA (0x2 << 9)
1091#define RT5616_PWR_MB_MASK (0x1 << 5)
1092#define RT5616_PWR_MB_SFT 5
1093#define RT5616_PWR_MB_PD (0x0 << 5)
1094#define RT5616_PWR_MB_PU (0x1 << 5)
1095#define RT5616_PWR_CLK12M_MASK (0x1 << 4)
1096#define RT5616_PWR_CLK12M_SFT 4
1097#define RT5616_PWR_CLK12M_PD (0x0 << 4)
1098#define RT5616_PWR_CLK12M_PU (0x1 << 4)
1099
1100/* Analog JD Control 1 (0x94) */
1101#define RT5616_JD2_CMP_MASK (0x7 << 12)
1102#define RT5616_JD2_CMP_SFT 12
1103#define RT5616_JD_PU (0x1 << 11)
1104#define RT5616_JD_PU_SFT 11
1105#define RT5616_JD_PD (0x1 << 10)
1106#define RT5616_JD_PD_SFT 10
1107#define RT5616_JD_MODE_SEL_MASK (0x3 << 8)
1108#define RT5616_JD_MODE_SEL_SFT 8
1109#define RT5616_JD_MODE_SEL_M0 (0x0 << 8)
1110#define RT5616_JD_MODE_SEL_M1 (0x1 << 8)
1111#define RT5616_JD_MODE_SEL_M2 (0x2 << 8)
1112#define RT5616_JD_M_CMP (0x7 << 4)
1113#define RT5616_JD_M_CMP_SFT 4
1114#define RT5616_JD_M_PU (0x1 << 3)
1115#define RT5616_JD_M_PU_SFT 3
1116#define RT5616_JD_M_PD (0x1 << 2)
1117#define RT5616_JD_M_PD_SFT 2
1118#define RT5616_JD_M_MODE_SEL_MASK (0x3)
1119#define RT5616_JD_M_MODE_SEL_SFT 0
1120#define RT5616_JD_M_MODE_SEL_M0 (0x0)
1121#define RT5616_JD_M_MODE_SEL_M1 (0x1)
1122#define RT5616_JD_M_MODE_SEL_M2 (0x2)
1123
1124/* Analog JD Control 2 (0x95) */
1125#define RT5616_JD3_CMP_MASK (0x7 << 12)
1126#define RT5616_JD3_CMP_SFT 12
1127
1128/* EQ Control 1 (0xb0) */
1129#define RT5616_EQ_SRC_MASK (0x1 << 15)
1130#define RT5616_EQ_SRC_SFT 15
1131#define RT5616_EQ_SRC_DAC (0x0 << 15)
1132#define RT5616_EQ_SRC_ADC (0x1 << 15)
1133#define RT5616_EQ_UPD (0x1 << 14)
1134#define RT5616_EQ_UPD_BIT 14
1135#define RT5616_EQ_CD_MASK (0x1 << 13)
1136#define RT5616_EQ_CD_SFT 13
1137#define RT5616_EQ_CD_DIS (0x0 << 13)
1138#define RT5616_EQ_CD_EN (0x1 << 13)
1139#define RT5616_EQ_DITH_MASK (0x3 << 8)
1140#define RT5616_EQ_DITH_SFT 8
1141#define RT5616_EQ_DITH_NOR (0x0 << 8)
1142#define RT5616_EQ_DITH_LSB (0x1 << 8)
1143#define RT5616_EQ_DITH_LSB_1 (0x2 << 8)
1144#define RT5616_EQ_DITH_LSB_2 (0x3 << 8)
1145#define RT5616_EQ_CD_F (0x1 << 7)
1146#define RT5616_EQ_CD_F_BIT 7
1147#define RT5616_EQ_STA_HP2 (0x1 << 6)
1148#define RT5616_EQ_STA_HP2_BIT 6
1149#define RT5616_EQ_STA_HP1 (0x1 << 5)
1150#define RT5616_EQ_STA_HP1_BIT 5
1151#define RT5616_EQ_STA_BP4 (0x1 << 4)
1152#define RT5616_EQ_STA_BP4_BIT 4
1153#define RT5616_EQ_STA_BP3 (0x1 << 3)
1154#define RT5616_EQ_STA_BP3_BIT 3
1155#define RT5616_EQ_STA_BP2 (0x1 << 2)
1156#define RT5616_EQ_STA_BP2_BIT 2
1157#define RT5616_EQ_STA_BP1 (0x1 << 1)
1158#define RT5616_EQ_STA_BP1_BIT 1
1159#define RT5616_EQ_STA_LP (0x1)
1160#define RT5616_EQ_STA_LP_BIT 0
1161
1162/* EQ Control 2 (0xb1) */
1163#define RT5616_EQ_HPF1_M_MASK (0x1 << 8)
1164#define RT5616_EQ_HPF1_M_SFT 8
1165#define RT5616_EQ_HPF1_M_HI (0x0 << 8)
1166#define RT5616_EQ_HPF1_M_1ST (0x1 << 8)
1167#define RT5616_EQ_LPF1_M_MASK (0x1 << 7)
1168#define RT5616_EQ_LPF1_M_SFT 7
1169#define RT5616_EQ_LPF1_M_LO (0x0 << 7)
1170#define RT5616_EQ_LPF1_M_1ST (0x1 << 7)
1171#define RT5616_EQ_HPF2_MASK (0x1 << 6)
1172#define RT5616_EQ_HPF2_SFT 6
1173#define RT5616_EQ_HPF2_DIS (0x0 << 6)
1174#define RT5616_EQ_HPF2_EN (0x1 << 6)
1175#define RT5616_EQ_HPF1_MASK (0x1 << 5)
1176#define RT5616_EQ_HPF1_SFT 5
1177#define RT5616_EQ_HPF1_DIS (0x0 << 5)
1178#define RT5616_EQ_HPF1_EN (0x1 << 5)
1179#define RT5616_EQ_BPF4_MASK (0x1 << 4)
1180#define RT5616_EQ_BPF4_SFT 4
1181#define RT5616_EQ_BPF4_DIS (0x0 << 4)
1182#define RT5616_EQ_BPF4_EN (0x1 << 4)
1183#define RT5616_EQ_BPF3_MASK (0x1 << 3)
1184#define RT5616_EQ_BPF3_SFT 3
1185#define RT5616_EQ_BPF3_DIS (0x0 << 3)
1186#define RT5616_EQ_BPF3_EN (0x1 << 3)
1187#define RT5616_EQ_BPF2_MASK (0x1 << 2)
1188#define RT5616_EQ_BPF2_SFT 2
1189#define RT5616_EQ_BPF2_DIS (0x0 << 2)
1190#define RT5616_EQ_BPF2_EN (0x1 << 2)
1191#define RT5616_EQ_BPF1_MASK (0x1 << 1)
1192#define RT5616_EQ_BPF1_SFT 1
1193#define RT5616_EQ_BPF1_DIS (0x0 << 1)
1194#define RT5616_EQ_BPF1_EN (0x1 << 1)
1195#define RT5616_EQ_LPF_MASK (0x1)
1196#define RT5616_EQ_LPF_SFT 0
1197#define RT5616_EQ_LPF_DIS (0x0)
1198#define RT5616_EQ_LPF_EN (0x1)
1199#define RT5616_EQ_CTRL_MASK (0x7f)
1200
1201/* Memory Test (0xb2) */
1202#define RT5616_MT_MASK (0x1 << 15)
1203#define RT5616_MT_SFT 15
1204#define RT5616_MT_DIS (0x0 << 15)
1205#define RT5616_MT_EN (0x1 << 15)
1206
1207/* DRC/AGC Control 1 (0xb4) */
1208#define RT5616_DRC_AGC_P_MASK (0x1 << 15)
1209#define RT5616_DRC_AGC_P_SFT 15
1210#define RT5616_DRC_AGC_P_DAC (0x0 << 15)
1211#define RT5616_DRC_AGC_P_ADC (0x1 << 15)
1212#define RT5616_DRC_AGC_MASK (0x1 << 14)
1213#define RT5616_DRC_AGC_SFT 14
1214#define RT5616_DRC_AGC_DIS (0x0 << 14)
1215#define RT5616_DRC_AGC_EN (0x1 << 14)
1216#define RT5616_DRC_AGC_UPD (0x1 << 13)
1217#define RT5616_DRC_AGC_UPD_BIT 13
1218#define RT5616_DRC_AGC_AR_MASK (0x1f << 8)
1219#define RT5616_DRC_AGC_AR_SFT 8
1220#define RT5616_DRC_AGC_R_MASK (0x7 << 5)
1221#define RT5616_DRC_AGC_R_SFT 5
1222#define RT5616_DRC_AGC_R_48K (0x1 << 5)
1223#define RT5616_DRC_AGC_R_96K (0x2 << 5)
1224#define RT5616_DRC_AGC_R_192K (0x3 << 5)
1225#define RT5616_DRC_AGC_R_441K (0x5 << 5)
1226#define RT5616_DRC_AGC_R_882K (0x6 << 5)
1227#define RT5616_DRC_AGC_R_1764K (0x7 << 5)
1228#define RT5616_DRC_AGC_RC_MASK (0x1f)
1229#define RT5616_DRC_AGC_RC_SFT 0
1230
1231/* DRC/AGC Control 2 (0xb5) */
1232#define RT5616_DRC_AGC_POB_MASK (0x3f << 8)
1233#define RT5616_DRC_AGC_POB_SFT 8
1234#define RT5616_DRC_AGC_CP_MASK (0x1 << 7)
1235#define RT5616_DRC_AGC_CP_SFT 7
1236#define RT5616_DRC_AGC_CP_DIS (0x0 << 7)
1237#define RT5616_DRC_AGC_CP_EN (0x1 << 7)
1238#define RT5616_DRC_AGC_CPR_MASK (0x3 << 5)
1239#define RT5616_DRC_AGC_CPR_SFT 5
1240#define RT5616_DRC_AGC_CPR_1_1 (0x0 << 5)
1241#define RT5616_DRC_AGC_CPR_1_2 (0x1 << 5)
1242#define RT5616_DRC_AGC_CPR_1_3 (0x2 << 5)
1243#define RT5616_DRC_AGC_CPR_1_4 (0x3 << 5)
1244#define RT5616_DRC_AGC_PRB_MASK (0x1f)
1245#define RT5616_DRC_AGC_PRB_SFT 0
1246
1247/* DRC/AGC Control 3 (0xb6) */
1248#define RT5616_DRC_AGC_NGB_MASK (0xf << 12)
1249#define RT5616_DRC_AGC_NGB_SFT 12
1250#define RT5616_DRC_AGC_TAR_MASK (0x1f << 7)
1251#define RT5616_DRC_AGC_TAR_SFT 7
1252#define RT5616_DRC_AGC_NG_MASK (0x1 << 6)
1253#define RT5616_DRC_AGC_NG_SFT 6
1254#define RT5616_DRC_AGC_NG_DIS (0x0 << 6)
1255#define RT5616_DRC_AGC_NG_EN (0x1 << 6)
1256#define RT5616_DRC_AGC_NGH_MASK (0x1 << 5)
1257#define RT5616_DRC_AGC_NGH_SFT 5
1258#define RT5616_DRC_AGC_NGH_DIS (0x0 << 5)
1259#define RT5616_DRC_AGC_NGH_EN (0x1 << 5)
1260#define RT5616_DRC_AGC_NGT_MASK (0x1f)
1261#define RT5616_DRC_AGC_NGT_SFT 0
1262
1263/* Jack Detect Control 1 (0xbb) */
1264#define RT5616_JD_MASK (0x7 << 13)
1265#define RT5616_JD_SFT 13
1266#define RT5616_JD_DIS (0x0 << 13)
1267#define RT5616_JD_GPIO1 (0x1 << 13)
1268#define RT5616_JD_GPIO2 (0x2 << 13)
1269#define RT5616_JD_GPIO3 (0x3 << 13)
1270#define RT5616_JD_GPIO4 (0x4 << 13)
1271#define RT5616_JD_GPIO5 (0x5 << 13)
1272#define RT5616_JD_GPIO6 (0x6 << 13)
1273#define RT5616_JD_HP_MASK (0x1 << 11)
1274#define RT5616_JD_HP_SFT 11
1275#define RT5616_JD_HP_DIS (0x0 << 11)
1276#define RT5616_JD_HP_EN (0x1 << 11)
1277#define RT5616_JD_HP_TRG_MASK (0x1 << 10)
1278#define RT5616_JD_HP_TRG_SFT 10
1279#define RT5616_JD_HP_TRG_LO (0x0 << 10)
1280#define RT5616_JD_HP_TRG_HI (0x1 << 10)
1281#define RT5616_JD_SPL_MASK (0x1 << 9)
1282#define RT5616_JD_SPL_SFT 9
1283#define RT5616_JD_SPL_DIS (0x0 << 9)
1284#define RT5616_JD_SPL_EN (0x1 << 9)
1285#define RT5616_JD_SPL_TRG_MASK (0x1 << 8)
1286#define RT5616_JD_SPL_TRG_SFT 8
1287#define RT5616_JD_SPL_TRG_LO (0x0 << 8)
1288#define RT5616_JD_SPL_TRG_HI (0x1 << 8)
1289#define RT5616_JD_SPR_MASK (0x1 << 7)
1290#define RT5616_JD_SPR_SFT 7
1291#define RT5616_JD_SPR_DIS (0x0 << 7)
1292#define RT5616_JD_SPR_EN (0x1 << 7)
1293#define RT5616_JD_SPR_TRG_MASK (0x1 << 6)
1294#define RT5616_JD_SPR_TRG_SFT 6
1295#define RT5616_JD_SPR_TRG_LO (0x0 << 6)
1296#define RT5616_JD_SPR_TRG_HI (0x1 << 6)
1297#define RT5616_JD_LO_MASK (0x1 << 3)
1298#define RT5616_JD_LO_SFT 3
1299#define RT5616_JD_LO_DIS (0x0 << 3)
1300#define RT5616_JD_LO_EN (0x1 << 3)
1301#define RT5616_JD_LO_TRG_MASK (0x1 << 2)
1302#define RT5616_JD_LO_TRG_SFT 2
1303#define RT5616_JD_LO_TRG_LO (0x0 << 2)
1304#define RT5616_JD_LO_TRG_HI (0x1 << 2)
1305
1306/* Jack Detect Control 2 (0xbc) */
1307#define RT5616_JD_TRG_SEL_MASK (0x7 << 9)
1308#define RT5616_JD_TRG_SEL_SFT 9
1309#define RT5616_JD_TRG_SEL_GPIO (0x0 << 9)
1310#define RT5616_JD_TRG_SEL_JD1_1 (0x1 << 9)
1311#define RT5616_JD_TRG_SEL_JD1_2 (0x2 << 9)
1312#define RT5616_JD_TRG_SEL_JD2 (0x3 << 9)
1313#define RT5616_JD_TRG_SEL_JD3 (0x4 << 9)
1314#define RT5616_JD3_IRQ_EN (0x1 << 8)
1315#define RT5616_JD3_IRQ_EN_SFT 8
1316#define RT5616_JD3_EN_STKY (0x1 << 7)
1317#define RT5616_JD3_EN_STKY_SFT 7
1318#define RT5616_JD3_INV (0x1 << 6)
1319#define RT5616_JD3_INV_SFT 6
1320
1321/* IRQ Control 1 (0xbd) */
1322#define RT5616_IRQ_JD_MASK (0x1 << 15)
1323#define RT5616_IRQ_JD_SFT 15
1324#define RT5616_IRQ_JD_BP (0x0 << 15)
1325#define RT5616_IRQ_JD_NOR (0x1 << 15)
1326#define RT5616_JD_STKY_MASK (0x1 << 13)
1327#define RT5616_JD_STKY_SFT 13
1328#define RT5616_JD_STKY_DIS (0x0 << 13)
1329#define RT5616_JD_STKY_EN (0x1 << 13)
1330#define RT5616_JD_P_MASK (0x1 << 11)
1331#define RT5616_JD_P_SFT 11
1332#define RT5616_JD_P_NOR (0x0 << 11)
1333#define RT5616_JD_P_INV (0x1 << 11)
1334#define RT5616_JD1_1_IRQ_EN (0x1 << 9)
1335#define RT5616_JD1_1_IRQ_EN_SFT 9
1336#define RT5616_JD1_1_EN_STKY (0x1 << 8)
1337#define RT5616_JD1_1_EN_STKY_SFT 8
1338#define RT5616_JD1_1_INV (0x1 << 7)
1339#define RT5616_JD1_1_INV_SFT 7
1340#define RT5616_JD1_2_IRQ_EN (0x1 << 6)
1341#define RT5616_JD1_2_IRQ_EN_SFT 6
1342#define RT5616_JD1_2_EN_STKY (0x1 << 5)
1343#define RT5616_JD1_2_EN_STKY_SFT 5
1344#define RT5616_JD1_2_INV (0x1 << 4)
1345#define RT5616_JD1_2_INV_SFT 4
1346#define RT5616_JD2_IRQ_EN (0x1 << 3)
1347#define RT5616_JD2_IRQ_EN_SFT 3
1348#define RT5616_JD2_EN_STKY (0x1 << 2)
1349#define RT5616_JD2_EN_STKY_SFT 2
1350#define RT5616_JD2_INV (0x1 << 1)
1351#define RT5616_JD2_INV_SFT 1
1352
1353/* IRQ Control 2 (0xbe) */
1354#define RT5616_IRQ_MB1_OC_MASK (0x1 << 15)
1355#define RT5616_IRQ_MB1_OC_SFT 15
1356#define RT5616_IRQ_MB1_OC_BP (0x0 << 15)
1357#define RT5616_IRQ_MB1_OC_NOR (0x1 << 15)
1358#define RT5616_MB1_OC_STKY_MASK (0x1 << 11)
1359#define RT5616_MB1_OC_STKY_SFT 11
1360#define RT5616_MB1_OC_STKY_DIS (0x0 << 11)
1361#define RT5616_MB1_OC_STKY_EN (0x1 << 11)
1362#define RT5616_MB1_OC_P_MASK (0x1 << 7)
1363#define RT5616_MB1_OC_P_SFT 7
1364#define RT5616_MB1_OC_P_NOR (0x0 << 7)
1365#define RT5616_MB1_OC_P_INV (0x1 << 7)
1366#define RT5616_MB2_OC_P_MASK (0x1 << 6)
1367#define RT5616_MB1_OC_CLR (0x1 << 3)
1368#define RT5616_MB1_OC_CLR_SFT 3
1369#define RT5616_STA_GPIO8 (0x1)
1370#define RT5616_STA_GPIO8_BIT 0
1371
1372/* Internal Status and GPIO status (0xbf) */
1373#define RT5616_STA_JD3 (0x1 << 15)
1374#define RT5616_STA_JD3_BIT 15
1375#define RT5616_STA_JD2 (0x1 << 14)
1376#define RT5616_STA_JD2_BIT 14
1377#define RT5616_STA_JD1_2 (0x1 << 13)
1378#define RT5616_STA_JD1_2_BIT 13
1379#define RT5616_STA_JD1_1 (0x1 << 12)
1380#define RT5616_STA_JD1_1_BIT 12
1381#define RT5616_STA_GP7 (0x1 << 11)
1382#define RT5616_STA_GP7_BIT 11
1383#define RT5616_STA_GP6 (0x1 << 10)
1384#define RT5616_STA_GP6_BIT 10
1385#define RT5616_STA_GP5 (0x1 << 9)
1386#define RT5616_STA_GP5_BIT 9
1387#define RT5616_STA_GP1 (0x1 << 8)
1388#define RT5616_STA_GP1_BIT 8
1389#define RT5616_STA_GP2 (0x1 << 7)
1390#define RT5616_STA_GP2_BIT 7
1391#define RT5616_STA_GP3 (0x1 << 6)
1392#define RT5616_STA_GP3_BIT 6
1393#define RT5616_STA_GP4 (0x1 << 5)
1394#define RT5616_STA_GP4_BIT 5
1395#define RT5616_STA_GP_JD (0x1 << 4)
1396#define RT5616_STA_GP_JD_BIT 4
1397
1398/* GPIO Control 1 (0xc0) */
1399#define RT5616_GP1_PIN_MASK (0x1 << 15)
1400#define RT5616_GP1_PIN_SFT 15
1401#define RT5616_GP1_PIN_GPIO1 (0x0 << 15)
1402#define RT5616_GP1_PIN_IRQ (0x1 << 15)
1403#define RT5616_GP2_PIN_MASK (0x1 << 14)
1404#define RT5616_GP2_PIN_SFT 14
1405#define RT5616_GP2_PIN_GPIO2 (0x0 << 14)
1406#define RT5616_GP2_PIN_DMIC1_SCL (0x1 << 14)
1407#define RT5616_GPIO_M_MASK (0x1 << 9)
1408#define RT5616_GPIO_M_SFT 9
1409#define RT5616_GPIO_M_FLT (0x0 << 9)
1410#define RT5616_GPIO_M_PH (0x1 << 9)
1411#define RT5616_I2S2_SEL_MASK (0x1 << 8)
1412#define RT5616_I2S2_SEL_SFT 8
1413#define RT5616_I2S2_SEL_I2S (0x0 << 8)
1414#define RT5616_I2S2_SEL_GPIO (0x1 << 8)
1415#define RT5616_GP5_PIN_MASK (0x1 << 7)
1416#define RT5616_GP5_PIN_SFT 7
1417#define RT5616_GP5_PIN_GPIO5 (0x0 << 7)
1418#define RT5616_GP5_PIN_IRQ (0x1 << 7)
1419#define RT5616_GP6_PIN_MASK (0x1 << 6)
1420#define RT5616_GP6_PIN_SFT 6
1421#define RT5616_GP6_PIN_GPIO6 (0x0 << 6)
1422#define RT5616_GP6_PIN_DMIC_SDA (0x1 << 6)
1423#define RT5616_GP7_PIN_MASK (0x1 << 5)
1424#define RT5616_GP7_PIN_SFT 5
1425#define RT5616_GP7_PIN_GPIO7 (0x0 << 5)
1426#define RT5616_GP7_PIN_IRQ (0x1 << 5)
1427#define RT5616_GP8_PIN_MASK (0x1 << 4)
1428#define RT5616_GP8_PIN_SFT 4
1429#define RT5616_GP8_PIN_GPIO8 (0x0 << 4)
1430#define RT5616_GP8_PIN_DMIC_SDA (0x1 << 4)
1431#define RT5616_GPIO_PDM_SEL_MASK (0x1 << 3)
1432#define RT5616_GPIO_PDM_SEL_SFT 3
1433#define RT5616_GPIO_PDM_SEL_GPIO (0x0 << 3)
1434#define RT5616_GPIO_PDM_SEL_PDM (0x1 << 3)
1435
1436/* GPIO Control 2 (0xc1) */
1437#define RT5616_GP5_DR_MASK (0x1 << 14)
1438#define RT5616_GP5_DR_SFT 14
1439#define RT5616_GP5_DR_IN (0x0 << 14)
1440#define RT5616_GP5_DR_OUT (0x1 << 14)
1441#define RT5616_GP5_OUT_MASK (0x1 << 13)
1442#define RT5616_GP5_OUT_SFT 13
1443#define RT5616_GP5_OUT_LO (0x0 << 13)
1444#define RT5616_GP5_OUT_HI (0x1 << 13)
1445#define RT5616_GP5_P_MASK (0x1 << 12)
1446#define RT5616_GP5_P_SFT 12
1447#define RT5616_GP5_P_NOR (0x0 << 12)
1448#define RT5616_GP5_P_INV (0x1 << 12)
1449#define RT5616_GP4_DR_MASK (0x1 << 11)
1450#define RT5616_GP4_DR_SFT 11
1451#define RT5616_GP4_DR_IN (0x0 << 11)
1452#define RT5616_GP4_DR_OUT (0x1 << 11)
1453#define RT5616_GP4_OUT_MASK (0x1 << 10)
1454#define RT5616_GP4_OUT_SFT 10
1455#define RT5616_GP4_OUT_LO (0x0 << 10)
1456#define RT5616_GP4_OUT_HI (0x1 << 10)
1457#define RT5616_GP4_P_MASK (0x1 << 9)
1458#define RT5616_GP4_P_SFT 9
1459#define RT5616_GP4_P_NOR (0x0 << 9)
1460#define RT5616_GP4_P_INV (0x1 << 9)
1461#define RT5616_GP3_DR_MASK (0x1 << 8)
1462#define RT5616_GP3_DR_SFT 8
1463#define RT5616_GP3_DR_IN (0x0 << 8)
1464#define RT5616_GP3_DR_OUT (0x1 << 8)
1465#define RT5616_GP3_OUT_MASK (0x1 << 7)
1466#define RT5616_GP3_OUT_SFT 7
1467#define RT5616_GP3_OUT_LO (0x0 << 7)
1468#define RT5616_GP3_OUT_HI (0x1 << 7)
1469#define RT5616_GP3_P_MASK (0x1 << 6)
1470#define RT5616_GP3_P_SFT 6
1471#define RT5616_GP3_P_NOR (0x0 << 6)
1472#define RT5616_GP3_P_INV (0x1 << 6)
1473#define RT5616_GP2_DR_MASK (0x1 << 5)
1474#define RT5616_GP2_DR_SFT 5
1475#define RT5616_GP2_DR_IN (0x0 << 5)
1476#define RT5616_GP2_DR_OUT (0x1 << 5)
1477#define RT5616_GP2_OUT_MASK (0x1 << 4)
1478#define RT5616_GP2_OUT_SFT 4
1479#define RT5616_GP2_OUT_LO (0x0 << 4)
1480#define RT5616_GP2_OUT_HI (0x1 << 4)
1481#define RT5616_GP2_P_MASK (0x1 << 3)
1482#define RT5616_GP2_P_SFT 3
1483#define RT5616_GP2_P_NOR (0x0 << 3)
1484#define RT5616_GP2_P_INV (0x1 << 3)
1485#define RT5616_GP1_DR_MASK (0x1 << 2)
1486#define RT5616_GP1_DR_SFT 2
1487#define RT5616_GP1_DR_IN (0x0 << 2)
1488#define RT5616_GP1_DR_OUT (0x1 << 2)
1489#define RT5616_GP1_OUT_MASK (0x1 << 1)
1490#define RT5616_GP1_OUT_SFT 1
1491#define RT5616_GP1_OUT_LO (0x0 << 1)
1492#define RT5616_GP1_OUT_HI (0x1 << 1)
1493#define RT5616_GP1_P_MASK (0x1)
1494#define RT5616_GP1_P_SFT 0
1495#define RT5616_GP1_P_NOR (0x0)
1496#define RT5616_GP1_P_INV (0x1)
1497
1498/* GPIO Control 3 (0xc2) */
1499#define RT5616_GP8_DR_MASK (0x1 << 8)
1500#define RT5616_GP8_DR_SFT 8
1501#define RT5616_GP8_DR_IN (0x0 << 8)
1502#define RT5616_GP8_DR_OUT (0x1 << 8)
1503#define RT5616_GP8_OUT_MASK (0x1 << 7)
1504#define RT5616_GP8_OUT_SFT 7
1505#define RT5616_GP8_OUT_LO (0x0 << 7)
1506#define RT5616_GP8_OUT_HI (0x1 << 7)
1507#define RT5616_GP8_P_MASK (0x1 << 6)
1508#define RT5616_GP8_P_SFT 6
1509#define RT5616_GP8_P_NOR (0x0 << 6)
1510#define RT5616_GP8_P_INV (0x1 << 6)
1511#define RT5616_GP7_DR_MASK (0x1 << 5)
1512#define RT5616_GP7_DR_SFT 5
1513#define RT5616_GP7_DR_IN (0x0 << 5)
1514#define RT5616_GP7_DR_OUT (0x1 << 5)
1515#define RT5616_GP7_OUT_MASK (0x1 << 4)
1516#define RT5616_GP7_OUT_SFT 4
1517#define RT5616_GP7_OUT_LO (0x0 << 4)
1518#define RT5616_GP7_OUT_HI (0x1 << 4)
1519#define RT5616_GP7_P_MASK (0x1 << 3)
1520#define RT5616_GP7_P_SFT 3
1521#define RT5616_GP7_P_NOR (0x0 << 3)
1522#define RT5616_GP7_P_INV (0x1 << 3)
1523#define RT5616_GP6_DR_MASK (0x1 << 2)
1524#define RT5616_GP6_DR_SFT 2
1525#define RT5616_GP6_DR_IN (0x0 << 2)
1526#define RT5616_GP6_DR_OUT (0x1 << 2)
1527#define RT5616_GP6_OUT_MASK (0x1 << 1)
1528#define RT5616_GP6_OUT_SFT 1
1529#define RT5616_GP6_OUT_LO (0x0 << 1)
1530#define RT5616_GP6_OUT_HI (0x1 << 1)
1531#define RT5616_GP6_P_MASK (0x1)
1532#define RT5616_GP6_P_SFT 0
1533#define RT5616_GP6_P_NOR (0x0)
1534#define RT5616_GP6_P_INV (0x1)
1535
1536/* Scramble Control (0xce) */
1537#define RT5616_SCB_SWAP_MASK (0x1 << 15)
1538#define RT5616_SCB_SWAP_SFT 15
1539#define RT5616_SCB_SWAP_DIS (0x0 << 15)
1540#define RT5616_SCB_SWAP_EN (0x1 << 15)
1541#define RT5616_SCB_MASK (0x1 << 14)
1542#define RT5616_SCB_SFT 14
1543#define RT5616_SCB_DIS (0x0 << 14)
1544#define RT5616_SCB_EN (0x1 << 14)
1545
1546/* Baseback Control (0xcf) */
1547#define RT5616_BB_MASK (0x1 << 15)
1548#define RT5616_BB_SFT 15
1549#define RT5616_BB_DIS (0x0 << 15)
1550#define RT5616_BB_EN (0x1 << 15)
1551#define RT5616_BB_CT_MASK (0x7 << 12)
1552#define RT5616_BB_CT_SFT 12
1553#define RT5616_BB_CT_A (0x0 << 12)
1554#define RT5616_BB_CT_B (0x1 << 12)
1555#define RT5616_BB_CT_C (0x2 << 12)
1556#define RT5616_BB_CT_D (0x3 << 12)
1557#define RT5616_M_BB_L_MASK (0x1 << 9)
1558#define RT5616_M_BB_L_SFT 9
1559#define RT5616_M_BB_R_MASK (0x1 << 8)
1560#define RT5616_M_BB_R_SFT 8
1561#define RT5616_M_BB_HPF_L_MASK (0x1 << 7)
1562#define RT5616_M_BB_HPF_L_SFT 7
1563#define RT5616_M_BB_HPF_R_MASK (0x1 << 6)
1564#define RT5616_M_BB_HPF_R_SFT 6
1565#define RT5616_G_BB_BST_MASK (0x3f)
1566#define RT5616_G_BB_BST_SFT 0
1567
1568/* MP3 Plus Control 1 (0xd0) */
1569#define RT5616_M_MP3_L_MASK (0x1 << 15)
1570#define RT5616_M_MP3_L_SFT 15
1571#define RT5616_M_MP3_R_MASK (0x1 << 14)
1572#define RT5616_M_MP3_R_SFT 14
1573#define RT5616_M_MP3_MASK (0x1 << 13)
1574#define RT5616_M_MP3_SFT 13
1575#define RT5616_M_MP3_DIS (0x0 << 13)
1576#define RT5616_M_MP3_EN (0x1 << 13)
1577#define RT5616_EG_MP3_MASK (0x1f << 8)
1578#define RT5616_EG_MP3_SFT 8
1579#define RT5616_MP3_HLP_MASK (0x1 << 7)
1580#define RT5616_MP3_HLP_SFT 7
1581#define RT5616_MP3_HLP_DIS (0x0 << 7)
1582#define RT5616_MP3_HLP_EN (0x1 << 7)
1583#define RT5616_M_MP3_ORG_L_MASK (0x1 << 6)
1584#define RT5616_M_MP3_ORG_L_SFT 6
1585#define RT5616_M_MP3_ORG_R_MASK (0x1 << 5)
1586#define RT5616_M_MP3_ORG_R_SFT 5
1587
1588/* MP3 Plus Control 2 (0xd1) */
1589#define RT5616_MP3_WT_MASK (0x1 << 13)
1590#define RT5616_MP3_WT_SFT 13
1591#define RT5616_MP3_WT_1_4 (0x0 << 13)
1592#define RT5616_MP3_WT_1_2 (0x1 << 13)
1593#define RT5616_OG_MP3_MASK (0x1f << 8)
1594#define RT5616_OG_MP3_SFT 8
1595#define RT5616_HG_MP3_MASK (0x3f)
1596#define RT5616_HG_MP3_SFT 0
1597
1598/* 3D HP Control 1 (0xd2) */
1599#define RT5616_3D_CF_MASK (0x1 << 15)
1600#define RT5616_3D_CF_SFT 15
1601#define RT5616_3D_CF_DIS (0x0 << 15)
1602#define RT5616_3D_CF_EN (0x1 << 15)
1603#define RT5616_3D_HP_MASK (0x1 << 14)
1604#define RT5616_3D_HP_SFT 14
1605#define RT5616_3D_HP_DIS (0x0 << 14)
1606#define RT5616_3D_HP_EN (0x1 << 14)
1607#define RT5616_3D_BT_MASK (0x1 << 13)
1608#define RT5616_3D_BT_SFT 13
1609#define RT5616_3D_BT_DIS (0x0 << 13)
1610#define RT5616_3D_BT_EN (0x1 << 13)
1611#define RT5616_3D_1F_MIX_MASK (0x3 << 11)
1612#define RT5616_3D_1F_MIX_SFT 11
1613#define RT5616_3D_HP_M_MASK (0x1 << 10)
1614#define RT5616_3D_HP_M_SFT 10
1615#define RT5616_3D_HP_M_SUR (0x0 << 10)
1616#define RT5616_3D_HP_M_FRO (0x1 << 10)
1617#define RT5616_M_3D_HRTF_MASK (0x1 << 9)
1618#define RT5616_M_3D_HRTF_SFT 9
1619#define RT5616_M_3D_D2H_MASK (0x1 << 8)
1620#define RT5616_M_3D_D2H_SFT 8
1621#define RT5616_M_3D_D2R_MASK (0x1 << 7)
1622#define RT5616_M_3D_D2R_SFT 7
1623#define RT5616_M_3D_REVB_MASK (0x1 << 6)
1624#define RT5616_M_3D_REVB_SFT 6
1625
1626/* Adjustable high pass filter control 1 (0xd3) */
1627#define RT5616_2ND_HPF_MASK (0x1 << 15)
1628#define RT5616_2ND_HPF_SFT 15
1629#define RT5616_2ND_HPF_DIS (0x0 << 15)
1630#define RT5616_2ND_HPF_EN (0x1 << 15)
1631#define RT5616_HPF_CF_L_MASK (0x7 << 12)
1632#define RT5616_HPF_CF_L_SFT 12
1633#define RT5616_HPF_CF_R_MASK (0x7 << 8)
1634#define RT5616_HPF_CF_R_SFT 8
1635#define RT5616_ZD_T_MASK (0x3 << 6)
1636#define RT5616_ZD_T_SFT 6
1637#define RT5616_ZD_F_MASK (0x3 << 4)
1638#define RT5616_ZD_F_SFT 4
1639#define RT5616_ZD_F_IM (0x0 << 4)
1640#define RT5616_ZD_F_ZC_IM (0x1 << 4)
1641#define RT5616_ZD_F_ZC_IOD (0x2 << 4)
1642#define RT5616_ZD_F_UN (0x3 << 4)
1643
1644/* Adjustable high pass filter control 2 (0xd4) */
1645#define RT5616_HPF_CF_L_NUM_MASK (0x3f << 8)
1646#define RT5616_HPF_CF_L_NUM_SFT 8
1647#define RT5616_HPF_CF_R_NUM_MASK (0x3f)
1648#define RT5616_HPF_CF_R_NUM_SFT 0
1649
1650/* HP calibration control and Amp detection (0xd6) */
1651#define RT5616_SI_DAC_MASK (0x1 << 11)
1652#define RT5616_SI_DAC_SFT 11
1653#define RT5616_SI_DAC_AUTO (0x0 << 11)
1654#define RT5616_SI_DAC_TEST (0x1 << 11)
1655#define RT5616_DC_CAL_M_MASK (0x1 << 10)
1656#define RT5616_DC_CAL_M_SFT 10
1657#define RT5616_DC_CAL_M_NOR (0x0 << 10)
1658#define RT5616_DC_CAL_M_CAL (0x1 << 10)
1659#define RT5616_DC_CAL_MASK (0x1 << 9)
1660#define RT5616_DC_CAL_SFT 9
1661#define RT5616_DC_CAL_DIS (0x0 << 9)
1662#define RT5616_DC_CAL_EN (0x1 << 9)
1663#define RT5616_HPD_RCV_MASK (0x7 << 6)
1664#define RT5616_HPD_RCV_SFT 6
1665#define RT5616_HPD_PS_MASK (0x1 << 5)
1666#define RT5616_HPD_PS_SFT 5
1667#define RT5616_HPD_PS_DIS (0x0 << 5)
1668#define RT5616_HPD_PS_EN (0x1 << 5)
1669#define RT5616_CAL_M_MASK (0x1 << 4)
1670#define RT5616_CAL_M_SFT 4
1671#define RT5616_CAL_M_DEP (0x0 << 4)
1672#define RT5616_CAL_M_CAL (0x1 << 4)
1673#define RT5616_CAL_MASK (0x1 << 3)
1674#define RT5616_CAL_SFT 3
1675#define RT5616_CAL_DIS (0x0 << 3)
1676#define RT5616_CAL_EN (0x1 << 3)
1677#define RT5616_CAL_TEST_MASK (0x1 << 2)
1678#define RT5616_CAL_TEST_SFT 2
1679#define RT5616_CAL_TEST_DIS (0x0 << 2)
1680#define RT5616_CAL_TEST_EN (0x1 << 2)
1681#define RT5616_CAL_P_MASK (0x3)
1682#define RT5616_CAL_P_SFT 0
1683#define RT5616_CAL_P_NONE (0x0)
1684#define RT5616_CAL_P_CAL (0x1)
1685#define RT5616_CAL_P_DAC_CAL (0x2)
1686
1687/* Soft volume and zero cross control 1 (0xd9) */
1688#define RT5616_SV_MASK (0x1 << 15)
1689#define RT5616_SV_SFT 15
1690#define RT5616_SV_DIS (0x0 << 15)
1691#define RT5616_SV_EN (0x1 << 15)
1692#define RT5616_OUT_SV_MASK (0x1 << 13)
1693#define RT5616_OUT_SV_SFT 13
1694#define RT5616_OUT_SV_DIS (0x0 << 13)
1695#define RT5616_OUT_SV_EN (0x1 << 13)
1696#define RT5616_HP_SV_MASK (0x1 << 12)
1697#define RT5616_HP_SV_SFT 12
1698#define RT5616_HP_SV_DIS (0x0 << 12)
1699#define RT5616_HP_SV_EN (0x1 << 12)
1700#define RT5616_ZCD_DIG_MASK (0x1 << 11)
1701#define RT5616_ZCD_DIG_SFT 11
1702#define RT5616_ZCD_DIG_DIS (0x0 << 11)
1703#define RT5616_ZCD_DIG_EN (0x1 << 11)
1704#define RT5616_ZCD_MASK (0x1 << 10)
1705#define RT5616_ZCD_SFT 10
1706#define RT5616_ZCD_PD (0x0 << 10)
1707#define RT5616_ZCD_PU (0x1 << 10)
1708#define RT5616_M_ZCD_MASK (0x3f << 4)
1709#define RT5616_M_ZCD_SFT 4
1710#define RT5616_M_ZCD_OM_L (0x1 << 7)
1711#define RT5616_M_ZCD_OM_R (0x1 << 6)
1712#define RT5616_M_ZCD_RM_L (0x1 << 5)
1713#define RT5616_M_ZCD_RM_R (0x1 << 4)
1714#define RT5616_SV_DLY_MASK (0xf)
1715#define RT5616_SV_DLY_SFT 0
1716
1717/* Soft volume and zero cross control 2 (0xda) */
1718#define RT5616_ZCD_HP_MASK (0x1 << 15)
1719#define RT5616_ZCD_HP_SFT 15
1720#define RT5616_ZCD_HP_DIS (0x0 << 15)
1721#define RT5616_ZCD_HP_EN (0x1 << 15)
1722
1723/* Digital Misc Control (0xfa) */
1724#define RT5616_I2S2_MS_SP_MASK (0x1 << 8)
1725#define RT5616_I2S2_MS_SP_SEL 8
1726#define RT5616_I2S2_MS_SP_64 (0x0 << 8)
1727#define RT5616_I2S2_MS_SP_50 (0x1 << 8)
1728#define RT5616_CLK_DET_EN (0x1 << 3)
1729#define RT5616_CLK_DET_EN_SFT 3
1730#define RT5616_AMP_DET_EN (0x1 << 1)
1731#define RT5616_AMP_DET_EN_SFT 1
1732#define RT5616_D_GATE_EN (0x1)
1733#define RT5616_D_GATE_EN_SFT 0
1734
1735/* Codec Private Register definition */
1736/* 3D Speaker Control (0x63) */
1737#define RT5616_3D_SPK_MASK (0x1 << 15)
1738#define RT5616_3D_SPK_SFT 15
1739#define RT5616_3D_SPK_DIS (0x0 << 15)
1740#define RT5616_3D_SPK_EN (0x1 << 15)
1741#define RT5616_3D_SPK_M_MASK (0x3 << 13)
1742#define RT5616_3D_SPK_M_SFT 13
1743#define RT5616_3D_SPK_CG_MASK (0x1f << 8)
1744#define RT5616_3D_SPK_CG_SFT 8
1745#define RT5616_3D_SPK_SG_MASK (0x1f)
1746#define RT5616_3D_SPK_SG_SFT 0
1747
1748/* Wind Noise Detection Control 1 (0x6c) */
1749#define RT5616_WND_MASK (0x1 << 15)
1750#define RT5616_WND_SFT 15
1751#define RT5616_WND_DIS (0x0 << 15)
1752#define RT5616_WND_EN (0x1 << 15)
1753
1754/* Wind Noise Detection Control 2 (0x6d) */
1755#define RT5616_WND_FC_NW_MASK (0x3f << 10)
1756#define RT5616_WND_FC_NW_SFT 10
1757#define RT5616_WND_FC_WK_MASK (0x3f << 4)
1758#define RT5616_WND_FC_WK_SFT 4
1759
1760/* Wind Noise Detection Control 3 (0x6e) */
1761#define RT5616_HPF_FC_MASK (0x3f << 6)
1762#define RT5616_HPF_FC_SFT 6
1763#define RT5616_WND_FC_ST_MASK (0x3f)
1764#define RT5616_WND_FC_ST_SFT 0
1765
1766/* Wind Noise Detection Control 4 (0x6f) */
1767#define RT5616_WND_TH_LO_MASK (0x3ff)
1768#define RT5616_WND_TH_LO_SFT 0
1769
1770/* Wind Noise Detection Control 5 (0x70) */
1771#define RT5616_WND_TH_HI_MASK (0x3ff)
1772#define RT5616_WND_TH_HI_SFT 0
1773
1774/* Wind Noise Detection Control 8 (0x73) */
1775#define RT5616_WND_WIND_MASK (0x1 << 13) /* Read-Only */
1776#define RT5616_WND_WIND_SFT 13
1777#define RT5616_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
1778#define RT5616_WND_STRONG_SFT 12
1779enum {
1780 RT5616_NO_WIND,
1781 RT5616_BREEZE,
1782 RT5616_STORM,
1783};
1784
1785/* Dipole Speaker Interface (0x75) */
1786#define RT5616_DP_ATT_MASK (0x3 << 14)
1787#define RT5616_DP_ATT_SFT 14
1788#define RT5616_DP_SPK_MASK (0x1 << 10)
1789#define RT5616_DP_SPK_SFT 10
1790#define RT5616_DP_SPK_DIS (0x0 << 10)
1791#define RT5616_DP_SPK_EN (0x1 << 10)
1792
1793/* EQ Pre Volume Control (0xb3) */
1794#define RT5616_EQ_PRE_VOL_MASK (0xffff)
1795#define RT5616_EQ_PRE_VOL_SFT 0
1796
1797/* EQ Post Volume Control (0xb4) */
1798#define RT5616_EQ_PST_VOL_MASK (0xffff)
1799#define RT5616_EQ_PST_VOL_SFT 0
1800
1801/* System Clock Source */
1802enum {
1803 RT5616_SCLK_S_MCLK,
1804 RT5616_SCLK_S_PLL1,
1805};
1806
1807/* PLL1 Source */
1808enum {
1809 RT5616_PLL1_S_MCLK,
1810 RT5616_PLL1_S_BCLK1,
1811 RT5616_PLL1_S_BCLK2,
1812};
1813
1814enum {
1815 RT5616_AIF1,
1816 RT5616_AIFS,
1817};
1818
1819#endif /* __RT5616_H__ */
diff --git a/sound/soc/codecs/rt5659.c b/sound/soc/codecs/rt5659.c
new file mode 100644
index 000000000000..820d8fa62b5e
--- /dev/null
+++ b/sound/soc/codecs/rt5659.c
@@ -0,0 +1,4223 @@
1/*
2 * rt5659.c -- RT5659/RT5658 ALSA SoC audio codec driver
3 *
4 * Copyright 2015 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
20#include <linux/acpi.h>
21#include <linux/gpio.h>
22#include <linux/gpio/consumer.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/jack.h>
27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h>
30#include <sound/tlv.h>
31#include <sound/rt5659.h>
32
33#include "rl6231.h"
34#include "rt5659.h"
35
36static const struct reg_default rt5659_reg[] = {
37 { 0x0000, 0x0000 },
38 { 0x0001, 0x4848 },
39 { 0x0002, 0x8080 },
40 { 0x0003, 0xc8c8 },
41 { 0x0004, 0xc80a },
42 { 0x0005, 0x0000 },
43 { 0x0006, 0x0000 },
44 { 0x0007, 0x0103 },
45 { 0x0008, 0x0080 },
46 { 0x0009, 0x0000 },
47 { 0x000a, 0x0000 },
48 { 0x000c, 0x0000 },
49 { 0x000d, 0x0000 },
50 { 0x000f, 0x0808 },
51 { 0x0010, 0x3080 },
52 { 0x0011, 0x4a00 },
53 { 0x0012, 0x4e00 },
54 { 0x0015, 0x42c1 },
55 { 0x0016, 0x0000 },
56 { 0x0018, 0x000b },
57 { 0x0019, 0xafaf },
58 { 0x001a, 0xafaf },
59 { 0x001b, 0x0011 },
60 { 0x001c, 0x2f2f },
61 { 0x001d, 0x2f2f },
62 { 0x001e, 0x2f2f },
63 { 0x001f, 0x0000 },
64 { 0x0020, 0x0000 },
65 { 0x0021, 0x0000 },
66 { 0x0022, 0x5757 },
67 { 0x0023, 0x0039 },
68 { 0x0026, 0xc060 },
69 { 0x0027, 0xd8d8 },
70 { 0x0029, 0x8080 },
71 { 0x002a, 0xaaaa },
72 { 0x002b, 0xaaaa },
73 { 0x002c, 0x00af },
74 { 0x002d, 0x0000 },
75 { 0x002f, 0x1002 },
76 { 0x0031, 0x5000 },
77 { 0x0032, 0x0000 },
78 { 0x0033, 0x0000 },
79 { 0x0034, 0x0000 },
80 { 0x0035, 0x0000 },
81 { 0x0036, 0x0000 },
82 { 0x003a, 0x0000 },
83 { 0x003b, 0x0000 },
84 { 0x003c, 0x007f },
85 { 0x003d, 0x0000 },
86 { 0x003e, 0x007f },
87 { 0x0040, 0x0808 },
88 { 0x0046, 0x001f },
89 { 0x0047, 0x001f },
90 { 0x0048, 0x0003 },
91 { 0x0049, 0xe061 },
92 { 0x004a, 0x0000 },
93 { 0x004b, 0x031f },
94 { 0x004d, 0x0000 },
95 { 0x004e, 0x001f },
96 { 0x004f, 0x0000 },
97 { 0x0050, 0x001f },
98 { 0x0052, 0xf000 },
99 { 0x0053, 0x0111 },
100 { 0x0054, 0x0064 },
101 { 0x0055, 0x0080 },
102 { 0x0056, 0xef0e },
103 { 0x0057, 0xf0f0 },
104 { 0x0058, 0xef0e },
105 { 0x0059, 0xf0f0 },
106 { 0x005a, 0xef0e },
107 { 0x005b, 0xf0f0 },
108 { 0x005c, 0xf000 },
109 { 0x005d, 0x0000 },
110 { 0x005e, 0x1f2c },
111 { 0x005f, 0x1f2c },
112 { 0x0060, 0x2717 },
113 { 0x0061, 0x0000 },
114 { 0x0062, 0x0000 },
115 { 0x0063, 0x003e },
116 { 0x0064, 0x0000 },
117 { 0x0065, 0x0000 },
118 { 0x0066, 0x0000 },
119 { 0x0067, 0x0000 },
120 { 0x006a, 0x0000 },
121 { 0x006b, 0x0000 },
122 { 0x006c, 0x0000 },
123 { 0x006e, 0x0000 },
124 { 0x006f, 0x0000 },
125 { 0x0070, 0x8000 },
126 { 0x0071, 0x8000 },
127 { 0x0072, 0x8000 },
128 { 0x0073, 0x1110 },
129 { 0x0074, 0xfe00 },
130 { 0x0075, 0x2409 },
131 { 0x0076, 0x000a },
132 { 0x0077, 0x00f0 },
133 { 0x0078, 0x0000 },
134 { 0x0079, 0x0000 },
135 { 0x007a, 0x0123 },
136 { 0x007b, 0x8003 },
137 { 0x0080, 0x0000 },
138 { 0x0081, 0x0000 },
139 { 0x0082, 0x0000 },
140 { 0x0083, 0x0000 },
141 { 0x0084, 0x0000 },
142 { 0x0085, 0x0000 },
143 { 0x0086, 0x0008 },
144 { 0x0087, 0x0000 },
145 { 0x0088, 0x0000 },
146 { 0x0089, 0x0000 },
147 { 0x008a, 0x0000 },
148 { 0x008b, 0x0000 },
149 { 0x008c, 0x0003 },
150 { 0x008e, 0x0000 },
151 { 0x008f, 0x1000 },
152 { 0x0090, 0x0646 },
153 { 0x0091, 0x0c16 },
154 { 0x0092, 0x0073 },
155 { 0x0093, 0x0000 },
156 { 0x0094, 0x0080 },
157 { 0x0097, 0x0000 },
158 { 0x0098, 0x0000 },
159 { 0x0099, 0x0000 },
160 { 0x009a, 0x0000 },
161 { 0x009b, 0x0000 },
162 { 0x009c, 0x007f },
163 { 0x009d, 0x0000 },
164 { 0x009e, 0x007f },
165 { 0x009f, 0x0000 },
166 { 0x00a0, 0x0060 },
167 { 0x00a1, 0x90a1 },
168 { 0x00ae, 0x2000 },
169 { 0x00af, 0x0000 },
170 { 0x00b0, 0x2000 },
171 { 0x00b1, 0x0000 },
172 { 0x00b2, 0x0000 },
173 { 0x00b6, 0x0000 },
174 { 0x00b7, 0x0000 },
175 { 0x00b8, 0x0000 },
176 { 0x00b9, 0x0000 },
177 { 0x00ba, 0x0000 },
178 { 0x00bb, 0x0000 },
179 { 0x00be, 0x0000 },
180 { 0x00bf, 0x0000 },
181 { 0x00c0, 0x0000 },
182 { 0x00c1, 0x0000 },
183 { 0x00c2, 0x0000 },
184 { 0x00c3, 0x0000 },
185 { 0x00c4, 0x0003 },
186 { 0x00c5, 0x0000 },
187 { 0x00cb, 0xa02f },
188 { 0x00cc, 0x0000 },
189 { 0x00cd, 0x0e02 },
190 { 0x00d6, 0x0000 },
191 { 0x00d7, 0x2244 },
192 { 0x00d9, 0x0809 },
193 { 0x00da, 0x0000 },
194 { 0x00db, 0x0008 },
195 { 0x00dc, 0x00c0 },
196 { 0x00dd, 0x6724 },
197 { 0x00de, 0x3131 },
198 { 0x00df, 0x0008 },
199 { 0x00e0, 0x4000 },
200 { 0x00e1, 0x3131 },
201 { 0x00e4, 0x400c },
202 { 0x00e5, 0x8031 },
203 { 0x00ea, 0xb320 },
204 { 0x00eb, 0x0000 },
205 { 0x00ec, 0xb300 },
206 { 0x00ed, 0x0000 },
207 { 0x00f0, 0x0000 },
208 { 0x00f1, 0x0202 },
209 { 0x00f2, 0x0ddd },
210 { 0x00f3, 0x0ddd },
211 { 0x00f4, 0x0ddd },
212 { 0x00f6, 0x0000 },
213 { 0x00f7, 0x0000 },
214 { 0x00f8, 0x0000 },
215 { 0x00f9, 0x0000 },
216 { 0x00fa, 0x8000 },
217 { 0x00fb, 0x0000 },
218 { 0x00fc, 0x0000 },
219 { 0x00fd, 0x0001 },
220 { 0x00fe, 0x10ec },
221 { 0x00ff, 0x6311 },
222 { 0x0100, 0xaaaa },
223 { 0x010a, 0xaaaa },
224 { 0x010b, 0x00a0 },
225 { 0x010c, 0xaeae },
226 { 0x010d, 0xaaaa },
227 { 0x010e, 0xaaa8 },
228 { 0x010f, 0xa0aa },
229 { 0x0110, 0xe02a },
230 { 0x0111, 0xa702 },
231 { 0x0112, 0xaaaa },
232 { 0x0113, 0x2800 },
233 { 0x0116, 0x0000 },
234 { 0x0117, 0x0f00 },
235 { 0x011a, 0x0020 },
236 { 0x011b, 0x0011 },
237 { 0x011c, 0x0150 },
238 { 0x011d, 0x0000 },
239 { 0x011e, 0x0000 },
240 { 0x011f, 0x0000 },
241 { 0x0120, 0x0000 },
242 { 0x0121, 0x009b },
243 { 0x0122, 0x5014 },
244 { 0x0123, 0x0421 },
245 { 0x0124, 0x7cea },
246 { 0x0125, 0x0420 },
247 { 0x0126, 0x5550 },
248 { 0x0132, 0x0000 },
249 { 0x0133, 0x0000 },
250 { 0x0137, 0x5055 },
251 { 0x0138, 0x3700 },
252 { 0x0139, 0x79a1 },
253 { 0x013a, 0x2020 },
254 { 0x013b, 0x2020 },
255 { 0x013c, 0x2005 },
256 { 0x013e, 0x1f00 },
257 { 0x013f, 0x0000 },
258 { 0x0145, 0x0002 },
259 { 0x0146, 0x0000 },
260 { 0x0147, 0x0000 },
261 { 0x0148, 0x0000 },
262 { 0x0150, 0x1813 },
263 { 0x0151, 0x0690 },
264 { 0x0152, 0x1c17 },
265 { 0x0153, 0x6883 },
266 { 0x0154, 0xd3ce },
267 { 0x0155, 0x352d },
268 { 0x0156, 0x00eb },
269 { 0x0157, 0x3717 },
270 { 0x0158, 0x4c6a },
271 { 0x0159, 0xe41b },
272 { 0x015a, 0x2a13 },
273 { 0x015b, 0xb600 },
274 { 0x015c, 0xc730 },
275 { 0x015d, 0x35d4 },
276 { 0x015e, 0x00bf },
277 { 0x0160, 0x0ec0 },
278 { 0x0161, 0x0020 },
279 { 0x0162, 0x0080 },
280 { 0x0163, 0x0800 },
281 { 0x0164, 0x0000 },
282 { 0x0165, 0x0000 },
283 { 0x0166, 0x0000 },
284 { 0x0167, 0x001f },
285 { 0x0170, 0x4e80 },
286 { 0x0171, 0x0020 },
287 { 0x0172, 0x0080 },
288 { 0x0173, 0x0800 },
289 { 0x0174, 0x000c },
290 { 0x0175, 0x0000 },
291 { 0x0190, 0x3300 },
292 { 0x0191, 0x2200 },
293 { 0x0192, 0x0000 },
294 { 0x01b0, 0x4b38 },
295 { 0x01b1, 0x0000 },
296 { 0x01b2, 0x0000 },
297 { 0x01b3, 0x0000 },
298 { 0x01c0, 0x0045 },
299 { 0x01c1, 0x0540 },
300 { 0x01c2, 0x0000 },
301 { 0x01c3, 0x0030 },
302 { 0x01c7, 0x0000 },
303 { 0x01c8, 0x5757 },
304 { 0x01c9, 0x5757 },
305 { 0x01ca, 0x5757 },
306 { 0x01cb, 0x5757 },
307 { 0x01cc, 0x5757 },
308 { 0x01cd, 0x5757 },
309 { 0x01ce, 0x006f },
310 { 0x01da, 0x0000 },
311 { 0x01db, 0x0000 },
312 { 0x01de, 0x7d00 },
313 { 0x01df, 0x10c0 },
314 { 0x01e0, 0x06a1 },
315 { 0x01e1, 0x0000 },
316 { 0x01e2, 0x0000 },
317 { 0x01e3, 0x0000 },
318 { 0x01e4, 0x0001 },
319 { 0x01e6, 0x0000 },
320 { 0x01e7, 0x0000 },
321 { 0x01e8, 0x0000 },
322 { 0x01ea, 0x0000 },
323 { 0x01eb, 0x0000 },
324 { 0x01ec, 0x0000 },
325 { 0x01ed, 0x0000 },
326 { 0x01ee, 0x0000 },
327 { 0x01ef, 0x0000 },
328 { 0x01f0, 0x0000 },
329 { 0x01f1, 0x0000 },
330 { 0x01f2, 0x0000 },
331 { 0x01f6, 0x1e04 },
332 { 0x01f7, 0x01a1 },
333 { 0x01f8, 0x0000 },
334 { 0x01f9, 0x0000 },
335 { 0x01fa, 0x0002 },
336 { 0x01fb, 0x0000 },
337 { 0x01fc, 0x0000 },
338 { 0x01fd, 0x0000 },
339 { 0x01fe, 0x0000 },
340 { 0x0200, 0x066c },
341 { 0x0201, 0x7fff },
342 { 0x0202, 0x7fff },
343 { 0x0203, 0x0000 },
344 { 0x0204, 0x0000 },
345 { 0x0205, 0x0000 },
346 { 0x0206, 0x0000 },
347 { 0x0207, 0x0000 },
348 { 0x0208, 0x0000 },
349 { 0x0256, 0x0000 },
350 { 0x0257, 0x0000 },
351 { 0x0258, 0x0000 },
352 { 0x0259, 0x0000 },
353 { 0x025a, 0x0000 },
354 { 0x025b, 0x3333 },
355 { 0x025c, 0x3333 },
356 { 0x025d, 0x3333 },
357 { 0x025e, 0x0000 },
358 { 0x025f, 0x0000 },
359 { 0x0260, 0x0000 },
360 { 0x0261, 0x0022 },
361 { 0x0262, 0x0300 },
362 { 0x0265, 0x1e80 },
363 { 0x0266, 0x0131 },
364 { 0x0267, 0x0003 },
365 { 0x0268, 0x0000 },
366 { 0x0269, 0x0000 },
367 { 0x026a, 0x0000 },
368 { 0x026b, 0x0000 },
369 { 0x026c, 0x0000 },
370 { 0x026d, 0x0000 },
371 { 0x026e, 0x0000 },
372 { 0x026f, 0x0000 },
373 { 0x0270, 0x0000 },
374 { 0x0271, 0x0000 },
375 { 0x0272, 0x0000 },
376 { 0x0273, 0x0000 },
377 { 0x0280, 0x0000 },
378 { 0x0281, 0x0000 },
379 { 0x0282, 0x0418 },
380 { 0x0283, 0x7fff },
381 { 0x0284, 0x7000 },
382 { 0x0290, 0x01d0 },
383 { 0x0291, 0x0100 },
384 { 0x02fa, 0x0000 },
385 { 0x02fb, 0x0000 },
386 { 0x02fc, 0x0000 },
387 { 0x0300, 0x001f },
388 { 0x0301, 0x032c },
389 { 0x0302, 0x5f21 },
390 { 0x0303, 0x4000 },
391 { 0x0304, 0x4000 },
392 { 0x0305, 0x0600 },
393 { 0x0306, 0x8000 },
394 { 0x0307, 0x0700 },
395 { 0x0308, 0x001f },
396 { 0x0309, 0x032c },
397 { 0x030a, 0x5f21 },
398 { 0x030b, 0x4000 },
399 { 0x030c, 0x4000 },
400 { 0x030d, 0x0600 },
401 { 0x030e, 0x8000 },
402 { 0x030f, 0x0700 },
403 { 0x0310, 0x4560 },
404 { 0x0311, 0xa4a8 },
405 { 0x0312, 0x7418 },
406 { 0x0313, 0x0000 },
407 { 0x0314, 0x0006 },
408 { 0x0315, 0x00ff },
409 { 0x0316, 0xc400 },
410 { 0x0317, 0x4560 },
411 { 0x0318, 0xa4a8 },
412 { 0x0319, 0x7418 },
413 { 0x031a, 0x0000 },
414 { 0x031b, 0x0006 },
415 { 0x031c, 0x00ff },
416 { 0x031d, 0xc400 },
417 { 0x0320, 0x0f20 },
418 { 0x0321, 0x8700 },
419 { 0x0322, 0x7dc2 },
420 { 0x0323, 0xa178 },
421 { 0x0324, 0x5383 },
422 { 0x0325, 0x7dc2 },
423 { 0x0326, 0xa178 },
424 { 0x0327, 0x5383 },
425 { 0x0328, 0x003e },
426 { 0x0329, 0x02c1 },
427 { 0x032a, 0xd37d },
428 { 0x0330, 0x00a6 },
429 { 0x0331, 0x04c3 },
430 { 0x0332, 0x27c8 },
431 { 0x0333, 0xbf50 },
432 { 0x0334, 0x0045 },
433 { 0x0335, 0x2007 },
434 { 0x0336, 0x7418 },
435 { 0x0337, 0x0501 },
436 { 0x0338, 0x0000 },
437 { 0x0339, 0x0010 },
438 { 0x033a, 0x1010 },
439 { 0x0340, 0x0800 },
440 { 0x0341, 0x0800 },
441 { 0x0342, 0x0800 },
442 { 0x0343, 0x0800 },
443 { 0x0344, 0x0000 },
444 { 0x0345, 0x0000 },
445 { 0x0346, 0x0000 },
446 { 0x0347, 0x0000 },
447 { 0x0348, 0x0000 },
448 { 0x0349, 0x0000 },
449 { 0x034a, 0x0000 },
450 { 0x034b, 0x0000 },
451 { 0x034c, 0x0000 },
452 { 0x034d, 0x0000 },
453 { 0x034e, 0x0000 },
454 { 0x034f, 0x0000 },
455 { 0x0350, 0x0000 },
456 { 0x0351, 0x0000 },
457 { 0x0352, 0x0000 },
458 { 0x0353, 0x0000 },
459 { 0x0354, 0x0000 },
460 { 0x0355, 0x0000 },
461 { 0x0356, 0x0000 },
462 { 0x0357, 0x0000 },
463 { 0x0358, 0x0000 },
464 { 0x0359, 0x0000 },
465 { 0x035a, 0x0000 },
466 { 0x035b, 0x0000 },
467 { 0x035c, 0x0000 },
468 { 0x035d, 0x0000 },
469 { 0x035e, 0x2000 },
470 { 0x035f, 0x0000 },
471 { 0x0360, 0x2000 },
472 { 0x0361, 0x2000 },
473 { 0x0362, 0x0000 },
474 { 0x0363, 0x2000 },
475 { 0x0364, 0x0200 },
476 { 0x0365, 0x0000 },
477 { 0x0366, 0x0000 },
478 { 0x0367, 0x0000 },
479 { 0x0368, 0x0000 },
480 { 0x0369, 0x0000 },
481 { 0x036a, 0x0000 },
482 { 0x036b, 0x0000 },
483 { 0x036c, 0x0000 },
484 { 0x036d, 0x0000 },
485 { 0x036e, 0x0200 },
486 { 0x036f, 0x0000 },
487 { 0x0370, 0x0000 },
488 { 0x0371, 0x0000 },
489 { 0x0372, 0x0000 },
490 { 0x0373, 0x0000 },
491 { 0x0374, 0x0000 },
492 { 0x0375, 0x0000 },
493 { 0x0376, 0x0000 },
494 { 0x0377, 0x0000 },
495 { 0x03d0, 0x0000 },
496 { 0x03d1, 0x0000 },
497 { 0x03d2, 0x0000 },
498 { 0x03d3, 0x0000 },
499 { 0x03d4, 0x2000 },
500 { 0x03d5, 0x2000 },
501 { 0x03d6, 0x0000 },
502 { 0x03d7, 0x0000 },
503 { 0x03d8, 0x2000 },
504 { 0x03d9, 0x2000 },
505 { 0x03da, 0x2000 },
506 { 0x03db, 0x2000 },
507 { 0x03dc, 0x0000 },
508 { 0x03dd, 0x0000 },
509 { 0x03de, 0x0000 },
510 { 0x03df, 0x2000 },
511 { 0x03e0, 0x0000 },
512 { 0x03e1, 0x0000 },
513 { 0x03e2, 0x0000 },
514 { 0x03e3, 0x0000 },
515 { 0x03e4, 0x0000 },
516 { 0x03e5, 0x0000 },
517 { 0x03e6, 0x0000 },
518 { 0x03e7, 0x0000 },
519 { 0x03e8, 0x0000 },
520 { 0x03e9, 0x0000 },
521 { 0x03ea, 0x0000 },
522 { 0x03eb, 0x0000 },
523 { 0x03ec, 0x0000 },
524 { 0x03ed, 0x0000 },
525 { 0x03ee, 0x0000 },
526 { 0x03ef, 0x0000 },
527 { 0x03f0, 0x0800 },
528 { 0x03f1, 0x0800 },
529 { 0x03f2, 0x0800 },
530 { 0x03f3, 0x0800 },
531};
532
533static bool rt5659_volatile_register(struct device *dev, unsigned int reg)
534{
535 switch (reg) {
536 case RT5659_RESET:
537 case RT5659_EJD_CTRL_2:
538 case RT5659_SILENCE_CTRL:
539 case RT5659_DAC2_DIG_VOL:
540 case RT5659_HP_IMP_GAIN_2:
541 case RT5659_PDM_OUT_CTRL:
542 case RT5659_PDM_DATA_CTRL_1:
543 case RT5659_PDM_DATA_CTRL_4:
544 case RT5659_HAPTIC_GEN_CTRL_1:
545 case RT5659_HAPTIC_GEN_CTRL_3:
546 case RT5659_HAPTIC_LPF_CTRL_3:
547 case RT5659_CLK_DET:
548 case RT5659_MICBIAS_1:
549 case RT5659_ASRC_11:
550 case RT5659_ADC_EQ_CTRL_1:
551 case RT5659_DAC_EQ_CTRL_1:
552 case RT5659_INT_ST_1:
553 case RT5659_INT_ST_2:
554 case RT5659_GPIO_STA:
555 case RT5659_SINE_GEN_CTRL_1:
556 case RT5659_IL_CMD_1:
557 case RT5659_4BTN_IL_CMD_1:
558 case RT5659_PSV_IL_CMD_1:
559 case RT5659_AJD1_CTRL:
560 case RT5659_AJD2_AJD3_CTRL:
561 case RT5659_JD_CTRL_3:
562 case RT5659_VENDOR_ID:
563 case RT5659_VENDOR_ID_1:
564 case RT5659_DEVICE_ID:
565 case RT5659_MEMORY_TEST:
566 case RT5659_SOFT_RAMP_DEPOP_DAC_CLK_CTRL:
567 case RT5659_VOL_TEST:
568 case RT5659_STO_NG2_CTRL_1:
569 case RT5659_STO_NG2_CTRL_5:
570 case RT5659_STO_NG2_CTRL_6:
571 case RT5659_STO_NG2_CTRL_7:
572 case RT5659_MONO_NG2_CTRL_1:
573 case RT5659_MONO_NG2_CTRL_5:
574 case RT5659_MONO_NG2_CTRL_6:
575 case RT5659_HP_IMP_SENS_CTRL_1:
576 case RT5659_HP_IMP_SENS_CTRL_3:
577 case RT5659_HP_IMP_SENS_CTRL_4:
578 case RT5659_HP_CALIB_CTRL_1:
579 case RT5659_HP_CALIB_CTRL_9:
580 case RT5659_HP_CALIB_STA_1:
581 case RT5659_HP_CALIB_STA_2:
582 case RT5659_HP_CALIB_STA_3:
583 case RT5659_HP_CALIB_STA_4:
584 case RT5659_HP_CALIB_STA_5:
585 case RT5659_HP_CALIB_STA_6:
586 case RT5659_HP_CALIB_STA_7:
587 case RT5659_HP_CALIB_STA_8:
588 case RT5659_HP_CALIB_STA_9:
589 case RT5659_MONO_AMP_CALIB_CTRL_1:
590 case RT5659_MONO_AMP_CALIB_CTRL_3:
591 case RT5659_MONO_AMP_CALIB_STA_1:
592 case RT5659_MONO_AMP_CALIB_STA_2:
593 case RT5659_MONO_AMP_CALIB_STA_3:
594 case RT5659_MONO_AMP_CALIB_STA_4:
595 case RT5659_SPK_PWR_LMT_STA_1:
596 case RT5659_SPK_PWR_LMT_STA_2:
597 case RT5659_SPK_PWR_LMT_STA_3:
598 case RT5659_SPK_PWR_LMT_STA_4:
599 case RT5659_SPK_PWR_LMT_STA_5:
600 case RT5659_SPK_PWR_LMT_STA_6:
601 case RT5659_SPK_DC_CAILB_CTRL_1:
602 case RT5659_SPK_DC_CAILB_STA_1:
603 case RT5659_SPK_DC_CAILB_STA_2:
604 case RT5659_SPK_DC_CAILB_STA_3:
605 case RT5659_SPK_DC_CAILB_STA_4:
606 case RT5659_SPK_DC_CAILB_STA_5:
607 case RT5659_SPK_DC_CAILB_STA_6:
608 case RT5659_SPK_DC_CAILB_STA_7:
609 case RT5659_SPK_DC_CAILB_STA_8:
610 case RT5659_SPK_DC_CAILB_STA_9:
611 case RT5659_SPK_DC_CAILB_STA_10:
612 case RT5659_SPK_VDD_STA_1:
613 case RT5659_SPK_VDD_STA_2:
614 case RT5659_SPK_DC_DET_CTRL_1:
615 case RT5659_PURE_DC_DET_CTRL_1:
616 case RT5659_PURE_DC_DET_CTRL_2:
617 case RT5659_DRC1_PRIV_1:
618 case RT5659_DRC1_PRIV_4:
619 case RT5659_DRC1_PRIV_5:
620 case RT5659_DRC1_PRIV_6:
621 case RT5659_DRC1_PRIV_7:
622 case RT5659_DRC2_PRIV_1:
623 case RT5659_DRC2_PRIV_4:
624 case RT5659_DRC2_PRIV_5:
625 case RT5659_DRC2_PRIV_6:
626 case RT5659_DRC2_PRIV_7:
627 case RT5659_ALC_PGA_STA_1:
628 case RT5659_ALC_PGA_STA_2:
629 case RT5659_ALC_PGA_STA_3:
630 return true;
631 default:
632 return false;
633 }
634}
635
636static bool rt5659_readable_register(struct device *dev, unsigned int reg)
637{
638 switch (reg) {
639 case RT5659_RESET:
640 case RT5659_SPO_VOL:
641 case RT5659_HP_VOL:
642 case RT5659_LOUT:
643 case RT5659_MONO_OUT:
644 case RT5659_HPL_GAIN:
645 case RT5659_HPR_GAIN:
646 case RT5659_MONO_GAIN:
647 case RT5659_SPDIF_CTRL_1:
648 case RT5659_SPDIF_CTRL_2:
649 case RT5659_CAL_BST_CTRL:
650 case RT5659_IN1_IN2:
651 case RT5659_IN3_IN4:
652 case RT5659_INL1_INR1_VOL:
653 case RT5659_EJD_CTRL_1:
654 case RT5659_EJD_CTRL_2:
655 case RT5659_EJD_CTRL_3:
656 case RT5659_SILENCE_CTRL:
657 case RT5659_PSV_CTRL:
658 case RT5659_SIDETONE_CTRL:
659 case RT5659_DAC1_DIG_VOL:
660 case RT5659_DAC2_DIG_VOL:
661 case RT5659_DAC_CTRL:
662 case RT5659_STO1_ADC_DIG_VOL:
663 case RT5659_MONO_ADC_DIG_VOL:
664 case RT5659_STO2_ADC_DIG_VOL:
665 case RT5659_STO1_BOOST:
666 case RT5659_MONO_BOOST:
667 case RT5659_STO2_BOOST:
668 case RT5659_HP_IMP_GAIN_1:
669 case RT5659_HP_IMP_GAIN_2:
670 case RT5659_STO1_ADC_MIXER:
671 case RT5659_MONO_ADC_MIXER:
672 case RT5659_AD_DA_MIXER:
673 case RT5659_STO_DAC_MIXER:
674 case RT5659_MONO_DAC_MIXER:
675 case RT5659_DIG_MIXER:
676 case RT5659_A_DAC_MUX:
677 case RT5659_DIG_INF23_DATA:
678 case RT5659_PDM_OUT_CTRL:
679 case RT5659_PDM_DATA_CTRL_1:
680 case RT5659_PDM_DATA_CTRL_2:
681 case RT5659_PDM_DATA_CTRL_3:
682 case RT5659_PDM_DATA_CTRL_4:
683 case RT5659_SPDIF_CTRL:
684 case RT5659_REC1_GAIN:
685 case RT5659_REC1_L1_MIXER:
686 case RT5659_REC1_L2_MIXER:
687 case RT5659_REC1_R1_MIXER:
688 case RT5659_REC1_R2_MIXER:
689 case RT5659_CAL_REC:
690 case RT5659_REC2_L1_MIXER:
691 case RT5659_REC2_L2_MIXER:
692 case RT5659_REC2_R1_MIXER:
693 case RT5659_REC2_R2_MIXER:
694 case RT5659_SPK_L_MIXER:
695 case RT5659_SPK_R_MIXER:
696 case RT5659_SPO_AMP_GAIN:
697 case RT5659_ALC_BACK_GAIN:
698 case RT5659_MONOMIX_GAIN:
699 case RT5659_MONOMIX_IN_GAIN:
700 case RT5659_OUT_L_GAIN:
701 case RT5659_OUT_L_MIXER:
702 case RT5659_OUT_R_GAIN:
703 case RT5659_OUT_R_MIXER:
704 case RT5659_LOUT_MIXER:
705 case RT5659_HAPTIC_GEN_CTRL_1:
706 case RT5659_HAPTIC_GEN_CTRL_2:
707 case RT5659_HAPTIC_GEN_CTRL_3:
708 case RT5659_HAPTIC_GEN_CTRL_4:
709 case RT5659_HAPTIC_GEN_CTRL_5:
710 case RT5659_HAPTIC_GEN_CTRL_6:
711 case RT5659_HAPTIC_GEN_CTRL_7:
712 case RT5659_HAPTIC_GEN_CTRL_8:
713 case RT5659_HAPTIC_GEN_CTRL_9:
714 case RT5659_HAPTIC_GEN_CTRL_10:
715 case RT5659_HAPTIC_GEN_CTRL_11:
716 case RT5659_HAPTIC_LPF_CTRL_1:
717 case RT5659_HAPTIC_LPF_CTRL_2:
718 case RT5659_HAPTIC_LPF_CTRL_3:
719 case RT5659_PWR_DIG_1:
720 case RT5659_PWR_DIG_2:
721 case RT5659_PWR_ANLG_1:
722 case RT5659_PWR_ANLG_2:
723 case RT5659_PWR_ANLG_3:
724 case RT5659_PWR_MIXER:
725 case RT5659_PWR_VOL:
726 case RT5659_PRIV_INDEX:
727 case RT5659_CLK_DET:
728 case RT5659_PRIV_DATA:
729 case RT5659_PRE_DIV_1:
730 case RT5659_PRE_DIV_2:
731 case RT5659_I2S1_SDP:
732 case RT5659_I2S2_SDP:
733 case RT5659_I2S3_SDP:
734 case RT5659_ADDA_CLK_1:
735 case RT5659_ADDA_CLK_2:
736 case RT5659_DMIC_CTRL_1:
737 case RT5659_DMIC_CTRL_2:
738 case RT5659_TDM_CTRL_1:
739 case RT5659_TDM_CTRL_2:
740 case RT5659_TDM_CTRL_3:
741 case RT5659_TDM_CTRL_4:
742 case RT5659_TDM_CTRL_5:
743 case RT5659_GLB_CLK:
744 case RT5659_PLL_CTRL_1:
745 case RT5659_PLL_CTRL_2:
746 case RT5659_ASRC_1:
747 case RT5659_ASRC_2:
748 case RT5659_ASRC_3:
749 case RT5659_ASRC_4:
750 case RT5659_ASRC_5:
751 case RT5659_ASRC_6:
752 case RT5659_ASRC_7:
753 case RT5659_ASRC_8:
754 case RT5659_ASRC_9:
755 case RT5659_ASRC_10:
756 case RT5659_DEPOP_1:
757 case RT5659_DEPOP_2:
758 case RT5659_DEPOP_3:
759 case RT5659_HP_CHARGE_PUMP_1:
760 case RT5659_HP_CHARGE_PUMP_2:
761 case RT5659_MICBIAS_1:
762 case RT5659_MICBIAS_2:
763 case RT5659_ASRC_11:
764 case RT5659_ASRC_12:
765 case RT5659_ASRC_13:
766 case RT5659_REC_M1_M2_GAIN_CTRL:
767 case RT5659_RC_CLK_CTRL:
768 case RT5659_CLASSD_CTRL_1:
769 case RT5659_CLASSD_CTRL_2:
770 case RT5659_ADC_EQ_CTRL_1:
771 case RT5659_ADC_EQ_CTRL_2:
772 case RT5659_DAC_EQ_CTRL_1:
773 case RT5659_DAC_EQ_CTRL_2:
774 case RT5659_DAC_EQ_CTRL_3:
775 case RT5659_IRQ_CTRL_1:
776 case RT5659_IRQ_CTRL_2:
777 case RT5659_IRQ_CTRL_3:
778 case RT5659_IRQ_CTRL_4:
779 case RT5659_IRQ_CTRL_5:
780 case RT5659_IRQ_CTRL_6:
781 case RT5659_INT_ST_1:
782 case RT5659_INT_ST_2:
783 case RT5659_GPIO_CTRL_1:
784 case RT5659_GPIO_CTRL_2:
785 case RT5659_GPIO_CTRL_3:
786 case RT5659_GPIO_CTRL_4:
787 case RT5659_GPIO_CTRL_5:
788 case RT5659_GPIO_STA:
789 case RT5659_SINE_GEN_CTRL_1:
790 case RT5659_SINE_GEN_CTRL_2:
791 case RT5659_SINE_GEN_CTRL_3:
792 case RT5659_HP_AMP_DET_CTRL_1:
793 case RT5659_HP_AMP_DET_CTRL_2:
794 case RT5659_SV_ZCD_1:
795 case RT5659_SV_ZCD_2:
796 case RT5659_IL_CMD_1:
797 case RT5659_IL_CMD_2:
798 case RT5659_IL_CMD_3:
799 case RT5659_IL_CMD_4:
800 case RT5659_4BTN_IL_CMD_1:
801 case RT5659_4BTN_IL_CMD_2:
802 case RT5659_4BTN_IL_CMD_3:
803 case RT5659_PSV_IL_CMD_1:
804 case RT5659_PSV_IL_CMD_2:
805 case RT5659_ADC_STO1_HP_CTRL_1:
806 case RT5659_ADC_STO1_HP_CTRL_2:
807 case RT5659_ADC_MONO_HP_CTRL_1:
808 case RT5659_ADC_MONO_HP_CTRL_2:
809 case RT5659_AJD1_CTRL:
810 case RT5659_AJD2_AJD3_CTRL:
811 case RT5659_JD1_THD:
812 case RT5659_JD2_THD:
813 case RT5659_JD3_THD:
814 case RT5659_JD_CTRL_1:
815 case RT5659_JD_CTRL_2:
816 case RT5659_JD_CTRL_3:
817 case RT5659_JD_CTRL_4:
818 case RT5659_DIG_MISC:
819 case RT5659_DUMMY_2:
820 case RT5659_DUMMY_3:
821 case RT5659_VENDOR_ID:
822 case RT5659_VENDOR_ID_1:
823 case RT5659_DEVICE_ID:
824 case RT5659_DAC_ADC_DIG_VOL:
825 case RT5659_BIAS_CUR_CTRL_1:
826 case RT5659_BIAS_CUR_CTRL_2:
827 case RT5659_BIAS_CUR_CTRL_3:
828 case RT5659_BIAS_CUR_CTRL_4:
829 case RT5659_BIAS_CUR_CTRL_5:
830 case RT5659_BIAS_CUR_CTRL_6:
831 case RT5659_BIAS_CUR_CTRL_7:
832 case RT5659_BIAS_CUR_CTRL_8:
833 case RT5659_BIAS_CUR_CTRL_9:
834 case RT5659_BIAS_CUR_CTRL_10:
835 case RT5659_MEMORY_TEST:
836 case RT5659_VREF_REC_OP_FB_CAP_CTRL:
837 case RT5659_CLASSD_0:
838 case RT5659_CLASSD_1:
839 case RT5659_CLASSD_2:
840 case RT5659_CLASSD_3:
841 case RT5659_CLASSD_4:
842 case RT5659_CLASSD_5:
843 case RT5659_CLASSD_6:
844 case RT5659_CLASSD_7:
845 case RT5659_CLASSD_8:
846 case RT5659_CLASSD_9:
847 case RT5659_CLASSD_10:
848 case RT5659_CHARGE_PUMP_1:
849 case RT5659_CHARGE_PUMP_2:
850 case RT5659_DIG_IN_CTRL_1:
851 case RT5659_DIG_IN_CTRL_2:
852 case RT5659_PAD_DRIVING_CTRL:
853 case RT5659_SOFT_RAMP_DEPOP:
854 case RT5659_PLL:
855 case RT5659_CHOP_DAC:
856 case RT5659_CHOP_ADC:
857 case RT5659_CALIB_ADC_CTRL:
858 case RT5659_SOFT_RAMP_DEPOP_DAC_CLK_CTRL:
859 case RT5659_VOL_TEST:
860 case RT5659_TEST_MODE_CTRL_1:
861 case RT5659_TEST_MODE_CTRL_2:
862 case RT5659_TEST_MODE_CTRL_3:
863 case RT5659_TEST_MODE_CTRL_4:
864 case RT5659_BASSBACK_CTRL:
865 case RT5659_MP3_PLUS_CTRL_1:
866 case RT5659_MP3_PLUS_CTRL_2:
867 case RT5659_MP3_HPF_A1:
868 case RT5659_MP3_HPF_A2:
869 case RT5659_MP3_HPF_H0:
870 case RT5659_MP3_LPF_H0:
871 case RT5659_3D_SPK_CTRL:
872 case RT5659_3D_SPK_COEF_1:
873 case RT5659_3D_SPK_COEF_2:
874 case RT5659_3D_SPK_COEF_3:
875 case RT5659_3D_SPK_COEF_4:
876 case RT5659_3D_SPK_COEF_5:
877 case RT5659_3D_SPK_COEF_6:
878 case RT5659_3D_SPK_COEF_7:
879 case RT5659_STO_NG2_CTRL_1:
880 case RT5659_STO_NG2_CTRL_2:
881 case RT5659_STO_NG2_CTRL_3:
882 case RT5659_STO_NG2_CTRL_4:
883 case RT5659_STO_NG2_CTRL_5:
884 case RT5659_STO_NG2_CTRL_6:
885 case RT5659_STO_NG2_CTRL_7:
886 case RT5659_STO_NG2_CTRL_8:
887 case RT5659_MONO_NG2_CTRL_1:
888 case RT5659_MONO_NG2_CTRL_2:
889 case RT5659_MONO_NG2_CTRL_3:
890 case RT5659_MONO_NG2_CTRL_4:
891 case RT5659_MONO_NG2_CTRL_5:
892 case RT5659_MONO_NG2_CTRL_6:
893 case RT5659_MID_HP_AMP_DET:
894 case RT5659_LOW_HP_AMP_DET:
895 case RT5659_LDO_CTRL:
896 case RT5659_HP_DECROSS_CTRL_1:
897 case RT5659_HP_DECROSS_CTRL_2:
898 case RT5659_HP_DECROSS_CTRL_3:
899 case RT5659_HP_DECROSS_CTRL_4:
900 case RT5659_HP_IMP_SENS_CTRL_1:
901 case RT5659_HP_IMP_SENS_CTRL_2:
902 case RT5659_HP_IMP_SENS_CTRL_3:
903 case RT5659_HP_IMP_SENS_CTRL_4:
904 case RT5659_HP_IMP_SENS_MAP_1:
905 case RT5659_HP_IMP_SENS_MAP_2:
906 case RT5659_HP_IMP_SENS_MAP_3:
907 case RT5659_HP_IMP_SENS_MAP_4:
908 case RT5659_HP_IMP_SENS_MAP_5:
909 case RT5659_HP_IMP_SENS_MAP_6:
910 case RT5659_HP_IMP_SENS_MAP_7:
911 case RT5659_HP_IMP_SENS_MAP_8:
912 case RT5659_HP_LOGIC_CTRL_1:
913 case RT5659_HP_LOGIC_CTRL_2:
914 case RT5659_HP_CALIB_CTRL_1:
915 case RT5659_HP_CALIB_CTRL_2:
916 case RT5659_HP_CALIB_CTRL_3:
917 case RT5659_HP_CALIB_CTRL_4:
918 case RT5659_HP_CALIB_CTRL_5:
919 case RT5659_HP_CALIB_CTRL_6:
920 case RT5659_HP_CALIB_CTRL_7:
921 case RT5659_HP_CALIB_CTRL_9:
922 case RT5659_HP_CALIB_CTRL_10:
923 case RT5659_HP_CALIB_CTRL_11:
924 case RT5659_HP_CALIB_STA_1:
925 case RT5659_HP_CALIB_STA_2:
926 case RT5659_HP_CALIB_STA_3:
927 case RT5659_HP_CALIB_STA_4:
928 case RT5659_HP_CALIB_STA_5:
929 case RT5659_HP_CALIB_STA_6:
930 case RT5659_HP_CALIB_STA_7:
931 case RT5659_HP_CALIB_STA_8:
932 case RT5659_HP_CALIB_STA_9:
933 case RT5659_MONO_AMP_CALIB_CTRL_1:
934 case RT5659_MONO_AMP_CALIB_CTRL_2:
935 case RT5659_MONO_AMP_CALIB_CTRL_3:
936 case RT5659_MONO_AMP_CALIB_CTRL_4:
937 case RT5659_MONO_AMP_CALIB_CTRL_5:
938 case RT5659_MONO_AMP_CALIB_STA_1:
939 case RT5659_MONO_AMP_CALIB_STA_2:
940 case RT5659_MONO_AMP_CALIB_STA_3:
941 case RT5659_MONO_AMP_CALIB_STA_4:
942 case RT5659_SPK_PWR_LMT_CTRL_1:
943 case RT5659_SPK_PWR_LMT_CTRL_2:
944 case RT5659_SPK_PWR_LMT_CTRL_3:
945 case RT5659_SPK_PWR_LMT_STA_1:
946 case RT5659_SPK_PWR_LMT_STA_2:
947 case RT5659_SPK_PWR_LMT_STA_3:
948 case RT5659_SPK_PWR_LMT_STA_4:
949 case RT5659_SPK_PWR_LMT_STA_5:
950 case RT5659_SPK_PWR_LMT_STA_6:
951 case RT5659_FLEX_SPK_BST_CTRL_1:
952 case RT5659_FLEX_SPK_BST_CTRL_2:
953 case RT5659_FLEX_SPK_BST_CTRL_3:
954 case RT5659_FLEX_SPK_BST_CTRL_4:
955 case RT5659_SPK_EX_LMT_CTRL_1:
956 case RT5659_SPK_EX_LMT_CTRL_2:
957 case RT5659_SPK_EX_LMT_CTRL_3:
958 case RT5659_SPK_EX_LMT_CTRL_4:
959 case RT5659_SPK_EX_LMT_CTRL_5:
960 case RT5659_SPK_EX_LMT_CTRL_6:
961 case RT5659_SPK_EX_LMT_CTRL_7:
962 case RT5659_ADJ_HPF_CTRL_1:
963 case RT5659_ADJ_HPF_CTRL_2:
964 case RT5659_SPK_DC_CAILB_CTRL_1:
965 case RT5659_SPK_DC_CAILB_CTRL_2:
966 case RT5659_SPK_DC_CAILB_CTRL_3:
967 case RT5659_SPK_DC_CAILB_CTRL_4:
968 case RT5659_SPK_DC_CAILB_CTRL_5:
969 case RT5659_SPK_DC_CAILB_STA_1:
970 case RT5659_SPK_DC_CAILB_STA_2:
971 case RT5659_SPK_DC_CAILB_STA_3:
972 case RT5659_SPK_DC_CAILB_STA_4:
973 case RT5659_SPK_DC_CAILB_STA_5:
974 case RT5659_SPK_DC_CAILB_STA_6:
975 case RT5659_SPK_DC_CAILB_STA_7:
976 case RT5659_SPK_DC_CAILB_STA_8:
977 case RT5659_SPK_DC_CAILB_STA_9:
978 case RT5659_SPK_DC_CAILB_STA_10:
979 case RT5659_SPK_VDD_STA_1:
980 case RT5659_SPK_VDD_STA_2:
981 case RT5659_SPK_DC_DET_CTRL_1:
982 case RT5659_SPK_DC_DET_CTRL_2:
983 case RT5659_SPK_DC_DET_CTRL_3:
984 case RT5659_PURE_DC_DET_CTRL_1:
985 case RT5659_PURE_DC_DET_CTRL_2:
986 case RT5659_DUMMY_4:
987 case RT5659_DUMMY_5:
988 case RT5659_DUMMY_6:
989 case RT5659_DRC1_CTRL_1:
990 case RT5659_DRC1_CTRL_2:
991 case RT5659_DRC1_CTRL_3:
992 case RT5659_DRC1_CTRL_4:
993 case RT5659_DRC1_CTRL_5:
994 case RT5659_DRC1_CTRL_6:
995 case RT5659_DRC1_HARD_LMT_CTRL_1:
996 case RT5659_DRC1_HARD_LMT_CTRL_2:
997 case RT5659_DRC2_CTRL_1:
998 case RT5659_DRC2_CTRL_2:
999 case RT5659_DRC2_CTRL_3:
1000 case RT5659_DRC2_CTRL_4:
1001 case RT5659_DRC2_CTRL_5:
1002 case RT5659_DRC2_CTRL_6:
1003 case RT5659_DRC2_HARD_LMT_CTRL_1:
1004 case RT5659_DRC2_HARD_LMT_CTRL_2:
1005 case RT5659_DRC1_PRIV_1:
1006 case RT5659_DRC1_PRIV_2:
1007 case RT5659_DRC1_PRIV_3:
1008 case RT5659_DRC1_PRIV_4:
1009 case RT5659_DRC1_PRIV_5:
1010 case RT5659_DRC1_PRIV_6:
1011 case RT5659_DRC1_PRIV_7:
1012 case RT5659_DRC2_PRIV_1:
1013 case RT5659_DRC2_PRIV_2:
1014 case RT5659_DRC2_PRIV_3:
1015 case RT5659_DRC2_PRIV_4:
1016 case RT5659_DRC2_PRIV_5:
1017 case RT5659_DRC2_PRIV_6:
1018 case RT5659_DRC2_PRIV_7:
1019 case RT5659_MULTI_DRC_CTRL:
1020 case RT5659_CROSS_OVER_1:
1021 case RT5659_CROSS_OVER_2:
1022 case RT5659_CROSS_OVER_3:
1023 case RT5659_CROSS_OVER_4:
1024 case RT5659_CROSS_OVER_5:
1025 case RT5659_CROSS_OVER_6:
1026 case RT5659_CROSS_OVER_7:
1027 case RT5659_CROSS_OVER_8:
1028 case RT5659_CROSS_OVER_9:
1029 case RT5659_CROSS_OVER_10:
1030 case RT5659_ALC_PGA_CTRL_1:
1031 case RT5659_ALC_PGA_CTRL_2:
1032 case RT5659_ALC_PGA_CTRL_3:
1033 case RT5659_ALC_PGA_CTRL_4:
1034 case RT5659_ALC_PGA_CTRL_5:
1035 case RT5659_ALC_PGA_CTRL_6:
1036 case RT5659_ALC_PGA_CTRL_7:
1037 case RT5659_ALC_PGA_CTRL_8:
1038 case RT5659_ALC_PGA_STA_1:
1039 case RT5659_ALC_PGA_STA_2:
1040 case RT5659_ALC_PGA_STA_3:
1041 case RT5659_DAC_L_EQ_PRE_VOL:
1042 case RT5659_DAC_R_EQ_PRE_VOL:
1043 case RT5659_DAC_L_EQ_POST_VOL:
1044 case RT5659_DAC_R_EQ_POST_VOL:
1045 case RT5659_DAC_L_EQ_LPF1_A1:
1046 case RT5659_DAC_L_EQ_LPF1_H0:
1047 case RT5659_DAC_R_EQ_LPF1_A1:
1048 case RT5659_DAC_R_EQ_LPF1_H0:
1049 case RT5659_DAC_L_EQ_BPF2_A1:
1050 case RT5659_DAC_L_EQ_BPF2_A2:
1051 case RT5659_DAC_L_EQ_BPF2_H0:
1052 case RT5659_DAC_R_EQ_BPF2_A1:
1053 case RT5659_DAC_R_EQ_BPF2_A2:
1054 case RT5659_DAC_R_EQ_BPF2_H0:
1055 case RT5659_DAC_L_EQ_BPF3_A1:
1056 case RT5659_DAC_L_EQ_BPF3_A2:
1057 case RT5659_DAC_L_EQ_BPF3_H0:
1058 case RT5659_DAC_R_EQ_BPF3_A1:
1059 case RT5659_DAC_R_EQ_BPF3_A2:
1060 case RT5659_DAC_R_EQ_BPF3_H0:
1061 case RT5659_DAC_L_EQ_BPF4_A1:
1062 case RT5659_DAC_L_EQ_BPF4_A2:
1063 case RT5659_DAC_L_EQ_BPF4_H0:
1064 case RT5659_DAC_R_EQ_BPF4_A1:
1065 case RT5659_DAC_R_EQ_BPF4_A2:
1066 case RT5659_DAC_R_EQ_BPF4_H0:
1067 case RT5659_DAC_L_EQ_HPF1_A1:
1068 case RT5659_DAC_L_EQ_HPF1_H0:
1069 case RT5659_DAC_R_EQ_HPF1_A1:
1070 case RT5659_DAC_R_EQ_HPF1_H0:
1071 case RT5659_DAC_L_EQ_HPF2_A1:
1072 case RT5659_DAC_L_EQ_HPF2_A2:
1073 case RT5659_DAC_L_EQ_HPF2_H0:
1074 case RT5659_DAC_R_EQ_HPF2_A1:
1075 case RT5659_DAC_R_EQ_HPF2_A2:
1076 case RT5659_DAC_R_EQ_HPF2_H0:
1077 case RT5659_DAC_L_BI_EQ_BPF1_H0_1:
1078 case RT5659_DAC_L_BI_EQ_BPF1_H0_2:
1079 case RT5659_DAC_L_BI_EQ_BPF1_B1_1:
1080 case RT5659_DAC_L_BI_EQ_BPF1_B1_2:
1081 case RT5659_DAC_L_BI_EQ_BPF1_B2_1:
1082 case RT5659_DAC_L_BI_EQ_BPF1_B2_2:
1083 case RT5659_DAC_L_BI_EQ_BPF1_A1_1:
1084 case RT5659_DAC_L_BI_EQ_BPF1_A1_2:
1085 case RT5659_DAC_L_BI_EQ_BPF1_A2_1:
1086 case RT5659_DAC_L_BI_EQ_BPF1_A2_2:
1087 case RT5659_DAC_R_BI_EQ_BPF1_H0_1:
1088 case RT5659_DAC_R_BI_EQ_BPF1_H0_2:
1089 case RT5659_DAC_R_BI_EQ_BPF1_B1_1:
1090 case RT5659_DAC_R_BI_EQ_BPF1_B1_2:
1091 case RT5659_DAC_R_BI_EQ_BPF1_B2_1:
1092 case RT5659_DAC_R_BI_EQ_BPF1_B2_2:
1093 case RT5659_DAC_R_BI_EQ_BPF1_A1_1:
1094 case RT5659_DAC_R_BI_EQ_BPF1_A1_2:
1095 case RT5659_DAC_R_BI_EQ_BPF1_A2_1:
1096 case RT5659_DAC_R_BI_EQ_BPF1_A2_2:
1097 case RT5659_ADC_L_EQ_LPF1_A1:
1098 case RT5659_ADC_R_EQ_LPF1_A1:
1099 case RT5659_ADC_L_EQ_LPF1_H0:
1100 case RT5659_ADC_R_EQ_LPF1_H0:
1101 case RT5659_ADC_L_EQ_BPF1_A1:
1102 case RT5659_ADC_R_EQ_BPF1_A1:
1103 case RT5659_ADC_L_EQ_BPF1_A2:
1104 case RT5659_ADC_R_EQ_BPF1_A2:
1105 case RT5659_ADC_L_EQ_BPF1_H0:
1106 case RT5659_ADC_R_EQ_BPF1_H0:
1107 case RT5659_ADC_L_EQ_BPF2_A1:
1108 case RT5659_ADC_R_EQ_BPF2_A1:
1109 case RT5659_ADC_L_EQ_BPF2_A2:
1110 case RT5659_ADC_R_EQ_BPF2_A2:
1111 case RT5659_ADC_L_EQ_BPF2_H0:
1112 case RT5659_ADC_R_EQ_BPF2_H0:
1113 case RT5659_ADC_L_EQ_BPF3_A1:
1114 case RT5659_ADC_R_EQ_BPF3_A1:
1115 case RT5659_ADC_L_EQ_BPF3_A2:
1116 case RT5659_ADC_R_EQ_BPF3_A2:
1117 case RT5659_ADC_L_EQ_BPF3_H0:
1118 case RT5659_ADC_R_EQ_BPF3_H0:
1119 case RT5659_ADC_L_EQ_BPF4_A1:
1120 case RT5659_ADC_R_EQ_BPF4_A1:
1121 case RT5659_ADC_L_EQ_BPF4_A2:
1122 case RT5659_ADC_R_EQ_BPF4_A2:
1123 case RT5659_ADC_L_EQ_BPF4_H0:
1124 case RT5659_ADC_R_EQ_BPF4_H0:
1125 case RT5659_ADC_L_EQ_HPF1_A1:
1126 case RT5659_ADC_R_EQ_HPF1_A1:
1127 case RT5659_ADC_L_EQ_HPF1_H0:
1128 case RT5659_ADC_R_EQ_HPF1_H0:
1129 case RT5659_ADC_L_EQ_PRE_VOL:
1130 case RT5659_ADC_R_EQ_PRE_VOL:
1131 case RT5659_ADC_L_EQ_POST_VOL:
1132 case RT5659_ADC_R_EQ_POST_VOL:
1133 return true;
1134 default:
1135 return false;
1136 }
1137}
1138
1139static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2325, 75, 0);
1140static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
1141static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
1142static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
1143static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
1144static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
1145static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
1146
1147/* Interface data select */
1148static const char * const rt5659_data_select[] = {
1149 "L/R", "R/L", "L/L", "R/R"
1150};
1151
1152static const SOC_ENUM_SINGLE_DECL(rt5659_if1_01_adc_enum,
1153 RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT01_SFT, rt5659_data_select);
1154
1155static const SOC_ENUM_SINGLE_DECL(rt5659_if1_23_adc_enum,
1156 RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT23_SFT, rt5659_data_select);
1157
1158static const SOC_ENUM_SINGLE_DECL(rt5659_if1_45_adc_enum,
1159 RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT45_SFT, rt5659_data_select);
1160
1161static const SOC_ENUM_SINGLE_DECL(rt5659_if1_67_adc_enum,
1162 RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT67_SFT, rt5659_data_select);
1163
1164static const SOC_ENUM_SINGLE_DECL(rt5659_if2_dac_enum,
1165 RT5659_DIG_INF23_DATA, RT5659_IF2_DAC_SEL_SFT, rt5659_data_select);
1166
1167static const SOC_ENUM_SINGLE_DECL(rt5659_if2_adc_enum,
1168 RT5659_DIG_INF23_DATA, RT5659_IF2_ADC_SEL_SFT, rt5659_data_select);
1169
1170static const SOC_ENUM_SINGLE_DECL(rt5659_if3_dac_enum,
1171 RT5659_DIG_INF23_DATA, RT5659_IF3_DAC_SEL_SFT, rt5659_data_select);
1172
1173static const SOC_ENUM_SINGLE_DECL(rt5659_if3_adc_enum,
1174 RT5659_DIG_INF23_DATA, RT5659_IF3_ADC_SEL_SFT, rt5659_data_select);
1175
1176static const struct snd_kcontrol_new rt5659_if1_01_adc_swap_mux =
1177 SOC_DAPM_ENUM("IF1 01 ADC Swap Source", rt5659_if1_01_adc_enum);
1178
1179static const struct snd_kcontrol_new rt5659_if1_23_adc_swap_mux =
1180 SOC_DAPM_ENUM("IF1 23 ADC1 Swap Source", rt5659_if1_23_adc_enum);
1181
1182static const struct snd_kcontrol_new rt5659_if1_45_adc_swap_mux =
1183 SOC_DAPM_ENUM("IF1 45 ADC1 Swap Source", rt5659_if1_45_adc_enum);
1184
1185static const struct snd_kcontrol_new rt5659_if1_67_adc_swap_mux =
1186 SOC_DAPM_ENUM("IF1 67 ADC1 Swap Source", rt5659_if1_67_adc_enum);
1187
1188static const struct snd_kcontrol_new rt5659_if2_dac_swap_mux =
1189 SOC_DAPM_ENUM("IF2 DAC Swap Source", rt5659_if2_dac_enum);
1190
1191static const struct snd_kcontrol_new rt5659_if2_adc_swap_mux =
1192 SOC_DAPM_ENUM("IF2 ADC Swap Source", rt5659_if2_adc_enum);
1193
1194static const struct snd_kcontrol_new rt5659_if3_dac_swap_mux =
1195 SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5659_if3_dac_enum);
1196
1197static const struct snd_kcontrol_new rt5659_if3_adc_swap_mux =
1198 SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5659_if3_adc_enum);
1199
1200static const char * const rt5659_asrc_clk_src[] = {
1201 "clk_sysy_div_out", "clk_i2s1_track", "clk_i2s2_track",
1202 "clk_i2s3_track", "clk_sys2", "clk_sys3"
1203};
1204
1205static unsigned int rt5659_asrc_clk_map_values[] = {
1206 0, 1, 2, 3, 5, 6,
1207};
1208
1209static const SOC_VALUE_ENUM_SINGLE_DECL(
1210 rt5659_da_sto_asrc_enum, RT5659_ASRC_2, RT5659_DA_STO_T_SFT, 0x7,
1211 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1212
1213static const SOC_VALUE_ENUM_SINGLE_DECL(
1214 rt5659_da_monol_asrc_enum, RT5659_ASRC_2, RT5659_DA_MONO_L_T_SFT, 0x7,
1215 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1216
1217static const SOC_VALUE_ENUM_SINGLE_DECL(
1218 rt5659_da_monor_asrc_enum, RT5659_ASRC_2, RT5659_DA_MONO_R_T_SFT, 0x7,
1219 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1220
1221static const SOC_VALUE_ENUM_SINGLE_DECL(
1222 rt5659_ad_sto1_asrc_enum, RT5659_ASRC_2, RT5659_AD_STO1_T_SFT, 0x7,
1223 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1224
1225static const SOC_VALUE_ENUM_SINGLE_DECL(
1226 rt5659_ad_sto2_asrc_enum, RT5659_ASRC_3, RT5659_AD_STO2_T_SFT, 0x7,
1227 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1228
1229static const SOC_VALUE_ENUM_SINGLE_DECL(
1230 rt5659_ad_monol_asrc_enum, RT5659_ASRC_3, RT5659_AD_MONO_L_T_SFT, 0x7,
1231 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1232
1233static const SOC_VALUE_ENUM_SINGLE_DECL(
1234 rt5659_ad_monor_asrc_enum, RT5659_ASRC_3, RT5659_AD_MONO_R_T_SFT, 0x7,
1235 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1236
1237static int rt5659_hp_vol_put(struct snd_kcontrol *kcontrol,
1238 struct snd_ctl_elem_value *ucontrol)
1239{
1240 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1241 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1242
1243 if (snd_soc_read(codec, RT5659_STO_NG2_CTRL_1) & RT5659_NG2_EN) {
1244 snd_soc_update_bits(codec, RT5659_STO_NG2_CTRL_1,
1245 RT5659_NG2_EN_MASK, RT5659_NG2_DIS);
1246 snd_soc_update_bits(codec, RT5659_STO_NG2_CTRL_1,
1247 RT5659_NG2_EN_MASK, RT5659_NG2_EN);
1248 }
1249
1250 return ret;
1251}
1252
1253static void rt5659_enable_push_button_irq(struct snd_soc_codec *codec,
1254 bool enable)
1255{
1256 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1257
1258 if (enable) {
1259 snd_soc_write(codec, RT5659_4BTN_IL_CMD_1, 0x000b);
1260
1261 /* MICBIAS1 and Mic Det Power for button detect*/
1262 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1263 snd_soc_dapm_force_enable_pin(dapm,
1264 "Mic Det Power");
1265 snd_soc_dapm_sync(dapm);
1266
1267 snd_soc_update_bits(codec, RT5659_PWR_ANLG_2,
1268 RT5659_PWR_MB1, RT5659_PWR_MB1);
1269 snd_soc_update_bits(codec, RT5659_PWR_VOL,
1270 RT5659_PWR_MIC_DET, RT5659_PWR_MIC_DET);
1271
1272 snd_soc_update_bits(codec, RT5659_IRQ_CTRL_2,
1273 RT5659_IL_IRQ_MASK, RT5659_IL_IRQ_EN);
1274 snd_soc_update_bits(codec, RT5659_4BTN_IL_CMD_2,
1275 RT5659_4BTN_IL_MASK, RT5659_4BTN_IL_EN);
1276 } else {
1277 snd_soc_update_bits(codec, RT5659_4BTN_IL_CMD_2,
1278 RT5659_4BTN_IL_MASK, RT5659_4BTN_IL_DIS);
1279 snd_soc_update_bits(codec, RT5659_IRQ_CTRL_2,
1280 RT5659_IL_IRQ_MASK, RT5659_IL_IRQ_DIS);
1281 /* MICBIAS1 and Mic Det Power for button detect*/
1282 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1283 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1284 snd_soc_dapm_sync(dapm);
1285 }
1286}
1287
1288/**
1289 * rt5659_headset_detect - Detect headset.
1290 * @codec: SoC audio codec device.
1291 * @jack_insert: Jack insert or not.
1292 *
1293 * Detect whether is headset or not when jack inserted.
1294 *
1295 * Returns detect status.
1296 */
1297
1298static int rt5659_headset_detect(struct snd_soc_codec *codec, int jack_insert)
1299{
1300 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1301 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1302 int reg_63;
1303
1304 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
1305
1306 if (jack_insert) {
1307 snd_soc_dapm_force_enable_pin(dapm,
1308 "Mic Det Power");
1309 snd_soc_dapm_sync(dapm);
1310 reg_63 = snd_soc_read(codec, RT5659_PWR_ANLG_1);
1311
1312 snd_soc_update_bits(codec, RT5659_PWR_ANLG_1,
1313 RT5659_PWR_VREF2 | RT5659_PWR_MB,
1314 RT5659_PWR_VREF2 | RT5659_PWR_MB);
1315 msleep(20);
1316 snd_soc_update_bits(codec, RT5659_PWR_ANLG_1,
1317 RT5659_PWR_FV2, RT5659_PWR_FV2);
1318
1319 snd_soc_write(codec, RT5659_EJD_CTRL_2, 0x4160);
1320 snd_soc_update_bits(codec, RT5659_EJD_CTRL_1,
1321 0x20, 0x0);
1322 msleep(20);
1323 snd_soc_update_bits(codec, RT5659_EJD_CTRL_1,
1324 0x20, 0x20);
1325
1326 while (i < 5) {
1327 msleep(sleep_time[i]);
1328 val = snd_soc_read(codec, RT5659_EJD_CTRL_2) & 0x0003;
1329 i++;
1330 if (val == 0x1 || val == 0x2 || val == 0x3)
1331 break;
1332 }
1333
1334 switch (val) {
1335 case 1:
1336 rt5659->jack_type = SND_JACK_HEADSET;
1337 rt5659_enable_push_button_irq(codec, true);
1338 break;
1339 default:
1340 snd_soc_write(codec, RT5659_PWR_ANLG_1, reg_63);
1341 rt5659->jack_type = SND_JACK_HEADPHONE;
1342 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1343 snd_soc_dapm_sync(dapm);
1344 break;
1345 }
1346 } else {
1347 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1348 snd_soc_dapm_sync(dapm);
1349 if (rt5659->jack_type == SND_JACK_HEADSET)
1350 rt5659_enable_push_button_irq(codec, false);
1351 rt5659->jack_type = 0;
1352 }
1353
1354 dev_dbg(codec->dev, "jack_type = %d\n", rt5659->jack_type);
1355 return rt5659->jack_type;
1356}
1357
1358static int rt5659_button_detect(struct snd_soc_codec *codec)
1359{
1360 int btn_type, val;
1361
1362 val = snd_soc_read(codec, RT5659_4BTN_IL_CMD_1);
1363 btn_type = val & 0xfff0;
1364 snd_soc_write(codec, RT5659_4BTN_IL_CMD_1, val);
1365
1366 return btn_type;
1367}
1368
1369static irqreturn_t rt5659_irq(int irq, void *data)
1370{
1371 struct rt5659_priv *rt5659 = data;
1372
1373 queue_delayed_work(system_power_efficient_wq,
1374 &rt5659->jack_detect_work, msecs_to_jiffies(250));
1375
1376 return IRQ_HANDLED;
1377}
1378
1379int rt5659_set_jack_detect(struct snd_soc_codec *codec,
1380 struct snd_soc_jack *hs_jack)
1381{
1382 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
1383
1384 rt5659->hs_jack = hs_jack;
1385
1386 rt5659_irq(0, rt5659);
1387
1388 return 0;
1389}
1390EXPORT_SYMBOL_GPL(rt5659_set_jack_detect);
1391
1392static void rt5659_jack_detect_work(struct work_struct *work)
1393{
1394 struct rt5659_priv *rt5659 =
1395 container_of(work, struct rt5659_priv, jack_detect_work.work);
1396 int val, btn_type, report = 0;
1397
1398 if (!rt5659->codec)
1399 return;
1400
1401 val = snd_soc_read(rt5659->codec, RT5659_INT_ST_1) & 0x0080;
1402 if (!val) {
1403 /* jack in */
1404 if (rt5659->jack_type == 0) {
1405 /* jack was out, report jack type */
1406 report = rt5659_headset_detect(rt5659->codec, 1);
1407 } else {
1408 /* jack is already in, report button event */
1409 report = SND_JACK_HEADSET;
1410 btn_type = rt5659_button_detect(rt5659->codec);
1411 /**
1412 * rt5659 can report three kinds of button behavior,
1413 * one click, double click and hold. However,
1414 * currently we will report button pressed/released
1415 * event. So all the three button behaviors are
1416 * treated as button pressed.
1417 */
1418 switch (btn_type) {
1419 case 0x8000:
1420 case 0x4000:
1421 case 0x2000:
1422 report |= SND_JACK_BTN_0;
1423 break;
1424 case 0x1000:
1425 case 0x0800:
1426 case 0x0400:
1427 report |= SND_JACK_BTN_1;
1428 break;
1429 case 0x0200:
1430 case 0x0100:
1431 case 0x0080:
1432 report |= SND_JACK_BTN_2;
1433 break;
1434 case 0x0040:
1435 case 0x0020:
1436 case 0x0010:
1437 report |= SND_JACK_BTN_3;
1438 break;
1439 case 0x0000: /* unpressed */
1440 break;
1441 default:
1442 btn_type = 0;
1443 dev_err(rt5659->codec->dev,
1444 "Unexpected button code 0x%04x\n",
1445 btn_type);
1446 break;
1447 }
1448
1449 /* button release or spurious interrput*/
1450 if (btn_type == 0)
1451 report = rt5659->jack_type;
1452 }
1453 } else {
1454 /* jack out */
1455 report = rt5659_headset_detect(rt5659->codec, 0);
1456 }
1457
1458 snd_soc_jack_report(rt5659->hs_jack, report, SND_JACK_HEADSET |
1459 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1460 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1461}
1462
1463static const struct snd_kcontrol_new rt5659_snd_controls[] = {
1464 /* Speaker Output Volume */
1465 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5659_SPO_VOL,
1466 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 39, 1, out_vol_tlv),
1467
1468 /* Headphone Output Volume */
1469 SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5659_HPL_GAIN,
1470 RT5659_HPR_GAIN, RT5659_G_HP_SFT, 31, 1, snd_soc_get_volsw,
1471 rt5659_hp_vol_put, hp_vol_tlv),
1472
1473 /* Mono Output Volume */
1474 SOC_SINGLE_TLV("Mono Playback Volume", RT5659_MONO_OUT,
1475 RT5659_L_VOL_SFT, 39, 1, out_vol_tlv),
1476
1477 /* Output Volume */
1478 SOC_DOUBLE_TLV("OUT Playback Volume", RT5659_LOUT,
1479 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 39, 1, out_vol_tlv),
1480
1481 /* DAC Digital Volume */
1482 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5659_DAC1_DIG_VOL,
1483 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 175, 0, dac_vol_tlv),
1484 SOC_DOUBLE("DAC1 Playback Switch", RT5659_AD_DA_MIXER,
1485 RT5659_M_DAC1_L_SFT, RT5659_M_DAC1_R_SFT, 1, 1),
1486
1487 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5659_DAC2_DIG_VOL,
1488 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 175, 0, dac_vol_tlv),
1489 SOC_DOUBLE("DAC2 Playback Switch", RT5659_DAC_CTRL,
1490 RT5659_M_DAC2_L_VOL_SFT, RT5659_M_DAC2_R_VOL_SFT, 1, 1),
1491
1492 /* IN1/IN2/IN3/IN4 Volume */
1493 SOC_SINGLE_TLV("IN1 Boost Volume", RT5659_IN1_IN2,
1494 RT5659_BST1_SFT, 69, 0, in_bst_tlv),
1495 SOC_SINGLE_TLV("IN2 Boost Volume", RT5659_IN1_IN2,
1496 RT5659_BST2_SFT, 69, 0, in_bst_tlv),
1497 SOC_SINGLE_TLV("IN3 Boost Volume", RT5659_IN3_IN4,
1498 RT5659_BST3_SFT, 69, 0, in_bst_tlv),
1499 SOC_SINGLE_TLV("IN4 Boost Volume", RT5659_IN3_IN4,
1500 RT5659_BST4_SFT, 69, 0, in_bst_tlv),
1501
1502 /* INL/INR Volume Control */
1503 SOC_DOUBLE_TLV("IN Capture Volume", RT5659_INL1_INR1_VOL,
1504 RT5659_INL_VOL_SFT, RT5659_INR_VOL_SFT, 31, 1, in_vol_tlv),
1505
1506 /* ADC Digital Volume Control */
1507 SOC_DOUBLE("STO1 ADC Capture Switch", RT5659_STO1_ADC_DIG_VOL,
1508 RT5659_L_MUTE_SFT, RT5659_R_MUTE_SFT, 1, 1),
1509 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5659_STO1_ADC_DIG_VOL,
1510 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 127, 0, adc_vol_tlv),
1511 SOC_DOUBLE("Mono ADC Capture Switch", RT5659_MONO_ADC_DIG_VOL,
1512 RT5659_L_MUTE_SFT, RT5659_R_MUTE_SFT, 1, 1),
1513 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5659_MONO_ADC_DIG_VOL,
1514 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 127, 0, adc_vol_tlv),
1515 SOC_DOUBLE("STO2 ADC Capture Switch", RT5659_STO2_ADC_DIG_VOL,
1516 RT5659_L_MUTE_SFT, RT5659_R_MUTE_SFT, 1, 1),
1517 SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5659_STO2_ADC_DIG_VOL,
1518 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 127, 0, adc_vol_tlv),
1519
1520 /* ADC Boost Volume Control */
1521 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5659_STO1_BOOST,
1522 RT5659_STO1_ADC_L_BST_SFT, RT5659_STO1_ADC_R_BST_SFT,
1523 3, 0, adc_bst_tlv),
1524
1525 SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5659_MONO_BOOST,
1526 RT5659_MONO_ADC_L_BST_SFT, RT5659_MONO_ADC_R_BST_SFT,
1527 3, 0, adc_bst_tlv),
1528
1529 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5659_STO2_BOOST,
1530 RT5659_STO2_ADC_L_BST_SFT, RT5659_STO2_ADC_R_BST_SFT,
1531 3, 0, adc_bst_tlv),
1532
1533 SOC_SINGLE("DAC IF1 DAC1 L Data Switch", RT5659_TDM_CTRL_4, 12, 7, 0),
1534 SOC_SINGLE("DAC IF1 DAC1 R Data Switch", RT5659_TDM_CTRL_4, 8, 7, 0),
1535 SOC_SINGLE("DAC IF1 DAC2 L Data Switch", RT5659_TDM_CTRL_4, 4, 7, 0),
1536 SOC_SINGLE("DAC IF1 DAC2 R Data Switch", RT5659_TDM_CTRL_4, 0, 7, 0),
1537};
1538
1539/**
1540 * set_dmic_clk - Set parameter of dmic.
1541 *
1542 * @w: DAPM widget.
1543 * @kcontrol: The kcontrol of this widget.
1544 * @event: Event id.
1545 *
1546 * Choose dmic clock between 1MHz and 3MHz.
1547 * It is better for clock to approximate 3MHz.
1548 */
1549static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1550 struct snd_kcontrol *kcontrol, int event)
1551{
1552 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1553 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
1554 int pd, idx = -EINVAL;
1555
1556 pd = rl6231_get_pre_div(rt5659->regmap,
1557 RT5659_ADDA_CLK_1, RT5659_I2S_PD1_SFT);
1558 idx = rl6231_calc_dmic_clk(rt5659->sysclk / pd);
1559
1560 if (idx < 0)
1561 dev_err(codec->dev, "Failed to set DMIC clock\n");
1562 else {
1563 snd_soc_update_bits(codec, RT5659_DMIC_CTRL_1,
1564 RT5659_DMIC_CLK_MASK, idx << RT5659_DMIC_CLK_SFT);
1565 }
1566 return idx;
1567}
1568
1569static int set_adc_clk(struct snd_soc_dapm_widget *w,
1570 struct snd_kcontrol *kcontrol, int event)
1571{
1572 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1573
1574 switch (event) {
1575 case SND_SOC_DAPM_POST_PMU:
1576 snd_soc_update_bits(codec, RT5659_CHOP_ADC,
1577 RT5659_CKXEN_ADCC_MASK | RT5659_CKGEN_ADCC_MASK,
1578 RT5659_CKXEN_ADCC_MASK | RT5659_CKGEN_ADCC_MASK);
1579 break;
1580
1581 case SND_SOC_DAPM_PRE_PMD:
1582 snd_soc_update_bits(codec, RT5659_CHOP_ADC,
1583 RT5659_CKXEN_ADCC_MASK | RT5659_CKGEN_ADCC_MASK, 0);
1584 break;
1585
1586 default:
1587 return 0;
1588 }
1589
1590 return 0;
1591
1592}
1593
1594static int rt5659_charge_pump_event(struct snd_soc_dapm_widget *w,
1595 struct snd_kcontrol *kcontrol, int event)
1596{
1597 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1598
1599 switch (event) {
1600 case SND_SOC_DAPM_PRE_PMU:
1601 /* Depop */
1602 snd_soc_write(codec, RT5659_DEPOP_1, 0x0009);
1603 break;
1604 case SND_SOC_DAPM_POST_PMD:
1605 snd_soc_write(codec, RT5659_HP_CHARGE_PUMP_1, 0x0c16);
1606 break;
1607 default:
1608 return 0;
1609 }
1610
1611 return 0;
1612}
1613
1614static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1615 struct snd_soc_dapm_widget *sink)
1616{
1617 unsigned int val;
1618 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1619
1620 val = snd_soc_read(codec, RT5659_GLB_CLK);
1621 val &= RT5659_SCLK_SRC_MASK;
1622 if (val == RT5659_SCLK_SRC_PLL1)
1623 return 1;
1624 else
1625 return 0;
1626}
1627
1628static int is_using_asrc(struct snd_soc_dapm_widget *w,
1629 struct snd_soc_dapm_widget *sink)
1630{
1631 unsigned int reg, shift, val;
1632 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1633
1634 switch (w->shift) {
1635 case RT5659_ADC_MONO_R_ASRC_SFT:
1636 reg = RT5659_ASRC_3;
1637 shift = RT5659_AD_MONO_R_T_SFT;
1638 break;
1639 case RT5659_ADC_MONO_L_ASRC_SFT:
1640 reg = RT5659_ASRC_3;
1641 shift = RT5659_AD_MONO_L_T_SFT;
1642 break;
1643 case RT5659_ADC_STO1_ASRC_SFT:
1644 reg = RT5659_ASRC_2;
1645 shift = RT5659_AD_STO1_T_SFT;
1646 break;
1647 case RT5659_DAC_MONO_R_ASRC_SFT:
1648 reg = RT5659_ASRC_2;
1649 shift = RT5659_DA_MONO_R_T_SFT;
1650 break;
1651 case RT5659_DAC_MONO_L_ASRC_SFT:
1652 reg = RT5659_ASRC_2;
1653 shift = RT5659_DA_MONO_L_T_SFT;
1654 break;
1655 case RT5659_DAC_STO_ASRC_SFT:
1656 reg = RT5659_ASRC_2;
1657 shift = RT5659_DA_STO_T_SFT;
1658 break;
1659 default:
1660 return 0;
1661 }
1662
1663 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
1664 switch (val) {
1665 case 1:
1666 case 2:
1667 case 3:
1668 /* I2S_Pre_Div1 should be 1 in asrc mode */
1669 snd_soc_update_bits(codec, RT5659_ADDA_CLK_1,
1670 RT5659_I2S_PD1_MASK, RT5659_I2S_PD1_2);
1671 return 1;
1672 default:
1673 return 0;
1674 }
1675
1676}
1677
1678/* Digital Mixer */
1679static const struct snd_kcontrol_new rt5659_sto1_adc_l_mix[] = {
1680 SOC_DAPM_SINGLE("ADC1 Switch", RT5659_STO1_ADC_MIXER,
1681 RT5659_M_STO1_ADC_L1_SFT, 1, 1),
1682 SOC_DAPM_SINGLE("ADC2 Switch", RT5659_STO1_ADC_MIXER,
1683 RT5659_M_STO1_ADC_L2_SFT, 1, 1),
1684};
1685
1686static const struct snd_kcontrol_new rt5659_sto1_adc_r_mix[] = {
1687 SOC_DAPM_SINGLE("ADC1 Switch", RT5659_STO1_ADC_MIXER,
1688 RT5659_M_STO1_ADC_R1_SFT, 1, 1),
1689 SOC_DAPM_SINGLE("ADC2 Switch", RT5659_STO1_ADC_MIXER,
1690 RT5659_M_STO1_ADC_R2_SFT, 1, 1),
1691};
1692
1693static const struct snd_kcontrol_new rt5659_mono_adc_l_mix[] = {
1694 SOC_DAPM_SINGLE("ADC1 Switch", RT5659_MONO_ADC_MIXER,
1695 RT5659_M_MONO_ADC_L1_SFT, 1, 1),
1696 SOC_DAPM_SINGLE("ADC2 Switch", RT5659_MONO_ADC_MIXER,
1697 RT5659_M_MONO_ADC_L2_SFT, 1, 1),
1698};
1699
1700static const struct snd_kcontrol_new rt5659_mono_adc_r_mix[] = {
1701 SOC_DAPM_SINGLE("ADC1 Switch", RT5659_MONO_ADC_MIXER,
1702 RT5659_M_MONO_ADC_R1_SFT, 1, 1),
1703 SOC_DAPM_SINGLE("ADC2 Switch", RT5659_MONO_ADC_MIXER,
1704 RT5659_M_MONO_ADC_R2_SFT, 1, 1),
1705};
1706
1707static const struct snd_kcontrol_new rt5659_dac_l_mix[] = {
1708 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5659_AD_DA_MIXER,
1709 RT5659_M_ADCMIX_L_SFT, 1, 1),
1710 SOC_DAPM_SINGLE("DAC1 Switch", RT5659_AD_DA_MIXER,
1711 RT5659_M_DAC1_L_SFT, 1, 1),
1712};
1713
1714static const struct snd_kcontrol_new rt5659_dac_r_mix[] = {
1715 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5659_AD_DA_MIXER,
1716 RT5659_M_ADCMIX_R_SFT, 1, 1),
1717 SOC_DAPM_SINGLE("DAC1 Switch", RT5659_AD_DA_MIXER,
1718 RT5659_M_DAC1_R_SFT, 1, 1),
1719};
1720
1721static const struct snd_kcontrol_new rt5659_sto_dac_l_mix[] = {
1722 SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_STO_DAC_MIXER,
1723 RT5659_M_DAC_L1_STO_L_SFT, 1, 1),
1724 SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_STO_DAC_MIXER,
1725 RT5659_M_DAC_R1_STO_L_SFT, 1, 1),
1726 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_STO_DAC_MIXER,
1727 RT5659_M_DAC_L2_STO_L_SFT, 1, 1),
1728 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_STO_DAC_MIXER,
1729 RT5659_M_DAC_R2_STO_L_SFT, 1, 1),
1730};
1731
1732static const struct snd_kcontrol_new rt5659_sto_dac_r_mix[] = {
1733 SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_STO_DAC_MIXER,
1734 RT5659_M_DAC_L1_STO_R_SFT, 1, 1),
1735 SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_STO_DAC_MIXER,
1736 RT5659_M_DAC_R1_STO_R_SFT, 1, 1),
1737 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_STO_DAC_MIXER,
1738 RT5659_M_DAC_L2_STO_R_SFT, 1, 1),
1739 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_STO_DAC_MIXER,
1740 RT5659_M_DAC_R2_STO_R_SFT, 1, 1),
1741};
1742
1743static const struct snd_kcontrol_new rt5659_mono_dac_l_mix[] = {
1744 SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_MONO_DAC_MIXER,
1745 RT5659_M_DAC_L1_MONO_L_SFT, 1, 1),
1746 SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_MONO_DAC_MIXER,
1747 RT5659_M_DAC_R1_MONO_L_SFT, 1, 1),
1748 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONO_DAC_MIXER,
1749 RT5659_M_DAC_L2_MONO_L_SFT, 1, 1),
1750 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_MONO_DAC_MIXER,
1751 RT5659_M_DAC_R2_MONO_L_SFT, 1, 1),
1752};
1753
1754static const struct snd_kcontrol_new rt5659_mono_dac_r_mix[] = {
1755 SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_MONO_DAC_MIXER,
1756 RT5659_M_DAC_L1_MONO_R_SFT, 1, 1),
1757 SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_MONO_DAC_MIXER,
1758 RT5659_M_DAC_R1_MONO_R_SFT, 1, 1),
1759 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONO_DAC_MIXER,
1760 RT5659_M_DAC_L2_MONO_R_SFT, 1, 1),
1761 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_MONO_DAC_MIXER,
1762 RT5659_M_DAC_R2_MONO_R_SFT, 1, 1),
1763};
1764
1765/* Analog Input Mixer */
1766static const struct snd_kcontrol_new rt5659_rec1_l_mix[] = {
1767 SOC_DAPM_SINGLE("SPKVOLL Switch", RT5659_REC1_L2_MIXER,
1768 RT5659_M_SPKVOLL_RM1_L_SFT, 1, 1),
1769 SOC_DAPM_SINGLE("INL Switch", RT5659_REC1_L2_MIXER,
1770 RT5659_M_INL_RM1_L_SFT, 1, 1),
1771 SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC1_L2_MIXER,
1772 RT5659_M_BST4_RM1_L_SFT, 1, 1),
1773 SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC1_L2_MIXER,
1774 RT5659_M_BST3_RM1_L_SFT, 1, 1),
1775 SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC1_L2_MIXER,
1776 RT5659_M_BST2_RM1_L_SFT, 1, 1),
1777 SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC1_L2_MIXER,
1778 RT5659_M_BST1_RM1_L_SFT, 1, 1),
1779};
1780
1781static const struct snd_kcontrol_new rt5659_rec1_r_mix[] = {
1782 SOC_DAPM_SINGLE("HPOVOLR Switch", RT5659_REC1_L2_MIXER,
1783 RT5659_M_HPOVOLR_RM1_R_SFT, 1, 1),
1784 SOC_DAPM_SINGLE("INR Switch", RT5659_REC1_R2_MIXER,
1785 RT5659_M_INR_RM1_R_SFT, 1, 1),
1786 SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC1_R2_MIXER,
1787 RT5659_M_BST4_RM1_R_SFT, 1, 1),
1788 SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC1_R2_MIXER,
1789 RT5659_M_BST3_RM1_R_SFT, 1, 1),
1790 SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC1_R2_MIXER,
1791 RT5659_M_BST2_RM1_R_SFT, 1, 1),
1792 SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC1_R2_MIXER,
1793 RT5659_M_BST1_RM1_R_SFT, 1, 1),
1794};
1795
1796static const struct snd_kcontrol_new rt5659_rec2_l_mix[] = {
1797 SOC_DAPM_SINGLE("SPKVOLL Switch", RT5659_REC2_L2_MIXER,
1798 RT5659_M_SPKVOL_RM2_L_SFT, 1, 1),
1799 SOC_DAPM_SINGLE("OUTVOLL Switch", RT5659_REC2_L2_MIXER,
1800 RT5659_M_OUTVOLL_RM2_L_SFT, 1, 1),
1801 SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC2_L2_MIXER,
1802 RT5659_M_BST4_RM2_L_SFT, 1, 1),
1803 SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC2_L2_MIXER,
1804 RT5659_M_BST3_RM2_L_SFT, 1, 1),
1805 SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC2_L2_MIXER,
1806 RT5659_M_BST2_RM2_L_SFT, 1, 1),
1807 SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC2_L2_MIXER,
1808 RT5659_M_BST1_RM2_L_SFT, 1, 1),
1809};
1810
1811static const struct snd_kcontrol_new rt5659_rec2_r_mix[] = {
1812 SOC_DAPM_SINGLE("MONOVOL Switch", RT5659_REC2_R2_MIXER,
1813 RT5659_M_MONOVOL_RM2_R_SFT, 1, 1),
1814 SOC_DAPM_SINGLE("OUTVOLR Switch", RT5659_REC2_R2_MIXER,
1815 RT5659_M_OUTVOLR_RM2_R_SFT, 1, 1),
1816 SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC2_R2_MIXER,
1817 RT5659_M_BST4_RM2_R_SFT, 1, 1),
1818 SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC2_R2_MIXER,
1819 RT5659_M_BST3_RM2_R_SFT, 1, 1),
1820 SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC2_R2_MIXER,
1821 RT5659_M_BST2_RM2_R_SFT, 1, 1),
1822 SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC2_R2_MIXER,
1823 RT5659_M_BST1_RM2_R_SFT, 1, 1),
1824};
1825
1826static const struct snd_kcontrol_new rt5659_spk_l_mix[] = {
1827 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_SPK_L_MIXER,
1828 RT5659_M_DAC_L2_SM_L_SFT, 1, 1),
1829 SOC_DAPM_SINGLE("BST1 Switch", RT5659_SPK_L_MIXER,
1830 RT5659_M_BST1_SM_L_SFT, 1, 1),
1831 SOC_DAPM_SINGLE("INL Switch", RT5659_SPK_L_MIXER,
1832 RT5659_M_IN_L_SM_L_SFT, 1, 1),
1833 SOC_DAPM_SINGLE("INR Switch", RT5659_SPK_L_MIXER,
1834 RT5659_M_IN_R_SM_L_SFT, 1, 1),
1835 SOC_DAPM_SINGLE("BST3 Switch", RT5659_SPK_L_MIXER,
1836 RT5659_M_BST3_SM_L_SFT, 1, 1),
1837};
1838
1839static const struct snd_kcontrol_new rt5659_spk_r_mix[] = {
1840 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_SPK_R_MIXER,
1841 RT5659_M_DAC_R2_SM_R_SFT, 1, 1),
1842 SOC_DAPM_SINGLE("BST4 Switch", RT5659_SPK_R_MIXER,
1843 RT5659_M_BST4_SM_R_SFT, 1, 1),
1844 SOC_DAPM_SINGLE("INL Switch", RT5659_SPK_R_MIXER,
1845 RT5659_M_IN_L_SM_R_SFT, 1, 1),
1846 SOC_DAPM_SINGLE("INR Switch", RT5659_SPK_R_MIXER,
1847 RT5659_M_IN_R_SM_R_SFT, 1, 1),
1848 SOC_DAPM_SINGLE("BST3 Switch", RT5659_SPK_R_MIXER,
1849 RT5659_M_BST3_SM_R_SFT, 1, 1),
1850};
1851
1852static const struct snd_kcontrol_new rt5659_monovol_mix[] = {
1853 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONOMIX_IN_GAIN,
1854 RT5659_M_DAC_L2_MM_SFT, 1, 1),
1855 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_MONOMIX_IN_GAIN,
1856 RT5659_M_DAC_R2_MM_SFT, 1, 1),
1857 SOC_DAPM_SINGLE("BST1 Switch", RT5659_MONOMIX_IN_GAIN,
1858 RT5659_M_BST1_MM_SFT, 1, 1),
1859 SOC_DAPM_SINGLE("BST2 Switch", RT5659_MONOMIX_IN_GAIN,
1860 RT5659_M_BST2_MM_SFT, 1, 1),
1861 SOC_DAPM_SINGLE("BST3 Switch", RT5659_MONOMIX_IN_GAIN,
1862 RT5659_M_BST3_MM_SFT, 1, 1),
1863};
1864
1865static const struct snd_kcontrol_new rt5659_out_l_mix[] = {
1866 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_OUT_L_MIXER,
1867 RT5659_M_DAC_L2_OM_L_SFT, 1, 1),
1868 SOC_DAPM_SINGLE("INL Switch", RT5659_OUT_L_MIXER,
1869 RT5659_M_IN_L_OM_L_SFT, 1, 1),
1870 SOC_DAPM_SINGLE("BST1 Switch", RT5659_OUT_L_MIXER,
1871 RT5659_M_BST1_OM_L_SFT, 1, 1),
1872 SOC_DAPM_SINGLE("BST2 Switch", RT5659_OUT_L_MIXER,
1873 RT5659_M_BST2_OM_L_SFT, 1, 1),
1874 SOC_DAPM_SINGLE("BST3 Switch", RT5659_OUT_L_MIXER,
1875 RT5659_M_BST3_OM_L_SFT, 1, 1),
1876};
1877
1878static const struct snd_kcontrol_new rt5659_out_r_mix[] = {
1879 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_OUT_R_MIXER,
1880 RT5659_M_DAC_R2_OM_R_SFT, 1, 1),
1881 SOC_DAPM_SINGLE("INR Switch", RT5659_OUT_R_MIXER,
1882 RT5659_M_IN_R_OM_R_SFT, 1, 1),
1883 SOC_DAPM_SINGLE("BST2 Switch", RT5659_OUT_R_MIXER,
1884 RT5659_M_BST2_OM_R_SFT, 1, 1),
1885 SOC_DAPM_SINGLE("BST3 Switch", RT5659_OUT_R_MIXER,
1886 RT5659_M_BST3_OM_R_SFT, 1, 1),
1887 SOC_DAPM_SINGLE("BST4 Switch", RT5659_OUT_R_MIXER,
1888 RT5659_M_BST4_OM_R_SFT, 1, 1),
1889};
1890
1891static const struct snd_kcontrol_new rt5659_spo_l_mix[] = {
1892 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_SPO_AMP_GAIN,
1893 RT5659_M_DAC_L2_SPKOMIX_SFT, 1, 0),
1894 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5659_SPO_AMP_GAIN,
1895 RT5659_M_SPKVOLL_SPKOMIX_SFT, 1, 0),
1896};
1897
1898static const struct snd_kcontrol_new rt5659_spo_r_mix[] = {
1899 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_SPO_AMP_GAIN,
1900 RT5659_M_DAC_R2_SPKOMIX_SFT, 1, 0),
1901 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5659_SPO_AMP_GAIN,
1902 RT5659_M_SPKVOLR_SPKOMIX_SFT, 1, 0),
1903};
1904
1905static const struct snd_kcontrol_new rt5659_mono_mix[] = {
1906 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONOMIX_IN_GAIN,
1907 RT5659_M_DAC_L2_MA_SFT, 1, 1),
1908 SOC_DAPM_SINGLE("MONOVOL Switch", RT5659_MONOMIX_IN_GAIN,
1909 RT5659_M_MONOVOL_MA_SFT, 1, 1),
1910};
1911
1912static const struct snd_kcontrol_new rt5659_lout_l_mix[] = {
1913 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_LOUT_MIXER,
1914 RT5659_M_DAC_L2_LM_SFT, 1, 1),
1915 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5659_LOUT_MIXER,
1916 RT5659_M_OV_L_LM_SFT, 1, 1),
1917};
1918
1919static const struct snd_kcontrol_new rt5659_lout_r_mix[] = {
1920 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_LOUT_MIXER,
1921 RT5659_M_DAC_R2_LM_SFT, 1, 1),
1922 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5659_LOUT_MIXER,
1923 RT5659_M_OV_R_LM_SFT, 1, 1),
1924};
1925
1926/*DAC L2, DAC R2*/
1927/*MX-1B [6:4], MX-1B [2:0]*/
1928static const char * const rt5659_dac2_src[] = {
1929 "IF1 DAC2", "IF2 DAC", "IF3 DAC", "Mono ADC MIX"
1930};
1931
1932static const SOC_ENUM_SINGLE_DECL(
1933 rt5659_dac_l2_enum, RT5659_DAC_CTRL,
1934 RT5659_DAC_L2_SEL_SFT, rt5659_dac2_src);
1935
1936static const struct snd_kcontrol_new rt5659_dac_l2_mux =
1937 SOC_DAPM_ENUM("DAC L2 Source", rt5659_dac_l2_enum);
1938
1939static const SOC_ENUM_SINGLE_DECL(
1940 rt5659_dac_r2_enum, RT5659_DAC_CTRL,
1941 RT5659_DAC_R2_SEL_SFT, rt5659_dac2_src);
1942
1943static const struct snd_kcontrol_new rt5659_dac_r2_mux =
1944 SOC_DAPM_ENUM("DAC R2 Source", rt5659_dac_r2_enum);
1945
1946
1947/* STO1 ADC1 Source */
1948/* MX-26 [13] */
1949static const char * const rt5659_sto1_adc1_src[] = {
1950 "DAC MIX", "ADC"
1951};
1952
1953static const SOC_ENUM_SINGLE_DECL(
1954 rt5659_sto1_adc1_enum, RT5659_STO1_ADC_MIXER,
1955 RT5659_STO1_ADC1_SRC_SFT, rt5659_sto1_adc1_src);
1956
1957static const struct snd_kcontrol_new rt5659_sto1_adc1_mux =
1958 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5659_sto1_adc1_enum);
1959
1960/* STO1 ADC Source */
1961/* MX-26 [12] */
1962static const char * const rt5659_sto1_adc_src[] = {
1963 "ADC1", "ADC2"
1964};
1965
1966static const SOC_ENUM_SINGLE_DECL(
1967 rt5659_sto1_adc_enum, RT5659_STO1_ADC_MIXER,
1968 RT5659_STO1_ADC_SRC_SFT, rt5659_sto1_adc_src);
1969
1970static const struct snd_kcontrol_new rt5659_sto1_adc_mux =
1971 SOC_DAPM_ENUM("Stereo1 ADC Source", rt5659_sto1_adc_enum);
1972
1973/* STO1 ADC2 Source */
1974/* MX-26 [11] */
1975static const char * const rt5659_sto1_adc2_src[] = {
1976 "DAC MIX", "DMIC"
1977};
1978
1979static const SOC_ENUM_SINGLE_DECL(
1980 rt5659_sto1_adc2_enum, RT5659_STO1_ADC_MIXER,
1981 RT5659_STO1_ADC2_SRC_SFT, rt5659_sto1_adc2_src);
1982
1983static const struct snd_kcontrol_new rt5659_sto1_adc2_mux =
1984 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5659_sto1_adc2_enum);
1985
1986/* STO1 DMIC Source */
1987/* MX-26 [8] */
1988static const char * const rt5659_sto1_dmic_src[] = {
1989 "DMIC1", "DMIC2"
1990};
1991
1992static const SOC_ENUM_SINGLE_DECL(
1993 rt5659_sto1_dmic_enum, RT5659_STO1_ADC_MIXER,
1994 RT5659_STO1_DMIC_SRC_SFT, rt5659_sto1_dmic_src);
1995
1996static const struct snd_kcontrol_new rt5659_sto1_dmic_mux =
1997 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5659_sto1_dmic_enum);
1998
1999
2000/* MONO ADC L2 Source */
2001/* MX-27 [12] */
2002static const char * const rt5659_mono_adc_l2_src[] = {
2003 "Mono DAC MIXL", "DMIC"
2004};
2005
2006static const SOC_ENUM_SINGLE_DECL(
2007 rt5659_mono_adc_l2_enum, RT5659_MONO_ADC_MIXER,
2008 RT5659_MONO_ADC_L2_SRC_SFT, rt5659_mono_adc_l2_src);
2009
2010static const struct snd_kcontrol_new rt5659_mono_adc_l2_mux =
2011 SOC_DAPM_ENUM("Mono ADC L2 Source", rt5659_mono_adc_l2_enum);
2012
2013
2014/* MONO ADC L1 Source */
2015/* MX-27 [11] */
2016static const char * const rt5659_mono_adc_l1_src[] = {
2017 "Mono DAC MIXL", "ADC"
2018};
2019
2020static const SOC_ENUM_SINGLE_DECL(
2021 rt5659_mono_adc_l1_enum, RT5659_MONO_ADC_MIXER,
2022 RT5659_MONO_ADC_L1_SRC_SFT, rt5659_mono_adc_l1_src);
2023
2024static const struct snd_kcontrol_new rt5659_mono_adc_l1_mux =
2025 SOC_DAPM_ENUM("Mono ADC L1 Source", rt5659_mono_adc_l1_enum);
2026
2027/* MONO ADC L Source, MONO ADC R Source*/
2028/* MX-27 [10:9], MX-27 [2:1] */
2029static const char * const rt5659_mono_adc_src[] = {
2030 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
2031};
2032
2033static const SOC_ENUM_SINGLE_DECL(
2034 rt5659_mono_adc_l_enum, RT5659_MONO_ADC_MIXER,
2035 RT5659_MONO_ADC_L_SRC_SFT, rt5659_mono_adc_src);
2036
2037static const struct snd_kcontrol_new rt5659_mono_adc_l_mux =
2038 SOC_DAPM_ENUM("Mono ADC L Source", rt5659_mono_adc_l_enum);
2039
2040static const SOC_ENUM_SINGLE_DECL(
2041 rt5659_mono_adcr_enum, RT5659_MONO_ADC_MIXER,
2042 RT5659_MONO_ADC_R_SRC_SFT, rt5659_mono_adc_src);
2043
2044static const struct snd_kcontrol_new rt5659_mono_adc_r_mux =
2045 SOC_DAPM_ENUM("Mono ADC R Source", rt5659_mono_adcr_enum);
2046
2047/* MONO DMIC L Source */
2048/* MX-27 [8] */
2049static const char * const rt5659_mono_dmic_l_src[] = {
2050 "DMIC1 L", "DMIC2 L"
2051};
2052
2053static const SOC_ENUM_SINGLE_DECL(
2054 rt5659_mono_dmic_l_enum, RT5659_MONO_ADC_MIXER,
2055 RT5659_MONO_DMIC_L_SRC_SFT, rt5659_mono_dmic_l_src);
2056
2057static const struct snd_kcontrol_new rt5659_mono_dmic_l_mux =
2058 SOC_DAPM_ENUM("Mono DMIC L Source", rt5659_mono_dmic_l_enum);
2059
2060/* MONO ADC R2 Source */
2061/* MX-27 [4] */
2062static const char * const rt5659_mono_adc_r2_src[] = {
2063 "Mono DAC MIXR", "DMIC"
2064};
2065
2066static const SOC_ENUM_SINGLE_DECL(
2067 rt5659_mono_adc_r2_enum, RT5659_MONO_ADC_MIXER,
2068 RT5659_MONO_ADC_R2_SRC_SFT, rt5659_mono_adc_r2_src);
2069
2070static const struct snd_kcontrol_new rt5659_mono_adc_r2_mux =
2071 SOC_DAPM_ENUM("Mono ADC R2 Source", rt5659_mono_adc_r2_enum);
2072
2073/* MONO ADC R1 Source */
2074/* MX-27 [3] */
2075static const char * const rt5659_mono_adc_r1_src[] = {
2076 "Mono DAC MIXR", "ADC"
2077};
2078
2079static const SOC_ENUM_SINGLE_DECL(
2080 rt5659_mono_adc_r1_enum, RT5659_MONO_ADC_MIXER,
2081 RT5659_MONO_ADC_R1_SRC_SFT, rt5659_mono_adc_r1_src);
2082
2083static const struct snd_kcontrol_new rt5659_mono_adc_r1_mux =
2084 SOC_DAPM_ENUM("Mono ADC R1 Source", rt5659_mono_adc_r1_enum);
2085
2086/* MONO DMIC R Source */
2087/* MX-27 [0] */
2088static const char * const rt5659_mono_dmic_r_src[] = {
2089 "DMIC1 R", "DMIC2 R"
2090};
2091
2092static const SOC_ENUM_SINGLE_DECL(
2093 rt5659_mono_dmic_r_enum, RT5659_MONO_ADC_MIXER,
2094 RT5659_MONO_DMIC_R_SRC_SFT, rt5659_mono_dmic_r_src);
2095
2096static const struct snd_kcontrol_new rt5659_mono_dmic_r_mux =
2097 SOC_DAPM_ENUM("Mono DMIC R Source", rt5659_mono_dmic_r_enum);
2098
2099
2100/* DAC R1 Source, DAC L1 Source*/
2101/* MX-29 [11:10], MX-29 [9:8]*/
2102static const char * const rt5659_dac1_src[] = {
2103 "IF1 DAC1", "IF2 DAC", "IF3 DAC"
2104};
2105
2106static const SOC_ENUM_SINGLE_DECL(
2107 rt5659_dac_r1_enum, RT5659_AD_DA_MIXER,
2108 RT5659_DAC1_R_SEL_SFT, rt5659_dac1_src);
2109
2110static const struct snd_kcontrol_new rt5659_dac_r1_mux =
2111 SOC_DAPM_ENUM("DAC R1 Source", rt5659_dac_r1_enum);
2112
2113static const SOC_ENUM_SINGLE_DECL(
2114 rt5659_dac_l1_enum, RT5659_AD_DA_MIXER,
2115 RT5659_DAC1_L_SEL_SFT, rt5659_dac1_src);
2116
2117static const struct snd_kcontrol_new rt5659_dac_l1_mux =
2118 SOC_DAPM_ENUM("DAC L1 Source", rt5659_dac_l1_enum);
2119
2120/* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/
2121/* MX-2C [6], MX-2C [4]*/
2122static const char * const rt5659_dig_dac_mix_src[] = {
2123 "Stereo DAC Mixer", "Mono DAC Mixer"
2124};
2125
2126static const SOC_ENUM_SINGLE_DECL(
2127 rt5659_dig_dac_mixl_enum, RT5659_DIG_MIXER,
2128 RT5659_DAC_MIX_L_SFT, rt5659_dig_dac_mix_src);
2129
2130static const struct snd_kcontrol_new rt5659_dig_dac_mixl_mux =
2131 SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5659_dig_dac_mixl_enum);
2132
2133static const SOC_ENUM_SINGLE_DECL(
2134 rt5659_dig_dac_mixr_enum, RT5659_DIG_MIXER,
2135 RT5659_DAC_MIX_R_SFT, rt5659_dig_dac_mix_src);
2136
2137static const struct snd_kcontrol_new rt5659_dig_dac_mixr_mux =
2138 SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5659_dig_dac_mixr_enum);
2139
2140/* Analog DAC L1 Source, Analog DAC R1 Source*/
2141/* MX-2D [3], MX-2D [2]*/
2142static const char * const rt5659_alg_dac1_src[] = {
2143 "DAC", "Stereo DAC Mixer"
2144};
2145
2146static const SOC_ENUM_SINGLE_DECL(
2147 rt5659_alg_dac_l1_enum, RT5659_A_DAC_MUX,
2148 RT5659_A_DACL1_SFT, rt5659_alg_dac1_src);
2149
2150static const struct snd_kcontrol_new rt5659_alg_dac_l1_mux =
2151 SOC_DAPM_ENUM("Analog DACL1 Source", rt5659_alg_dac_l1_enum);
2152
2153static const SOC_ENUM_SINGLE_DECL(
2154 rt5659_alg_dac_r1_enum, RT5659_A_DAC_MUX,
2155 RT5659_A_DACR1_SFT, rt5659_alg_dac1_src);
2156
2157static const struct snd_kcontrol_new rt5659_alg_dac_r1_mux =
2158 SOC_DAPM_ENUM("Analog DACR1 Source", rt5659_alg_dac_r1_enum);
2159
2160/* Analog DAC LR Source, Analog DAC R2 Source*/
2161/* MX-2D [1], MX-2D [0]*/
2162static const char * const rt5659_alg_dac2_src[] = {
2163 "Stereo DAC Mixer", "Mono DAC Mixer"
2164};
2165
2166static const SOC_ENUM_SINGLE_DECL(
2167 rt5659_alg_dac_l2_enum, RT5659_A_DAC_MUX,
2168 RT5659_A_DACL2_SFT, rt5659_alg_dac2_src);
2169
2170static const struct snd_kcontrol_new rt5659_alg_dac_l2_mux =
2171 SOC_DAPM_ENUM("Analog DAC L2 Source", rt5659_alg_dac_l2_enum);
2172
2173static const SOC_ENUM_SINGLE_DECL(
2174 rt5659_alg_dac_r2_enum, RT5659_A_DAC_MUX,
2175 RT5659_A_DACR2_SFT, rt5659_alg_dac2_src);
2176
2177static const struct snd_kcontrol_new rt5659_alg_dac_r2_mux =
2178 SOC_DAPM_ENUM("Analog DAC R2 Source", rt5659_alg_dac_r2_enum);
2179
2180/* Interface2 ADC Data Input*/
2181/* MX-2F [13:12] */
2182static const char * const rt5659_if2_adc_in_src[] = {
2183 "IF_ADC1", "IF_ADC2", "DAC_REF", "IF_ADC3"
2184};
2185
2186static const SOC_ENUM_SINGLE_DECL(
2187 rt5659_if2_adc_in_enum, RT5659_DIG_INF23_DATA,
2188 RT5659_IF2_ADC_IN_SFT, rt5659_if2_adc_in_src);
2189
2190static const struct snd_kcontrol_new rt5659_if2_adc_in_mux =
2191 SOC_DAPM_ENUM("IF2 ADC IN Source", rt5659_if2_adc_in_enum);
2192
2193/* Interface3 ADC Data Input*/
2194/* MX-2F [1:0] */
2195static const char * const rt5659_if3_adc_in_src[] = {
2196 "IF_ADC1", "IF_ADC2", "DAC_REF", "Stereo2_ADC_L/R"
2197};
2198
2199static const SOC_ENUM_SINGLE_DECL(
2200 rt5659_if3_adc_in_enum, RT5659_DIG_INF23_DATA,
2201 RT5659_IF3_ADC_IN_SFT, rt5659_if3_adc_in_src);
2202
2203static const struct snd_kcontrol_new rt5659_if3_adc_in_mux =
2204 SOC_DAPM_ENUM("IF3 ADC IN Source", rt5659_if3_adc_in_enum);
2205
2206/* PDM 1 L/R*/
2207/* MX-31 [15] [13] */
2208static const char * const rt5659_pdm_src[] = {
2209 "Mono DAC", "Stereo DAC"
2210};
2211
2212static const SOC_ENUM_SINGLE_DECL(
2213 rt5659_pdm_l_enum, RT5659_PDM_OUT_CTRL,
2214 RT5659_PDM1_L_SFT, rt5659_pdm_src);
2215
2216static const struct snd_kcontrol_new rt5659_pdm_l_mux =
2217 SOC_DAPM_ENUM("PDM L Source", rt5659_pdm_l_enum);
2218
2219static const SOC_ENUM_SINGLE_DECL(
2220 rt5659_pdm_r_enum, RT5659_PDM_OUT_CTRL,
2221 RT5659_PDM1_R_SFT, rt5659_pdm_src);
2222
2223static const struct snd_kcontrol_new rt5659_pdm_r_mux =
2224 SOC_DAPM_ENUM("PDM R Source", rt5659_pdm_r_enum);
2225
2226/* SPDIF Output source*/
2227/* MX-36 [1:0] */
2228static const char * const rt5659_spdif_src[] = {
2229 "IF1_DAC1", "IF1_DAC2", "IF2_DAC", "IF3_DAC"
2230};
2231
2232static const SOC_ENUM_SINGLE_DECL(
2233 rt5659_spdif_enum, RT5659_SPDIF_CTRL,
2234 RT5659_SPDIF_SEL_SFT, rt5659_spdif_src);
2235
2236static const struct snd_kcontrol_new rt5659_spdif_mux =
2237 SOC_DAPM_ENUM("SPDIF Source", rt5659_spdif_enum);
2238
2239/* I2S1 TDM ADCDAT Source */
2240/* MX-78[4:0] */
2241static const char * const rt5659_rx_adc_data_src[] = {
2242 "AD1:AD2:DAC:NUL", "AD1:AD2:NUL:DAC", "AD1:DAC:AD2:NUL",
2243 "AD1:DAC:NUL:AD2", "AD1:NUL:DAC:AD2", "AD1:NUL:AD2:DAC",
2244 "AD2:AD1:DAC:NUL", "AD2:AD1:NUL:DAC", "AD2:DAC:AD1:NUL",
2245 "AD2:DAC:NUL:AD1", "AD2:NUL:DAC:AD1", "AD1:NUL:AD1:DAC",
2246 "DAC:AD1:AD2:NUL", "DAC:AD1:NUL:AD2", "DAC:AD2:AD1:NUL",
2247 "DAC:AD2:NUL:AD1", "DAC:NUL:DAC:AD2", "DAC:NUL:AD2:DAC",
2248 "NUL:AD1:AD2:DAC", "NUL:AD1:DAC:AD2", "NUL:AD2:AD1:DAC",
2249 "NUL:AD2:DAC:AD1", "NUL:DAC:DAC:AD2", "NUL:DAC:AD2:DAC"
2250};
2251
2252static const SOC_ENUM_SINGLE_DECL(
2253 rt5659_rx_adc_data_enum, RT5659_TDM_CTRL_2,
2254 RT5659_ADCDAT_SRC_SFT, rt5659_rx_adc_data_src);
2255
2256static const struct snd_kcontrol_new rt5659_rx_adc_dac_mux =
2257 SOC_DAPM_ENUM("TDM ADCDAT Source", rt5659_rx_adc_data_enum);
2258
2259/* Out Volume Switch */
2260static const struct snd_kcontrol_new spkvol_l_switch =
2261 SOC_DAPM_SINGLE("Switch", RT5659_SPO_VOL, RT5659_VOL_L_SFT, 1, 1);
2262
2263static const struct snd_kcontrol_new spkvol_r_switch =
2264 SOC_DAPM_SINGLE("Switch", RT5659_SPO_VOL, RT5659_VOL_R_SFT, 1, 1);
2265
2266static const struct snd_kcontrol_new monovol_switch =
2267 SOC_DAPM_SINGLE("Switch", RT5659_MONO_OUT, RT5659_VOL_L_SFT, 1, 1);
2268
2269static const struct snd_kcontrol_new outvol_l_switch =
2270 SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_VOL_L_SFT, 1, 1);
2271
2272static const struct snd_kcontrol_new outvol_r_switch =
2273 SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_VOL_R_SFT, 1, 1);
2274
2275/* Out Switch */
2276static const struct snd_kcontrol_new spo_switch =
2277 SOC_DAPM_SINGLE("Switch", RT5659_CLASSD_2, RT5659_M_RF_DIG_SFT, 1, 1);
2278
2279static const struct snd_kcontrol_new mono_switch =
2280 SOC_DAPM_SINGLE("Switch", RT5659_MONO_OUT, RT5659_L_MUTE_SFT, 1, 1);
2281
2282static const struct snd_kcontrol_new hpo_l_switch =
2283 SOC_DAPM_SINGLE("Switch", RT5659_HP_VOL, RT5659_L_MUTE_SFT, 1, 1);
2284
2285static const struct snd_kcontrol_new hpo_r_switch =
2286 SOC_DAPM_SINGLE("Switch", RT5659_HP_VOL, RT5659_R_MUTE_SFT, 1, 1);
2287
2288static const struct snd_kcontrol_new lout_l_switch =
2289 SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_L_MUTE_SFT, 1, 1);
2290
2291static const struct snd_kcontrol_new lout_r_switch =
2292 SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_R_MUTE_SFT, 1, 1);
2293
2294static const struct snd_kcontrol_new pdm_l_switch =
2295 SOC_DAPM_SINGLE("Switch", RT5659_PDM_OUT_CTRL, RT5659_M_PDM1_L_SFT, 1,
2296 1);
2297
2298static const struct snd_kcontrol_new pdm_r_switch =
2299 SOC_DAPM_SINGLE("Switch", RT5659_PDM_OUT_CTRL, RT5659_M_PDM1_R_SFT, 1,
2300 1);
2301
2302static int rt5659_spk_event(struct snd_soc_dapm_widget *w,
2303 struct snd_kcontrol *kcontrol, int event)
2304{
2305 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2306
2307 switch (event) {
2308 case SND_SOC_DAPM_PRE_PMU:
2309 snd_soc_update_bits(codec, RT5659_CLASSD_CTRL_1,
2310 RT5659_POW_CLSD_DB_MASK, RT5659_POW_CLSD_DB_EN);
2311 snd_soc_update_bits(codec, RT5659_CLASSD_2,
2312 RT5659_M_RI_DIG, RT5659_M_RI_DIG);
2313 snd_soc_write(codec, RT5659_CLASSD_1, 0x0803);
2314 snd_soc_write(codec, RT5659_SPK_DC_CAILB_CTRL_3, 0x0000);
2315 break;
2316
2317 case SND_SOC_DAPM_POST_PMD:
2318 snd_soc_write(codec, RT5659_CLASSD_1, 0x0011);
2319 snd_soc_update_bits(codec, RT5659_CLASSD_2,
2320 RT5659_M_RI_DIG, 0x0);
2321 snd_soc_write(codec, RT5659_SPK_DC_CAILB_CTRL_3, 0x0003);
2322 snd_soc_update_bits(codec, RT5659_CLASSD_CTRL_1,
2323 RT5659_POW_CLSD_DB_MASK, RT5659_POW_CLSD_DB_DIS);
2324 break;
2325
2326 default:
2327 return 0;
2328 }
2329
2330 return 0;
2331
2332}
2333
2334static int rt5659_mono_event(struct snd_soc_dapm_widget *w,
2335 struct snd_kcontrol *kcontrol, int event)
2336{
2337 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2338
2339 switch (event) {
2340 case SND_SOC_DAPM_PRE_PMU:
2341 snd_soc_write(codec, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e00);
2342 break;
2343
2344 case SND_SOC_DAPM_POST_PMD:
2345 snd_soc_write(codec, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e04);
2346 break;
2347
2348 default:
2349 return 0;
2350 }
2351
2352 return 0;
2353
2354}
2355
2356static int rt5659_hp_event(struct snd_soc_dapm_widget *w,
2357 struct snd_kcontrol *kcontrol, int event)
2358{
2359 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2360
2361 switch (event) {
2362 case SND_SOC_DAPM_POST_PMU:
2363 snd_soc_write(codec, RT5659_HP_CHARGE_PUMP_1, 0x0e1e);
2364 snd_soc_update_bits(codec, RT5659_DEPOP_1, 0x0010, 0x0010);
2365 break;
2366
2367 case SND_SOC_DAPM_PRE_PMD:
2368 snd_soc_write(codec, RT5659_DEPOP_1, 0x0000);
2369 break;
2370
2371 default:
2372 return 0;
2373 }
2374
2375 return 0;
2376}
2377
2378static int set_dmic_power(struct snd_soc_dapm_widget *w,
2379 struct snd_kcontrol *kcontrol, int event)
2380{
2381 switch (event) {
2382 case SND_SOC_DAPM_POST_PMU:
2383 /*Add delay to avoid pop noise*/
2384 msleep(450);
2385 break;
2386
2387 default:
2388 return 0;
2389 }
2390
2391 return 0;
2392}
2393
2394static const struct snd_soc_dapm_widget rt5659_dapm_widgets[] = {
2395 SND_SOC_DAPM_SUPPLY("LDO2", RT5659_PWR_ANLG_3, RT5659_PWR_LDO2_BIT, 0,
2396 NULL, 0),
2397 SND_SOC_DAPM_SUPPLY("PLL", RT5659_PWR_ANLG_3, RT5659_PWR_PLL_BIT, 0,
2398 NULL, 0),
2399 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5659_PWR_VOL,
2400 RT5659_PWR_MIC_DET_BIT, 0, NULL, 0),
2401 SND_SOC_DAPM_SUPPLY("Mono Vref", RT5659_PWR_ANLG_1,
2402 RT5659_PWR_VREF3_BIT, 0, NULL, 0),
2403
2404 /* ASRC */
2405 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5659_ASRC_1,
2406 RT5659_I2S1_ASRC_SFT, 0, NULL, 0),
2407 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5659_ASRC_1,
2408 RT5659_I2S2_ASRC_SFT, 0, NULL, 0),
2409 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5659_ASRC_1,
2410 RT5659_I2S3_ASRC_SFT, 0, NULL, 0),
2411 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5659_ASRC_1,
2412 RT5659_DAC_STO_ASRC_SFT, 0, NULL, 0),
2413 SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5659_ASRC_1,
2414 RT5659_DAC_MONO_L_ASRC_SFT, 0, NULL, 0),
2415 SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5659_ASRC_1,
2416 RT5659_DAC_MONO_R_ASRC_SFT, 0, NULL, 0),
2417 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5659_ASRC_1,
2418 RT5659_ADC_STO1_ASRC_SFT, 0, NULL, 0),
2419 SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5659_ASRC_1,
2420 RT5659_ADC_MONO_L_ASRC_SFT, 0, NULL, 0),
2421 SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5659_ASRC_1,
2422 RT5659_ADC_MONO_R_ASRC_SFT, 0, NULL, 0),
2423
2424 /* Input Side */
2425 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5659_PWR_ANLG_2, RT5659_PWR_MB1_BIT,
2426 0, NULL, 0),
2427 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5659_PWR_ANLG_2, RT5659_PWR_MB2_BIT,
2428 0, NULL, 0),
2429 SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5659_PWR_ANLG_2, RT5659_PWR_MB3_BIT,
2430 0, NULL, 0),
2431
2432 /* Input Lines */
2433 SND_SOC_DAPM_INPUT("DMIC L1"),
2434 SND_SOC_DAPM_INPUT("DMIC R1"),
2435 SND_SOC_DAPM_INPUT("DMIC L2"),
2436 SND_SOC_DAPM_INPUT("DMIC R2"),
2437
2438 SND_SOC_DAPM_INPUT("IN1P"),
2439 SND_SOC_DAPM_INPUT("IN1N"),
2440 SND_SOC_DAPM_INPUT("IN2P"),
2441 SND_SOC_DAPM_INPUT("IN2N"),
2442 SND_SOC_DAPM_INPUT("IN3P"),
2443 SND_SOC_DAPM_INPUT("IN3N"),
2444 SND_SOC_DAPM_INPUT("IN4P"),
2445 SND_SOC_DAPM_INPUT("IN4N"),
2446
2447 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2448 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2449
2450 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2451 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2452 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5659_DMIC_CTRL_1,
2453 RT5659_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2454 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5659_DMIC_CTRL_1,
2455 RT5659_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2456
2457 /* Boost */
2458 SND_SOC_DAPM_PGA("BST1", RT5659_PWR_ANLG_2,
2459 RT5659_PWR_BST1_P_BIT, 0, NULL, 0),
2460 SND_SOC_DAPM_PGA("BST2", RT5659_PWR_ANLG_2,
2461 RT5659_PWR_BST2_P_BIT, 0, NULL, 0),
2462 SND_SOC_DAPM_PGA("BST3", RT5659_PWR_ANLG_2,
2463 RT5659_PWR_BST3_P_BIT, 0, NULL, 0),
2464 SND_SOC_DAPM_PGA("BST4", RT5659_PWR_ANLG_2,
2465 RT5659_PWR_BST4_P_BIT, 0, NULL, 0),
2466 SND_SOC_DAPM_SUPPLY("BST1 Power", RT5659_PWR_ANLG_2,
2467 RT5659_PWR_BST1_BIT, 0, NULL, 0),
2468 SND_SOC_DAPM_SUPPLY("BST2 Power", RT5659_PWR_ANLG_2,
2469 RT5659_PWR_BST2_BIT, 0, NULL, 0),
2470 SND_SOC_DAPM_SUPPLY("BST3 Power", RT5659_PWR_ANLG_2,
2471 RT5659_PWR_BST3_BIT, 0, NULL, 0),
2472 SND_SOC_DAPM_SUPPLY("BST4 Power", RT5659_PWR_ANLG_2,
2473 RT5659_PWR_BST4_BIT, 0, NULL, 0),
2474
2475
2476 /* Input Volume */
2477 SND_SOC_DAPM_PGA("INL VOL", RT5659_PWR_VOL, RT5659_PWR_IN_L_BIT,
2478 0, NULL, 0),
2479 SND_SOC_DAPM_PGA("INR VOL", RT5659_PWR_VOL, RT5659_PWR_IN_R_BIT,
2480 0, NULL, 0),
2481
2482 /* REC Mixer */
2483 SND_SOC_DAPM_MIXER("RECMIX1L", RT5659_PWR_MIXER, RT5659_PWR_RM1_L_BIT,
2484 0, rt5659_rec1_l_mix, ARRAY_SIZE(rt5659_rec1_l_mix)),
2485 SND_SOC_DAPM_MIXER("RECMIX1R", RT5659_PWR_MIXER, RT5659_PWR_RM1_R_BIT,
2486 0, rt5659_rec1_r_mix, ARRAY_SIZE(rt5659_rec1_r_mix)),
2487 SND_SOC_DAPM_MIXER("RECMIX2L", RT5659_PWR_MIXER, RT5659_PWR_RM2_L_BIT,
2488 0, rt5659_rec2_l_mix, ARRAY_SIZE(rt5659_rec2_l_mix)),
2489 SND_SOC_DAPM_MIXER("RECMIX2R", RT5659_PWR_MIXER, RT5659_PWR_RM2_R_BIT,
2490 0, rt5659_rec2_r_mix, ARRAY_SIZE(rt5659_rec2_r_mix)),
2491
2492 /* ADCs */
2493 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
2494 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
2495 SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0),
2496 SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0),
2497
2498 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5659_PWR_DIG_1,
2499 RT5659_PWR_ADC_L1_BIT, 0, NULL, 0),
2500 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5659_PWR_DIG_1,
2501 RT5659_PWR_ADC_R1_BIT, 0, NULL, 0),
2502 SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5659_PWR_DIG_2,
2503 RT5659_PWR_ADC_L2_BIT, 0, NULL, 0),
2504 SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5659_PWR_DIG_2,
2505 RT5659_PWR_ADC_R2_BIT, 0, NULL, 0),
2506 SND_SOC_DAPM_SUPPLY("ADC1 clock", SND_SOC_NOPM, 0, 0, set_adc_clk,
2507 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2508 SND_SOC_DAPM_SUPPLY("ADC2 clock", SND_SOC_NOPM, 0, 0, set_adc_clk,
2509 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2510
2511 /* ADC Mux */
2512 SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2513 &rt5659_sto1_dmic_mux),
2514 SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2515 &rt5659_sto1_dmic_mux),
2516 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2517 &rt5659_sto1_adc1_mux),
2518 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2519 &rt5659_sto1_adc1_mux),
2520 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2521 &rt5659_sto1_adc2_mux),
2522 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2523 &rt5659_sto1_adc2_mux),
2524 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2525 &rt5659_sto1_adc_mux),
2526 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2527 &rt5659_sto1_adc_mux),
2528 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2529 &rt5659_mono_adc_l2_mux),
2530 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2531 &rt5659_mono_adc_r2_mux),
2532 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2533 &rt5659_mono_adc_l1_mux),
2534 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2535 &rt5659_mono_adc_r1_mux),
2536 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2537 &rt5659_mono_dmic_l_mux),
2538 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2539 &rt5659_mono_dmic_r_mux),
2540 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
2541 &rt5659_mono_adc_l_mux),
2542 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
2543 &rt5659_mono_adc_r_mux),
2544 /* ADC Mixer */
2545 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5659_PWR_DIG_2,
2546 RT5659_PWR_ADC_S1F_BIT, 0, NULL, 0),
2547 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5659_PWR_DIG_2,
2548 RT5659_PWR_ADC_S2F_BIT, 0, NULL, 0),
2549 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM,
2550 0, 0, rt5659_sto1_adc_l_mix,
2551 ARRAY_SIZE(rt5659_sto1_adc_l_mix)),
2552 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM,
2553 0, 0, rt5659_sto1_adc_r_mix,
2554 ARRAY_SIZE(rt5659_sto1_adc_r_mix)),
2555 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5659_PWR_DIG_2,
2556 RT5659_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2557 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5659_MONO_ADC_DIG_VOL,
2558 RT5659_L_MUTE_SFT, 1, rt5659_mono_adc_l_mix,
2559 ARRAY_SIZE(rt5659_mono_adc_l_mix)),
2560 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5659_PWR_DIG_2,
2561 RT5659_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2562 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5659_MONO_ADC_DIG_VOL,
2563 RT5659_R_MUTE_SFT, 1, rt5659_mono_adc_r_mix,
2564 ARRAY_SIZE(rt5659_mono_adc_r_mix)),
2565
2566 /* ADC PGA */
2567 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2568 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2569 SND_SOC_DAPM_PGA("IF_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2570 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2571 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2572 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2573 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2574 SND_SOC_DAPM_PGA("Stereo2 ADC LR", SND_SOC_NOPM, 0, 0, NULL, 0),
2575
2576 SND_SOC_DAPM_PGA("Stereo1 ADC Volume L", RT5659_STO1_ADC_DIG_VOL,
2577 RT5659_L_MUTE_SFT, 1, NULL, 0),
2578 SND_SOC_DAPM_PGA("Stereo1 ADC Volume R", RT5659_STO1_ADC_DIG_VOL,
2579 RT5659_R_MUTE_SFT, 1, NULL, 0),
2580
2581 /* Digital Interface */
2582 SND_SOC_DAPM_SUPPLY("I2S1", RT5659_PWR_DIG_1, RT5659_PWR_I2S1_BIT,
2583 0, NULL, 0),
2584 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2585 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2586 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2587 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2588 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2589 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2590 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2591 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2592 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2593 SND_SOC_DAPM_SUPPLY("I2S2", RT5659_PWR_DIG_1, RT5659_PWR_I2S2_BIT, 0,
2594 NULL, 0),
2595 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2596 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2597 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2598 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2599 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2600 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2601 SND_SOC_DAPM_SUPPLY("I2S3", RT5659_PWR_DIG_1, RT5659_PWR_I2S3_BIT, 0,
2602 NULL, 0),
2603 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2604 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2605 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2606 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2607 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2608 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2609
2610 /* Digital Interface Select */
2611 SND_SOC_DAPM_PGA("TDM AD1:AD2:DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2612 SND_SOC_DAPM_PGA("TDM AD2:DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2613 SND_SOC_DAPM_MUX("TDM Data Mux", SND_SOC_NOPM, 0, 0,
2614 &rt5659_rx_adc_dac_mux),
2615 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 0, 0,
2616 &rt5659_if2_adc_in_mux),
2617 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2618 &rt5659_if3_adc_in_mux),
2619 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2620 &rt5659_if1_01_adc_swap_mux),
2621 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2622 &rt5659_if1_23_adc_swap_mux),
2623 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2624 &rt5659_if1_45_adc_swap_mux),
2625 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2626 &rt5659_if1_67_adc_swap_mux),
2627 SND_SOC_DAPM_MUX("IF2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2628 &rt5659_if2_dac_swap_mux),
2629 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2630 &rt5659_if2_adc_swap_mux),
2631 SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2632 &rt5659_if3_dac_swap_mux),
2633 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2634 &rt5659_if3_adc_swap_mux),
2635
2636 /* Audio Interface */
2637 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2638 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2639 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2640 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2641 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2642 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2643
2644 /* Output Side */
2645 /* DAC mixer before sound effect */
2646 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2647 rt5659_dac_l_mix, ARRAY_SIZE(rt5659_dac_l_mix)),
2648 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2649 rt5659_dac_r_mix, ARRAY_SIZE(rt5659_dac_r_mix)),
2650
2651 /* DAC channel Mux */
2652 SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_l1_mux),
2653 SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_r1_mux),
2654 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_l2_mux),
2655 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_r2_mux),
2656
2657 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
2658 &rt5659_alg_dac_l1_mux),
2659 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
2660 &rt5659_alg_dac_r1_mux),
2661 SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0,
2662 &rt5659_alg_dac_l2_mux),
2663 SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0,
2664 &rt5659_alg_dac_r2_mux),
2665
2666 /* DAC Mixer */
2667 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5659_PWR_DIG_2,
2668 RT5659_PWR_DAC_S1F_BIT, 0, NULL, 0),
2669 SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5659_PWR_DIG_2,
2670 RT5659_PWR_DAC_MF_L_BIT, 0, NULL, 0),
2671 SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5659_PWR_DIG_2,
2672 RT5659_PWR_DAC_MF_R_BIT, 0, NULL, 0),
2673 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2674 rt5659_sto_dac_l_mix, ARRAY_SIZE(rt5659_sto_dac_l_mix)),
2675 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2676 rt5659_sto_dac_r_mix, ARRAY_SIZE(rt5659_sto_dac_r_mix)),
2677 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2678 rt5659_mono_dac_l_mix, ARRAY_SIZE(rt5659_mono_dac_l_mix)),
2679 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2680 rt5659_mono_dac_r_mix, ARRAY_SIZE(rt5659_mono_dac_r_mix)),
2681 SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0,
2682 &rt5659_dig_dac_mixl_mux),
2683 SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0,
2684 &rt5659_dig_dac_mixr_mux),
2685
2686 /* DACs */
2687 SND_SOC_DAPM_SUPPLY_S("DAC L1 Power", 1, RT5659_PWR_DIG_1,
2688 RT5659_PWR_DAC_L1_BIT, 0, NULL, 0),
2689 SND_SOC_DAPM_SUPPLY_S("DAC R1 Power", 1, RT5659_PWR_DIG_1,
2690 RT5659_PWR_DAC_R1_BIT, 0, NULL, 0),
2691 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
2692 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
2693
2694 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5659_PWR_DIG_1,
2695 RT5659_PWR_DAC_L2_BIT, 0, NULL, 0),
2696 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5659_PWR_DIG_1,
2697 RT5659_PWR_DAC_R2_BIT, 0, NULL, 0),
2698 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
2699 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
2700 SND_SOC_DAPM_PGA("DAC_REF", SND_SOC_NOPM, 0, 0, NULL, 0),
2701
2702 /* OUT Mixer */
2703 SND_SOC_DAPM_MIXER("SPK MIXL", RT5659_PWR_MIXER, RT5659_PWR_SM_L_BIT,
2704 0, rt5659_spk_l_mix, ARRAY_SIZE(rt5659_spk_l_mix)),
2705 SND_SOC_DAPM_MIXER("SPK MIXR", RT5659_PWR_MIXER, RT5659_PWR_SM_R_BIT,
2706 0, rt5659_spk_r_mix, ARRAY_SIZE(rt5659_spk_r_mix)),
2707 SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5659_PWR_MIXER, RT5659_PWR_MM_BIT,
2708 0, rt5659_monovol_mix, ARRAY_SIZE(rt5659_monovol_mix)),
2709 SND_SOC_DAPM_MIXER("OUT MIXL", RT5659_PWR_MIXER, RT5659_PWR_OM_L_BIT,
2710 0, rt5659_out_l_mix, ARRAY_SIZE(rt5659_out_l_mix)),
2711 SND_SOC_DAPM_MIXER("OUT MIXR", RT5659_PWR_MIXER, RT5659_PWR_OM_R_BIT,
2712 0, rt5659_out_r_mix, ARRAY_SIZE(rt5659_out_r_mix)),
2713
2714 /* Output Volume */
2715 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5659_PWR_VOL, RT5659_PWR_SV_L_BIT, 0,
2716 &spkvol_l_switch),
2717 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5659_PWR_VOL, RT5659_PWR_SV_R_BIT, 0,
2718 &spkvol_r_switch),
2719 SND_SOC_DAPM_SWITCH("MONOVOL", RT5659_PWR_VOL, RT5659_PWR_MV_BIT, 0,
2720 &monovol_switch),
2721 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5659_PWR_VOL, RT5659_PWR_OV_L_BIT, 0,
2722 &outvol_l_switch),
2723 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5659_PWR_VOL, RT5659_PWR_OV_R_BIT, 0,
2724 &outvol_r_switch),
2725
2726 /* SPO/MONO/HPO/LOUT */
2727 SND_SOC_DAPM_MIXER("SPO L MIX", SND_SOC_NOPM, 0, 0, rt5659_spo_l_mix,
2728 ARRAY_SIZE(rt5659_spo_l_mix)),
2729 SND_SOC_DAPM_MIXER("SPO R MIX", SND_SOC_NOPM, 0, 0, rt5659_spo_r_mix,
2730 ARRAY_SIZE(rt5659_spo_r_mix)),
2731 SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5659_mono_mix,
2732 ARRAY_SIZE(rt5659_mono_mix)),
2733 SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5659_lout_l_mix,
2734 ARRAY_SIZE(rt5659_lout_l_mix)),
2735 SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5659_lout_r_mix,
2736 ARRAY_SIZE(rt5659_lout_r_mix)),
2737
2738 SND_SOC_DAPM_PGA_S("SPK Amp", 1, RT5659_PWR_DIG_1, RT5659_PWR_CLS_D_BIT,
2739 0, rt5659_spk_event, SND_SOC_DAPM_POST_PMD |
2740 SND_SOC_DAPM_PRE_PMU),
2741 SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5659_PWR_ANLG_1, RT5659_PWR_MA_BIT,
2742 0, rt5659_mono_event, SND_SOC_DAPM_POST_PMD |
2743 SND_SOC_DAPM_PRE_PMU),
2744 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5659_hp_event,
2745 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2746 SND_SOC_DAPM_PGA("LOUT Amp", SND_SOC_NOPM, 0, 0, NULL, 0),
2747
2748 SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0,
2749 rt5659_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
2750 SND_SOC_DAPM_POST_PMD),
2751
2752 SND_SOC_DAPM_SWITCH("SPO Playback", SND_SOC_NOPM, 0, 0, &spo_switch),
2753 SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0,
2754 &mono_switch),
2755 SND_SOC_DAPM_SWITCH("HPO L Playback", SND_SOC_NOPM, 0, 0,
2756 &hpo_l_switch),
2757 SND_SOC_DAPM_SWITCH("HPO R Playback", SND_SOC_NOPM, 0, 0,
2758 &hpo_r_switch),
2759 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
2760 &lout_l_switch),
2761 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
2762 &lout_r_switch),
2763 SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0,
2764 &pdm_l_switch),
2765 SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0,
2766 &pdm_r_switch),
2767
2768 /* PDM */
2769 SND_SOC_DAPM_SUPPLY("PDM Power", RT5659_PWR_DIG_2,
2770 RT5659_PWR_PDM1_BIT, 0, NULL, 0),
2771 SND_SOC_DAPM_MUX("PDM L Mux", RT5659_PDM_OUT_CTRL,
2772 RT5659_M_PDM1_L_SFT, 1, &rt5659_pdm_l_mux),
2773 SND_SOC_DAPM_MUX("PDM R Mux", RT5659_PDM_OUT_CTRL,
2774 RT5659_M_PDM1_R_SFT, 1, &rt5659_pdm_r_mux),
2775
2776 /* SPDIF */
2777 SND_SOC_DAPM_MUX("SPDIF Mux", SND_SOC_NOPM, 0, 0, &rt5659_spdif_mux),
2778
2779 SND_SOC_DAPM_SUPPLY("SYS CLK DET", RT5659_CLK_DET, 3, 0, NULL, 0),
2780 SND_SOC_DAPM_SUPPLY("CLKDET", RT5659_CLK_DET, 0, 0, NULL, 0),
2781
2782 /* Output Lines */
2783 SND_SOC_DAPM_OUTPUT("HPOL"),
2784 SND_SOC_DAPM_OUTPUT("HPOR"),
2785 SND_SOC_DAPM_OUTPUT("SPOL"),
2786 SND_SOC_DAPM_OUTPUT("SPOR"),
2787 SND_SOC_DAPM_OUTPUT("LOUTL"),
2788 SND_SOC_DAPM_OUTPUT("LOUTR"),
2789 SND_SOC_DAPM_OUTPUT("MONOOUT"),
2790 SND_SOC_DAPM_OUTPUT("PDML"),
2791 SND_SOC_DAPM_OUTPUT("PDMR"),
2792 SND_SOC_DAPM_OUTPUT("SPDIF"),
2793};
2794
2795static const struct snd_soc_dapm_route rt5659_dapm_routes[] = {
2796 /*PLL*/
2797 { "ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll },
2798 { "ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll },
2799 { "ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll },
2800 { "ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll },
2801 { "DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll },
2802 { "DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll },
2803 { "DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll },
2804
2805 /*ASRC*/
2806 { "ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc },
2807 { "ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc },
2808 { "ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc },
2809 { "DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc },
2810 { "DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc },
2811 { "DAC Stereo1 Filter", NULL, "DAC STO ASRC", is_using_asrc },
2812
2813 { "SYS CLK DET", NULL, "CLKDET" },
2814
2815 { "I2S1", NULL, "I2S1 ASRC" },
2816 { "I2S2", NULL, "I2S2 ASRC" },
2817 { "I2S3", NULL, "I2S3 ASRC" },
2818
2819 { "IN1P", NULL, "LDO2" },
2820 { "IN2P", NULL, "LDO2" },
2821 { "IN3P", NULL, "LDO2" },
2822 { "IN4P", NULL, "LDO2" },
2823
2824 { "DMIC1", NULL, "DMIC L1" },
2825 { "DMIC1", NULL, "DMIC R1" },
2826 { "DMIC2", NULL, "DMIC L2" },
2827 { "DMIC2", NULL, "DMIC R2" },
2828
2829 { "BST1", NULL, "IN1P" },
2830 { "BST1", NULL, "IN1N" },
2831 { "BST1", NULL, "BST1 Power" },
2832 { "BST2", NULL, "IN2P" },
2833 { "BST2", NULL, "IN2N" },
2834 { "BST2", NULL, "BST2 Power" },
2835 { "BST3", NULL, "IN3P" },
2836 { "BST3", NULL, "IN3N" },
2837 { "BST3", NULL, "BST3 Power" },
2838 { "BST4", NULL, "IN4P" },
2839 { "BST4", NULL, "IN4N" },
2840 { "BST4", NULL, "BST4 Power" },
2841
2842 { "INL VOL", NULL, "IN2P" },
2843 { "INR VOL", NULL, "IN2N" },
2844
2845 { "RECMIX1L", "SPKVOLL Switch", "SPKVOL L" },
2846 { "RECMIX1L", "INL Switch", "INL VOL" },
2847 { "RECMIX1L", "BST4 Switch", "BST4" },
2848 { "RECMIX1L", "BST3 Switch", "BST3" },
2849 { "RECMIX1L", "BST2 Switch", "BST2" },
2850 { "RECMIX1L", "BST1 Switch", "BST1" },
2851
2852 { "RECMIX1R", "HPOVOLR Switch", "HPO R Playback" },
2853 { "RECMIX1R", "INR Switch", "INR VOL" },
2854 { "RECMIX1R", "BST4 Switch", "BST4" },
2855 { "RECMIX1R", "BST3 Switch", "BST3" },
2856 { "RECMIX1R", "BST2 Switch", "BST2" },
2857 { "RECMIX1R", "BST1 Switch", "BST1" },
2858
2859 { "RECMIX2L", "SPKVOLL Switch", "SPKVOL L" },
2860 { "RECMIX2L", "OUTVOLL Switch", "OUTVOL L" },
2861 { "RECMIX2L", "BST4 Switch", "BST4" },
2862 { "RECMIX2L", "BST3 Switch", "BST3" },
2863 { "RECMIX2L", "BST2 Switch", "BST2" },
2864 { "RECMIX2L", "BST1 Switch", "BST1" },
2865
2866 { "RECMIX2R", "MONOVOL Switch", "MONOVOL" },
2867 { "RECMIX2R", "OUTVOLR Switch", "OUTVOL R" },
2868 { "RECMIX2R", "BST4 Switch", "BST4" },
2869 { "RECMIX2R", "BST3 Switch", "BST3" },
2870 { "RECMIX2R", "BST2 Switch", "BST2" },
2871 { "RECMIX2R", "BST1 Switch", "BST1" },
2872
2873 { "ADC1 L", NULL, "RECMIX1L" },
2874 { "ADC1 L", NULL, "ADC1 L Power" },
2875 { "ADC1 L", NULL, "ADC1 clock" },
2876 { "ADC1 R", NULL, "RECMIX1R" },
2877 { "ADC1 R", NULL, "ADC1 R Power" },
2878 { "ADC1 R", NULL, "ADC1 clock" },
2879
2880 { "ADC2 L", NULL, "RECMIX2L" },
2881 { "ADC2 L", NULL, "ADC2 L Power" },
2882 { "ADC2 L", NULL, "ADC2 clock" },
2883 { "ADC2 R", NULL, "RECMIX2R" },
2884 { "ADC2 R", NULL, "ADC2 R Power" },
2885 { "ADC2 R", NULL, "ADC2 clock" },
2886
2887 { "DMIC L1", NULL, "DMIC CLK" },
2888 { "DMIC L1", NULL, "DMIC1 Power" },
2889 { "DMIC R1", NULL, "DMIC CLK" },
2890 { "DMIC R1", NULL, "DMIC1 Power" },
2891 { "DMIC L2", NULL, "DMIC CLK" },
2892 { "DMIC L2", NULL, "DMIC2 Power" },
2893 { "DMIC R2", NULL, "DMIC CLK" },
2894 { "DMIC R2", NULL, "DMIC2 Power" },
2895
2896 { "Stereo1 DMIC L Mux", "DMIC1", "DMIC L1" },
2897 { "Stereo1 DMIC L Mux", "DMIC2", "DMIC L2" },
2898
2899 { "Stereo1 DMIC R Mux", "DMIC1", "DMIC R1" },
2900 { "Stereo1 DMIC R Mux", "DMIC2", "DMIC R2" },
2901
2902 { "Mono DMIC L Mux", "DMIC1 L", "DMIC L1" },
2903 { "Mono DMIC L Mux", "DMIC2 L", "DMIC L2" },
2904
2905 { "Mono DMIC R Mux", "DMIC1 R", "DMIC R1" },
2906 { "Mono DMIC R Mux", "DMIC2 R", "DMIC R2" },
2907
2908 { "Stereo1 ADC L Mux", "ADC1", "ADC1 L" },
2909 { "Stereo1 ADC L Mux", "ADC2", "ADC2 L" },
2910 { "Stereo1 ADC R Mux", "ADC1", "ADC1 R" },
2911 { "Stereo1 ADC R Mux", "ADC2", "ADC2 R" },
2912
2913 { "Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux" },
2914 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
2915 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux" },
2916 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2917
2918 { "Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux" },
2919 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2920 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux" },
2921 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2922
2923 { "Mono ADC L Mux", "ADC1 L", "ADC1 L" },
2924 { "Mono ADC L Mux", "ADC1 R", "ADC1 R" },
2925 { "Mono ADC L Mux", "ADC2 L", "ADC2 L" },
2926 { "Mono ADC L Mux", "ADC2 R", "ADC2 R" },
2927
2928 { "Mono ADC R Mux", "ADC1 L", "ADC1 L" },
2929 { "Mono ADC R Mux", "ADC1 R", "ADC1 R" },
2930 { "Mono ADC R Mux", "ADC2 L", "ADC2 L" },
2931 { "Mono ADC R Mux", "ADC2 R", "ADC2 R" },
2932
2933 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
2934 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2935 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2936 { "Mono ADC L1 Mux", "ADC", "Mono ADC L Mux" },
2937
2938 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2939 { "Mono ADC R1 Mux", "ADC", "Mono ADC R Mux" },
2940 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
2941 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2942
2943 { "Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
2944 { "Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
2945 { "Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter" },
2946
2947 { "Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
2948 { "Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
2949 { "Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter" },
2950
2951 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
2952 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
2953 { "Mono ADC MIXL", NULL, "ADC Mono Left Filter" },
2954
2955 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
2956 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
2957 { "Mono ADC MIXR", NULL, "ADC Mono Right Filter" },
2958
2959 { "Stereo1 ADC Volume L", NULL, "Stereo1 ADC MIXL" },
2960 { "Stereo1 ADC Volume R", NULL, "Stereo1 ADC MIXR" },
2961
2962 { "IF_ADC1", NULL, "Stereo1 ADC Volume L" },
2963 { "IF_ADC1", NULL, "Stereo1 ADC Volume R" },
2964 { "IF_ADC2", NULL, "Mono ADC MIXL" },
2965 { "IF_ADC2", NULL, "Mono ADC MIXR" },
2966
2967 { "TDM AD1:AD2:DAC", NULL, "IF_ADC1" },
2968 { "TDM AD1:AD2:DAC", NULL, "IF_ADC2" },
2969 { "TDM AD1:AD2:DAC", NULL, "DAC_REF" },
2970 { "TDM AD2:DAC", NULL, "IF_ADC2" },
2971 { "TDM AD2:DAC", NULL, "DAC_REF" },
2972 { "TDM Data Mux", "AD1:AD2:DAC:NUL", "TDM AD1:AD2:DAC" },
2973 { "TDM Data Mux", "AD1:AD2:NUL:DAC", "TDM AD1:AD2:DAC" },
2974 { "TDM Data Mux", "AD1:DAC:AD2:NUL", "TDM AD1:AD2:DAC" },
2975 { "TDM Data Mux", "AD1:DAC:NUL:AD2", "TDM AD1:AD2:DAC" },
2976 { "TDM Data Mux", "AD1:NUL:DAC:AD2", "TDM AD1:AD2:DAC" },
2977 { "TDM Data Mux", "AD1:NUL:AD2:DAC", "TDM AD1:AD2:DAC" },
2978 { "TDM Data Mux", "AD2:AD1:DAC:NUL", "TDM AD1:AD2:DAC" },
2979 { "TDM Data Mux", "AD2:AD1:NUL:DAC", "TDM AD1:AD2:DAC" },
2980 { "TDM Data Mux", "AD2:DAC:AD1:NUL", "TDM AD1:AD2:DAC" },
2981 { "TDM Data Mux", "AD2:DAC:NUL:AD1", "TDM AD1:AD2:DAC" },
2982 { "TDM Data Mux", "AD2:NUL:DAC:AD1", "TDM AD1:AD2:DAC" },
2983 { "TDM Data Mux", "AD1:NUL:AD1:DAC", "TDM AD1:AD2:DAC" },
2984 { "TDM Data Mux", "DAC:AD1:AD2:NUL", "TDM AD1:AD2:DAC" },
2985 { "TDM Data Mux", "DAC:AD1:NUL:AD2", "TDM AD1:AD2:DAC" },
2986 { "TDM Data Mux", "DAC:AD2:AD1:NUL", "TDM AD1:AD2:DAC" },
2987 { "TDM Data Mux", "DAC:AD2:NUL:AD1", "TDM AD1:AD2:DAC" },
2988 { "TDM Data Mux", "DAC:NUL:DAC:AD2", "TDM AD2:DAC" },
2989 { "TDM Data Mux", "DAC:NUL:AD2:DAC", "TDM AD2:DAC" },
2990 { "TDM Data Mux", "NUL:AD1:AD2:DAC", "TDM AD1:AD2:DAC" },
2991 { "TDM Data Mux", "NUL:AD1:DAC:AD2", "TDM AD1:AD2:DAC" },
2992 { "TDM Data Mux", "NUL:AD2:AD1:DAC", "TDM AD1:AD2:DAC" },
2993 { "TDM Data Mux", "NUL:AD2:DAC:AD1", "TDM AD1:AD2:DAC" },
2994 { "TDM Data Mux", "NUL:DAC:DAC:AD2", "TDM AD2:DAC" },
2995 { "TDM Data Mux", "NUL:DAC:AD2:DAC", "TDM AD2:DAC" },
2996 { "IF1 01 ADC Swap Mux", "L/R", "TDM Data Mux" },
2997 { "IF1 01 ADC Swap Mux", "R/L", "TDM Data Mux" },
2998 { "IF1 01 ADC Swap Mux", "L/L", "TDM Data Mux" },
2999 { "IF1 01 ADC Swap Mux", "R/R", "TDM Data Mux" },
3000 { "IF1 23 ADC Swap Mux", "L/R", "TDM Data Mux" },
3001 { "IF1 23 ADC Swap Mux", "R/L", "TDM Data Mux" },
3002 { "IF1 23 ADC Swap Mux", "L/L", "TDM Data Mux" },
3003 { "IF1 23 ADC Swap Mux", "R/R", "TDM Data Mux" },
3004 { "IF1 45 ADC Swap Mux", "L/R", "TDM Data Mux" },
3005 { "IF1 45 ADC Swap Mux", "R/L", "TDM Data Mux" },
3006 { "IF1 45 ADC Swap Mux", "L/L", "TDM Data Mux" },
3007 { "IF1 45 ADC Swap Mux", "R/R", "TDM Data Mux" },
3008 { "IF1 67 ADC Swap Mux", "L/R", "TDM Data Mux" },
3009 { "IF1 67 ADC Swap Mux", "R/L", "TDM Data Mux" },
3010 { "IF1 67 ADC Swap Mux", "L/L", "TDM Data Mux" },
3011 { "IF1 67 ADC Swap Mux", "R/R", "TDM Data Mux" },
3012 { "IF1 ADC", NULL, "IF1 01 ADC Swap Mux" },
3013 { "IF1 ADC", NULL, "IF1 23 ADC Swap Mux" },
3014 { "IF1 ADC", NULL, "IF1 45 ADC Swap Mux" },
3015 { "IF1 ADC", NULL, "IF1 67 ADC Swap Mux" },
3016 { "IF1 ADC", NULL, "I2S1" },
3017
3018 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
3019 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
3020 { "IF2 ADC Mux", "IF_ADC3", "IF_ADC3" },
3021 { "IF2 ADC Mux", "DAC_REF", "DAC_REF" },
3022 { "IF2 ADC", NULL, "IF2 ADC Mux"},
3023 { "IF2 ADC", NULL, "I2S2" },
3024
3025 { "IF3 ADC Mux", "IF_ADC1", "IF_ADC1" },
3026 { "IF3 ADC Mux", "IF_ADC2", "IF_ADC2" },
3027 { "IF3 ADC Mux", "Stereo2_ADC_L/R", "Stereo2 ADC LR" },
3028 { "IF3 ADC Mux", "DAC_REF", "DAC_REF" },
3029 { "IF3 ADC", NULL, "IF3 ADC Mux"},
3030 { "IF3 ADC", NULL, "I2S3" },
3031
3032 { "AIF1TX", NULL, "IF1 ADC" },
3033 { "IF2 ADC Swap Mux", "L/R", "IF2 ADC" },
3034 { "IF2 ADC Swap Mux", "R/L", "IF2 ADC" },
3035 { "IF2 ADC Swap Mux", "L/L", "IF2 ADC" },
3036 { "IF2 ADC Swap Mux", "R/R", "IF2 ADC" },
3037 { "AIF2TX", NULL, "IF2 ADC Swap Mux" },
3038 { "IF3 ADC Swap Mux", "L/R", "IF3 ADC" },
3039 { "IF3 ADC Swap Mux", "R/L", "IF3 ADC" },
3040 { "IF3 ADC Swap Mux", "L/L", "IF3 ADC" },
3041 { "IF3 ADC Swap Mux", "R/R", "IF3 ADC" },
3042 { "AIF3TX", NULL, "IF3 ADC Swap Mux" },
3043
3044 { "IF1 DAC1", NULL, "AIF1RX" },
3045 { "IF1 DAC2", NULL, "AIF1RX" },
3046 { "IF2 DAC Swap Mux", "L/R", "AIF2RX" },
3047 { "IF2 DAC Swap Mux", "R/L", "AIF2RX" },
3048 { "IF2 DAC Swap Mux", "L/L", "AIF2RX" },
3049 { "IF2 DAC Swap Mux", "R/R", "AIF2RX" },
3050 { "IF2 DAC", NULL, "IF2 DAC Swap Mux" },
3051 { "IF3 DAC Swap Mux", "L/R", "AIF3RX" },
3052 { "IF3 DAC Swap Mux", "R/L", "AIF3RX" },
3053 { "IF3 DAC Swap Mux", "L/L", "AIF3RX" },
3054 { "IF3 DAC Swap Mux", "R/R", "AIF3RX" },
3055 { "IF3 DAC", NULL, "IF3 DAC Swap Mux" },
3056
3057 { "IF1 DAC1", NULL, "I2S1" },
3058 { "IF1 DAC2", NULL, "I2S1" },
3059 { "IF2 DAC", NULL, "I2S2" },
3060 { "IF3 DAC", NULL, "I2S3" },
3061
3062 { "IF1 DAC2 L", NULL, "IF1 DAC2" },
3063 { "IF1 DAC2 R", NULL, "IF1 DAC2" },
3064 { "IF1 DAC1 L", NULL, "IF1 DAC1" },
3065 { "IF1 DAC1 R", NULL, "IF1 DAC1" },
3066 { "IF2 DAC L", NULL, "IF2 DAC" },
3067 { "IF2 DAC R", NULL, "IF2 DAC" },
3068 { "IF3 DAC L", NULL, "IF3 DAC" },
3069 { "IF3 DAC R", NULL, "IF3 DAC" },
3070
3071 { "DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L" },
3072 { "DAC L1 Mux", "IF2 DAC", "IF2 DAC L" },
3073 { "DAC L1 Mux", "IF3 DAC", "IF3 DAC L" },
3074 { "DAC L1 Mux", NULL, "DAC Stereo1 Filter" },
3075
3076 { "DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R" },
3077 { "DAC R1 Mux", "IF2 DAC", "IF2 DAC R" },
3078 { "DAC R1 Mux", "IF3 DAC", "IF3 DAC R" },
3079 { "DAC R1 Mux", NULL, "DAC Stereo1 Filter" },
3080
3081 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC Volume L" },
3082 { "DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux" },
3083 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC Volume R" },
3084 { "DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux" },
3085
3086 { "DAC_REF", NULL, "DAC1 MIXL" },
3087 { "DAC_REF", NULL, "DAC1 MIXR" },
3088
3089 { "DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L" },
3090 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
3091 { "DAC L2 Mux", "IF3 DAC", "IF3 DAC L" },
3092 { "DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL" },
3093 { "DAC L2 Mux", NULL, "DAC Mono Left Filter" },
3094
3095 { "DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R" },
3096 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
3097 { "DAC R2 Mux", "IF3 DAC", "IF3 DAC R" },
3098 { "DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR" },
3099 { "DAC R2 Mux", NULL, "DAC Mono Right Filter" },
3100
3101 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
3102 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
3103 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Mux" },
3104 { "Stereo DAC MIXL", "DAC R2 Switch", "DAC R2 Mux" },
3105
3106 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
3107 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
3108 { "Stereo DAC MIXR", "DAC L2 Switch", "DAC L2 Mux" },
3109 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Mux" },
3110
3111 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
3112 { "Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
3113 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux" },
3114 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux" },
3115 { "Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
3116 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
3117 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux" },
3118 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux" },
3119
3120 { "DAC MIXL", "Stereo DAC Mixer", "Stereo DAC MIXL" },
3121 { "DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL" },
3122 { "DAC MIXR", "Stereo DAC Mixer", "Stereo DAC MIXR" },
3123 { "DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR" },
3124
3125 { "DAC L1 Source", NULL, "DAC L1 Power" },
3126 { "DAC L1 Source", "DAC", "DAC1 MIXL" },
3127 { "DAC L1 Source", "Stereo DAC Mixer", "Stereo DAC MIXL" },
3128 { "DAC R1 Source", NULL, "DAC R1 Power" },
3129 { "DAC R1 Source", "DAC", "DAC1 MIXR" },
3130 { "DAC R1 Source", "Stereo DAC Mixer", "Stereo DAC MIXR" },
3131 { "DAC L2 Source", "Stereo DAC Mixer", "Stereo DAC MIXL" },
3132 { "DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL" },
3133 { "DAC L2 Source", NULL, "DAC L2 Power" },
3134 { "DAC R2 Source", "Stereo DAC Mixer", "Stereo DAC MIXR" },
3135 { "DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR" },
3136 { "DAC R2 Source", NULL, "DAC R2 Power" },
3137
3138 { "DAC L1", NULL, "DAC L1 Source" },
3139 { "DAC R1", NULL, "DAC R1 Source" },
3140 { "DAC L2", NULL, "DAC L2 Source" },
3141 { "DAC R2", NULL, "DAC R2 Source" },
3142
3143 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
3144 { "SPK MIXL", "BST1 Switch", "BST1" },
3145 { "SPK MIXL", "INL Switch", "INL VOL" },
3146 { "SPK MIXL", "INR Switch", "INR VOL" },
3147 { "SPK MIXL", "BST3 Switch", "BST3" },
3148 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
3149 { "SPK MIXR", "BST4 Switch", "BST4" },
3150 { "SPK MIXR", "INL Switch", "INL VOL" },
3151 { "SPK MIXR", "INR Switch", "INR VOL" },
3152 { "SPK MIXR", "BST3 Switch", "BST3" },
3153
3154 { "MONOVOL MIX", "DAC L2 Switch", "DAC L2" },
3155 { "MONOVOL MIX", "DAC R2 Switch", "DAC R2" },
3156 { "MONOVOL MIX", "BST1 Switch", "BST1" },
3157 { "MONOVOL MIX", "BST2 Switch", "BST2" },
3158 { "MONOVOL MIX", "BST3 Switch", "BST3" },
3159
3160 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
3161 { "OUT MIXL", "INL Switch", "INL VOL" },
3162 { "OUT MIXL", "BST1 Switch", "BST1" },
3163 { "OUT MIXL", "BST2 Switch", "BST2" },
3164 { "OUT MIXL", "BST3 Switch", "BST3" },
3165 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
3166 { "OUT MIXR", "INR Switch", "INR VOL" },
3167 { "OUT MIXR", "BST2 Switch", "BST2" },
3168 { "OUT MIXR", "BST3 Switch", "BST3" },
3169 { "OUT MIXR", "BST4 Switch", "BST4" },
3170
3171 { "SPKVOL L", "Switch", "SPK MIXL" },
3172 { "SPKVOL R", "Switch", "SPK MIXR" },
3173 { "SPO L MIX", "DAC L2 Switch", "DAC L2" },
3174 { "SPO L MIX", "SPKVOL L Switch", "SPKVOL L" },
3175 { "SPO R MIX", "DAC R2 Switch", "DAC R2" },
3176 { "SPO R MIX", "SPKVOL R Switch", "SPKVOL R" },
3177 { "SPK Amp", NULL, "SPO L MIX" },
3178 { "SPK Amp", NULL, "SPO R MIX" },
3179 { "SPK Amp", NULL, "SYS CLK DET" },
3180 { "SPO Playback", "Switch", "SPK Amp" },
3181 { "SPOL", NULL, "SPO Playback" },
3182 { "SPOR", NULL, "SPO Playback" },
3183
3184 { "MONOVOL", "Switch", "MONOVOL MIX" },
3185 { "Mono MIX", "DAC L2 Switch", "DAC L2" },
3186 { "Mono MIX", "MONOVOL Switch", "MONOVOL" },
3187 { "Mono Amp", NULL, "Mono MIX" },
3188 { "Mono Amp", NULL, "Mono Vref" },
3189 { "Mono Amp", NULL, "SYS CLK DET" },
3190 { "Mono Playback", "Switch", "Mono Amp" },
3191 { "MONOOUT", NULL, "Mono Playback" },
3192
3193 { "HP Amp", NULL, "DAC L1" },
3194 { "HP Amp", NULL, "DAC R1" },
3195 { "HP Amp", NULL, "Charge Pump" },
3196 { "HP Amp", NULL, "SYS CLK DET" },
3197 { "HPO L Playback", "Switch", "HP Amp"},
3198 { "HPO R Playback", "Switch", "HP Amp"},
3199 { "HPOL", NULL, "HPO L Playback" },
3200 { "HPOR", NULL, "HPO R Playback" },
3201
3202 { "OUTVOL L", "Switch", "OUT MIXL" },
3203 { "OUTVOL R", "Switch", "OUT MIXR" },
3204 { "LOUT L MIX", "DAC L2 Switch", "DAC L2" },
3205 { "LOUT L MIX", "OUTVOL L Switch", "OUTVOL L" },
3206 { "LOUT R MIX", "DAC R2 Switch", "DAC R2" },
3207 { "LOUT R MIX", "OUTVOL R Switch", "OUTVOL R" },
3208 { "LOUT Amp", NULL, "LOUT L MIX" },
3209 { "LOUT Amp", NULL, "LOUT R MIX" },
3210 { "LOUT Amp", NULL, "SYS CLK DET" },
3211 { "LOUT L Playback", "Switch", "LOUT Amp" },
3212 { "LOUT R Playback", "Switch", "LOUT Amp" },
3213 { "LOUTL", NULL, "LOUT L Playback" },
3214 { "LOUTR", NULL, "LOUT R Playback" },
3215
3216 { "PDM L Mux", "Mono DAC", "Mono DAC MIXL" },
3217 { "PDM L Mux", "Stereo DAC", "Stereo DAC MIXL" },
3218 { "PDM L Mux", NULL, "PDM Power" },
3219 { "PDM R Mux", "Mono DAC", "Mono DAC MIXR" },
3220 { "PDM R Mux", "Stereo DAC", "Stereo DAC MIXR" },
3221 { "PDM R Mux", NULL, "PDM Power" },
3222 { "PDM L Playback", "Switch", "PDM L Mux" },
3223 { "PDM R Playback", "Switch", "PDM R Mux" },
3224 { "PDML", NULL, "PDM L Playback" },
3225 { "PDMR", NULL, "PDM R Playback" },
3226
3227 { "SPDIF Mux", "IF3_DAC", "IF3 DAC" },
3228 { "SPDIF Mux", "IF2_DAC", "IF2 DAC" },
3229 { "SPDIF Mux", "IF1_DAC2", "IF1 DAC2" },
3230 { "SPDIF Mux", "IF1_DAC1", "IF1 DAC1" },
3231 { "SPDIF", NULL, "SPDIF Mux" },
3232};
3233
3234static int rt5659_hw_params(struct snd_pcm_substream *substream,
3235 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
3236{
3237 struct snd_soc_codec *codec = dai->codec;
3238 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
3239 unsigned int val_len = 0, val_clk, mask_clk;
3240 int pre_div, frame_size;
3241
3242 rt5659->lrck[dai->id] = params_rate(params);
3243 pre_div = rl6231_get_clk_info(rt5659->sysclk, rt5659->lrck[dai->id]);
3244 if (pre_div < 0) {
3245 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
3246 rt5659->lrck[dai->id], dai->id);
3247 return -EINVAL;
3248 }
3249 frame_size = snd_soc_params_to_frame_size(params);
3250 if (frame_size < 0) {
3251 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
3252 return -EINVAL;
3253 }
3254
3255 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
3256 rt5659->lrck[dai->id], pre_div, dai->id);
3257
3258 switch (params_width(params)) {
3259 case 16:
3260 break;
3261 case 20:
3262 val_len |= RT5659_I2S_DL_20;
3263 break;
3264 case 24:
3265 val_len |= RT5659_I2S_DL_24;
3266 break;
3267 case 8:
3268 val_len |= RT5659_I2S_DL_8;
3269 break;
3270 default:
3271 return -EINVAL;
3272 }
3273
3274 switch (dai->id) {
3275 case RT5659_AIF1:
3276 mask_clk = RT5659_I2S_PD1_MASK;
3277 val_clk = pre_div << RT5659_I2S_PD1_SFT;
3278 snd_soc_update_bits(codec, RT5659_I2S1_SDP,
3279 RT5659_I2S_DL_MASK, val_len);
3280 break;
3281 case RT5659_AIF2:
3282 mask_clk = RT5659_I2S_PD2_MASK;
3283 val_clk = pre_div << RT5659_I2S_PD2_SFT;
3284 snd_soc_update_bits(codec, RT5659_I2S2_SDP,
3285 RT5659_I2S_DL_MASK, val_len);
3286 break;
3287 case RT5659_AIF3:
3288 mask_clk = RT5659_I2S_PD3_MASK;
3289 val_clk = pre_div << RT5659_I2S_PD3_SFT;
3290 snd_soc_update_bits(codec, RT5659_I2S3_SDP,
3291 RT5659_I2S_DL_MASK, val_len);
3292 break;
3293 default:
3294 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
3295 return -EINVAL;
3296 }
3297
3298 snd_soc_update_bits(codec, RT5659_ADDA_CLK_1, mask_clk, val_clk);
3299
3300 switch (rt5659->lrck[dai->id]) {
3301 case 192000:
3302 snd_soc_update_bits(codec, RT5659_ADDA_CLK_1,
3303 RT5659_DAC_OSR_MASK, RT5659_DAC_OSR_32);
3304 break;
3305 case 96000:
3306 snd_soc_update_bits(codec, RT5659_ADDA_CLK_1,
3307 RT5659_DAC_OSR_MASK, RT5659_DAC_OSR_64);
3308 break;
3309 default:
3310 snd_soc_update_bits(codec, RT5659_ADDA_CLK_1,
3311 RT5659_DAC_OSR_MASK, RT5659_DAC_OSR_128);
3312 break;
3313 }
3314
3315 return 0;
3316}
3317
3318static int rt5659_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3319{
3320 struct snd_soc_codec *codec = dai->codec;
3321 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
3322 unsigned int reg_val = 0;
3323
3324 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
3325 case SND_SOC_DAIFMT_CBM_CFM:
3326 rt5659->master[dai->id] = 1;
3327 break;
3328 case SND_SOC_DAIFMT_CBS_CFS:
3329 reg_val |= RT5659_I2S_MS_S;
3330 rt5659->master[dai->id] = 0;
3331 break;
3332 default:
3333 return -EINVAL;
3334 }
3335
3336 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3337 case SND_SOC_DAIFMT_NB_NF:
3338 break;
3339 case SND_SOC_DAIFMT_IB_NF:
3340 reg_val |= RT5659_I2S_BP_INV;
3341 break;
3342 default:
3343 return -EINVAL;
3344 }
3345
3346 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
3347 case SND_SOC_DAIFMT_I2S:
3348 break;
3349 case SND_SOC_DAIFMT_LEFT_J:
3350 reg_val |= RT5659_I2S_DF_LEFT;
3351 break;
3352 case SND_SOC_DAIFMT_DSP_A:
3353 reg_val |= RT5659_I2S_DF_PCM_A;
3354 break;
3355 case SND_SOC_DAIFMT_DSP_B:
3356 reg_val |= RT5659_I2S_DF_PCM_B;
3357 break;
3358 default:
3359 return -EINVAL;
3360 }
3361
3362 switch (dai->id) {
3363 case RT5659_AIF1:
3364 snd_soc_update_bits(codec, RT5659_I2S1_SDP,
3365 RT5659_I2S_MS_MASK | RT5659_I2S_BP_MASK |
3366 RT5659_I2S_DF_MASK, reg_val);
3367 break;
3368 case RT5659_AIF2:
3369 snd_soc_update_bits(codec, RT5659_I2S2_SDP,
3370 RT5659_I2S_MS_MASK | RT5659_I2S_BP_MASK |
3371 RT5659_I2S_DF_MASK, reg_val);
3372 break;
3373 case RT5659_AIF3:
3374 snd_soc_update_bits(codec, RT5659_I2S3_SDP,
3375 RT5659_I2S_MS_MASK | RT5659_I2S_BP_MASK |
3376 RT5659_I2S_DF_MASK, reg_val);
3377 break;
3378 default:
3379 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
3380 return -EINVAL;
3381 }
3382 return 0;
3383}
3384
3385static int rt5659_set_dai_sysclk(struct snd_soc_dai *dai,
3386 int clk_id, unsigned int freq, int dir)
3387{
3388 struct snd_soc_codec *codec = dai->codec;
3389 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
3390 unsigned int reg_val = 0;
3391
3392 if (freq == rt5659->sysclk && clk_id == rt5659->sysclk_src)
3393 return 0;
3394
3395 switch (clk_id) {
3396 case RT5659_SCLK_S_MCLK:
3397 reg_val |= RT5659_SCLK_SRC_MCLK;
3398 break;
3399 case RT5659_SCLK_S_PLL1:
3400 reg_val |= RT5659_SCLK_SRC_PLL1;
3401 break;
3402 case RT5659_SCLK_S_RCCLK:
3403 reg_val |= RT5659_SCLK_SRC_RCCLK;
3404 break;
3405 default:
3406 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
3407 return -EINVAL;
3408 }
3409 snd_soc_update_bits(codec, RT5659_GLB_CLK,
3410 RT5659_SCLK_SRC_MASK, reg_val);
3411 rt5659->sysclk = freq;
3412 rt5659->sysclk_src = clk_id;
3413
3414 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
3415
3416 return 0;
3417}
3418
3419static int rt5659_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int Source,
3420 unsigned int freq_in, unsigned int freq_out)
3421{
3422 struct snd_soc_codec *codec = dai->codec;
3423 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
3424 struct rl6231_pll_code pll_code;
3425 int ret;
3426
3427 if (Source == rt5659->pll_src && freq_in == rt5659->pll_in &&
3428 freq_out == rt5659->pll_out)
3429 return 0;
3430
3431 if (!freq_in || !freq_out) {
3432 dev_dbg(codec->dev, "PLL disabled\n");
3433
3434 rt5659->pll_in = 0;
3435 rt5659->pll_out = 0;
3436 snd_soc_update_bits(codec, RT5659_GLB_CLK,
3437 RT5659_SCLK_SRC_MASK, RT5659_SCLK_SRC_MCLK);
3438 return 0;
3439 }
3440
3441 switch (Source) {
3442 case RT5659_PLL1_S_MCLK:
3443 snd_soc_update_bits(codec, RT5659_GLB_CLK,
3444 RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_MCLK);
3445 break;
3446 case RT5659_PLL1_S_BCLK1:
3447 snd_soc_update_bits(codec, RT5659_GLB_CLK,
3448 RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_BCLK1);
3449 break;
3450 case RT5659_PLL1_S_BCLK2:
3451 snd_soc_update_bits(codec, RT5659_GLB_CLK,
3452 RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_BCLK2);
3453 break;
3454 case RT5659_PLL1_S_BCLK3:
3455 snd_soc_update_bits(codec, RT5659_GLB_CLK,
3456 RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_BCLK3);
3457 break;
3458 default:
3459 dev_err(codec->dev, "Unknown PLL Source %d\n", Source);
3460 return -EINVAL;
3461 }
3462
3463 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
3464 if (ret < 0) {
3465 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
3466 return ret;
3467 }
3468
3469 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
3470 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
3471 pll_code.n_code, pll_code.k_code);
3472
3473 snd_soc_write(codec, RT5659_PLL_CTRL_1,
3474 pll_code.n_code << RT5659_PLL_N_SFT | pll_code.k_code);
3475 snd_soc_write(codec, RT5659_PLL_CTRL_2,
3476 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5659_PLL_M_SFT |
3477 pll_code.m_bp << RT5659_PLL_M_BP_SFT);
3478
3479 rt5659->pll_in = freq_in;
3480 rt5659->pll_out = freq_out;
3481 rt5659->pll_src = Source;
3482
3483 return 0;
3484}
3485
3486static int rt5659_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
3487 unsigned int rx_mask, int slots, int slot_width)
3488{
3489 struct snd_soc_codec *codec = dai->codec;
3490 unsigned int val = 0;
3491
3492 if (rx_mask || tx_mask)
3493 val |= (1 << 15);
3494
3495 switch (slots) {
3496 case 4:
3497 val |= (1 << 10);
3498 val |= (1 << 8);
3499 break;
3500 case 6:
3501 val |= (2 << 10);
3502 val |= (2 << 8);
3503 break;
3504 case 8:
3505 val |= (3 << 10);
3506 val |= (3 << 8);
3507 break;
3508 case 2:
3509 break;
3510 default:
3511 return -EINVAL;
3512 }
3513
3514 switch (slot_width) {
3515 case 20:
3516 val |= (1 << 6);
3517 val |= (1 << 4);
3518 break;
3519 case 24:
3520 val |= (2 << 6);
3521 val |= (2 << 4);
3522 break;
3523 case 32:
3524 val |= (3 << 6);
3525 val |= (3 << 4);
3526 break;
3527 case 16:
3528 break;
3529 default:
3530 return -EINVAL;
3531 }
3532
3533 snd_soc_update_bits(codec, RT5659_TDM_CTRL_1, 0x8ff0, val);
3534
3535 return 0;
3536}
3537
3538static int rt5659_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
3539{
3540 struct snd_soc_codec *codec = dai->codec;
3541 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
3542
3543 dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
3544
3545 rt5659->bclk[dai->id] = ratio;
3546
3547 if (ratio == 64) {
3548 switch (dai->id) {
3549 case RT5659_AIF2:
3550 snd_soc_update_bits(codec, RT5659_ADDA_CLK_1,
3551 RT5659_I2S_BCLK_MS2_MASK,
3552 RT5659_I2S_BCLK_MS2_64);
3553 break;
3554 case RT5659_AIF3:
3555 snd_soc_update_bits(codec, RT5659_ADDA_CLK_1,
3556 RT5659_I2S_BCLK_MS3_MASK,
3557 RT5659_I2S_BCLK_MS3_64);
3558 break;
3559 }
3560 }
3561
3562 return 0;
3563}
3564
3565static int rt5659_set_bias_level(struct snd_soc_codec *codec,
3566 enum snd_soc_bias_level level)
3567{
3568 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
3569
3570 switch (level) {
3571 case SND_SOC_BIAS_PREPARE:
3572 regmap_update_bits(rt5659->regmap, RT5659_DIG_MISC,
3573 RT5659_DIG_GATE_CTRL, RT5659_DIG_GATE_CTRL);
3574 regmap_update_bits(rt5659->regmap, RT5659_PWR_DIG_1,
3575 RT5659_PWR_LDO, RT5659_PWR_LDO);
3576 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
3577 RT5659_PWR_MB | RT5659_PWR_VREF1 | RT5659_PWR_VREF2,
3578 RT5659_PWR_MB | RT5659_PWR_VREF1 | RT5659_PWR_VREF2);
3579 msleep(20);
3580 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
3581 RT5659_PWR_FV1 | RT5659_PWR_FV2,
3582 RT5659_PWR_FV1 | RT5659_PWR_FV2);
3583 break;
3584
3585 case SND_SOC_BIAS_OFF:
3586 regmap_update_bits(rt5659->regmap, RT5659_PWR_DIG_1,
3587 RT5659_PWR_LDO, 0);
3588 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
3589 RT5659_PWR_MB | RT5659_PWR_VREF1 | RT5659_PWR_VREF2
3590 | RT5659_PWR_FV1 | RT5659_PWR_FV2,
3591 RT5659_PWR_MB | RT5659_PWR_VREF2);
3592 regmap_update_bits(rt5659->regmap, RT5659_DIG_MISC,
3593 RT5659_DIG_GATE_CTRL, 0);
3594 break;
3595
3596 default:
3597 break;
3598 }
3599
3600 return 0;
3601}
3602
3603static int rt5659_probe(struct snd_soc_codec *codec)
3604{
3605 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
3606
3607 rt5659->codec = codec;
3608
3609 return 0;
3610}
3611
3612static int rt5659_remove(struct snd_soc_codec *codec)
3613{
3614 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
3615
3616 regmap_write(rt5659->regmap, RT5659_RESET, 0);
3617
3618 return 0;
3619}
3620
3621#ifdef CONFIG_PM
3622static int rt5659_suspend(struct snd_soc_codec *codec)
3623{
3624 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
3625
3626 regcache_cache_only(rt5659->regmap, true);
3627 regcache_mark_dirty(rt5659->regmap);
3628 return 0;
3629}
3630
3631static int rt5659_resume(struct snd_soc_codec *codec)
3632{
3633 struct rt5659_priv *rt5659 = snd_soc_codec_get_drvdata(codec);
3634
3635 regcache_cache_only(rt5659->regmap, false);
3636 regcache_sync(rt5659->regmap);
3637
3638 return 0;
3639}
3640#else
3641#define rt5659_suspend NULL
3642#define rt5659_resume NULL
3643#endif
3644
3645#define RT5659_STEREO_RATES SNDRV_PCM_RATE_8000_192000
3646#define RT5659_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3647 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3648
3649static const struct snd_soc_dai_ops rt5659_aif_dai_ops = {
3650 .hw_params = rt5659_hw_params,
3651 .set_fmt = rt5659_set_dai_fmt,
3652 .set_sysclk = rt5659_set_dai_sysclk,
3653 .set_tdm_slot = rt5659_set_tdm_slot,
3654 .set_pll = rt5659_set_dai_pll,
3655 .set_bclk_ratio = rt5659_set_bclk_ratio,
3656};
3657
3658static struct snd_soc_dai_driver rt5659_dai[] = {
3659 {
3660 .name = "rt5659-aif1",
3661 .id = RT5659_AIF1,
3662 .playback = {
3663 .stream_name = "AIF1 Playback",
3664 .channels_min = 1,
3665 .channels_max = 2,
3666 .rates = RT5659_STEREO_RATES,
3667 .formats = RT5659_FORMATS,
3668 },
3669 .capture = {
3670 .stream_name = "AIF1 Capture",
3671 .channels_min = 1,
3672 .channels_max = 2,
3673 .rates = RT5659_STEREO_RATES,
3674 .formats = RT5659_FORMATS,
3675 },
3676 .ops = &rt5659_aif_dai_ops,
3677 },
3678 {
3679 .name = "rt5659-aif2",
3680 .id = RT5659_AIF2,
3681 .playback = {
3682 .stream_name = "AIF2 Playback",
3683 .channels_min = 1,
3684 .channels_max = 2,
3685 .rates = RT5659_STEREO_RATES,
3686 .formats = RT5659_FORMATS,
3687 },
3688 .capture = {
3689 .stream_name = "AIF2 Capture",
3690 .channels_min = 1,
3691 .channels_max = 2,
3692 .rates = RT5659_STEREO_RATES,
3693 .formats = RT5659_FORMATS,
3694 },
3695 .ops = &rt5659_aif_dai_ops,
3696 },
3697 {
3698 .name = "rt5659-aif3",
3699 .id = RT5659_AIF3,
3700 .playback = {
3701 .stream_name = "AIF3 Playback",
3702 .channels_min = 1,
3703 .channels_max = 2,
3704 .rates = RT5659_STEREO_RATES,
3705 .formats = RT5659_FORMATS,
3706 },
3707 .capture = {
3708 .stream_name = "AIF3 Capture",
3709 .channels_min = 1,
3710 .channels_max = 2,
3711 .rates = RT5659_STEREO_RATES,
3712 .formats = RT5659_FORMATS,
3713 },
3714 .ops = &rt5659_aif_dai_ops,
3715 },
3716};
3717
3718static struct snd_soc_codec_driver soc_codec_dev_rt5659 = {
3719 .probe = rt5659_probe,
3720 .remove = rt5659_remove,
3721 .suspend = rt5659_suspend,
3722 .resume = rt5659_resume,
3723 .set_bias_level = rt5659_set_bias_level,
3724 .idle_bias_off = true,
3725 .controls = rt5659_snd_controls,
3726 .num_controls = ARRAY_SIZE(rt5659_snd_controls),
3727 .dapm_widgets = rt5659_dapm_widgets,
3728 .num_dapm_widgets = ARRAY_SIZE(rt5659_dapm_widgets),
3729 .dapm_routes = rt5659_dapm_routes,
3730 .num_dapm_routes = ARRAY_SIZE(rt5659_dapm_routes),
3731};
3732
3733
3734static const struct regmap_config rt5659_regmap = {
3735 .reg_bits = 16,
3736 .val_bits = 16,
3737 .max_register = 0x0400,
3738 .volatile_reg = rt5659_volatile_register,
3739 .readable_reg = rt5659_readable_register,
3740 .cache_type = REGCACHE_RBTREE,
3741 .reg_defaults = rt5659_reg,
3742 .num_reg_defaults = ARRAY_SIZE(rt5659_reg),
3743};
3744
3745static const struct i2c_device_id rt5659_i2c_id[] = {
3746 { "rt5658", 0 },
3747 { "rt5659", 0 },
3748 { }
3749};
3750MODULE_DEVICE_TABLE(i2c, rt5659_i2c_id);
3751
3752static int rt5659_parse_dt(struct rt5659_priv *rt5659, struct device *dev)
3753{
3754 rt5659->pdata.in1_diff = device_property_read_bool(dev,
3755 "realtek,in1-differential");
3756 rt5659->pdata.in3_diff = device_property_read_bool(dev,
3757 "realtek,in3-differential");
3758 rt5659->pdata.in4_diff = device_property_read_bool(dev,
3759 "realtek,in4-differential");
3760
3761
3762 device_property_read_u32(dev, "realtek,dmic1-data-pin",
3763 &rt5659->pdata.dmic1_data_pin);
3764 device_property_read_u32(dev, "realtek,dmic2-data-pin",
3765 &rt5659->pdata.dmic2_data_pin);
3766 device_property_read_u32(dev, "realtek,jd-src",
3767 &rt5659->pdata.jd_src);
3768
3769 return 0;
3770}
3771
3772static void rt5659_calibrate(struct rt5659_priv *rt5659)
3773{
3774 int value, count;
3775
3776 /* Calibrate HPO Start */
3777 /* Fine tune HP Performance */
3778 regmap_write(rt5659->regmap, RT5659_BIAS_CUR_CTRL_8, 0xa502);
3779 regmap_write(rt5659->regmap, RT5659_CHOP_DAC, 0x3030);
3780
3781 regmap_write(rt5659->regmap, RT5659_PRE_DIV_1, 0xef00);
3782 regmap_write(rt5659->regmap, RT5659_PRE_DIV_2, 0xeffc);
3783 regmap_write(rt5659->regmap, RT5659_MICBIAS_2, 0x0280);
3784 regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x0001);
3785 regmap_write(rt5659->regmap, RT5659_GLB_CLK, 0x8000);
3786
3787 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xaa7e);
3788 msleep(60);
3789 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xfe7e);
3790 msleep(50);
3791 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0004);
3792 regmap_write(rt5659->regmap, RT5659_PWR_DIG_2, 0x0400);
3793 msleep(50);
3794 regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0080);
3795 usleep_range(10000, 10005);
3796 regmap_write(rt5659->regmap, RT5659_DEPOP_1, 0x0009);
3797 msleep(50);
3798 regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0f80);
3799 msleep(50);
3800 regmap_write(rt5659->regmap, RT5659_HP_CHARGE_PUMP_1, 0x0e16);
3801 msleep(50);
3802
3803 /* Enalbe K ADC Power And Clock */
3804 regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0505);
3805 msleep(50);
3806 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0184);
3807 regmap_write(rt5659->regmap, RT5659_CALIB_ADC_CTRL, 0x3c05);
3808 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c1);
3809
3810 /* K Headphone */
3811 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1);
3812 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x5100);
3813 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0014);
3814 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0xd100);
3815 msleep(60);
3816
3817 /* Manual K ADC Offset */
3818 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1);
3819 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x4900);
3820 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0016);
3821 regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_1,
3822 0x8000, 0x8000);
3823
3824 count = 0;
3825 while (true) {
3826 regmap_read(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, &value);
3827 if (value & 0x8000)
3828 usleep_range(10000, 10005);
3829 else
3830 break;
3831
3832 if (count > 30) {
3833 dev_err(rt5659->codec->dev,
3834 "HP Calibration 1 Failure\n");
3835 return;
3836 }
3837
3838 count++;
3839 }
3840
3841 /* Manual K Internal Path Offset */
3842 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1);
3843 regmap_write(rt5659->regmap, RT5659_HP_VOL, 0x0000);
3844 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x4500);
3845 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x001f);
3846 regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_1,
3847 0x8000, 0x8000);
3848
3849 count = 0;
3850 while (true) {
3851 regmap_read(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, &value);
3852 if (value & 0x8000)
3853 usleep_range(10000, 10005);
3854 else
3855 break;
3856
3857 if (count > 85) {
3858 dev_err(rt5659->codec->dev,
3859 "HP Calibration 2 Failure\n");
3860 return;
3861 }
3862
3863 count++;
3864 }
3865
3866 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0000);
3867 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c0);
3868 /* Calibrate HPO End */
3869
3870 /* Calibrate SPO Start */
3871 regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x2021);
3872 regmap_write(rt5659->regmap, RT5659_CLASSD_CTRL_1, 0x0260);
3873 regmap_write(rt5659->regmap, RT5659_PWR_MIXER, 0x3000);
3874 regmap_write(rt5659->regmap, RT5659_PWR_VOL, 0xc000);
3875 regmap_write(rt5659->regmap, RT5659_A_DAC_MUX, 0x000c);
3876 regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x8000);
3877 regmap_write(rt5659->regmap, RT5659_SPO_VOL, 0x0808);
3878 regmap_write(rt5659->regmap, RT5659_SPK_L_MIXER, 0x001e);
3879 regmap_write(rt5659->regmap, RT5659_SPK_R_MIXER, 0x001e);
3880 regmap_write(rt5659->regmap, RT5659_CLASSD_1, 0x0803);
3881 regmap_write(rt5659->regmap, RT5659_CLASSD_2, 0x0554);
3882 regmap_write(rt5659->regmap, RT5659_SPO_AMP_GAIN, 0x1103);
3883
3884 /* Enalbe K ADC Power And Clock */
3885 regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0909);
3886 regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x0001,
3887 0x0001);
3888
3889 /* Start Calibration */
3890 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x0000);
3891 regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x0021);
3892 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_1, 0x3e80);
3893 regmap_update_bits(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_1,
3894 0x8000, 0x8000);
3895
3896 count = 0;
3897 while (true) {
3898 regmap_read(rt5659->regmap,
3899 RT5659_SPK_DC_CAILB_CTRL_1, &value);
3900 if (value & 0x8000)
3901 usleep_range(10000, 10005);
3902 else
3903 break;
3904
3905 if (count > 10) {
3906 dev_err(rt5659->codec->dev,
3907 "SPK Calibration Failure\n");
3908 return;
3909 }
3910
3911 count++;
3912 }
3913 /* Calibrate SPO End */
3914
3915 /* Calibrate MONO Start */
3916 regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x0000);
3917 regmap_write(rt5659->regmap, RT5659_MONOMIX_IN_GAIN, 0x021f);
3918 regmap_write(rt5659->regmap, RT5659_MONO_OUT, 0x480a);
3919 /* MONO NG2 GAIN 5dB */
3920 regmap_write(rt5659->regmap, RT5659_MONO_GAIN, 0x0003);
3921 regmap_write(rt5659->regmap, RT5659_MONO_NG2_CTRL_5, 0x0009);
3922
3923 /* Start Calibration */
3924 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x000f);
3925 regmap_write(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e00);
3926 regmap_update_bits(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1,
3927 0x8000, 0x8000);
3928
3929 count = 0;
3930 while (true) {
3931 regmap_read(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1,
3932 &value);
3933 if (value & 0x8000)
3934 usleep_range(10000, 10005);
3935 else
3936 break;
3937
3938 if (count > 35) {
3939 dev_err(rt5659->codec->dev,
3940 "Mono Calibration Failure\n");
3941 return;
3942 }
3943
3944 count++;
3945 }
3946
3947 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x0003);
3948 /* Calibrate MONO End */
3949
3950 /* Power Off */
3951 regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0808);
3952 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0000);
3953 regmap_write(rt5659->regmap, RT5659_CALIB_ADC_CTRL, 0x2005);
3954 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c0);
3955 regmap_write(rt5659->regmap, RT5659_DEPOP_1, 0x0000);
3956 regmap_write(rt5659->regmap, RT5659_CLASSD_1, 0x0011);
3957 regmap_write(rt5659->regmap, RT5659_CLASSD_2, 0x0150);
3958 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xfe3e);
3959 regmap_write(rt5659->regmap, RT5659_MONO_OUT, 0xc80a);
3960 regmap_write(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e04);
3961 regmap_write(rt5659->regmap, RT5659_PWR_MIXER, 0x0000);
3962 regmap_write(rt5659->regmap, RT5659_PWR_VOL, 0x0000);
3963 regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0000);
3964 regmap_write(rt5659->regmap, RT5659_PWR_DIG_2, 0x0000);
3965 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0x003e);
3966 regmap_write(rt5659->regmap, RT5659_CLASSD_CTRL_1, 0x0060);
3967 regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x2021);
3968 regmap_write(rt5659->regmap, RT5659_GLB_CLK, 0x0000);
3969 regmap_write(rt5659->regmap, RT5659_MICBIAS_2, 0x0080);
3970 regmap_write(rt5659->regmap, RT5659_HP_VOL, 0x8080);
3971 regmap_write(rt5659->regmap, RT5659_HP_CHARGE_PUMP_1, 0x0c16);
3972}
3973
3974static int rt5659_i2c_probe(struct i2c_client *i2c,
3975 const struct i2c_device_id *id)
3976{
3977 struct rt5659_platform_data *pdata = dev_get_platdata(&i2c->dev);
3978 struct rt5659_priv *rt5659;
3979 int ret;
3980 unsigned int val;
3981
3982 rt5659 = devm_kzalloc(&i2c->dev, sizeof(struct rt5659_priv),
3983 GFP_KERNEL);
3984
3985 if (rt5659 == NULL)
3986 return -ENOMEM;
3987
3988 rt5659->i2c = i2c;
3989 i2c_set_clientdata(i2c, rt5659);
3990
3991 if (pdata)
3992 rt5659->pdata = *pdata;
3993 else
3994 rt5659_parse_dt(rt5659, &i2c->dev);
3995
3996 rt5659->gpiod_ldo1_en = devm_gpiod_get_optional(&i2c->dev, "ldo1-en",
3997 GPIOD_OUT_HIGH);
3998 if (IS_ERR(rt5659->gpiod_ldo1_en))
3999 dev_warn(&i2c->dev, "Request ldo1-en GPIO failed\n");
4000
4001 rt5659->gpiod_reset = devm_gpiod_get_optional(&i2c->dev, "reset",
4002 GPIOD_OUT_HIGH);
4003
4004 /* Sleep for 300 ms miniumum */
4005 usleep_range(300000, 350000);
4006
4007 rt5659->regmap = devm_regmap_init_i2c(i2c, &rt5659_regmap);
4008 if (IS_ERR(rt5659->regmap)) {
4009 ret = PTR_ERR(rt5659->regmap);
4010 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4011 ret);
4012 return ret;
4013 }
4014
4015 regmap_read(rt5659->regmap, RT5659_DEVICE_ID, &val);
4016 if (val != DEVICE_ID) {
4017 dev_err(&i2c->dev,
4018 "Device with ID register %x is not rt5659\n", val);
4019 return -ENODEV;
4020 }
4021
4022 regmap_write(rt5659->regmap, RT5659_RESET, 0);
4023
4024 rt5659_calibrate(rt5659);
4025
4026 /* line in diff mode*/
4027 if (rt5659->pdata.in1_diff)
4028 regmap_update_bits(rt5659->regmap, RT5659_IN1_IN2,
4029 RT5659_IN1_DF_MASK, RT5659_IN1_DF_MASK);
4030 if (rt5659->pdata.in3_diff)
4031 regmap_update_bits(rt5659->regmap, RT5659_IN3_IN4,
4032 RT5659_IN3_DF_MASK, RT5659_IN3_DF_MASK);
4033 if (rt5659->pdata.in4_diff)
4034 regmap_update_bits(rt5659->regmap, RT5659_IN3_IN4,
4035 RT5659_IN4_DF_MASK, RT5659_IN4_DF_MASK);
4036
4037 /* DMIC pin*/
4038 if (rt5659->pdata.dmic1_data_pin != RT5659_DMIC1_NULL ||
4039 rt5659->pdata.dmic2_data_pin != RT5659_DMIC2_NULL) {
4040 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4041 RT5659_GP2_PIN_MASK, RT5659_GP2_PIN_DMIC1_SCL);
4042
4043 switch (rt5659->pdata.dmic1_data_pin) {
4044 case RT5659_DMIC1_DATA_IN2N:
4045 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
4046 RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_IN2N);
4047 break;
4048
4049 case RT5659_DMIC1_DATA_GPIO5:
4050 regmap_update_bits(rt5659->regmap,
4051 RT5659_GPIO_CTRL_3,
4052 RT5659_I2S2_PIN_MASK,
4053 RT5659_I2S2_PIN_GPIO);
4054 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
4055 RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_GPIO5);
4056 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4057 RT5659_GP5_PIN_MASK, RT5659_GP5_PIN_DMIC1_SDA);
4058 break;
4059
4060 case RT5659_DMIC1_DATA_GPIO9:
4061 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
4062 RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_GPIO9);
4063 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4064 RT5659_GP9_PIN_MASK, RT5659_GP9_PIN_DMIC1_SDA);
4065 break;
4066
4067 case RT5659_DMIC1_DATA_GPIO11:
4068 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
4069 RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_GPIO11);
4070 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4071 RT5659_GP11_PIN_MASK,
4072 RT5659_GP11_PIN_DMIC1_SDA);
4073 break;
4074
4075 default:
4076 dev_dbg(&i2c->dev, "no DMIC1\n");
4077 break;
4078 }
4079
4080 switch (rt5659->pdata.dmic2_data_pin) {
4081 case RT5659_DMIC2_DATA_IN2P:
4082 regmap_update_bits(rt5659->regmap,
4083 RT5659_DMIC_CTRL_1,
4084 RT5659_DMIC_2_DP_MASK,
4085 RT5659_DMIC_2_DP_IN2P);
4086 break;
4087
4088 case RT5659_DMIC2_DATA_GPIO6:
4089 regmap_update_bits(rt5659->regmap,
4090 RT5659_DMIC_CTRL_1,
4091 RT5659_DMIC_2_DP_MASK,
4092 RT5659_DMIC_2_DP_GPIO6);
4093 regmap_update_bits(rt5659->regmap,
4094 RT5659_GPIO_CTRL_1,
4095 RT5659_GP6_PIN_MASK,
4096 RT5659_GP6_PIN_DMIC2_SDA);
4097 break;
4098
4099 case RT5659_DMIC2_DATA_GPIO10:
4100 regmap_update_bits(rt5659->regmap,
4101 RT5659_DMIC_CTRL_1,
4102 RT5659_DMIC_2_DP_MASK,
4103 RT5659_DMIC_2_DP_GPIO10);
4104 regmap_update_bits(rt5659->regmap,
4105 RT5659_GPIO_CTRL_1,
4106 RT5659_GP10_PIN_MASK,
4107 RT5659_GP10_PIN_DMIC2_SDA);
4108 break;
4109
4110 case RT5659_DMIC2_DATA_GPIO12:
4111 regmap_update_bits(rt5659->regmap,
4112 RT5659_DMIC_CTRL_1,
4113 RT5659_DMIC_2_DP_MASK,
4114 RT5659_DMIC_2_DP_GPIO12);
4115 regmap_update_bits(rt5659->regmap,
4116 RT5659_GPIO_CTRL_1,
4117 RT5659_GP12_PIN_MASK,
4118 RT5659_GP12_PIN_DMIC2_SDA);
4119 break;
4120
4121 default:
4122 dev_dbg(&i2c->dev, "no DMIC2\n");
4123 break;
4124
4125 }
4126 } else {
4127 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4128 RT5659_GP2_PIN_MASK | RT5659_GP5_PIN_MASK |
4129 RT5659_GP9_PIN_MASK | RT5659_GP11_PIN_MASK |
4130 RT5659_GP6_PIN_MASK | RT5659_GP10_PIN_MASK |
4131 RT5659_GP12_PIN_MASK,
4132 RT5659_GP2_PIN_GPIO2 | RT5659_GP5_PIN_GPIO5 |
4133 RT5659_GP9_PIN_GPIO9 | RT5659_GP11_PIN_GPIO11 |
4134 RT5659_GP6_PIN_GPIO6 | RT5659_GP10_PIN_GPIO10 |
4135 RT5659_GP12_PIN_GPIO12);
4136 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
4137 RT5659_DMIC_1_DP_MASK | RT5659_DMIC_2_DP_MASK,
4138 RT5659_DMIC_1_DP_IN2N | RT5659_DMIC_2_DP_IN2P);
4139 }
4140
4141 switch (rt5659->pdata.jd_src) {
4142 case RT5659_JD3:
4143 regmap_write(rt5659->regmap, RT5659_EJD_CTRL_1, 0xa880);
4144 regmap_write(rt5659->regmap, RT5659_RC_CLK_CTRL, 0x9000);
4145 regmap_write(rt5659->regmap, RT5659_GPIO_CTRL_1, 0xc800);
4146 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
4147 RT5659_PWR_MB, RT5659_PWR_MB);
4148 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_2, 0x0001);
4149 regmap_write(rt5659->regmap, RT5659_IRQ_CTRL_2, 0x0040);
4150 break;
4151 case RT5659_JD_NULL:
4152 break;
4153 default:
4154 dev_warn(&i2c->dev, "Currently, support JD3 only\n");
4155 break;
4156 }
4157
4158 INIT_DELAYED_WORK(&rt5659->jack_detect_work, rt5659_jack_detect_work);
4159
4160 if (rt5659->i2c->irq) {
4161 ret = request_threaded_irq(rt5659->i2c->irq, NULL, rt5659_irq,
4162 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
4163 | IRQF_ONESHOT, "rt5659", rt5659);
4164 if (ret)
4165 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
4166
4167 }
4168
4169 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5659,
4170 rt5659_dai, ARRAY_SIZE(rt5659_dai));
4171
4172 if (ret) {
4173 if (rt5659->i2c->irq)
4174 free_irq(rt5659->i2c->irq, rt5659);
4175 }
4176
4177 return 0;
4178}
4179
4180static int rt5659_i2c_remove(struct i2c_client *i2c)
4181{
4182 snd_soc_unregister_codec(&i2c->dev);
4183
4184 return 0;
4185}
4186
4187void rt5659_i2c_shutdown(struct i2c_client *client)
4188{
4189 struct rt5659_priv *rt5659 = i2c_get_clientdata(client);
4190
4191 regmap_write(rt5659->regmap, RT5659_RESET, 0);
4192}
4193
4194static const struct of_device_id rt5659_of_match[] = {
4195 { .compatible = "realtek,rt5658", },
4196 { .compatible = "realtek,rt5659", },
4197 {},
4198};
4199
4200static struct acpi_device_id rt5659_acpi_match[] = {
4201 { "10EC5658", 0},
4202 { "10EC5659", 0},
4203 { },
4204};
4205MODULE_DEVICE_TABLE(acpi, rt5659_acpi_match);
4206
4207struct i2c_driver rt5659_i2c_driver = {
4208 .driver = {
4209 .name = "rt5659",
4210 .owner = THIS_MODULE,
4211 .of_match_table = rt5659_of_match,
4212 .acpi_match_table = ACPI_PTR(rt5659_acpi_match),
4213 },
4214 .probe = rt5659_i2c_probe,
4215 .remove = rt5659_i2c_remove,
4216 .shutdown = rt5659_i2c_shutdown,
4217 .id_table = rt5659_i2c_id,
4218};
4219module_i2c_driver(rt5659_i2c_driver);
4220
4221MODULE_DESCRIPTION("ASoC RT5659 driver");
4222MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4223MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/rt5659.h b/sound/soc/codecs/rt5659.h
new file mode 100644
index 000000000000..8f07ee903eaa
--- /dev/null
+++ b/sound/soc/codecs/rt5659.h
@@ -0,0 +1,1819 @@
1/*
2 * rt5659.h -- RT5659/RT5658 ALSA SoC audio driver
3 *
4 * Copyright 2015 Realtek Microelectronics
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __RT5659_H__
13#define __RT5659_H__
14
15#include <sound/rt5659.h>
16
17#define DEVICE_ID 0x6311
18
19/* Info */
20#define RT5659_RESET 0x0000
21#define RT5659_VENDOR_ID 0x00fd
22#define RT5659_VENDOR_ID_1 0x00fe
23#define RT5659_DEVICE_ID 0x00ff
24/* I/O - Output */
25#define RT5659_SPO_VOL 0x0001
26#define RT5659_HP_VOL 0x0002
27#define RT5659_LOUT 0x0003
28#define RT5659_MONO_OUT 0x0004
29#define RT5659_HPL_GAIN 0x0005
30#define RT5659_HPR_GAIN 0x0006
31#define RT5659_MONO_GAIN 0x0007
32#define RT5659_SPDIF_CTRL_1 0x0008
33#define RT5659_SPDIF_CTRL_2 0x0009
34/* I/O - Input */
35#define RT5659_CAL_BST_CTRL 0x000a
36#define RT5659_IN1_IN2 0x000c
37#define RT5659_IN3_IN4 0x000d
38#define RT5659_INL1_INR1_VOL 0x000f
39/* I/O - Speaker */
40#define RT5659_EJD_CTRL_1 0x0010
41#define RT5659_EJD_CTRL_2 0x0011
42#define RT5659_EJD_CTRL_3 0x0012
43#define RT5659_SILENCE_CTRL 0x0015
44#define RT5659_PSV_CTRL 0x0016
45/* I/O - Sidetone */
46#define RT5659_SIDETONE_CTRL 0x0018
47/* I/O - ADC/DAC/DMIC */
48#define RT5659_DAC1_DIG_VOL 0x0019
49#define RT5659_DAC2_DIG_VOL 0x001a
50#define RT5659_DAC_CTRL 0x001b
51#define RT5659_STO1_ADC_DIG_VOL 0x001c
52#define RT5659_MONO_ADC_DIG_VOL 0x001d
53#define RT5659_STO2_ADC_DIG_VOL 0x001e
54#define RT5659_STO1_BOOST 0x001f
55#define RT5659_MONO_BOOST 0x0020
56#define RT5659_STO2_BOOST 0x0021
57#define RT5659_HP_IMP_GAIN_1 0x0022
58#define RT5659_HP_IMP_GAIN_2 0x0023
59/* Mixer - D-D */
60#define RT5659_STO1_ADC_MIXER 0x0026
61#define RT5659_MONO_ADC_MIXER 0x0027
62#define RT5659_AD_DA_MIXER 0x0029
63#define RT5659_STO_DAC_MIXER 0x002a
64#define RT5659_MONO_DAC_MIXER 0x002b
65#define RT5659_DIG_MIXER 0x002c
66#define RT5659_A_DAC_MUX 0x002d
67#define RT5659_DIG_INF23_DATA 0x002f
68/* Mixer - PDM */
69#define RT5659_PDM_OUT_CTRL 0x0031
70#define RT5659_PDM_DATA_CTRL_1 0x0032
71#define RT5659_PDM_DATA_CTRL_2 0x0033
72#define RT5659_PDM_DATA_CTRL_3 0x0034
73#define RT5659_PDM_DATA_CTRL_4 0x0035
74#define RT5659_SPDIF_CTRL 0x0036
75
76/* Mixer - ADC */
77#define RT5659_REC1_GAIN 0x003a
78#define RT5659_REC1_L1_MIXER 0x003b
79#define RT5659_REC1_L2_MIXER 0x003c
80#define RT5659_REC1_R1_MIXER 0x003d
81#define RT5659_REC1_R2_MIXER 0x003e
82#define RT5659_CAL_REC 0x0040
83#define RT5659_REC2_L1_MIXER 0x009b
84#define RT5659_REC2_L2_MIXER 0x009c
85#define RT5659_REC2_R1_MIXER 0x009d
86#define RT5659_REC2_R2_MIXER 0x009e
87#define RT5659_RC_CLK_CTRL 0x009f
88/* Mixer - DAC */
89#define RT5659_SPK_L_MIXER 0x0046
90#define RT5659_SPK_R_MIXER 0x0047
91#define RT5659_SPO_AMP_GAIN 0x0048
92#define RT5659_ALC_BACK_GAIN 0x0049
93#define RT5659_MONOMIX_GAIN 0x004a
94#define RT5659_MONOMIX_IN_GAIN 0x004b
95#define RT5659_OUT_L_GAIN 0x004d
96#define RT5659_OUT_L_MIXER 0x004e
97#define RT5659_OUT_R_GAIN 0x004f
98#define RT5659_OUT_R_MIXER 0x0050
99#define RT5659_LOUT_MIXER 0x0052
100
101#define RT5659_HAPTIC_GEN_CTRL_1 0x0053
102#define RT5659_HAPTIC_GEN_CTRL_2 0x0054
103#define RT5659_HAPTIC_GEN_CTRL_3 0x0055
104#define RT5659_HAPTIC_GEN_CTRL_4 0x0056
105#define RT5659_HAPTIC_GEN_CTRL_5 0x0057
106#define RT5659_HAPTIC_GEN_CTRL_6 0x0058
107#define RT5659_HAPTIC_GEN_CTRL_7 0x0059
108#define RT5659_HAPTIC_GEN_CTRL_8 0x005a
109#define RT5659_HAPTIC_GEN_CTRL_9 0x005b
110#define RT5659_HAPTIC_GEN_CTRL_10 0x005c
111#define RT5659_HAPTIC_GEN_CTRL_11 0x005d
112#define RT5659_HAPTIC_LPF_CTRL_1 0x005e
113#define RT5659_HAPTIC_LPF_CTRL_2 0x005f
114#define RT5659_HAPTIC_LPF_CTRL_3 0x0060
115/* Power */
116#define RT5659_PWR_DIG_1 0x0061
117#define RT5659_PWR_DIG_2 0x0062
118#define RT5659_PWR_ANLG_1 0x0063
119#define RT5659_PWR_ANLG_2 0x0064
120#define RT5659_PWR_ANLG_3 0x0065
121#define RT5659_PWR_MIXER 0x0066
122#define RT5659_PWR_VOL 0x0067
123/* Private Register Control */
124#define RT5659_PRIV_INDEX 0x006a
125#define RT5659_CLK_DET 0x006b
126#define RT5659_PRIV_DATA 0x006c
127/* System Clock Pre Divider Gating Control */
128#define RT5659_PRE_DIV_1 0x006e
129#define RT5659_PRE_DIV_2 0x006f
130/* Format - ADC/DAC */
131#define RT5659_I2S1_SDP 0x0070
132#define RT5659_I2S2_SDP 0x0071
133#define RT5659_I2S3_SDP 0x0072
134#define RT5659_ADDA_CLK_1 0x0073
135#define RT5659_ADDA_CLK_2 0x0074
136#define RT5659_DMIC_CTRL_1 0x0075
137#define RT5659_DMIC_CTRL_2 0x0076
138/* Format - TDM Control */
139#define RT5659_TDM_CTRL_1 0x0077
140#define RT5659_TDM_CTRL_2 0x0078
141#define RT5659_TDM_CTRL_3 0x0079
142#define RT5659_TDM_CTRL_4 0x007a
143#define RT5659_TDM_CTRL_5 0x007b
144
145/* Function - Analog */
146#define RT5659_GLB_CLK 0x0080
147#define RT5659_PLL_CTRL_1 0x0081
148#define RT5659_PLL_CTRL_2 0x0082
149#define RT5659_ASRC_1 0x0083
150#define RT5659_ASRC_2 0x0084
151#define RT5659_ASRC_3 0x0085
152#define RT5659_ASRC_4 0x0086
153#define RT5659_ASRC_5 0x0087
154#define RT5659_ASRC_6 0x0088
155#define RT5659_ASRC_7 0x0089
156#define RT5659_ASRC_8 0x008a
157#define RT5659_ASRC_9 0x008b
158#define RT5659_ASRC_10 0x008c
159#define RT5659_DEPOP_1 0x008e
160#define RT5659_DEPOP_2 0x008f
161#define RT5659_DEPOP_3 0x0090
162#define RT5659_HP_CHARGE_PUMP_1 0x0091
163#define RT5659_HP_CHARGE_PUMP_2 0x0092
164#define RT5659_MICBIAS_1 0x0093
165#define RT5659_MICBIAS_2 0x0094
166#define RT5659_ASRC_11 0x0097
167#define RT5659_ASRC_12 0x0098
168#define RT5659_ASRC_13 0x0099
169#define RT5659_REC_M1_M2_GAIN_CTRL 0x009a
170#define RT5659_CLASSD_CTRL_1 0x00a0
171#define RT5659_CLASSD_CTRL_2 0x00a1
172
173/* Function - Digital */
174#define RT5659_ADC_EQ_CTRL_1 0x00ae
175#define RT5659_ADC_EQ_CTRL_2 0x00af
176#define RT5659_DAC_EQ_CTRL_1 0x00b0
177#define RT5659_DAC_EQ_CTRL_2 0x00b1
178#define RT5659_DAC_EQ_CTRL_3 0x00b2
179
180#define RT5659_IRQ_CTRL_1 0x00b6
181#define RT5659_IRQ_CTRL_2 0x00b7
182#define RT5659_IRQ_CTRL_3 0x00b8
183#define RT5659_IRQ_CTRL_4 0x00b9
184#define RT5659_IRQ_CTRL_5 0x00ba
185#define RT5659_IRQ_CTRL_6 0x00bb
186#define RT5659_INT_ST_1 0x00be
187#define RT5659_INT_ST_2 0x00bf
188#define RT5659_GPIO_CTRL_1 0x00c0
189#define RT5659_GPIO_CTRL_2 0x00c1
190#define RT5659_GPIO_CTRL_3 0x00c2
191#define RT5659_GPIO_CTRL_4 0x00c3
192#define RT5659_GPIO_CTRL_5 0x00c4
193#define RT5659_GPIO_STA 0x00c5
194#define RT5659_SINE_GEN_CTRL_1 0x00cb
195#define RT5659_SINE_GEN_CTRL_2 0x00cc
196#define RT5659_SINE_GEN_CTRL_3 0x00cd
197#define RT5659_HP_AMP_DET_CTRL_1 0x00d6
198#define RT5659_HP_AMP_DET_CTRL_2 0x00d7
199#define RT5659_SV_ZCD_1 0x00d9
200#define RT5659_SV_ZCD_2 0x00da
201#define RT5659_IL_CMD_1 0x00db
202#define RT5659_IL_CMD_2 0x00dc
203#define RT5659_IL_CMD_3 0x00dd
204#define RT5659_IL_CMD_4 0x00de
205#define RT5659_4BTN_IL_CMD_1 0x00df
206#define RT5659_4BTN_IL_CMD_2 0x00e0
207#define RT5659_4BTN_IL_CMD_3 0x00e1
208#define RT5659_PSV_IL_CMD_1 0x00e4
209#define RT5659_PSV_IL_CMD_2 0x00e5
210
211#define RT5659_ADC_STO1_HP_CTRL_1 0x00ea
212#define RT5659_ADC_STO1_HP_CTRL_2 0x00eb
213#define RT5659_ADC_MONO_HP_CTRL_1 0x00ec
214#define RT5659_ADC_MONO_HP_CTRL_2 0x00ed
215#define RT5659_AJD1_CTRL 0x00f0
216#define RT5659_AJD2_AJD3_CTRL 0x00f1
217#define RT5659_JD1_THD 0x00f2
218#define RT5659_JD2_THD 0x00f3
219#define RT5659_JD3_THD 0x00f4
220#define RT5659_JD_CTRL_1 0x00f6
221#define RT5659_JD_CTRL_2 0x00f7
222#define RT5659_JD_CTRL_3 0x00f8
223#define RT5659_JD_CTRL_4 0x00f9
224/* General Control */
225#define RT5659_DIG_MISC 0x00fa
226#define RT5659_DUMMY_2 0x00fb
227#define RT5659_DUMMY_3 0x00fc
228
229#define RT5659_DAC_ADC_DIG_VOL 0x0100
230#define RT5659_BIAS_CUR_CTRL_1 0x010a
231#define RT5659_BIAS_CUR_CTRL_2 0x010b
232#define RT5659_BIAS_CUR_CTRL_3 0x010c
233#define RT5659_BIAS_CUR_CTRL_4 0x010d
234#define RT5659_BIAS_CUR_CTRL_5 0x010e
235#define RT5659_BIAS_CUR_CTRL_6 0x010f
236#define RT5659_BIAS_CUR_CTRL_7 0x0110
237#define RT5659_BIAS_CUR_CTRL_8 0x0111
238#define RT5659_BIAS_CUR_CTRL_9 0x0112
239#define RT5659_BIAS_CUR_CTRL_10 0x0113
240#define RT5659_MEMORY_TEST 0x0116
241#define RT5659_VREF_REC_OP_FB_CAP_CTRL 0x0117
242#define RT5659_CLASSD_0 0x011a
243#define RT5659_CLASSD_1 0x011b
244#define RT5659_CLASSD_2 0x011c
245#define RT5659_CLASSD_3 0x011d
246#define RT5659_CLASSD_4 0x011e
247#define RT5659_CLASSD_5 0x011f
248#define RT5659_CLASSD_6 0x0120
249#define RT5659_CLASSD_7 0x0121
250#define RT5659_CLASSD_8 0x0122
251#define RT5659_CLASSD_9 0x0123
252#define RT5659_CLASSD_10 0x0124
253#define RT5659_CHARGE_PUMP_1 0x0125
254#define RT5659_CHARGE_PUMP_2 0x0126
255#define RT5659_DIG_IN_CTRL_1 0x0132
256#define RT5659_DIG_IN_CTRL_2 0x0133
257#define RT5659_PAD_DRIVING_CTRL 0x0137
258#define RT5659_SOFT_RAMP_DEPOP 0x0138
259#define RT5659_PLL 0x0139
260#define RT5659_CHOP_DAC 0x013a
261#define RT5659_CHOP_ADC 0x013b
262#define RT5659_CALIB_ADC_CTRL 0x013c
263#define RT5659_SOFT_RAMP_DEPOP_DAC_CLK_CTRL 0x013e
264#define RT5659_VOL_TEST 0x013f
265#define RT5659_TEST_MODE_CTRL_1 0x0145
266#define RT5659_TEST_MODE_CTRL_2 0x0146
267#define RT5659_TEST_MODE_CTRL_3 0x0147
268#define RT5659_TEST_MODE_CTRL_4 0x0148
269#define RT5659_BASSBACK_CTRL 0x0150
270#define RT5659_MP3_PLUS_CTRL_1 0x0151
271#define RT5659_MP3_PLUS_CTRL_2 0x0152
272#define RT5659_MP3_HPF_A1 0x0153
273#define RT5659_MP3_HPF_A2 0x0154
274#define RT5659_MP3_HPF_H0 0x0155
275#define RT5659_MP3_LPF_H0 0x0156
276#define RT5659_3D_SPK_CTRL 0x0157
277#define RT5659_3D_SPK_COEF_1 0x0158
278#define RT5659_3D_SPK_COEF_2 0x0159
279#define RT5659_3D_SPK_COEF_3 0x015a
280#define RT5659_3D_SPK_COEF_4 0x015b
281#define RT5659_3D_SPK_COEF_5 0x015c
282#define RT5659_3D_SPK_COEF_6 0x015d
283#define RT5659_3D_SPK_COEF_7 0x015e
284#define RT5659_STO_NG2_CTRL_1 0x0160
285#define RT5659_STO_NG2_CTRL_2 0x0161
286#define RT5659_STO_NG2_CTRL_3 0x0162
287#define RT5659_STO_NG2_CTRL_4 0x0163
288#define RT5659_STO_NG2_CTRL_5 0x0164
289#define RT5659_STO_NG2_CTRL_6 0x0165
290#define RT5659_STO_NG2_CTRL_7 0x0166
291#define RT5659_STO_NG2_CTRL_8 0x0167
292#define RT5659_MONO_NG2_CTRL_1 0x0170
293#define RT5659_MONO_NG2_CTRL_2 0x0171
294#define RT5659_MONO_NG2_CTRL_3 0x0172
295#define RT5659_MONO_NG2_CTRL_4 0x0173
296#define RT5659_MONO_NG2_CTRL_5 0x0174
297#define RT5659_MONO_NG2_CTRL_6 0x0175
298#define RT5659_MID_HP_AMP_DET 0x0190
299#define RT5659_LOW_HP_AMP_DET 0x0191
300#define RT5659_LDO_CTRL 0x0192
301#define RT5659_HP_DECROSS_CTRL_1 0x01b0
302#define RT5659_HP_DECROSS_CTRL_2 0x01b1
303#define RT5659_HP_DECROSS_CTRL_3 0x01b2
304#define RT5659_HP_DECROSS_CTRL_4 0x01b3
305#define RT5659_HP_IMP_SENS_CTRL_1 0x01c0
306#define RT5659_HP_IMP_SENS_CTRL_2 0x01c1
307#define RT5659_HP_IMP_SENS_CTRL_3 0x01c2
308#define RT5659_HP_IMP_SENS_CTRL_4 0x01c3
309#define RT5659_HP_IMP_SENS_MAP_1 0x01c7
310#define RT5659_HP_IMP_SENS_MAP_2 0x01c8
311#define RT5659_HP_IMP_SENS_MAP_3 0x01c9
312#define RT5659_HP_IMP_SENS_MAP_4 0x01ca
313#define RT5659_HP_IMP_SENS_MAP_5 0x01cb
314#define RT5659_HP_IMP_SENS_MAP_6 0x01cc
315#define RT5659_HP_IMP_SENS_MAP_7 0x01cd
316#define RT5659_HP_IMP_SENS_MAP_8 0x01ce
317#define RT5659_HP_LOGIC_CTRL_1 0x01da
318#define RT5659_HP_LOGIC_CTRL_2 0x01db
319#define RT5659_HP_CALIB_CTRL_1 0x01de
320#define RT5659_HP_CALIB_CTRL_2 0x01df
321#define RT5659_HP_CALIB_CTRL_3 0x01e0
322#define RT5659_HP_CALIB_CTRL_4 0x01e1
323#define RT5659_HP_CALIB_CTRL_5 0x01e2
324#define RT5659_HP_CALIB_CTRL_6 0x01e3
325#define RT5659_HP_CALIB_CTRL_7 0x01e4
326#define RT5659_HP_CALIB_CTRL_9 0x01e6
327#define RT5659_HP_CALIB_CTRL_10 0x01e7
328#define RT5659_HP_CALIB_CTRL_11 0x01e8
329#define RT5659_HP_CALIB_STA_1 0x01ea
330#define RT5659_HP_CALIB_STA_2 0x01eb
331#define RT5659_HP_CALIB_STA_3 0x01ec
332#define RT5659_HP_CALIB_STA_4 0x01ed
333#define RT5659_HP_CALIB_STA_5 0x01ee
334#define RT5659_HP_CALIB_STA_6 0x01ef
335#define RT5659_HP_CALIB_STA_7 0x01f0
336#define RT5659_HP_CALIB_STA_8 0x01f1
337#define RT5659_HP_CALIB_STA_9 0x01f2
338#define RT5659_MONO_AMP_CALIB_CTRL_1 0x01f6
339#define RT5659_MONO_AMP_CALIB_CTRL_2 0x01f7
340#define RT5659_MONO_AMP_CALIB_CTRL_3 0x01f8
341#define RT5659_MONO_AMP_CALIB_CTRL_4 0x01f9
342#define RT5659_MONO_AMP_CALIB_CTRL_5 0x01fa
343#define RT5659_MONO_AMP_CALIB_STA_1 0x01fb
344#define RT5659_MONO_AMP_CALIB_STA_2 0x01fc
345#define RT5659_MONO_AMP_CALIB_STA_3 0x01fd
346#define RT5659_MONO_AMP_CALIB_STA_4 0x01fe
347#define RT5659_SPK_PWR_LMT_CTRL_1 0x0200
348#define RT5659_SPK_PWR_LMT_CTRL_2 0x0201
349#define RT5659_SPK_PWR_LMT_CTRL_3 0x0202
350#define RT5659_SPK_PWR_LMT_STA_1 0x0203
351#define RT5659_SPK_PWR_LMT_STA_2 0x0204
352#define RT5659_SPK_PWR_LMT_STA_3 0x0205
353#define RT5659_SPK_PWR_LMT_STA_4 0x0206
354#define RT5659_SPK_PWR_LMT_STA_5 0x0207
355#define RT5659_SPK_PWR_LMT_STA_6 0x0208
356#define RT5659_FLEX_SPK_BST_CTRL_1 0x0256
357#define RT5659_FLEX_SPK_BST_CTRL_2 0x0257
358#define RT5659_FLEX_SPK_BST_CTRL_3 0x0258
359#define RT5659_FLEX_SPK_BST_CTRL_4 0x0259
360#define RT5659_SPK_EX_LMT_CTRL_1 0x025a
361#define RT5659_SPK_EX_LMT_CTRL_2 0x025b
362#define RT5659_SPK_EX_LMT_CTRL_3 0x025c
363#define RT5659_SPK_EX_LMT_CTRL_4 0x025d
364#define RT5659_SPK_EX_LMT_CTRL_5 0x025e
365#define RT5659_SPK_EX_LMT_CTRL_6 0x025f
366#define RT5659_SPK_EX_LMT_CTRL_7 0x0260
367#define RT5659_ADJ_HPF_CTRL_1 0x0261
368#define RT5659_ADJ_HPF_CTRL_2 0x0262
369#define RT5659_SPK_DC_CAILB_CTRL_1 0x0265
370#define RT5659_SPK_DC_CAILB_CTRL_2 0x0266
371#define RT5659_SPK_DC_CAILB_CTRL_3 0x0267
372#define RT5659_SPK_DC_CAILB_CTRL_4 0x0268
373#define RT5659_SPK_DC_CAILB_CTRL_5 0x0269
374#define RT5659_SPK_DC_CAILB_STA_1 0x026a
375#define RT5659_SPK_DC_CAILB_STA_2 0x026b
376#define RT5659_SPK_DC_CAILB_STA_3 0x026c
377#define RT5659_SPK_DC_CAILB_STA_4 0x026d
378#define RT5659_SPK_DC_CAILB_STA_5 0x026e
379#define RT5659_SPK_DC_CAILB_STA_6 0x026f
380#define RT5659_SPK_DC_CAILB_STA_7 0x0270
381#define RT5659_SPK_DC_CAILB_STA_8 0x0271
382#define RT5659_SPK_DC_CAILB_STA_9 0x0272
383#define RT5659_SPK_DC_CAILB_STA_10 0x0273
384#define RT5659_SPK_VDD_STA_1 0x0280
385#define RT5659_SPK_VDD_STA_2 0x0281
386#define RT5659_SPK_DC_DET_CTRL_1 0x0282
387#define RT5659_SPK_DC_DET_CTRL_2 0x0283
388#define RT5659_SPK_DC_DET_CTRL_3 0x0284
389#define RT5659_PURE_DC_DET_CTRL_1 0x0290
390#define RT5659_PURE_DC_DET_CTRL_2 0x0291
391#define RT5659_DUMMY_4 0x02fa
392#define RT5659_DUMMY_5 0x02fb
393#define RT5659_DUMMY_6 0x02fc
394#define RT5659_DRC1_CTRL_1 0x0300
395#define RT5659_DRC1_CTRL_2 0x0301
396#define RT5659_DRC1_CTRL_3 0x0302
397#define RT5659_DRC1_CTRL_4 0x0303
398#define RT5659_DRC1_CTRL_5 0x0304
399#define RT5659_DRC1_CTRL_6 0x0305
400#define RT5659_DRC1_HARD_LMT_CTRL_1 0x0306
401#define RT5659_DRC1_HARD_LMT_CTRL_2 0x0307
402#define RT5659_DRC2_CTRL_1 0x0308
403#define RT5659_DRC2_CTRL_2 0x0309
404#define RT5659_DRC2_CTRL_3 0x030a
405#define RT5659_DRC2_CTRL_4 0x030b
406#define RT5659_DRC2_CTRL_5 0x030c
407#define RT5659_DRC2_CTRL_6 0x030d
408#define RT5659_DRC2_HARD_LMT_CTRL_1 0x030e
409#define RT5659_DRC2_HARD_LMT_CTRL_2 0x030f
410#define RT5659_DRC1_PRIV_1 0x0310
411#define RT5659_DRC1_PRIV_2 0x0311
412#define RT5659_DRC1_PRIV_3 0x0312
413#define RT5659_DRC1_PRIV_4 0x0313
414#define RT5659_DRC1_PRIV_5 0x0314
415#define RT5659_DRC1_PRIV_6 0x0315
416#define RT5659_DRC1_PRIV_7 0x0316
417#define RT5659_DRC2_PRIV_1 0x0317
418#define RT5659_DRC2_PRIV_2 0x0318
419#define RT5659_DRC2_PRIV_3 0x0319
420#define RT5659_DRC2_PRIV_4 0x031a
421#define RT5659_DRC2_PRIV_5 0x031b
422#define RT5659_DRC2_PRIV_6 0x031c
423#define RT5659_DRC2_PRIV_7 0x031d
424#define RT5659_MULTI_DRC_CTRL 0x0320
425#define RT5659_CROSS_OVER_1 0x0321
426#define RT5659_CROSS_OVER_2 0x0322
427#define RT5659_CROSS_OVER_3 0x0323
428#define RT5659_CROSS_OVER_4 0x0324
429#define RT5659_CROSS_OVER_5 0x0325
430#define RT5659_CROSS_OVER_6 0x0326
431#define RT5659_CROSS_OVER_7 0x0327
432#define RT5659_CROSS_OVER_8 0x0328
433#define RT5659_CROSS_OVER_9 0x0329
434#define RT5659_CROSS_OVER_10 0x032a
435#define RT5659_ALC_PGA_CTRL_1 0x0330
436#define RT5659_ALC_PGA_CTRL_2 0x0331
437#define RT5659_ALC_PGA_CTRL_3 0x0332
438#define RT5659_ALC_PGA_CTRL_4 0x0333
439#define RT5659_ALC_PGA_CTRL_5 0x0334
440#define RT5659_ALC_PGA_CTRL_6 0x0335
441#define RT5659_ALC_PGA_CTRL_7 0x0336
442#define RT5659_ALC_PGA_CTRL_8 0x0337
443#define RT5659_ALC_PGA_STA_1 0x0338
444#define RT5659_ALC_PGA_STA_2 0x0339
445#define RT5659_ALC_PGA_STA_3 0x033a
446#define RT5659_DAC_L_EQ_PRE_VOL 0x0340
447#define RT5659_DAC_R_EQ_PRE_VOL 0x0341
448#define RT5659_DAC_L_EQ_POST_VOL 0x0342
449#define RT5659_DAC_R_EQ_POST_VOL 0x0343
450#define RT5659_DAC_L_EQ_LPF1_A1 0x0344
451#define RT5659_DAC_L_EQ_LPF1_H0 0x0345
452#define RT5659_DAC_R_EQ_LPF1_A1 0x0346
453#define RT5659_DAC_R_EQ_LPF1_H0 0x0347
454#define RT5659_DAC_L_EQ_BPF2_A1 0x0348
455#define RT5659_DAC_L_EQ_BPF2_A2 0x0349
456#define RT5659_DAC_L_EQ_BPF2_H0 0x034a
457#define RT5659_DAC_R_EQ_BPF2_A1 0x034b
458#define RT5659_DAC_R_EQ_BPF2_A2 0x034c
459#define RT5659_DAC_R_EQ_BPF2_H0 0x034d
460#define RT5659_DAC_L_EQ_BPF3_A1 0x034e
461#define RT5659_DAC_L_EQ_BPF3_A2 0x034f
462#define RT5659_DAC_L_EQ_BPF3_H0 0x0350
463#define RT5659_DAC_R_EQ_BPF3_A1 0x0351
464#define RT5659_DAC_R_EQ_BPF3_A2 0x0352
465#define RT5659_DAC_R_EQ_BPF3_H0 0x0353
466#define RT5659_DAC_L_EQ_BPF4_A1 0x0354
467#define RT5659_DAC_L_EQ_BPF4_A2 0x0355
468#define RT5659_DAC_L_EQ_BPF4_H0 0x0356
469#define RT5659_DAC_R_EQ_BPF4_A1 0x0357
470#define RT5659_DAC_R_EQ_BPF4_A2 0x0358
471#define RT5659_DAC_R_EQ_BPF4_H0 0x0359
472#define RT5659_DAC_L_EQ_HPF1_A1 0x035a
473#define RT5659_DAC_L_EQ_HPF1_H0 0x035b
474#define RT5659_DAC_R_EQ_HPF1_A1 0x035c
475#define RT5659_DAC_R_EQ_HPF1_H0 0x035d
476#define RT5659_DAC_L_EQ_HPF2_A1 0x035e
477#define RT5659_DAC_L_EQ_HPF2_A2 0x035f
478#define RT5659_DAC_L_EQ_HPF2_H0 0x0360
479#define RT5659_DAC_R_EQ_HPF2_A1 0x0361
480#define RT5659_DAC_R_EQ_HPF2_A2 0x0362
481#define RT5659_DAC_R_EQ_HPF2_H0 0x0363
482#define RT5659_DAC_L_BI_EQ_BPF1_H0_1 0x0364
483#define RT5659_DAC_L_BI_EQ_BPF1_H0_2 0x0365
484#define RT5659_DAC_L_BI_EQ_BPF1_B1_1 0x0366
485#define RT5659_DAC_L_BI_EQ_BPF1_B1_2 0x0367
486#define RT5659_DAC_L_BI_EQ_BPF1_B2_1 0x0368
487#define RT5659_DAC_L_BI_EQ_BPF1_B2_2 0x0369
488#define RT5659_DAC_L_BI_EQ_BPF1_A1_1 0x036a
489#define RT5659_DAC_L_BI_EQ_BPF1_A1_2 0x036b
490#define RT5659_DAC_L_BI_EQ_BPF1_A2_1 0x036c
491#define RT5659_DAC_L_BI_EQ_BPF1_A2_2 0x036d
492#define RT5659_DAC_R_BI_EQ_BPF1_H0_1 0x036e
493#define RT5659_DAC_R_BI_EQ_BPF1_H0_2 0x036f
494#define RT5659_DAC_R_BI_EQ_BPF1_B1_1 0x0370
495#define RT5659_DAC_R_BI_EQ_BPF1_B1_2 0x0371
496#define RT5659_DAC_R_BI_EQ_BPF1_B2_1 0x0372
497#define RT5659_DAC_R_BI_EQ_BPF1_B2_2 0x0373
498#define RT5659_DAC_R_BI_EQ_BPF1_A1_1 0x0374
499#define RT5659_DAC_R_BI_EQ_BPF1_A1_2 0x0375
500#define RT5659_DAC_R_BI_EQ_BPF1_A2_1 0x0376
501#define RT5659_DAC_R_BI_EQ_BPF1_A2_2 0x0377
502#define RT5659_ADC_L_EQ_LPF1_A1 0x03d0
503#define RT5659_ADC_R_EQ_LPF1_A1 0x03d1
504#define RT5659_ADC_L_EQ_LPF1_H0 0x03d2
505#define RT5659_ADC_R_EQ_LPF1_H0 0x03d3
506#define RT5659_ADC_L_EQ_BPF1_A1 0x03d4
507#define RT5659_ADC_R_EQ_BPF1_A1 0x03d5
508#define RT5659_ADC_L_EQ_BPF1_A2 0x03d6
509#define RT5659_ADC_R_EQ_BPF1_A2 0x03d7
510#define RT5659_ADC_L_EQ_BPF1_H0 0x03d8
511#define RT5659_ADC_R_EQ_BPF1_H0 0x03d9
512#define RT5659_ADC_L_EQ_BPF2_A1 0x03da
513#define RT5659_ADC_R_EQ_BPF2_A1 0x03db
514#define RT5659_ADC_L_EQ_BPF2_A2 0x03dc
515#define RT5659_ADC_R_EQ_BPF2_A2 0x03dd
516#define RT5659_ADC_L_EQ_BPF2_H0 0x03de
517#define RT5659_ADC_R_EQ_BPF2_H0 0x03df
518#define RT5659_ADC_L_EQ_BPF3_A1 0x03e0
519#define RT5659_ADC_R_EQ_BPF3_A1 0x03e1
520#define RT5659_ADC_L_EQ_BPF3_A2 0x03e2
521#define RT5659_ADC_R_EQ_BPF3_A2 0x03e3
522#define RT5659_ADC_L_EQ_BPF3_H0 0x03e4
523#define RT5659_ADC_R_EQ_BPF3_H0 0x03e5
524#define RT5659_ADC_L_EQ_BPF4_A1 0x03e6
525#define RT5659_ADC_R_EQ_BPF4_A1 0x03e7
526#define RT5659_ADC_L_EQ_BPF4_A2 0x03e8
527#define RT5659_ADC_R_EQ_BPF4_A2 0x03e9
528#define RT5659_ADC_L_EQ_BPF4_H0 0x03ea
529#define RT5659_ADC_R_EQ_BPF4_H0 0x03eb
530#define RT5659_ADC_L_EQ_HPF1_A1 0x03ec
531#define RT5659_ADC_R_EQ_HPF1_A1 0x03ed
532#define RT5659_ADC_L_EQ_HPF1_H0 0x03ee
533#define RT5659_ADC_R_EQ_HPF1_H0 0x03ef
534#define RT5659_ADC_L_EQ_PRE_VOL 0x03f0
535#define RT5659_ADC_R_EQ_PRE_VOL 0x03f1
536#define RT5659_ADC_L_EQ_POST_VOL 0x03f2
537#define RT5659_ADC_R_EQ_POST_VOL 0x03f3
538
539
540
541/* global definition */
542#define RT5659_L_MUTE (0x1 << 15)
543#define RT5659_L_MUTE_SFT 15
544#define RT5659_VOL_L_MUTE (0x1 << 14)
545#define RT5659_VOL_L_SFT 14
546#define RT5659_R_MUTE (0x1 << 7)
547#define RT5659_R_MUTE_SFT 7
548#define RT5659_VOL_R_MUTE (0x1 << 6)
549#define RT5659_VOL_R_SFT 6
550#define RT5659_L_VOL_MASK (0x3f << 8)
551#define RT5659_L_VOL_SFT 8
552#define RT5659_R_VOL_MASK (0x3f)
553#define RT5659_R_VOL_SFT 0
554
555/*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/
556#define RT5659_G_HP (0x1f << 8)
557#define RT5659_G_HP_SFT 8
558#define RT5659_G_STO_DA_DMIX (0x1f)
559#define RT5659_G_STO_DA_SFT 0
560
561/* IN1/IN2 Control (0x000c) */
562#define RT5659_IN1_DF_MASK (0x1 << 15)
563#define RT5659_IN1_DF 15
564#define RT5659_BST1_MASK (0x7f << 8)
565#define RT5659_BST1_SFT 8
566#define RT5659_BST2_MASK (0x7f)
567#define RT5659_BST2_SFT 0
568
569/* IN3/IN4 Control (0x000d) */
570#define RT5659_IN3_DF_MASK (0x1 << 15)
571#define RT5659_IN3_DF 15
572#define RT5659_BST3_MASK (0x7f << 8)
573#define RT5659_BST3_SFT 8
574#define RT5659_IN4_DF_MASK (0x1 << 7)
575#define RT5659_IN4_DF 7
576#define RT5659_BST4_MASK (0x7f)
577#define RT5659_BST4_SFT 0
578
579/* INL and INR Volume Control (0x000f) */
580#define RT5659_INL_VOL_MASK (0x1f << 8)
581#define RT5659_INL_VOL_SFT 8
582#define RT5659_INR_VOL_MASK (0x1f)
583#define RT5659_INR_VOL_SFT 0
584
585/* Embeeded Jack and Type Detection Control 1 (0x0010) */
586#define RT5659_EMB_JD_EN (0x1 << 15)
587#define RT5659_EMB_JD_EN_SFT 15
588#define RT5659_JD_MODE (0x1 << 13)
589#define RT5659_JD_MODE_SFT 13
590#define RT5659_EXT_JD_EN (0x1 << 11)
591#define RT5659_EXT_JD_EN_SFT 11
592#define RT5659_EXT_JD_DIG (0x1 << 9)
593
594/* Embeeded Jack and Type Detection Control 2 (0x0011) */
595#define RT5659_EXT_JD_SRC (0x7 << 4)
596#define RT5659_EXT_JD_SRC_SFT 4
597#define RT5659_EXT_JD_SRC_GPIO_JD1 (0x0 << 4)
598#define RT5659_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)
599#define RT5659_EXT_JD_SRC_JD1_1 (0x2 << 4)
600#define RT5659_EXT_JD_SRC_JD1_2 (0x3 << 4)
601#define RT5659_EXT_JD_SRC_JD2 (0x4 << 4)
602#define RT5659_EXT_JD_SRC_JD3 (0x5 << 4)
603#define RT5659_EXT_JD_SRC_MANUAL (0x6 << 4)
604
605/* Slience Detection Control (0x0015) */
606#define RT5659_SIL_DET_MASK (0x1 << 15)
607#define RT5659_SIL_DET_DIS (0x0 << 15)
608#define RT5659_SIL_DET_EN (0x1 << 15)
609
610/* Sidetone Control (0x0018) */
611#define RT5659_ST_SEL_MASK (0x7 << 9)
612#define RT5659_ST_SEL_SFT 9
613#define RT5659_ST_EN (0x1 << 6)
614#define RT5659_ST_EN_SFT 6
615
616/* DAC1 Digital Volume (0x0019) */
617#define RT5659_DAC_L1_VOL_MASK (0xff << 8)
618#define RT5659_DAC_L1_VOL_SFT 8
619#define RT5659_DAC_R1_VOL_MASK (0xff)
620#define RT5659_DAC_R1_VOL_SFT 0
621
622/* DAC2 Digital Volume (0x001a) */
623#define RT5659_DAC_L2_VOL_MASK (0xff << 8)
624#define RT5659_DAC_L2_VOL_SFT 8
625#define RT5659_DAC_R2_VOL_MASK (0xff)
626#define RT5659_DAC_R2_VOL_SFT 0
627
628/* DAC2 Control (0x001b) */
629#define RT5659_M_DAC2_L_VOL (0x1 << 13)
630#define RT5659_M_DAC2_L_VOL_SFT 13
631#define RT5659_M_DAC2_R_VOL (0x1 << 12)
632#define RT5659_M_DAC2_R_VOL_SFT 12
633#define RT5659_DAC_L2_SEL_MASK (0x7 << 4)
634#define RT5659_DAC_L2_SEL_SFT 4
635#define RT5659_DAC_R2_SEL_MASK (0x7 << 0)
636#define RT5659_DAC_R2_SEL_SFT 0
637
638/* ADC Digital Volume Control (0x001c) */
639#define RT5659_ADC_L_VOL_MASK (0x7f << 8)
640#define RT5659_ADC_L_VOL_SFT 8
641#define RT5659_ADC_R_VOL_MASK (0x7f)
642#define RT5659_ADC_R_VOL_SFT 0
643
644/* Mono ADC Digital Volume Control (0x001d) */
645#define RT5659_MONO_ADC_L_VOL_MASK (0x7f << 8)
646#define RT5659_MONO_ADC_L_VOL_SFT 8
647#define RT5659_MONO_ADC_R_VOL_MASK (0x7f)
648#define RT5659_MONO_ADC_R_VOL_SFT 0
649
650/* Stereo1 ADC Boost Gain Control (0x001f) */
651#define RT5659_STO1_ADC_L_BST_MASK (0x3 << 14)
652#define RT5659_STO1_ADC_L_BST_SFT 14
653#define RT5659_STO1_ADC_R_BST_MASK (0x3 << 12)
654#define RT5659_STO1_ADC_R_BST_SFT 12
655
656/* Mono ADC Boost Gain Control (0x0020) */
657#define RT5659_MONO_ADC_L_BST_MASK (0x3 << 14)
658#define RT5659_MONO_ADC_L_BST_SFT 14
659#define RT5659_MONO_ADC_R_BST_MASK (0x3 << 12)
660#define RT5659_MONO_ADC_R_BST_SFT 12
661
662/* Stereo1 ADC Boost Gain Control (0x001f) */
663#define RT5659_STO2_ADC_L_BST_MASK (0x3 << 14)
664#define RT5659_STO2_ADC_L_BST_SFT 14
665#define RT5659_STO2_ADC_R_BST_MASK (0x3 << 12)
666#define RT5659_STO2_ADC_R_BST_SFT 12
667
668/* Stereo ADC Mixer Control (0x0026) */
669#define RT5659_M_STO1_ADC_L1 (0x1 << 15)
670#define RT5659_M_STO1_ADC_L1_SFT 15
671#define RT5659_M_STO1_ADC_L2 (0x1 << 14)
672#define RT5659_M_STO1_ADC_L2_SFT 14
673#define RT5659_STO1_ADC1_SRC_MASK (0x1 << 13)
674#define RT5659_STO1_ADC1_SRC_SFT 13
675#define RT5659_STO1_ADC1_SRC_ADC (0x1 << 13)
676#define RT5659_STO1_ADC1_SRC_DACMIX (0x0 << 13)
677#define RT5659_STO1_ADC_SRC_MASK (0x1 << 12)
678#define RT5659_STO1_ADC_SRC_SFT 12
679#define RT5659_STO1_ADC_SRC_ADC1 (0x1 << 12)
680#define RT5659_STO1_ADC_SRC_ADC2 (0x0 << 12)
681#define RT5659_STO1_ADC2_SRC_MASK (0x1 << 11)
682#define RT5659_STO1_ADC2_SRC_SFT 11
683#define RT5659_STO1_DMIC_SRC_MASK (0x1 << 8)
684#define RT5659_STO1_DMIC_SRC_SFT 8
685#define RT5659_STO1_DMIC_SRC_DMIC2 (0x1 << 8)
686#define RT5659_STO1_DMIC_SRC_DMIC1 (0x0 << 8)
687#define RT5659_M_STO1_ADC_R1 (0x1 << 6)
688#define RT5659_M_STO1_ADC_R1_SFT 6
689#define RT5659_M_STO1_ADC_R2 (0x1 << 5)
690#define RT5659_M_STO1_ADC_R2_SFT 5
691
692/* Mono1 ADC Mixer control (0x0027) */
693#define RT5659_M_MONO_ADC_L1 (0x1 << 15)
694#define RT5659_M_MONO_ADC_L1_SFT 15
695#define RT5659_M_MONO_ADC_L2 (0x1 << 14)
696#define RT5659_M_MONO_ADC_L2_SFT 14
697#define RT5659_MONO_ADC_L2_SRC_MASK (0x1 << 12)
698#define RT5659_MONO_ADC_L2_SRC_SFT 12
699#define RT5659_MONO_ADC_L1_SRC_MASK (0x1 << 11)
700#define RT5659_MONO_ADC_L1_SRC_SFT 11
701#define RT5659_MONO_ADC_L_SRC_MASK (0x3 << 9)
702#define RT5659_MONO_ADC_L_SRC_SFT 9
703#define RT5659_MONO_DMIC_L_SRC_MASK (0x1 << 8)
704#define RT5659_MONO_DMIC_L_SRC_SFT 8
705#define RT5659_M_MONO_ADC_R1 (0x1 << 7)
706#define RT5659_M_MONO_ADC_R1_SFT 7
707#define RT5659_M_MONO_ADC_R2 (0x1 << 6)
708#define RT5659_M_MONO_ADC_R2_SFT 6
709#define RT5659_STO2_ADC_SRC_MASK (0x1 << 5)
710#define RT5659_STO2_ADC_SRC_SFT 5
711#define RT5659_MONO_ADC_R2_SRC_MASK (0x1 << 4)
712#define RT5659_MONO_ADC_R2_SRC_SFT 4
713#define RT5659_MONO_ADC_R1_SRC_MASK (0x1 << 3)
714#define RT5659_MONO_ADC_R1_SRC_SFT 3
715#define RT5659_MONO_ADC_R_SRC_MASK (0x3 << 1)
716#define RT5659_MONO_ADC_R_SRC_SFT 1
717#define RT5659_MONO_DMIC_R_SRC_MASK 0x1
718#define RT5659_MONO_DMIC_R_SRC_SFT 0
719
720/* ADC Mixer to DAC Mixer Control (0x0029) */
721#define RT5659_M_ADCMIX_L (0x1 << 15)
722#define RT5659_M_ADCMIX_L_SFT 15
723#define RT5659_M_DAC1_L (0x1 << 14)
724#define RT5659_M_DAC1_L_SFT 14
725#define RT5659_DAC1_R_SEL_MASK (0x3 << 10)
726#define RT5659_DAC1_R_SEL_SFT 10
727#define RT5659_DAC1_R_SEL_IF1 (0x0 << 10)
728#define RT5659_DAC1_R_SEL_IF2 (0x1 << 10)
729#define RT5659_DAC1_R_SEL_IF3 (0x2 << 10)
730#define RT5659_DAC1_L_SEL_MASK (0x3 << 8)
731#define RT5659_DAC1_L_SEL_SFT 8
732#define RT5659_DAC1_L_SEL_IF1 (0x0 << 8)
733#define RT5659_DAC1_L_SEL_IF2 (0x1 << 8)
734#define RT5659_DAC1_L_SEL_IF3 (0x2 << 8)
735#define RT5659_M_ADCMIX_R (0x1 << 7)
736#define RT5659_M_ADCMIX_R_SFT 7
737#define RT5659_M_DAC1_R (0x1 << 6)
738#define RT5659_M_DAC1_R_SFT 6
739
740/* Stereo DAC Mixer Control (0x002a) */
741#define RT5659_M_DAC_L1_STO_L (0x1 << 15)
742#define RT5659_M_DAC_L1_STO_L_SFT 15
743#define RT5659_G_DAC_L1_STO_L_MASK (0x1 << 14)
744#define RT5659_G_DAC_L1_STO_L_SFT 14
745#define RT5659_M_DAC_R1_STO_L (0x1 << 13)
746#define RT5659_M_DAC_R1_STO_L_SFT 13
747#define RT5659_G_DAC_R1_STO_L_MASK (0x1 << 12)
748#define RT5659_G_DAC_R1_STO_L_SFT 12
749#define RT5659_M_DAC_L2_STO_L (0x1 << 11)
750#define RT5659_M_DAC_L2_STO_L_SFT 11
751#define RT5659_G_DAC_L2_STO_L_MASK (0x1 << 10)
752#define RT5659_G_DAC_L2_STO_L_SFT 10
753#define RT5659_M_DAC_R2_STO_L (0x1 << 9)
754#define RT5659_M_DAC_R2_STO_L_SFT 9
755#define RT5659_G_DAC_R2_STO_L_MASK (0x1 << 8)
756#define RT5659_G_DAC_R2_STO_L_SFT 8
757#define RT5659_M_DAC_L1_STO_R (0x1 << 7)
758#define RT5659_M_DAC_L1_STO_R_SFT 7
759#define RT5659_G_DAC_L1_STO_R_MASK (0x1 << 6)
760#define RT5659_G_DAC_L1_STO_R_SFT 6
761#define RT5659_M_DAC_R1_STO_R (0x1 << 5)
762#define RT5659_M_DAC_R1_STO_R_SFT 5
763#define RT5659_G_DAC_R1_STO_R_MASK (0x1 << 4)
764#define RT5659_G_DAC_R1_STO_R_SFT 4
765#define RT5659_M_DAC_L2_STO_R (0x1 << 3)
766#define RT5659_M_DAC_L2_STO_R_SFT 3
767#define RT5659_G_DAC_L2_STO_R_MASK (0x1 << 2)
768#define RT5659_G_DAC_L2_STO_R_SFT 2
769#define RT5659_M_DAC_R2_STO_R (0x1 << 1)
770#define RT5659_M_DAC_R2_STO_R_SFT 1
771#define RT5659_G_DAC_R2_STO_R_MASK (0x1)
772#define RT5659_G_DAC_R2_STO_R_SFT 0
773
774/* Mono DAC Mixer Control (0x002b) */
775#define RT5659_M_DAC_L1_MONO_L (0x1 << 15)
776#define RT5659_M_DAC_L1_MONO_L_SFT 15
777#define RT5659_G_DAC_L1_MONO_L_MASK (0x1 << 14)
778#define RT5659_G_DAC_L1_MONO_L_SFT 14
779#define RT5659_M_DAC_R1_MONO_L (0x1 << 13)
780#define RT5659_M_DAC_R1_MONO_L_SFT 13
781#define RT5659_G_DAC_R1_MONO_L_MASK (0x1 << 12)
782#define RT5659_G_DAC_R1_MONO_L_SFT 12
783#define RT5659_M_DAC_L2_MONO_L (0x1 << 11)
784#define RT5659_M_DAC_L2_MONO_L_SFT 11
785#define RT5659_G_DAC_L2_MONO_L_MASK (0x1 << 10)
786#define RT5659_G_DAC_L2_MONO_L_SFT 10
787#define RT5659_M_DAC_R2_MONO_L (0x1 << 9)
788#define RT5659_M_DAC_R2_MONO_L_SFT 9
789#define RT5659_G_DAC_R2_MONO_L_MASK (0x1 << 8)
790#define RT5659_G_DAC_R2_MONO_L_SFT 8
791#define RT5659_M_DAC_L1_MONO_R (0x1 << 7)
792#define RT5659_M_DAC_L1_MONO_R_SFT 7
793#define RT5659_G_DAC_L1_MONO_R_MASK (0x1 << 6)
794#define RT5659_G_DAC_L1_MONO_R_SFT 6
795#define RT5659_M_DAC_R1_MONO_R (0x1 << 5)
796#define RT5659_M_DAC_R1_MONO_R_SFT 5
797#define RT5659_G_DAC_R1_MONO_R_MASK (0x1 << 4)
798#define RT5659_G_DAC_R1_MONO_R_SFT 4
799#define RT5659_M_DAC_L2_MONO_R (0x1 << 3)
800#define RT5659_M_DAC_L2_MONO_R_SFT 3
801#define RT5659_G_DAC_L2_MONO_R_MASK (0x1 << 2)
802#define RT5659_G_DAC_L2_MONO_R_SFT 2
803#define RT5659_M_DAC_R2_MONO_R (0x1 << 1)
804#define RT5659_M_DAC_R2_MONO_R_SFT 1
805#define RT5659_G_DAC_R2_MONO_R_MASK (0x1)
806#define RT5659_G_DAC_R2_MONO_R_SFT 0
807
808/* Digital Mixer Control (0x002c) */
809#define RT5659_M_DAC_MIX_L (0x1 << 7)
810#define RT5659_M_DAC_MIX_L_SFT 7
811#define RT5659_DAC_MIX_L_MASK (0x1 << 6)
812#define RT5659_DAC_MIX_L_SFT 6
813#define RT5659_M_DAC_MIX_R (0x1 << 5)
814#define RT5659_M_DAC_MIX_R_SFT 5
815#define RT5659_DAC_MIX_R_MASK (0x1 << 4)
816#define RT5659_DAC_MIX_R_SFT 4
817
818/* Analog DAC Input Source Control (0x002d) */
819#define RT5659_A_DACL1_SEL (0x1 << 3)
820#define RT5659_A_DACL1_SFT 3
821#define RT5659_A_DACR1_SEL (0x1 << 2)
822#define RT5659_A_DACR1_SFT 2
823#define RT5659_A_DACL2_SEL (0x1 << 1)
824#define RT5659_A_DACL2_SFT 1
825#define RT5659_A_DACR2_SEL (0x1 << 0)
826#define RT5659_A_DACR2_SFT 0
827
828/* Digital Interface Data Control (0x002f) */
829#define RT5659_IF2_ADC3_IN_MASK (0x3 << 14)
830#define RT5659_IF2_ADC3_IN_SFT 14
831#define RT5659_IF2_ADC_IN_MASK (0x3 << 12)
832#define RT5659_IF2_ADC_IN_SFT 12
833#define RT5659_IF2_DAC_SEL_MASK (0x3 << 10)
834#define RT5659_IF2_DAC_SEL_SFT 10
835#define RT5659_IF2_ADC_SEL_MASK (0x3 << 8)
836#define RT5659_IF2_ADC_SEL_SFT 8
837#define RT5659_IF3_DAC_SEL_MASK (0x3 << 6)
838#define RT5659_IF3_DAC_SEL_SFT 6
839#define RT5659_IF3_ADC_SEL_MASK (0x3 << 4)
840#define RT5659_IF3_ADC_SEL_SFT 4
841#define RT5659_IF3_ADC_IN_MASK (0x3 << 0)
842#define RT5659_IF3_ADC_IN_SFT 0
843
844/* PDM Output Control (0x0031) */
845#define RT5659_PDM1_L_MASK (0x1 << 15)
846#define RT5659_PDM1_L_SFT 15
847#define RT5659_M_PDM1_L (0x1 << 14)
848#define RT5659_M_PDM1_L_SFT 14
849#define RT5659_PDM1_R_MASK (0x1 << 13)
850#define RT5659_PDM1_R_SFT 13
851#define RT5659_M_PDM1_R (0x1 << 12)
852#define RT5659_M_PDM1_R_SFT 12
853#define RT5659_PDM2_BUSY (0x1 << 7)
854#define RT5659_PDM1_BUSY (0x1 << 6)
855#define RT5659_PDM_PATTERN (0x1 << 5)
856#define RT5659_PDM_GAIN (0x1 << 4)
857#define RT5659_PDM_DIV_MASK (0x3)
858
859/*S/PDIF Output Control (0x0036) */
860#define RT5659_SPDIF_SEL_MASK (0x3 << 0)
861#define RT5659_SPDIF_SEL_SFT 0
862
863/* REC Left Mixer Control 2 (0x003c) */
864#define RT5659_M_BST1_RM1_L (0x1 << 5)
865#define RT5659_M_BST1_RM1_L_SFT 5
866#define RT5659_M_BST2_RM1_L (0x1 << 4)
867#define RT5659_M_BST2_RM1_L_SFT 4
868#define RT5659_M_BST3_RM1_L (0x1 << 3)
869#define RT5659_M_BST3_RM1_L_SFT 3
870#define RT5659_M_BST4_RM1_L (0x1 << 2)
871#define RT5659_M_BST4_RM1_L_SFT 2
872#define RT5659_M_INL_RM1_L (0x1 << 1)
873#define RT5659_M_INL_RM1_L_SFT 1
874#define RT5659_M_SPKVOLL_RM1_L (0x1)
875#define RT5659_M_SPKVOLL_RM1_L_SFT 0
876
877/* REC Right Mixer Control 2 (0x003e) */
878#define RT5659_M_BST1_RM1_R (0x1 << 5)
879#define RT5659_M_BST1_RM1_R_SFT 5
880#define RT5659_M_BST2_RM1_R (0x1 << 4)
881#define RT5659_M_BST2_RM1_R_SFT 4
882#define RT5659_M_BST3_RM1_R (0x1 << 3)
883#define RT5659_M_BST3_RM1_R_SFT 3
884#define RT5659_M_BST4_RM1_R (0x1 << 2)
885#define RT5659_M_BST4_RM1_R_SFT 2
886#define RT5659_M_INR_RM1_R (0x1 << 1)
887#define RT5659_M_INR_RM1_R_SFT 1
888#define RT5659_M_HPOVOLR_RM1_R (0x1)
889#define RT5659_M_HPOVOLR_RM1_R_SFT 0
890
891/* SPK Left Mixer Control (0x0046) */
892#define RT5659_M_BST3_SM_L (0x1 << 4)
893#define RT5659_M_BST3_SM_L_SFT 4
894#define RT5659_M_IN_R_SM_L (0x1 << 3)
895#define RT5659_M_IN_R_SM_L_SFT 3
896#define RT5659_M_IN_L_SM_L (0x1 << 2)
897#define RT5659_M_IN_L_SM_L_SFT 2
898#define RT5659_M_BST1_SM_L (0x1 << 1)
899#define RT5659_M_BST1_SM_L_SFT 1
900#define RT5659_M_DAC_L2_SM_L (0x1)
901#define RT5659_M_DAC_L2_SM_L_SFT 0
902
903/* SPK Right Mixer Control (0x0047) */
904#define RT5659_M_BST3_SM_R (0x1 << 4)
905#define RT5659_M_BST3_SM_R_SFT 4
906#define RT5659_M_IN_R_SM_R (0x1 << 3)
907#define RT5659_M_IN_R_SM_R_SFT 3
908#define RT5659_M_IN_L_SM_R (0x1 << 2)
909#define RT5659_M_IN_L_SM_R_SFT 2
910#define RT5659_M_BST4_SM_R (0x1 << 1)
911#define RT5659_M_BST4_SM_R_SFT 1
912#define RT5659_M_DAC_R2_SM_R (0x1)
913#define RT5659_M_DAC_R2_SM_R_SFT 0
914
915/* SPO Amp Input and Gain Control (0x0048) */
916#define RT5659_M_DAC_L2_SPKOMIX (0x1 << 13)
917#define RT5659_M_DAC_L2_SPKOMIX_SFT 13
918#define RT5659_M_SPKVOLL_SPKOMIX (0x1 << 12)
919#define RT5659_M_SPKVOLL_SPKOMIX_SFT 12
920#define RT5659_M_DAC_R2_SPKOMIX (0x1 << 9)
921#define RT5659_M_DAC_R2_SPKOMIX_SFT 9
922#define RT5659_M_SPKVOLR_SPKOMIX (0x1 << 8)
923#define RT5659_M_SPKVOLR_SPKOMIX_SFT 8
924
925/* MONOMIX Input and Gain Control (0x004b) */
926#define RT5659_M_MONOVOL_MA (0x1 << 9)
927#define RT5659_M_MONOVOL_MA_SFT 9
928#define RT5659_M_DAC_L2_MA (0x1 << 8)
929#define RT5659_M_DAC_L2_MA_SFT 8
930#define RT5659_M_BST3_MM (0x1 << 4)
931#define RT5659_M_BST3_MM_SFT 4
932#define RT5659_M_BST2_MM (0x1 << 3)
933#define RT5659_M_BST2_MM_SFT 3
934#define RT5659_M_BST1_MM (0x1 << 2)
935#define RT5659_M_BST1_MM_SFT 2
936#define RT5659_M_DAC_R2_MM (0x1 << 1)
937#define RT5659_M_DAC_R2_MM_SFT 1
938#define RT5659_M_DAC_L2_MM (0x1)
939#define RT5659_M_DAC_L2_MM_SFT 0
940
941/* Output Left Mixer Control 1 (0x004d) */
942#define RT5659_G_BST3_OM_L_MASK (0x7 << 12)
943#define RT5659_G_BST3_OM_L_SFT 12
944#define RT5659_G_BST2_OM_L_MASK (0x7 << 9)
945#define RT5659_G_BST2_OM_L_SFT 9
946#define RT5659_G_BST1_OM_L_MASK (0x7 << 6)
947#define RT5659_G_BST1_OM_L_SFT 6
948#define RT5659_G_IN_L_OM_L_MASK (0x7 << 3)
949#define RT5659_G_IN_L_OM_L_SFT 3
950#define RT5659_G_DAC_L2_OM_L_MASK (0x7 << 0)
951#define RT5659_G_DAC_L2_OM_L_SFT 0
952
953/* Output Left Mixer Input Control (0x004e) */
954#define RT5659_M_BST3_OM_L (0x1 << 4)
955#define RT5659_M_BST3_OM_L_SFT 4
956#define RT5659_M_BST2_OM_L (0x1 << 3)
957#define RT5659_M_BST2_OM_L_SFT 3
958#define RT5659_M_BST1_OM_L (0x1 << 2)
959#define RT5659_M_BST1_OM_L_SFT 2
960#define RT5659_M_IN_L_OM_L (0x1 << 1)
961#define RT5659_M_IN_L_OM_L_SFT 1
962#define RT5659_M_DAC_L2_OM_L (0x1)
963#define RT5659_M_DAC_L2_OM_L_SFT 0
964
965/* Output Right Mixer Input Control (0x0050) */
966#define RT5659_M_BST4_OM_R (0x1 << 4)
967#define RT5659_M_BST4_OM_R_SFT 4
968#define RT5659_M_BST3_OM_R (0x1 << 3)
969#define RT5659_M_BST3_OM_R_SFT 3
970#define RT5659_M_BST2_OM_R (0x1 << 2)
971#define RT5659_M_BST2_OM_R_SFT 2
972#define RT5659_M_IN_R_OM_R (0x1 << 1)
973#define RT5659_M_IN_R_OM_R_SFT 1
974#define RT5659_M_DAC_R2_OM_R (0x1)
975#define RT5659_M_DAC_R2_OM_R_SFT 0
976
977/* LOUT Mixer Control (0x0052) */
978#define RT5659_M_DAC_L2_LM (0x1 << 15)
979#define RT5659_M_DAC_L2_LM_SFT 15
980#define RT5659_M_DAC_R2_LM (0x1 << 14)
981#define RT5659_M_DAC_R2_LM_SFT 14
982#define RT5659_M_OV_L_LM (0x1 << 13)
983#define RT5659_M_OV_L_LM_SFT 13
984#define RT5659_M_OV_R_LM (0x1 << 12)
985#define RT5659_M_OV_R_LM_SFT 12
986
987/* Power Management for Digital 1 (0x0061) */
988#define RT5659_PWR_I2S1 (0x1 << 15)
989#define RT5659_PWR_I2S1_BIT 15
990#define RT5659_PWR_I2S2 (0x1 << 14)
991#define RT5659_PWR_I2S2_BIT 14
992#define RT5659_PWR_I2S3 (0x1 << 13)
993#define RT5659_PWR_I2S3_BIT 13
994#define RT5659_PWR_SPDIF (0x1 << 12)
995#define RT5659_PWR_SPDIF_BIT 12
996#define RT5659_PWR_DAC_L1 (0x1 << 11)
997#define RT5659_PWR_DAC_L1_BIT 11
998#define RT5659_PWR_DAC_R1 (0x1 << 10)
999#define RT5659_PWR_DAC_R1_BIT 10
1000#define RT5659_PWR_DAC_L2 (0x1 << 9)
1001#define RT5659_PWR_DAC_L2_BIT 9
1002#define RT5659_PWR_DAC_R2 (0x1 << 8)
1003#define RT5659_PWR_DAC_R2_BIT 8
1004#define RT5659_PWR_LDO (0x1 << 7)
1005#define RT5659_PWR_LDO_BIT 7
1006#define RT5659_PWR_ADC_L1 (0x1 << 4)
1007#define RT5659_PWR_ADC_L1_BIT 4
1008#define RT5659_PWR_ADC_R1 (0x1 << 3)
1009#define RT5659_PWR_ADC_R1_BIT 3
1010#define RT5659_PWR_ADC_L2 (0x1 << 2)
1011#define RT5659_PWR_ADC_L2_BIT 4
1012#define RT5659_PWR_ADC_R2 (0x1 << 1)
1013#define RT5659_PWR_ADC_R2_BIT 1
1014#define RT5659_PWR_CLS_D (0x1)
1015#define RT5659_PWR_CLS_D_BIT 0
1016
1017/* Power Management for Digital 2 (0x0062) */
1018#define RT5659_PWR_ADC_S1F (0x1 << 15)
1019#define RT5659_PWR_ADC_S1F_BIT 15
1020#define RT5659_PWR_ADC_S2F (0x1 << 14)
1021#define RT5659_PWR_ADC_S2F_BIT 14
1022#define RT5659_PWR_ADC_MF_L (0x1 << 13)
1023#define RT5659_PWR_ADC_MF_L_BIT 13
1024#define RT5659_PWR_ADC_MF_R (0x1 << 12)
1025#define RT5659_PWR_ADC_MF_R_BIT 12
1026#define RT5659_PWR_DAC_S1F (0x1 << 10)
1027#define RT5659_PWR_DAC_S1F_BIT 10
1028#define RT5659_PWR_DAC_MF_L (0x1 << 9)
1029#define RT5659_PWR_DAC_MF_L_BIT 9
1030#define RT5659_PWR_DAC_MF_R (0x1 << 8)
1031#define RT5659_PWR_DAC_MF_R_BIT 8
1032#define RT5659_PWR_PDM1 (0x1 << 7)
1033#define RT5659_PWR_PDM1_BIT 7
1034
1035/* Power Management for Analog 1 (0x0063) */
1036#define RT5659_PWR_VREF1 (0x1 << 15)
1037#define RT5659_PWR_VREF1_BIT 15
1038#define RT5659_PWR_FV1 (0x1 << 14)
1039#define RT5659_PWR_FV1_BIT 14
1040#define RT5659_PWR_VREF2 (0x1 << 13)
1041#define RT5659_PWR_VREF2_BIT 13
1042#define RT5659_PWR_FV2 (0x1 << 12)
1043#define RT5659_PWR_FV2_BIT 12
1044#define RT5659_PWR_VREF3 (0x1 << 11)
1045#define RT5659_PWR_VREF3_BIT 11
1046#define RT5659_PWR_FV3 (0x1 << 10)
1047#define RT5659_PWR_FV3_BIT 10
1048#define RT5659_PWR_MB (0x1 << 9)
1049#define RT5659_PWR_MB_BIT 9
1050#define RT5659_PWR_LM (0x1 << 8)
1051#define RT5659_PWR_LM_BIT 8
1052#define RT5659_PWR_BG (0x1 << 7)
1053#define RT5659_PWR_BG_BIT 7
1054#define RT5659_PWR_MA (0x1 << 6)
1055#define RT5659_PWR_MA_BIT 6
1056#define RT5659_PWR_HA_L (0x1 << 5)
1057#define RT5659_PWR_HA_L_BIT 5
1058#define RT5659_PWR_HA_R (0x1 << 4)
1059#define RT5659_PWR_HA_R_BIT 4
1060
1061/* Power Management for Analog 2 (0x0064) */
1062#define RT5659_PWR_BST1 (0x1 << 15)
1063#define RT5659_PWR_BST1_BIT 15
1064#define RT5659_PWR_BST2 (0x1 << 14)
1065#define RT5659_PWR_BST2_BIT 14
1066#define RT5659_PWR_BST3 (0x1 << 13)
1067#define RT5659_PWR_BST3_BIT 13
1068#define RT5659_PWR_BST4 (0x1 << 12)
1069#define RT5659_PWR_BST4_BIT 12
1070#define RT5659_PWR_MB1 (0x1 << 11)
1071#define RT5659_PWR_MB1_BIT 11
1072#define RT5659_PWR_MB2 (0x1 << 10)
1073#define RT5659_PWR_MB2_BIT 10
1074#define RT5659_PWR_MB3 (0x1 << 9)
1075#define RT5659_PWR_MB3_BIT 9
1076#define RT5659_PWR_BST1_P (0x1 << 6)
1077#define RT5659_PWR_BST1_P_BIT 6
1078#define RT5659_PWR_BST2_P (0x1 << 5)
1079#define RT5659_PWR_BST2_P_BIT 5
1080#define RT5659_PWR_BST3_P (0x1 << 4)
1081#define RT5659_PWR_BST3_P_BIT 4
1082#define RT5659_PWR_BST4_P (0x1 << 3)
1083#define RT5659_PWR_BST4_P_BIT 3
1084#define RT5659_PWR_JD1 (0x1 << 2)
1085#define RT5659_PWR_JD1_BIT 2
1086#define RT5659_PWR_JD2 (0x1 << 1)
1087#define RT5659_PWR_JD2_BIT 1
1088#define RT5659_PWR_JD3 (0x1)
1089#define RT5659_PWR_JD3_BIT 0
1090
1091/* Power Management for Analog 3 (0x0065) */
1092#define RT5659_PWR_BST_L (0x1 << 8)
1093#define RT5659_PWR_BST_L_BIT 8
1094#define RT5659_PWR_BST_R (0x1 << 7)
1095#define RT5659_PWR_BST_R_BIT 7
1096#define RT5659_PWR_PLL (0x1 << 6)
1097#define RT5659_PWR_PLL_BIT 6
1098#define RT5659_PWR_LDO5 (0x1 << 5)
1099#define RT5659_PWR_LDO5_BIT 5
1100#define RT5659_PWR_LDO4 (0x1 << 4)
1101#define RT5659_PWR_LDO4_BIT 4
1102#define RT5659_PWR_LDO3 (0x1 << 3)
1103#define RT5659_PWR_LDO3_BIT 3
1104#define RT5659_PWR_LDO2 (0x1 << 2)
1105#define RT5659_PWR_LDO2_BIT 2
1106#define RT5659_PWR_SVD (0x1 << 1)
1107#define RT5659_PWR_SVD_BIT 1
1108
1109/* Power Management for Mixer (0x0066) */
1110#define RT5659_PWR_OM_L (0x1 << 15)
1111#define RT5659_PWR_OM_L_BIT 15
1112#define RT5659_PWR_OM_R (0x1 << 14)
1113#define RT5659_PWR_OM_R_BIT 14
1114#define RT5659_PWR_SM_L (0x1 << 13)
1115#define RT5659_PWR_SM_L_BIT 13
1116#define RT5659_PWR_SM_R (0x1 << 12)
1117#define RT5659_PWR_SM_R_BIT 12
1118#define RT5659_PWR_RM1_L (0x1 << 11)
1119#define RT5659_PWR_RM1_L_BIT 11
1120#define RT5659_PWR_RM1_R (0x1 << 10)
1121#define RT5659_PWR_RM1_R_BIT 10
1122#define RT5659_PWR_MM (0x1 << 8)
1123#define RT5659_PWR_MM_BIT 8
1124#define RT5659_PWR_RM2_L (0x1 << 3)
1125#define RT5659_PWR_RM2_L_BIT 3
1126#define RT5659_PWR_RM2_R (0x1 << 2)
1127#define RT5659_PWR_RM2_R_BIT 2
1128
1129/* Power Management for Volume (0x0067) */
1130#define RT5659_PWR_SV_L (0x1 << 15)
1131#define RT5659_PWR_SV_L_BIT 15
1132#define RT5659_PWR_SV_R (0x1 << 14)
1133#define RT5659_PWR_SV_R_BIT 14
1134#define RT5659_PWR_OV_L (0x1 << 13)
1135#define RT5659_PWR_OV_L_BIT 13
1136#define RT5659_PWR_OV_R (0x1 << 12)
1137#define RT5659_PWR_OV_R_BIT 12
1138#define RT5659_PWR_IN_L (0x1 << 9)
1139#define RT5659_PWR_IN_L_BIT 9
1140#define RT5659_PWR_IN_R (0x1 << 8)
1141#define RT5659_PWR_IN_R_BIT 8
1142#define RT5659_PWR_MV (0x1 << 7)
1143#define RT5659_PWR_MV_BIT 7
1144#define RT5659_PWR_MIC_DET (0x1 << 5)
1145#define RT5659_PWR_MIC_DET_BIT 5
1146
1147/* I2S1/2/3 Audio Serial Data Port Control (0x0070 0x0071 0x0072) */
1148#define RT5659_I2S_MS_MASK (0x1 << 15)
1149#define RT5659_I2S_MS_SFT 15
1150#define RT5659_I2S_MS_M (0x0 << 15)
1151#define RT5659_I2S_MS_S (0x1 << 15)
1152#define RT5659_I2S_O_CP_MASK (0x3 << 12)
1153#define RT5659_I2S_O_CP_SFT 12
1154#define RT5659_I2S_O_CP_OFF (0x0 << 12)
1155#define RT5659_I2S_O_CP_U_LAW (0x1 << 12)
1156#define RT5659_I2S_O_CP_A_LAW (0x2 << 12)
1157#define RT5659_I2S_I_CP_MASK (0x3 << 10)
1158#define RT5659_I2S_I_CP_SFT 10
1159#define RT5659_I2S_I_CP_OFF (0x0 << 10)
1160#define RT5659_I2S_I_CP_U_LAW (0x1 << 10)
1161#define RT5659_I2S_I_CP_A_LAW (0x2 << 10)
1162#define RT5659_I2S_BP_MASK (0x1 << 8)
1163#define RT5659_I2S_BP_SFT 8
1164#define RT5659_I2S_BP_NOR (0x0 << 8)
1165#define RT5659_I2S_BP_INV (0x1 << 8)
1166#define RT5659_I2S_DL_MASK (0x3 << 4)
1167#define RT5659_I2S_DL_SFT 4
1168#define RT5659_I2S_DL_16 (0x0 << 4)
1169#define RT5659_I2S_DL_20 (0x1 << 4)
1170#define RT5659_I2S_DL_24 (0x2 << 4)
1171#define RT5659_I2S_DL_8 (0x3 << 4)
1172#define RT5659_I2S_DF_MASK (0x7)
1173#define RT5659_I2S_DF_SFT 0
1174#define RT5659_I2S_DF_I2S (0x0)
1175#define RT5659_I2S_DF_LEFT (0x1)
1176#define RT5659_I2S_DF_PCM_A (0x2)
1177#define RT5659_I2S_DF_PCM_B (0x3)
1178#define RT5659_I2S_DF_PCM_A_N (0x6)
1179#define RT5659_I2S_DF_PCM_B_N (0x7)
1180
1181/* ADC/DAC Clock Control 1 (0x0073) */
1182#define RT5659_I2S_PD1_MASK (0x7 << 12)
1183#define RT5659_I2S_PD1_SFT 12
1184#define RT5659_I2S_PD1_1 (0x0 << 12)
1185#define RT5659_I2S_PD1_2 (0x1 << 12)
1186#define RT5659_I2S_PD1_3 (0x2 << 12)
1187#define RT5659_I2S_PD1_4 (0x3 << 12)
1188#define RT5659_I2S_PD1_6 (0x4 << 12)
1189#define RT5659_I2S_PD1_8 (0x5 << 12)
1190#define RT5659_I2S_PD1_12 (0x6 << 12)
1191#define RT5659_I2S_PD1_16 (0x7 << 12)
1192#define RT5659_I2S_BCLK_MS2_MASK (0x1 << 11)
1193#define RT5659_I2S_BCLK_MS2_SFT 11
1194#define RT5659_I2S_BCLK_MS2_32 (0x0 << 11)
1195#define RT5659_I2S_BCLK_MS2_64 (0x1 << 11)
1196#define RT5659_I2S_PD2_MASK (0x7 << 8)
1197#define RT5659_I2S_PD2_SFT 8
1198#define RT5659_I2S_PD2_1 (0x0 << 8)
1199#define RT5659_I2S_PD2_2 (0x1 << 8)
1200#define RT5659_I2S_PD2_3 (0x2 << 8)
1201#define RT5659_I2S_PD2_4 (0x3 << 8)
1202#define RT5659_I2S_PD2_6 (0x4 << 8)
1203#define RT5659_I2S_PD2_8 (0x5 << 8)
1204#define RT5659_I2S_PD2_12 (0x6 << 8)
1205#define RT5659_I2S_PD2_16 (0x7 << 8)
1206#define RT5659_I2S_BCLK_MS3_MASK (0x1 << 7)
1207#define RT5659_I2S_BCLK_MS3_SFT 7
1208#define RT5659_I2S_BCLK_MS3_32 (0x0 << 7)
1209#define RT5659_I2S_BCLK_MS3_64 (0x1 << 7)
1210#define RT5659_I2S_PD3_MASK (0x7 << 4)
1211#define RT5659_I2S_PD3_SFT 4
1212#define RT5659_I2S_PD3_1 (0x0 << 4)
1213#define RT5659_I2S_PD3_2 (0x1 << 4)
1214#define RT5659_I2S_PD3_3 (0x2 << 4)
1215#define RT5659_I2S_PD3_4 (0x3 << 4)
1216#define RT5659_I2S_PD3_6 (0x4 << 4)
1217#define RT5659_I2S_PD3_8 (0x5 << 4)
1218#define RT5659_I2S_PD3_12 (0x6 << 4)
1219#define RT5659_I2S_PD3_16 (0x7 << 4)
1220#define RT5659_DAC_OSR_MASK (0x3 << 2)
1221#define RT5659_DAC_OSR_SFT 2
1222#define RT5659_DAC_OSR_128 (0x0 << 2)
1223#define RT5659_DAC_OSR_64 (0x1 << 2)
1224#define RT5659_DAC_OSR_32 (0x2 << 2)
1225#define RT5659_DAC_OSR_16 (0x3 << 2)
1226#define RT5659_ADC_OSR_MASK (0x3)
1227#define RT5659_ADC_OSR_SFT 0
1228#define RT5659_ADC_OSR_128 (0x0)
1229#define RT5659_ADC_OSR_64 (0x1)
1230#define RT5659_ADC_OSR_32 (0x2)
1231#define RT5659_ADC_OSR_16 (0x3)
1232
1233/* Digital Microphone Control (0x0075) */
1234#define RT5659_DMIC_1_EN_MASK (0x1 << 15)
1235#define RT5659_DMIC_1_EN_SFT 15
1236#define RT5659_DMIC_1_DIS (0x0 << 15)
1237#define RT5659_DMIC_1_EN (0x1 << 15)
1238#define RT5659_DMIC_2_EN_MASK (0x1 << 14)
1239#define RT5659_DMIC_2_EN_SFT 14
1240#define RT5659_DMIC_2_DIS (0x0 << 14)
1241#define RT5659_DMIC_2_EN (0x1 << 14)
1242#define RT5659_DMIC_1L_LH_MASK (0x1 << 13)
1243#define RT5659_DMIC_1L_LH_SFT 13
1244#define RT5659_DMIC_1L_LH_RISING (0x0 << 13)
1245#define RT5659_DMIC_1L_LH_FALLING (0x1 << 13)
1246#define RT5659_DMIC_1R_LH_MASK (0x1 << 12)
1247#define RT5659_DMIC_1R_LH_SFT 12
1248#define RT5659_DMIC_1R_LH_RISING (0x0 << 12)
1249#define RT5659_DMIC_1R_LH_FALLING (0x1 << 12)
1250#define RT5659_DMIC_2_DP_MASK (0x3 << 10)
1251#define RT5659_DMIC_2_DP_SFT 10
1252#define RT5659_DMIC_2_DP_GPIO6 (0x0 << 10)
1253#define RT5659_DMIC_2_DP_GPIO10 (0x1 << 10)
1254#define RT5659_DMIC_2_DP_GPIO12 (0x2 << 10)
1255#define RT5659_DMIC_2_DP_IN2P (0x3 << 10)
1256#define RT5659_DMIC_CLK_MASK (0x7 << 5)
1257#define RT5659_DMIC_CLK_SFT 5
1258#define RT5659_DMIC_1_DP_MASK (0x3 << 0)
1259#define RT5659_DMIC_1_DP_SFT 0
1260#define RT5659_DMIC_1_DP_GPIO5 (0x0 << 0)
1261#define RT5659_DMIC_1_DP_GPIO9 (0x1 << 0)
1262#define RT5659_DMIC_1_DP_GPIO11 (0x2 << 0)
1263#define RT5659_DMIC_1_DP_IN2N (0x3 << 0)
1264
1265/* TDM control 1 (0x0078)*/
1266#define RT5659_DS_ADC_SLOT01_SFT 14
1267#define RT5659_DS_ADC_SLOT23_SFT 12
1268#define RT5659_DS_ADC_SLOT45_SFT 10
1269#define RT5659_DS_ADC_SLOT67_SFT 8
1270#define RT5659_ADCDAT_SRC_MASK 0x1f
1271#define RT5659_ADCDAT_SRC_SFT 0
1272
1273/* Global Clock Control (0x0080) */
1274#define RT5659_SCLK_SRC_MASK (0x3 << 14)
1275#define RT5659_SCLK_SRC_SFT 14
1276#define RT5659_SCLK_SRC_MCLK (0x0 << 14)
1277#define RT5659_SCLK_SRC_PLL1 (0x1 << 14)
1278#define RT5659_SCLK_SRC_RCCLK (0x2 << 14)
1279#define RT5659_PLL1_SRC_MASK (0x7 << 11)
1280#define RT5659_PLL1_SRC_SFT 11
1281#define RT5659_PLL1_SRC_MCLK (0x0 << 11)
1282#define RT5659_PLL1_SRC_BCLK1 (0x1 << 11)
1283#define RT5659_PLL1_SRC_BCLK2 (0x2 << 11)
1284#define RT5659_PLL1_SRC_BCLK3 (0x3 << 11)
1285#define RT5659_PLL1_PD_MASK (0x1 << 3)
1286#define RT5659_PLL1_PD_SFT 3
1287#define RT5659_PLL1_PD_1 (0x0 << 3)
1288#define RT5659_PLL1_PD_2 (0x1 << 3)
1289
1290#define RT5659_PLL_INP_MAX 40000000
1291#define RT5659_PLL_INP_MIN 256000
1292/* PLL M/N/K Code Control 1 (0x0081) */
1293#define RT5659_PLL_N_MAX 0x001ff
1294#define RT5659_PLL_N_MASK (RT5659_PLL_N_MAX << 7)
1295#define RT5659_PLL_N_SFT 7
1296#define RT5659_PLL_K_MAX 0x001f
1297#define RT5659_PLL_K_MASK (RT5659_PLL_K_MAX)
1298#define RT5659_PLL_K_SFT 0
1299
1300/* PLL M/N/K Code Control 2 (0x0082) */
1301#define RT5659_PLL_M_MAX 0x00f
1302#define RT5659_PLL_M_MASK (RT5659_PLL_M_MAX << 12)
1303#define RT5659_PLL_M_SFT 12
1304#define RT5659_PLL_M_BP (0x1 << 11)
1305#define RT5659_PLL_M_BP_SFT 11
1306
1307/* PLL tracking mode 1 (0x0083) */
1308#define RT5659_I2S3_ASRC_MASK (0x1 << 13)
1309#define RT5659_I2S3_ASRC_SFT 13
1310#define RT5659_I2S2_ASRC_MASK (0x1 << 12)
1311#define RT5659_I2S2_ASRC_SFT 12
1312#define RT5659_I2S1_ASRC_MASK (0x1 << 11)
1313#define RT5659_I2S1_ASRC_SFT 11
1314#define RT5659_DAC_STO_ASRC_MASK (0x1 << 10)
1315#define RT5659_DAC_STO_ASRC_SFT 10
1316#define RT5659_DAC_MONO_L_ASRC_MASK (0x1 << 9)
1317#define RT5659_DAC_MONO_L_ASRC_SFT 9
1318#define RT5659_DAC_MONO_R_ASRC_MASK (0x1 << 8)
1319#define RT5659_DAC_MONO_R_ASRC_SFT 8
1320#define RT5659_DMIC_STO1_ASRC_MASK (0x1 << 7)
1321#define RT5659_DMIC_STO1_ASRC_SFT 7
1322#define RT5659_DMIC_MONO_L_ASRC_MASK (0x1 << 5)
1323#define RT5659_DMIC_MONO_L_ASRC_SFT 5
1324#define RT5659_DMIC_MONO_R_ASRC_MASK (0x1 << 4)
1325#define RT5659_DMIC_MONO_R_ASRC_SFT 4
1326#define RT5659_ADC_STO1_ASRC_MASK (0x1 << 3)
1327#define RT5659_ADC_STO1_ASRC_SFT 3
1328#define RT5659_ADC_MONO_L_ASRC_MASK (0x1 << 1)
1329#define RT5659_ADC_MONO_L_ASRC_SFT 1
1330#define RT5659_ADC_MONO_R_ASRC_MASK (0x1)
1331#define RT5659_ADC_MONO_R_ASRC_SFT 0
1332
1333/* PLL tracking mode 2 (0x0084)*/
1334#define RT5659_DA_STO_T_MASK (0x7 << 12)
1335#define RT5659_DA_STO_T_SFT 12
1336#define RT5659_DA_MONO_L_T_MASK (0x7 << 8)
1337#define RT5659_DA_MONO_L_T_SFT 8
1338#define RT5659_DA_MONO_R_T_MASK (0x7 << 4)
1339#define RT5659_DA_MONO_R_T_SFT 4
1340#define RT5659_AD_STO1_T_MASK (0x7)
1341#define RT5659_AD_STO1_T_SFT 0
1342
1343/* PLL tracking mode 3 (0x0085)*/
1344#define RT5659_AD_STO2_T_MASK (0x7 << 8)
1345#define RT5659_AD_STO2_T_SFT 8
1346#define RT5659_AD_MONO_L_T_MASK (0x7 << 4)
1347#define RT5659_AD_MONO_L_T_SFT 4
1348#define RT5659_AD_MONO_R_T_MASK (0x7)
1349#define RT5659_AD_MONO_R_T_SFT 0
1350
1351/* ASRC Control 4 (0x0086) */
1352#define RT5659_I2S1_RATE_MASK (0xf << 12)
1353#define RT5659_I2S1_RATE_SFT 12
1354#define RT5659_I2S2_RATE_MASK (0xf << 8)
1355#define RT5659_I2S2_RATE_SFT 8
1356#define RT5659_I2S3_RATE_MASK (0xf << 4)
1357#define RT5659_I2S3_RATE_SFT 4
1358
1359/* Depop Mode Control 1 (0x8e) */
1360#define RT5659_SMT_TRIG_MASK (0x1 << 15)
1361#define RT5659_SMT_TRIG_SFT 15
1362#define RT5659_SMT_TRIG_DIS (0x0 << 15)
1363#define RT5659_SMT_TRIG_EN (0x1 << 15)
1364#define RT5659_HP_L_SMT_MASK (0x1 << 9)
1365#define RT5659_HP_L_SMT_SFT 9
1366#define RT5659_HP_L_SMT_DIS (0x0 << 9)
1367#define RT5659_HP_L_SMT_EN (0x1 << 9)
1368#define RT5659_HP_R_SMT_MASK (0x1 << 8)
1369#define RT5659_HP_R_SMT_SFT 8
1370#define RT5659_HP_R_SMT_DIS (0x0 << 8)
1371#define RT5659_HP_R_SMT_EN (0x1 << 8)
1372#define RT5659_HP_CD_PD_MASK (0x1 << 7)
1373#define RT5659_HP_CD_PD_SFT 7
1374#define RT5659_HP_CD_PD_DIS (0x0 << 7)
1375#define RT5659_HP_CD_PD_EN (0x1 << 7)
1376#define RT5659_RSTN_MASK (0x1 << 6)
1377#define RT5659_RSTN_SFT 6
1378#define RT5659_RSTN_DIS (0x0 << 6)
1379#define RT5659_RSTN_EN (0x1 << 6)
1380#define RT5659_RSTP_MASK (0x1 << 5)
1381#define RT5659_RSTP_SFT 5
1382#define RT5659_RSTP_DIS (0x0 << 5)
1383#define RT5659_RSTP_EN (0x1 << 5)
1384#define RT5659_HP_CO_MASK (0x1 << 4)
1385#define RT5659_HP_CO_SFT 4
1386#define RT5659_HP_CO_DIS (0x0 << 4)
1387#define RT5659_HP_CO_EN (0x1 << 4)
1388#define RT5659_HP_CP_MASK (0x1 << 3)
1389#define RT5659_HP_CP_SFT 3
1390#define RT5659_HP_CP_PD (0x0 << 3)
1391#define RT5659_HP_CP_PU (0x1 << 3)
1392#define RT5659_HP_SG_MASK (0x1 << 2)
1393#define RT5659_HP_SG_SFT 2
1394#define RT5659_HP_SG_DIS (0x0 << 2)
1395#define RT5659_HP_SG_EN (0x1 << 2)
1396#define RT5659_HP_DP_MASK (0x1 << 1)
1397#define RT5659_HP_DP_SFT 1
1398#define RT5659_HP_DP_PD (0x0 << 1)
1399#define RT5659_HP_DP_PU (0x1 << 1)
1400#define RT5659_HP_CB_MASK (0x1)
1401#define RT5659_HP_CB_SFT 0
1402#define RT5659_HP_CB_PD (0x0)
1403#define RT5659_HP_CB_PU (0x1)
1404
1405/* Depop Mode Control 2 (0x8f) */
1406#define RT5659_DEPOP_MASK (0x1 << 13)
1407#define RT5659_DEPOP_SFT 13
1408#define RT5659_DEPOP_AUTO (0x0 << 13)
1409#define RT5659_DEPOP_MAN (0x1 << 13)
1410#define RT5659_RAMP_MASK (0x1 << 12)
1411#define RT5659_RAMP_SFT 12
1412#define RT5659_RAMP_DIS (0x0 << 12)
1413#define RT5659_RAMP_EN (0x1 << 12)
1414#define RT5659_BPS_MASK (0x1 << 11)
1415#define RT5659_BPS_SFT 11
1416#define RT5659_BPS_DIS (0x0 << 11)
1417#define RT5659_BPS_EN (0x1 << 11)
1418#define RT5659_FAST_UPDN_MASK (0x1 << 10)
1419#define RT5659_FAST_UPDN_SFT 10
1420#define RT5659_FAST_UPDN_DIS (0x0 << 10)
1421#define RT5659_FAST_UPDN_EN (0x1 << 10)
1422#define RT5659_MRES_MASK (0x3 << 8)
1423#define RT5659_MRES_SFT 8
1424#define RT5659_MRES_15MO (0x0 << 8)
1425#define RT5659_MRES_25MO (0x1 << 8)
1426#define RT5659_MRES_35MO (0x2 << 8)
1427#define RT5659_MRES_45MO (0x3 << 8)
1428#define RT5659_VLO_MASK (0x1 << 7)
1429#define RT5659_VLO_SFT 7
1430#define RT5659_VLO_3V (0x0 << 7)
1431#define RT5659_VLO_32V (0x1 << 7)
1432#define RT5659_DIG_DP_MASK (0x1 << 6)
1433#define RT5659_DIG_DP_SFT 6
1434#define RT5659_DIG_DP_DIS (0x0 << 6)
1435#define RT5659_DIG_DP_EN (0x1 << 6)
1436#define RT5659_DP_TH_MASK (0x3 << 4)
1437#define RT5659_DP_TH_SFT 4
1438
1439/* Depop Mode Control 3 (0x90) */
1440#define RT5659_CP_SYS_MASK (0x7 << 12)
1441#define RT5659_CP_SYS_SFT 12
1442#define RT5659_CP_FQ1_MASK (0x7 << 8)
1443#define RT5659_CP_FQ1_SFT 8
1444#define RT5659_CP_FQ2_MASK (0x7 << 4)
1445#define RT5659_CP_FQ2_SFT 4
1446#define RT5659_CP_FQ3_MASK (0x7)
1447#define RT5659_CP_FQ3_SFT 0
1448#define RT5659_CP_FQ_1_5_KHZ 0
1449#define RT5659_CP_FQ_3_KHZ 1
1450#define RT5659_CP_FQ_6_KHZ 2
1451#define RT5659_CP_FQ_12_KHZ 3
1452#define RT5659_CP_FQ_24_KHZ 4
1453#define RT5659_CP_FQ_48_KHZ 5
1454#define RT5659_CP_FQ_96_KHZ 6
1455#define RT5659_CP_FQ_192_KHZ 7
1456
1457/* HPOUT charge pump 1 (0x0091) */
1458#define RT5659_OSW_L_MASK (0x1 << 11)
1459#define RT5659_OSW_L_SFT 11
1460#define RT5659_OSW_L_DIS (0x0 << 11)
1461#define RT5659_OSW_L_EN (0x1 << 11)
1462#define RT5659_OSW_R_MASK (0x1 << 10)
1463#define RT5659_OSW_R_SFT 10
1464#define RT5659_OSW_R_DIS (0x0 << 10)
1465#define RT5659_OSW_R_EN (0x1 << 10)
1466#define RT5659_PM_HP_MASK (0x3 << 8)
1467#define RT5659_PM_HP_SFT 8
1468#define RT5659_PM_HP_LV (0x0 << 8)
1469#define RT5659_PM_HP_MV (0x1 << 8)
1470#define RT5659_PM_HP_HV (0x2 << 8)
1471#define RT5659_IB_HP_MASK (0x3 << 6)
1472#define RT5659_IB_HP_SFT 6
1473#define RT5659_IB_HP_125IL (0x0 << 6)
1474#define RT5659_IB_HP_25IL (0x1 << 6)
1475#define RT5659_IB_HP_5IL (0x2 << 6)
1476#define RT5659_IB_HP_1IL (0x3 << 6)
1477
1478/* PV detection and SPK gain control (0x92) */
1479#define RT5659_PVDD_DET_MASK (0x1 << 15)
1480#define RT5659_PVDD_DET_SFT 15
1481#define RT5659_PVDD_DET_DIS (0x0 << 15)
1482#define RT5659_PVDD_DET_EN (0x1 << 15)
1483#define RT5659_SPK_AG_MASK (0x1 << 14)
1484#define RT5659_SPK_AG_SFT 14
1485#define RT5659_SPK_AG_DIS (0x0 << 14)
1486#define RT5659_SPK_AG_EN (0x1 << 14)
1487
1488/* Micbias Control (0x93) */
1489#define RT5659_MIC1_BS_MASK (0x1 << 15)
1490#define RT5659_MIC1_BS_SFT 15
1491#define RT5659_MIC1_BS_9AV (0x0 << 15)
1492#define RT5659_MIC1_BS_75AV (0x1 << 15)
1493#define RT5659_MIC2_BS_MASK (0x1 << 14)
1494#define RT5659_MIC2_BS_SFT 14
1495#define RT5659_MIC2_BS_9AV (0x0 << 14)
1496#define RT5659_MIC2_BS_75AV (0x1 << 14)
1497#define RT5659_MIC1_CLK_MASK (0x1 << 13)
1498#define RT5659_MIC1_CLK_SFT 13
1499#define RT5659_MIC1_CLK_DIS (0x0 << 13)
1500#define RT5659_MIC1_CLK_EN (0x1 << 13)
1501#define RT5659_MIC2_CLK_MASK (0x1 << 12)
1502#define RT5659_MIC2_CLK_SFT 12
1503#define RT5659_MIC2_CLK_DIS (0x0 << 12)
1504#define RT5659_MIC2_CLK_EN (0x1 << 12)
1505#define RT5659_MIC1_OVCD_MASK (0x1 << 11)
1506#define RT5659_MIC1_OVCD_SFT 11
1507#define RT5659_MIC1_OVCD_DIS (0x0 << 11)
1508#define RT5659_MIC1_OVCD_EN (0x1 << 11)
1509#define RT5659_MIC1_OVTH_MASK (0x3 << 9)
1510#define RT5659_MIC1_OVTH_SFT 9
1511#define RT5659_MIC1_OVTH_600UA (0x0 << 9)
1512#define RT5659_MIC1_OVTH_1500UA (0x1 << 9)
1513#define RT5659_MIC1_OVTH_2000UA (0x2 << 9)
1514#define RT5659_MIC2_OVCD_MASK (0x1 << 8)
1515#define RT5659_MIC2_OVCD_SFT 8
1516#define RT5659_MIC2_OVCD_DIS (0x0 << 8)
1517#define RT5659_MIC2_OVCD_EN (0x1 << 8)
1518#define RT5659_MIC2_OVTH_MASK (0x3 << 6)
1519#define RT5659_MIC2_OVTH_SFT 6
1520#define RT5659_MIC2_OVTH_600UA (0x0 << 6)
1521#define RT5659_MIC2_OVTH_1500UA (0x1 << 6)
1522#define RT5659_MIC2_OVTH_2000UA (0x2 << 6)
1523#define RT5659_PWR_MB_MASK (0x1 << 5)
1524#define RT5659_PWR_MB_SFT 5
1525#define RT5659_PWR_MB_PD (0x0 << 5)
1526#define RT5659_PWR_MB_PU (0x1 << 5)
1527#define RT5659_PWR_CLK25M_MASK (0x1 << 4)
1528#define RT5659_PWR_CLK25M_SFT 4
1529#define RT5659_PWR_CLK25M_PD (0x0 << 4)
1530#define RT5659_PWR_CLK25M_PU (0x1 << 4)
1531
1532/* REC Mixer 2 Left Control 2 (0x009c) */
1533#define RT5659_M_BST1_RM2_L (0x1 << 5)
1534#define RT5659_M_BST1_RM2_L_SFT 5
1535#define RT5659_M_BST2_RM2_L (0x1 << 4)
1536#define RT5659_M_BST2_RM2_L_SFT 4
1537#define RT5659_M_BST3_RM2_L (0x1 << 3)
1538#define RT5659_M_BST3_RM2_L_SFT 3
1539#define RT5659_M_BST4_RM2_L (0x1 << 2)
1540#define RT5659_M_BST4_RM2_L_SFT 2
1541#define RT5659_M_OUTVOLL_RM2_L (0x1 << 1)
1542#define RT5659_M_OUTVOLL_RM2_L_SFT 1
1543#define RT5659_M_SPKVOL_RM2_L (0x1)
1544#define RT5659_M_SPKVOL_RM2_L_SFT 0
1545
1546/* REC Mixer 2 Right Control 2 (0x009e) */
1547#define RT5659_M_BST1_RM2_R (0x1 << 5)
1548#define RT5659_M_BST1_RM2_R_SFT 5
1549#define RT5659_M_BST2_RM2_R (0x1 << 4)
1550#define RT5659_M_BST2_RM2_R_SFT 4
1551#define RT5659_M_BST3_RM2_R (0x1 << 3)
1552#define RT5659_M_BST3_RM2_R_SFT 3
1553#define RT5659_M_BST4_RM2_R (0x1 << 2)
1554#define RT5659_M_BST4_RM2_R_SFT 2
1555#define RT5659_M_OUTVOLR_RM2_R (0x1 << 1)
1556#define RT5659_M_OUTVOLR_RM2_R_SFT 1
1557#define RT5659_M_MONOVOL_RM2_R (0x1)
1558#define RT5659_M_MONOVOL_RM2_R_SFT 0
1559
1560/* Class D Output Control (0x00a0) */
1561#define RT5659_POW_CLSD_DB_MASK (0x1 << 9)
1562#define RT5659_POW_CLSD_DB_EN (0x1 << 9)
1563#define RT5659_POW_CLSD_DB_DIS (0x0 << 9)
1564
1565/* EQ Control 1 (0x00b0) */
1566#define RT5659_EQ_SRC_DAC (0x0 << 15)
1567#define RT5659_EQ_SRC_ADC (0x1 << 15)
1568#define RT5659_EQ_UPD (0x1 << 14)
1569#define RT5659_EQ_UPD_BIT 14
1570#define RT5659_EQ_CD_MASK (0x1 << 13)
1571#define RT5659_EQ_CD_SFT 13
1572#define RT5659_EQ_CD_DIS (0x0 << 13)
1573#define RT5659_EQ_CD_EN (0x1 << 13)
1574#define RT5659_EQ_DITH_MASK (0x3 << 8)
1575#define RT5659_EQ_DITH_SFT 8
1576#define RT5659_EQ_DITH_NOR (0x0 << 8)
1577#define RT5659_EQ_DITH_LSB (0x1 << 8)
1578#define RT5659_EQ_DITH_LSB_1 (0x2 << 8)
1579#define RT5659_EQ_DITH_LSB_2 (0x3 << 8)
1580
1581/* IRQ Control 1 (0x00b7) */
1582#define RT5659_JD1_1_EN_MASK (0x1 << 15)
1583#define RT5659_JD1_1_EN_SFT 15
1584#define RT5659_JD1_1_DIS (0x0 << 15)
1585#define RT5659_JD1_1_EN (0x1 << 15)
1586#define RT5659_JD1_2_EN_MASK (0x1 << 12)
1587#define RT5659_JD1_2_EN_SFT 12
1588#define RT5659_JD1_2_DIS (0x0 << 12)
1589#define RT5659_JD1_2_EN (0x1 << 12)
1590#define RT5659_IL_IRQ_MASK (0x1 << 3)
1591#define RT5659_IL_IRQ_DIS (0x0 << 3)
1592#define RT5659_IL_IRQ_EN (0x1 << 3)
1593
1594/* IRQ Control 5 (0x00ba) */
1595#define RT5659_IRQ_JD_EN (0x1 << 3)
1596#define RT5659_IRQ_JD_EN_SFT 3
1597
1598/* GPIO Control 1 (0x00c0) */
1599#define RT5659_GP1_PIN_MASK (0x1 << 15)
1600#define RT5659_GP1_PIN_SFT 15
1601#define RT5659_GP1_PIN_GPIO1 (0x0 << 15)
1602#define RT5659_GP1_PIN_IRQ (0x1 << 15)
1603#define RT5659_GP2_PIN_MASK (0x1 << 14)
1604#define RT5659_GP2_PIN_SFT 14
1605#define RT5659_GP2_PIN_GPIO2 (0x0 << 14)
1606#define RT5659_GP2_PIN_DMIC1_SCL (0x1 << 14)
1607#define RT5659_GP3_PIN_MASK (0x1 << 13)
1608#define RT5659_GP3_PIN_SFT 13
1609#define RT5659_GP3_PIN_GPIO3 (0x0 << 13)
1610#define RT5659_GP3_PIN_PDM_SCL (0x1 << 13)
1611#define RT5659_GP4_PIN_MASK (0x1 << 12)
1612#define RT5659_GP4_PIN_SFT 12
1613#define RT5659_GP4_PIN_GPIO4 (0x0 << 12)
1614#define RT5659_GP4_PIN_PDM_SDA (0x1 << 12)
1615#define RT5659_GP5_PIN_MASK (0x1 << 11)
1616#define RT5659_GP5_PIN_SFT 11
1617#define RT5659_GP5_PIN_GPIO5 (0x0 << 11)
1618#define RT5659_GP5_PIN_DMIC1_SDA (0x1 << 11)
1619#define RT5659_GP6_PIN_MASK (0x1 << 10)
1620#define RT5659_GP6_PIN_SFT 10
1621#define RT5659_GP6_PIN_GPIO6 (0x0 << 10)
1622#define RT5659_GP6_PIN_DMIC2_SDA (0x1 << 10)
1623#define RT5659_GP7_PIN_MASK (0x1 << 9)
1624#define RT5659_GP7_PIN_SFT 9
1625#define RT5659_GP7_PIN_GPIO7 (0x0 << 9)
1626#define RT5659_GP7_PIN_PDM_SCL (0x1 << 9)
1627#define RT5659_GP8_PIN_MASK (0x1 << 8)
1628#define RT5659_GP8_PIN_SFT 8
1629#define RT5659_GP8_PIN_GPIO8 (0x0 << 8)
1630#define RT5659_GP8_PIN_PDM_SDA (0x1 << 8)
1631#define RT5659_GP9_PIN_MASK (0x1 << 7)
1632#define RT5659_GP9_PIN_SFT 7
1633#define RT5659_GP9_PIN_GPIO9 (0x0 << 7)
1634#define RT5659_GP9_PIN_DMIC1_SDA (0x1 << 7)
1635#define RT5659_GP10_PIN_MASK (0x1 << 6)
1636#define RT5659_GP10_PIN_SFT 6
1637#define RT5659_GP10_PIN_GPIO10 (0x0 << 6)
1638#define RT5659_GP10_PIN_DMIC2_SDA (0x1 << 6)
1639#define RT5659_GP11_PIN_MASK (0x1 << 5)
1640#define RT5659_GP11_PIN_SFT 5
1641#define RT5659_GP11_PIN_GPIO11 (0x0 << 5)
1642#define RT5659_GP11_PIN_DMIC1_SDA (0x1 << 5)
1643#define RT5659_GP12_PIN_MASK (0x1 << 4)
1644#define RT5659_GP12_PIN_SFT 4
1645#define RT5659_GP12_PIN_GPIO12 (0x0 << 4)
1646#define RT5659_GP12_PIN_DMIC2_SDA (0x1 << 4)
1647#define RT5659_GP13_PIN_MASK (0x3 << 2)
1648#define RT5659_GP13_PIN_SFT 2
1649#define RT5659_GP13_PIN_GPIO13 (0x0 << 2)
1650#define RT5659_GP13_PIN_SPDIF_SDA (0x1 << 2)
1651#define RT5659_GP13_PIN_DMIC2_SCL (0x2 << 2)
1652#define RT5659_GP13_PIN_PDM_SCL (0x3 << 2)
1653#define RT5659_GP15_PIN_MASK (0x3)
1654#define RT5659_GP15_PIN_SFT 0
1655#define RT5659_GP15_PIN_GPIO15 (0x0)
1656#define RT5659_GP15_PIN_DMIC3_SCL (0x1)
1657#define RT5659_GP15_PIN_PDM_SDA (0x2)
1658
1659/* GPIO Control 2 (0x00c1)*/
1660#define RT5659_GP1_PF_IN (0x0 << 2)
1661#define RT5659_GP1_PF_OUT (0x1 << 2)
1662#define RT5659_GP1_PF_MASK (0x1 << 2)
1663#define RT5659_GP1_PF_SFT 2
1664
1665/* GPIO Control 3 (0x00c2) */
1666#define RT5659_I2S2_PIN_MASK (0x1 << 15)
1667#define RT5659_I2S2_PIN_SFT 15
1668#define RT5659_I2S2_PIN_I2S (0x0 << 15)
1669#define RT5659_I2S2_PIN_GPIO (0x1 << 15)
1670
1671/* Soft volume and zero cross control 1 (0x00d9) */
1672#define RT5659_SV_MASK (0x1 << 15)
1673#define RT5659_SV_SFT 15
1674#define RT5659_SV_DIS (0x0 << 15)
1675#define RT5659_SV_EN (0x1 << 15)
1676#define RT5659_OUT_SV_MASK (0x1 << 13)
1677#define RT5659_OUT_SV_SFT 13
1678#define RT5659_OUT_SV_DIS (0x0 << 13)
1679#define RT5659_OUT_SV_EN (0x1 << 13)
1680#define RT5659_HP_SV_MASK (0x1 << 12)
1681#define RT5659_HP_SV_SFT 12
1682#define RT5659_HP_SV_DIS (0x0 << 12)
1683#define RT5659_HP_SV_EN (0x1 << 12)
1684#define RT5659_ZCD_DIG_MASK (0x1 << 11)
1685#define RT5659_ZCD_DIG_SFT 11
1686#define RT5659_ZCD_DIG_DIS (0x0 << 11)
1687#define RT5659_ZCD_DIG_EN (0x1 << 11)
1688#define RT5659_ZCD_MASK (0x1 << 10)
1689#define RT5659_ZCD_SFT 10
1690#define RT5659_ZCD_PD (0x0 << 10)
1691#define RT5659_ZCD_PU (0x1 << 10)
1692#define RT5659_SV_DLY_MASK (0xf)
1693#define RT5659_SV_DLY_SFT 0
1694
1695/* Soft volume and zero cross control 2 (0x00da) */
1696#define RT5659_ZCD_HP_MASK (0x1 << 15)
1697#define RT5659_ZCD_HP_SFT 15
1698#define RT5659_ZCD_HP_DIS (0x0 << 15)
1699#define RT5659_ZCD_HP_EN (0x1 << 15)
1700
1701/* 4 Button Inline Command Control 2 (0x00e0) */
1702#define RT5659_4BTN_IL_MASK (0x1 << 15)
1703#define RT5659_4BTN_IL_EN (0x1 << 15)
1704#define RT5659_4BTN_IL_DIS (0x0 << 15)
1705
1706/* Analog JD Control 1 (0x00f0) */
1707#define RT5659_JD1_MODE_MASK (0x3 << 0)
1708#define RT5659_JD1_MODE_0 (0x0 << 0)
1709#define RT5659_JD1_MODE_1 (0x1 << 0)
1710#define RT5659_JD1_MODE_2 (0x2 << 0)
1711
1712/* Jack Detect Control 3 (0x00f8) */
1713#define RT5659_JD_TRI_HPO_SEL_MASK (0x7)
1714#define RT5659_JD_TRI_HPO_SEL_SFT (0)
1715#define RT5659_JD_HPO_GPIO_JD1 (0x0)
1716#define RT5659_JD_HPO_JD1_1 (0x1)
1717#define RT5659_JD_HPO_JD1_2 (0x2)
1718#define RT5659_JD_HPO_JD2 (0x3)
1719#define RT5659_JD_HPO_GPIO_JD2 (0x4)
1720#define RT5659_JD_HPO_JD3 (0x5)
1721#define RT5659_JD_HPO_JD_D (0x6)
1722
1723/* Digital Misc Control (0x00fa) */
1724#define RT5659_AM_MASK (0x1 << 7)
1725#define RT5659_AM_EN (0x1 << 7)
1726#define RT5659_AM_DIS (0x1 << 7)
1727#define RT5659_DIG_GATE_CTRL 0x1
1728#define RT5659_DIG_GATE_CTRL_SFT (0)
1729
1730/* Chopper and Clock control for ADC (0x011c)*/
1731#define RT5659_M_RF_DIG_MASK (0x1 << 12)
1732#define RT5659_M_RF_DIG_SFT 12
1733#define RT5659_M_RI_DIG (0x1 << 11)
1734
1735/* Chopper and Clock control for DAC (0x013a)*/
1736#define RT5659_CKXEN_DAC1_MASK (0x1 << 13)
1737#define RT5659_CKXEN_DAC1_SFT 13
1738#define RT5659_CKGEN_DAC1_MASK (0x1 << 12)
1739#define RT5659_CKGEN_DAC1_SFT 12
1740#define RT5659_CKXEN_DAC2_MASK (0x1 << 5)
1741#define RT5659_CKXEN_DAC2_SFT 5
1742#define RT5659_CKGEN_DAC2_MASK (0x1 << 4)
1743#define RT5659_CKGEN_DAC2_SFT 4
1744
1745/* Chopper and Clock control for ADC (0x013b)*/
1746#define RT5659_CKXEN_ADCC_MASK (0x1 << 13)
1747#define RT5659_CKXEN_ADCC_SFT 13
1748#define RT5659_CKGEN_ADCC_MASK (0x1 << 12)
1749#define RT5659_CKGEN_ADCC_SFT 12
1750
1751/* Test Mode Control 1 (0x0145) */
1752#define RT5659_AD2DA_LB_MASK (0x1 << 9)
1753#define RT5659_AD2DA_LB_SFT 9
1754
1755/* Stereo Noise Gate Control 1 (0x0160) */
1756#define RT5659_NG2_EN_MASK (0x1 << 15)
1757#define RT5659_NG2_EN (0x1 << 15)
1758#define RT5659_NG2_DIS (0x0 << 15)
1759
1760/* System Clock Source */
1761enum {
1762 RT5659_SCLK_S_MCLK,
1763 RT5659_SCLK_S_PLL1,
1764 RT5659_SCLK_S_RCCLK,
1765};
1766
1767/* PLL1 Source */
1768enum {
1769 RT5659_PLL1_S_MCLK,
1770 RT5659_PLL1_S_BCLK1,
1771 RT5659_PLL1_S_BCLK2,
1772 RT5659_PLL1_S_BCLK3,
1773 RT5659_PLL1_S_BCLK4,
1774};
1775
1776enum {
1777 RT5659_AIF1,
1778 RT5659_AIF2,
1779 RT5659_AIF3,
1780 RT5659_AIF4,
1781 RT5659_AIFS,
1782};
1783
1784struct rt5659_pll_code {
1785 bool m_bp;
1786 int m_code;
1787 int n_code;
1788 int k_code;
1789};
1790
1791struct rt5659_priv {
1792 struct snd_soc_codec *codec;
1793 struct rt5659_platform_data pdata;
1794 struct regmap *regmap;
1795 struct i2c_client *i2c;
1796 struct gpio_desc *gpiod_ldo1_en;
1797 struct gpio_desc *gpiod_reset;
1798 struct snd_soc_jack *hs_jack;
1799 struct delayed_work jack_detect_work;
1800
1801 int sysclk;
1802 int sysclk_src;
1803 int lrck[RT5659_AIFS];
1804 int bclk[RT5659_AIFS];
1805 int master[RT5659_AIFS];
1806 int v_id;
1807
1808 int pll_src;
1809 int pll_in;
1810 int pll_out;
1811
1812 int jack_type;
1813
1814};
1815
1816int rt5659_set_jack_detect(struct snd_soc_codec *codec,
1817 struct snd_soc_jack *hs_jack);
1818
1819#endif /* __RT5659_H__ */
diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c
index 69d987a9935c..f2156af29e10 100644
--- a/sound/soc/codecs/rt5677.c
+++ b/sound/soc/codecs/rt5677.c
@@ -4788,7 +4788,7 @@ static int rt5677_remove(struct snd_soc_codec *codec)
4788 4788
4789 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec); 4789 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
4790 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); 4790 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4791 gpiod_set_value_cansleep(rt5677->reset_pin, 0); 4791 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4792 4792
4793 return 0; 4793 return 0;
4794} 4794}
@@ -4803,7 +4803,7 @@ static int rt5677_suspend(struct snd_soc_codec *codec)
4803 regcache_mark_dirty(rt5677->regmap); 4803 regcache_mark_dirty(rt5677->regmap);
4804 4804
4805 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0); 4805 gpiod_set_value_cansleep(rt5677->pow_ldo2, 0);
4806 gpiod_set_value_cansleep(rt5677->reset_pin, 0); 4806 gpiod_set_value_cansleep(rt5677->reset_pin, 1);
4807 } 4807 }
4808 4808
4809 return 0; 4809 return 0;
@@ -4814,8 +4814,11 @@ static int rt5677_resume(struct snd_soc_codec *codec)
4814 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec); 4814 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
4815 4815
4816 if (!rt5677->dsp_vad_en) { 4816 if (!rt5677->dsp_vad_en) {
4817 rt5677->pll_src = 0;
4818 rt5677->pll_in = 0;
4819 rt5677->pll_out = 0;
4817 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1); 4820 gpiod_set_value_cansleep(rt5677->pow_ldo2, 1);
4818 gpiod_set_value_cansleep(rt5677->reset_pin, 1); 4821 gpiod_set_value_cansleep(rt5677->reset_pin, 0);
4819 if (rt5677->pow_ldo2 || rt5677->reset_pin) 4822 if (rt5677->pow_ldo2 || rt5677->reset_pin)
4820 msleep(10); 4823 msleep(10);
4821 4824
@@ -5160,7 +5163,7 @@ static int rt5677_i2c_probe(struct i2c_client *i2c,
5160 return ret; 5163 return ret;
5161 } 5164 }
5162 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev, 5165 rt5677->reset_pin = devm_gpiod_get_optional(&i2c->dev,
5163 "realtek,reset", GPIOD_OUT_HIGH); 5166 "realtek,reset", GPIOD_OUT_LOW);
5164 if (IS_ERR(rt5677->reset_pin)) { 5167 if (IS_ERR(rt5677->reset_pin)) {
5165 ret = PTR_ERR(rt5677->reset_pin); 5168 ret = PTR_ERR(rt5677->reset_pin);
5166 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret); 5169 dev_err(&i2c->dev, "Failed to request RESET: %d\n", ret);
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-29 10:43:30 -0500