1 files changed, 11 insertions, 1 deletions

diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
index 3f5c350716bb..0bd1294ba517 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
@@ -1871,7 +1871,12 @@ s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
         if (enable_addr != 0)
                 rar_high |= IXGBE_RAH_AV;
 
+        /* Record lower 32 bits of MAC address and then make
+         * sure that write is flushed to hardware before writing
+         * the upper 16 bits and setting the valid bit.
+         */
         IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
+        IXGBE_WRITE_FLUSH(hw);
         IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
 
         return 0;
@@ -1903,8 +1908,13 @@ s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
         rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
         rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
 
-        IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
+        /* Clear the address valid bit and upper 16 bits of the address
+         * before clearing the lower bits. This way we aren't updating
+         * a live filter.
+         */
         IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
+        IXGBE_WRITE_FLUSH(hw);
+        IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
 
         /* clear VMDq pool/queue selection for this RAR */
         hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);