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-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi197
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi373
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi1191
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-tm2.dts1087
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts42
-rw-r--r--arch/arm64/boot/dts/exynos/exynos5433.dtsi123
-rw-r--r--arch/arm64/boot/dts/exynos/exynos7-espresso.dts49
-rw-r--r--arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi302
-rw-r--r--arch/arm64/boot/dts/exynos/exynos7.dtsi34
-rw-r--r--drivers/clk/samsung/clk-exynos5433.c8
-rw-r--r--include/dt-bindings/clock/exynos5433.h5
-rw-r--r--include/dt-bindings/pinctrl/samsung.h22
12 files changed, 2036 insertions, 1397 deletions
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi
new file mode 100644
index 000000000000..c42dc39c3223
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi
@@ -0,0 +1,197 @@
1/*
2 * Samsung's Exynos5433 SoC Memory interface and AMBA bus device tree source
3 *
4 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
5 * Chanwoo Choi <cw00.choi@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12&soc {
13 bus_g2d_400: bus0 {
14 compatible = "samsung,exynos-bus";
15 clocks = <&cmu_top CLK_ACLK_G2D_400>;
16 clock-names = "bus";
17 operating-points-v2 = <&bus_g2d_400_opp_table>;
18 status = "disabled";
19 };
20
21 bus_g2d_266: bus1 {
22 compatible = "samsung,exynos-bus";
23 clocks = <&cmu_top CLK_ACLK_G2D_266>;
24 clock-names = "bus";
25 operating-points-v2 = <&bus_g2d_266_opp_table>;
26 status = "disabled";
27 };
28
29 bus_gscl: bus2 {
30 compatible = "samsung,exynos-bus";
31 clocks = <&cmu_top CLK_ACLK_GSCL_333>;
32 clock-names = "bus";
33 operating-points-v2 = <&bus_gscl_opp_table>;
34 status = "disabled";
35 };
36
37 bus_hevc: bus3 {
38 compatible = "samsung,exynos-bus";
39 clocks = <&cmu_top CLK_ACLK_HEVC_400>;
40 clock-names = "bus";
41 operating-points-v2 = <&bus_hevc_opp_table>;
42 status = "disabled";
43 };
44
45 bus_jpeg: bus4 {
46 compatible = "samsung,exynos-bus";
47 clocks = <&cmu_top CLK_SCLK_JPEG_MSCL>;
48 clock-names = "bus";
49 operating-points-v2 = <&bus_g2d_400_opp_table>;
50 status = "disabled";
51 };
52
53 bus_mfc: bus5 {
54 compatible = "samsung,exynos-bus";
55 clocks = <&cmu_top CLK_ACLK_MFC_400>;
56 clock-names = "bus";
57 operating-points-v2 = <&bus_g2d_400_opp_table>;
58 status = "disabled";
59 };
60
61 bus_mscl: bus6 {
62 compatible = "samsung,exynos-bus";
63 clocks = <&cmu_top CLK_ACLK_MSCL_400>;
64 clock-names = "bus";
65 operating-points-v2 = <&bus_g2d_400_opp_table>;
66 status = "disabled";
67 };
68
69 bus_noc0: bus7 {
70 compatible = "samsung,exynos-bus";
71 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
72 clock-names = "bus";
73 operating-points-v2 = <&bus_hevc_opp_table>;
74 status = "disabled";
75 };
76
77 bus_noc1: bus8 {
78 compatible = "samsung,exynos-bus";
79 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
80 clock-names = "bus";
81 operating-points-v2 = <&bus_hevc_opp_table>;
82 status = "disabled";
83 };
84
85 bus_noc2: bus9 {
86 compatible = "samsung,exynos-bus";
87 clocks = <&cmu_mif CLK_ACLK_BUS2_400>;
88 clock-names = "bus";
89 operating-points-v2 = <&bus_noc2_opp_table>;
90 status = "disabled";
91 };
92
93 bus_g2d_400_opp_table: opp_table2 {
94 compatible = "operating-points-v2";
95 opp-shared;
96
97 opp@400000000 {
98 opp-hz = /bits/ 64 <400000000>;
99 opp-microvolt = <1075000>;
100 };
101 opp@267000000 {
102 opp-hz = /bits/ 64 <267000000>;
103 opp-microvolt = <1000000>;
104 };
105 opp@200000000 {
106 opp-hz = /bits/ 64 <200000000>;
107 opp-microvolt = <975000>;
108 };
109 opp@160000000 {
110 opp-hz = /bits/ 64 <160000000>;
111 opp-microvolt = <962500>;
112 };
113 opp@134000000 {
114 opp-hz = /bits/ 64 <134000000>;
115 opp-microvolt = <950000>;
116 };
117 opp@100000000 {
118 opp-hz = /bits/ 64 <100000000>;
119 opp-microvolt = <937500>;
120 };
121 };
122
123 bus_g2d_266_opp_table: opp_table3 {
124 compatible = "operating-points-v2";
125
126 opp@267000000 {
127 opp-hz = /bits/ 64 <267000000>;
128 };
129 opp@200000000 {
130 opp-hz = /bits/ 64 <200000000>;
131 };
132 opp@160000000 {
133 opp-hz = /bits/ 64 <160000000>;
134 };
135 opp@134000000 {
136 opp-hz = /bits/ 64 <134000000>;
137 };
138 opp@100000000 {
139 opp-hz = /bits/ 64 <100000000>;
140 };
141 };
142
143 bus_gscl_opp_table: opp_table4 {
144 compatible = "operating-points-v2";
145
146 opp@333000000 {
147 opp-hz = /bits/ 64 <333000000>;
148 };
149 opp@222000000 {
150 opp-hz = /bits/ 64 <222000000>;
151 };
152 opp@166500000 {
153 opp-hz = /bits/ 64 <166500000>;
154 };
155 };
156
157 bus_hevc_opp_table: opp_table5 {
158 compatible = "operating-points-v2";
159 opp-shared;
160
161 opp@400000000 {
162 opp-hz = /bits/ 64 <400000000>;
163 };
164 opp@267000000 {
165 opp-hz = /bits/ 64 <267000000>;
166 };
167 opp@200000000 {
168 opp-hz = /bits/ 64 <200000000>;
169 };
170 opp@160000000 {
171 opp-hz = /bits/ 64 <160000000>;
172 };
173 opp@134000000 {
174 opp-hz = /bits/ 64 <134000000>;
175 };
176 opp@100000000 {
177 opp-hz = /bits/ 64 <100000000>;
178 };
179 };
180
181 bus_noc2_opp_table: opp_table6 {
182 compatible = "operating-points-v2";
183
184 opp@400000000 {
185 opp-hz = /bits/ 64 <400000000>;
186 };
187 opp@200000000 {
188 opp-hz = /bits/ 64 <200000000>;
189 };
190 opp@134000000 {
191 opp-hz = /bits/ 64 <134000000>;
192 };
193 opp@100000000 {
194 opp-hz = /bits/ 64 <100000000>;
195 };
196 };
197};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
index ad71247b074f..50403700274b 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
@@ -12,25 +12,14 @@
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 */ 13 */
14 14
15#define PIN_PULL_NONE 0 15#include <dt-bindings/pinctrl/samsung.h>
16#define PIN_PULL_DOWN 1 16
17#define PIN_PULL_UP 3 17#define PIN(_func, _pin, _pull, _drv) \
18 18 _pin { \
19#define PIN_DRV_LV1 0 19 samsung,pins = #_pin; \
20#define PIN_DRV_LV2 2 20 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
21#define PIN_DRV_LV3 1 21 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
22#define PIN_DRV_LV4 3 22 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
23
24#define PIN_IN 0
25#define PIN_OUT 1
26#define PIN_FUNC1 2
27
28#define PIN(_func, _pin, _pull, _drv) \
29 _pin { \
30 samsung,pins = #_pin; \
31 samsung,pin-function = <PIN_ ##_func>; \
32 samsung,pin-pud = <PIN_PULL_ ##_pull>; \
33 samsung,pin-drv = <PIN_DRV_ ##_drv>; \
34 } 23 }
35 24
36&pinctrl_alive { 25&pinctrl_alive {
@@ -145,23 +134,23 @@
145 i2s0_bus: i2s0-bus { 134 i2s0_bus: i2s0-bus {
146 samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3", 135 samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3",
147 "gpz0-4", "gpz0-5", "gpz0-6"; 136 "gpz0-4", "gpz0-5", "gpz0-6";
148 samsung,pin-function = <2>; 137 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
149 samsung,pin-pud = <1>; 138 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
150 samsung,pin-drv = <0>; 139 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
151 }; 140 };
152 141
153 pcm0_bus: pcm0-bus { 142 pcm0_bus: pcm0-bus {
154 samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3"; 143 samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3";
155 samsung,pin-function = <3>; 144 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
156 samsung,pin-pud = <1>; 145 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
157 samsung,pin-drv = <0>; 146 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
158 }; 147 };
159 148
160 uart_aud_bus: uart-aud-bus { 149 uart_aud_bus: uart-aud-bus {
161 samsung,pins = "gpz1-3", "gpz1-2", "gpz1-1", "gpz1-0"; 150 samsung,pins = "gpz1-3", "gpz1-2", "gpz1-1", "gpz1-0";
162 samsung,pin-function = <2>; 151 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
163 samsung,pin-pud = <0>; 152 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
164 samsung,pin-drv = <0>; 153 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
165 }; 154 };
166}; 155};
167 156
@@ -196,16 +185,16 @@
196 185
197 spi2_bus: spi2-bus { 186 spi2_bus: spi2-bus {
198 samsung,pins = "gpd5-0", "gpd5-2", "gpd5-3"; 187 samsung,pins = "gpd5-0", "gpd5-2", "gpd5-3";
199 samsung,pin-function = <2>; 188 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
200 samsung,pin-pud = <3>; 189 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
201 samsung,pin-drv = <0>; 190 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
202 }; 191 };
203 192
204 hs_i2c6_bus: hs-i2c6-bus { 193 hs_i2c6_bus: hs-i2c6-bus {
205 samsung,pins = "gpd5-3", "gpd5-2"; 194 samsung,pins = "gpd5-3", "gpd5-2";
206 samsung,pin-function = <4>; 195 samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
207 samsung,pin-pud = <3>; 196 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
208 samsung,pin-drv = <0>; 197 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
209 }; 198 };
210}; 199};
211 200
@@ -260,141 +249,141 @@
260 249
261 sd0_clk: sd0-clk { 250 sd0_clk: sd0-clk {
262 samsung,pins = "gpr0-0"; 251 samsung,pins = "gpr0-0";
263 samsung,pin-function = <2>; 252 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
264 samsung,pin-pud = <0>; 253 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
265 samsung,pin-drv = <3>; 254 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
266 }; 255 };
267 256
268 sd0_cmd: sd0-cmd { 257 sd0_cmd: sd0-cmd {
269 samsung,pins = "gpr0-1"; 258 samsung,pins = "gpr0-1";
270 samsung,pin-function = <2>; 259 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
271 samsung,pin-pud = <0>; 260 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
272 samsung,pin-drv = <3>; 261 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
273 }; 262 };
274 263
275 sd0_rdqs: sd0-rdqs { 264 sd0_rdqs: sd0-rdqs {
276 samsung,pins = "gpr0-2"; 265 samsung,pins = "gpr0-2";
277 samsung,pin-function = <2>; 266 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
278 samsung,pin-pud = <1>; 267 samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
279 samsung,pin-drv = <3>; 268 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
280 }; 269 };
281 270
282 sd0_qrdy: sd0-qrdy { 271 sd0_qrdy: sd0-qrdy {
283 samsung,pins = "gpr0-3"; 272 samsung,pins = "gpr0-3";
284 samsung,pin-function = <2>; 273 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
285 samsung,pin-pud = <1>; 274 samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
286 samsung,pin-drv = <3>; 275 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
287 }; 276 };
288 277
289 sd0_bus1: sd0-bus-width1 { 278 sd0_bus1: sd0-bus-width1 {
290 samsung,pins = "gpr1-0"; 279 samsung,pins = "gpr1-0";
291 samsung,pin-function = <2>; 280 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
292 samsung,pin-pud = <3>; 281 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
293 samsung,pin-drv = <3>; 282 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
294 }; 283 };
295 284
296 sd0_bus4: sd0-bus-width4 { 285 sd0_bus4: sd0-bus-width4 {
297 samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3"; 286 samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3";
298 samsung,pin-function = <2>; 287 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
299 samsung,pin-pud = <3>; 288 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
300 samsung,pin-drv = <3>; 289 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
301 }; 290 };
302 291
303 sd0_bus8: sd0-bus-width8 { 292 sd0_bus8: sd0-bus-width8 {
304 samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7"; 293 samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7";
305 samsung,pin-function = <2>; 294 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
306 samsung,pin-pud = <3>; 295 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
307 samsung,pin-drv = <3>; 296 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
308 }; 297 };
309 298
310 sd1_clk: sd1-clk { 299 sd1_clk: sd1-clk {
311 samsung,pins = "gpr2-0"; 300 samsung,pins = "gpr2-0";
312 samsung,pin-function = <2>; 301 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
313 samsung,pin-pud = <0>; 302 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
314 samsung,pin-drv = <3>; 303 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
315 }; 304 };
316 305
317 sd1_cmd: sd1-cmd { 306 sd1_cmd: sd1-cmd {
318 samsung,pins = "gpr2-1"; 307 samsung,pins = "gpr2-1";
319 samsung,pin-function = <2>; 308 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
320 samsung,pin-pud = <0>; 309 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
321 samsung,pin-drv = <3>; 310 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
322 }; 311 };
323 312
324 sd1_bus1: sd1-bus-width1 { 313 sd1_bus1: sd1-bus-width1 {
325 samsung,pins = "gpr3-0"; 314 samsung,pins = "gpr3-0";
326 samsung,pin-function = <2>; 315 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
327 samsung,pin-pud = <3>; 316 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
328 samsung,pin-drv = <3>; 317 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
329 }; 318 };
330 319
331 sd1_bus4: sd1-bus-width4 { 320 sd1_bus4: sd1-bus-width4 {
332 samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3"; 321 samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3";
333 samsung,pin-function = <2>; 322 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
334 samsung,pin-pud = <3>; 323 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
335 samsung,pin-drv = <3>; 324 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
336 }; 325 };
337 326
338 sd1_bus8: sd1-bus-width8 { 327 sd1_bus8: sd1-bus-width8 {
339 samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; 328 samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
340 samsung,pin-function = <2>; 329 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
341 samsung,pin-pud = <3>; 330 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
342 samsung,pin-drv = <3>; 331 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
343 }; 332 };
344 333
345 pcie_bus: pcie_bus { 334 pcie_bus: pcie_bus {
346 samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; 335 samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
347 samsung,pin-function = <3>; 336 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
348 samsung,pin-pud = <3>; 337 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
349 }; 338 };
350 339
351 sd2_clk: sd2-clk { 340 sd2_clk: sd2-clk {
352 samsung,pins = "gpr4-0"; 341 samsung,pins = "gpr4-0";
353 samsung,pin-function = <2>; 342 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
354 samsung,pin-pud = <0>; 343 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
355 samsung,pin-drv = <3>; 344 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
356 }; 345 };
357 346
358 sd2_cmd: sd2-cmd { 347 sd2_cmd: sd2-cmd {
359 samsung,pins = "gpr4-1"; 348 samsung,pins = "gpr4-1";
360 samsung,pin-function = <2>; 349 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
361 samsung,pin-pud = <0>; 350 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
362 samsung,pin-drv = <3>; 351 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
363 }; 352 };
364 353
365 sd2_cd: sd2-cd { 354 sd2_cd: sd2-cd {
366 samsung,pins = "gpr4-2"; 355 samsung,pins = "gpr4-2";
367 samsung,pin-function = <2>; 356 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
368 samsung,pin-pud = <3>; 357 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
369 samsung,pin-drv = <3>; 358 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
370 }; 359 };
371 360
372 sd2_bus1: sd2-bus-width1 { 361 sd2_bus1: sd2-bus-width1 {
373 samsung,pins = "gpr4-3"; 362 samsung,pins = "gpr4-3";
374 samsung,pin-function = <2>; 363 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
375 samsung,pin-pud = <3>; 364 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
376 samsung,pin-drv = <3>; 365 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
377 }; 366 };
378 367
379 sd2_bus4: sd2-bus-width4 { 368 sd2_bus4: sd2-bus-width4 {
380 samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6"; 369 samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6";
381 samsung,pin-function = <2>; 370 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
382 samsung,pin-pud = <3>; 371 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
383 samsung,pin-drv = <3>; 372 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
384 }; 373 };
385 374
386 sd2_clk_output: sd2-clk-output { 375 sd2_clk_output: sd2-clk-output {
387 samsung,pins = "gpr4-0"; 376 samsung,pins = "gpr4-0";
388 samsung,pin-function = <1>; 377 samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
389 samsung,pin-pud = <0>; 378 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
390 samsung,pin-drv = <2>; 379 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR3>;
391 }; 380 };
392 381
393 sd2_cmd_output: sd2-cmd-output { 382 sd2_cmd_output: sd2-cmd-output {
394 samsung,pins = "gpr4-1"; 383 samsung,pins = "gpr4-1";
395 samsung,pin-function = <1>; 384 samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
396 samsung,pin-pud = <0>; 385 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
397 samsung,pin-drv = <2>; 386 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR3>;
398 }; 387 };
399}; 388};
400 389
@@ -419,9 +408,9 @@
419 408
420 hs_i2c4_bus: hs-i2c4-bus { 409 hs_i2c4_bus: hs-i2c4-bus {
421 samsung,pins = "gpj0-1", "gpj0-0"; 410 samsung,pins = "gpj0-1", "gpj0-0";
422 samsung,pin-function = <4>; 411 samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
423 samsung,pin-pud = <3>; 412 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
424 samsung,pin-drv = <0>; 413 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
425 }; 414 };
426}; 415};
427 416
@@ -564,225 +553,225 @@
564 553
565 hs_i2c8_bus: hs-i2c8-bus { 554 hs_i2c8_bus: hs-i2c8-bus {
566 samsung,pins = "gpb0-1", "gpb0-0"; 555 samsung,pins = "gpb0-1", "gpb0-0";
567 samsung,pin-function = <4>; 556 samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
568 samsung,pin-pud = <3>; 557 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
569 samsung,pin-drv = <0>; 558 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
570 }; 559 };
571 560
572 hs_i2c9_bus: hs-i2c9-bus { 561 hs_i2c9_bus: hs-i2c9-bus {
573 samsung,pins = "gpb0-3", "gpb0-2"; 562 samsung,pins = "gpb0-3", "gpb0-2";
574 samsung,pin-function = <4>; 563 samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
575 samsung,pin-pud = <3>; 564 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
576 samsung,pin-drv = <0>; 565 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
577 }; 566 };
578 567
579 i2s1_bus: i2s1-bus { 568 i2s1_bus: i2s1-bus {
580 samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", 569 samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2",
581 "gpd4-3", "gpd4-4"; 570 "gpd4-3", "gpd4-4";
582 samsung,pin-function = <2>; 571 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
583 samsung,pin-pud = <1>; 572 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
584 samsung,pin-drv = <0>; 573 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
585 }; 574 };
586 575
587 pcm1_bus: pcm1-bus { 576 pcm1_bus: pcm1-bus {
588 samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", 577 samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2",
589 "gpd4-3", "gpd4-4"; 578 "gpd4-3", "gpd4-4";
590 samsung,pin-function = <3>; 579 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
591 samsung,pin-pud = <1>; 580 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
592 samsung,pin-drv = <0>; 581 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
593 }; 582 };
594 583
595 spdif_bus: spdif-bus { 584 spdif_bus: spdif-bus {
596 samsung,pins = "gpd4-3", "gpd4-4"; 585 samsung,pins = "gpd4-3", "gpd4-4";
597 samsung,pin-function = <4>; 586 samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
598 samsung,pin-pud = <1>; 587 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
599 samsung,pin-drv = <0>; 588 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
600 }; 589 };
601 590
602 fimc_is_spi_pin0: fimc-is-spi-pin0 { 591 fimc_is_spi_pin0: fimc-is-spi-pin0 {
603 samsung,pins = "gpc3-3", "gpc3-2", "gpc3-1", "gpc3-0"; 592 samsung,pins = "gpc3-3", "gpc3-2", "gpc3-1", "gpc3-0";
604 samsung,pin-function = <2>; 593 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
605 samsung,pin-pud = <0>; 594 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
606 samsung,pin-drv = <0>; 595 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
607 }; 596 };
608 597
609 fimc_is_spi_pin1: fimc-is-spi-pin1 { 598 fimc_is_spi_pin1: fimc-is-spi-pin1 {
610 samsung,pins = "gpc3-7", "gpc3-6", "gpc3-5", "gpc3-4"; 599 samsung,pins = "gpc3-7", "gpc3-6", "gpc3-5", "gpc3-4";
611 samsung,pin-function = <2>; 600 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
612 samsung,pin-pud = <0>; 601 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
613 samsung,pin-drv = <0>; 602 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
614 }; 603 };
615 604
616 uart0_bus: uart0-bus { 605 uart0_bus: uart0-bus {
617 samsung,pins = "gpd0-3", "gpd0-2", "gpd0-1", "gpd0-0"; 606 samsung,pins = "gpd0-3", "gpd0-2", "gpd0-1", "gpd0-0";
618 samsung,pin-function = <2>; 607 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
619 samsung,pin-pud = <0>; 608 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
620 }; 609 };
621 610
622 hs_i2c2_bus: hs-i2c2-bus { 611 hs_i2c2_bus: hs-i2c2-bus {
623 samsung,pins = "gpd0-3", "gpd0-2"; 612 samsung,pins = "gpd0-3", "gpd0-2";
624 samsung,pin-function = <3>; 613 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
625 samsung,pin-pud = <3>; 614 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
626 samsung,pin-drv = <0>; 615 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
627 }; 616 };
628 617
629 uart2_bus: uart2-bus { 618 uart2_bus: uart2-bus {
630 samsung,pins = "gpd1-5", "gpd1-4"; 619 samsung,pins = "gpd1-5", "gpd1-4";
631 samsung,pin-function = <2>; 620 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
632 samsung,pin-pud = <0>; 621 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
633 }; 622 };
634 623
635 uart1_bus: uart1-bus { 624 uart1_bus: uart1-bus {
636 samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0"; 625 samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0";
637 samsung,pin-function = <2>; 626 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
638 samsung,pin-pud = <0>; 627 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
639 }; 628 };
640 629
641 hs_i2c3_bus: hs-i2c3-bus { 630 hs_i2c3_bus: hs-i2c3-bus {
642 samsung,pins = "gpd1-3", "gpd1-2"; 631 samsung,pins = "gpd1-3", "gpd1-2";
643 samsung,pin-function = <3>; 632 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
644 samsung,pin-pud = <3>; 633 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
645 samsung,pin-drv = <0>; 634 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
646 }; 635 };
647 636
648 hs_i2c0_bus: hs-i2c0-bus { 637 hs_i2c0_bus: hs-i2c0-bus {
649 samsung,pins = "gpd2-1", "gpd2-0"; 638 samsung,pins = "gpd2-1", "gpd2-0";
650 samsung,pin-function = <2>; 639 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
651 samsung,pin-pud = <3>; 640 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
652 samsung,pin-drv = <0>; 641 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
653 }; 642 };
654 643
655 hs_i2c1_bus: hs-i2c1-bus { 644 hs_i2c1_bus: hs-i2c1-bus {
656 samsung,pins = "gpd2-3", "gpd2-2"; 645 samsung,pins = "gpd2-3", "gpd2-2";
657 samsung,pin-function = <2>; 646 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
658 samsung,pin-pud = <3>; 647 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
659 samsung,pin-drv = <0>; 648 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
660 }; 649 };
661 650
662 pwm0_out: pwm0-out { 651 pwm0_out: pwm0-out {
663 samsung,pins = "gpd2-4"; 652 samsung,pins = "gpd2-4";
664 samsung,pin-function = <2>; 653 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
665 samsung,pin-pud = <0>; 654 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
666 samsung,pin-drv = <0>; 655 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
667 }; 656 };
668 657
669 pwm1_out: pwm1-out { 658 pwm1_out: pwm1-out {
670 samsung,pins = "gpd2-5"; 659 samsung,pins = "gpd2-5";
671 samsung,pin-function = <2>; 660 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
672 samsung,pin-pud = <0>; 661 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
673 samsung,pin-drv = <0>; 662 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
674 }; 663 };
675 664
676 pwm2_out: pwm2-out { 665 pwm2_out: pwm2-out {
677 samsung,pins = "gpd2-6"; 666 samsung,pins = "gpd2-6";
678 samsung,pin-function = <2>; 667 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
679 samsung,pin-pud = <0>; 668 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
680 samsung,pin-drv = <0>; 669 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
681 }; 670 };
682 671
683 pwm3_out: pwm3-out { 672 pwm3_out: pwm3-out {
684 samsung,pins = "gpd2-7"; 673 samsung,pins = "gpd2-7";
685 samsung,pin-function = <2>; 674 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
686 samsung,pin-pud = <0>; 675 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
687 samsung,pin-drv = <0>; 676 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
688 }; 677 };
689 678
690 spi1_bus: spi1-bus { 679 spi1_bus: spi1-bus {
691 samsung,pins = "gpd6-2", "gpd6-4", "gpd6-5"; 680 samsung,pins = "gpd6-2", "gpd6-4", "gpd6-5";
692 samsung,pin-function = <2>; 681 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
693 samsung,pin-pud = <3>; 682 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
694 samsung,pin-drv = <0>; 683 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
695 }; 684 };
696 685
697 hs_i2c7_bus: hs-i2c7-bus { 686 hs_i2c7_bus: hs-i2c7-bus {
698 samsung,pins = "gpd2-7", "gpd2-6"; 687 samsung,pins = "gpd2-7", "gpd2-6";
699 samsung,pin-function = <4>; 688 samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
700 samsung,pin-pud = <3>; 689 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
701 samsung,pin-drv = <0>; 690 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
702 }; 691 };
703 692
704 spi0_bus: spi0-bus { 693 spi0_bus: spi0-bus {
705 samsung,pins = "gpd8-0", "gpd6-0", "gpd6-1"; 694 samsung,pins = "gpd8-0", "gpd6-0", "gpd6-1";
706 samsung,pin-function = <2>; 695 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
707 samsung,pin-pud = <3>; 696 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
708 samsung,pin-drv = <0>; 697 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
709 }; 698 };
710 699
711 hs_i2c10_bus: hs-i2c10-bus { 700 hs_i2c10_bus: hs-i2c10-bus {
712 samsung,pins = "gpg3-1", "gpg3-0"; 701 samsung,pins = "gpg3-1", "gpg3-0";
713 samsung,pin-function = <4>; 702 samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
714 samsung,pin-pud = <3>; 703 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
715 samsung,pin-drv = <0>; 704 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
716 }; 705 };
717 706
718 hs_i2c11_bus: hs-i2c11-bus { 707 hs_i2c11_bus: hs-i2c11-bus {
719 samsung,pins = "gpg3-3", "gpg3-2"; 708 samsung,pins = "gpg3-3", "gpg3-2";
720 samsung,pin-function = <4>; 709 samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
721 samsung,pin-pud = <3>; 710 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
722 samsung,pin-drv = <0>; 711 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
723 }; 712 };
724 713
725 spi3_bus: spi3-bus { 714 spi3_bus: spi3-bus {
726 samsung,pins = "gpg3-4", "gpg3-6", "gpg3-7"; 715 samsung,pins = "gpg3-4", "gpg3-6", "gpg3-7";
727 samsung,pin-function = <3>; 716 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
728 samsung,pin-pud = <3>; 717 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
729 samsung,pin-drv = <0>; 718 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
730 }; 719 };
731 720
732 spi4_bus: spi4-bus { 721 spi4_bus: spi4-bus {
733 samsung,pins = "gpv7-1", "gpv7-3", "gpv7-4"; 722 samsung,pins = "gpv7-1", "gpv7-3", "gpv7-4";
734 samsung,pin-function = <3>; 723 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
735 samsung,pin-pud = <3>; 724 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
736 samsung,pin-drv = <0>; 725 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
737 }; 726 };
738 727
739 fimc_is_uart: fimc-is-uart { 728 fimc_is_uart: fimc-is-uart {
740 samsung,pins = "gpc1-1", "gpc0-7"; 729 samsung,pins = "gpc1-1", "gpc0-7";
741 samsung,pin-function = <3>; 730 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
742 samsung,pin-pud = <0>; 731 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
743 samsung,pin-drv = <0>; 732 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
744 }; 733 };
745 734
746 fimc_is_ch0_i2c: fimc-is-ch0_i2c { 735 fimc_is_ch0_i2c: fimc-is-ch0_i2c {
747 samsung,pins = "gpc2-1", "gpc2-0"; 736 samsung,pins = "gpc2-1", "gpc2-0";
748 samsung,pin-function = <2>; 737 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
749 samsung,pin-pud = <0>; 738 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
750 samsung,pin-drv = <0>; 739 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
751 }; 740 };
752 741
753 fimc_is_ch0_mclk: fimc-is-ch0_mclk { 742 fimc_is_ch0_mclk: fimc-is-ch0_mclk {
754 samsung,pins = "gpd7-0"; 743 samsung,pins = "gpd7-0";
755 samsung,pin-function = <2>; 744 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
756 samsung,pin-pud = <0>; 745 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
757 samsung,pin-drv = <0>; 746 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
758 }; 747 };
759 748
760 fimc_is_ch1_i2c: fimc-is-ch1-i2c { 749 fimc_is_ch1_i2c: fimc-is-ch1-i2c {
761 samsung,pins = "gpc2-3", "gpc2-2"; 750 samsung,pins = "gpc2-3", "gpc2-2";
762 samsung,pin-function = <2>; 751 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
763 samsung,pin-pud = <0>; 752 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
764 samsung,pin-drv = <0>; 753 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
765 }; 754 };
766 755
767 fimc_is_ch1_mclk: fimc-is-ch1-mclk { 756 fimc_is_ch1_mclk: fimc-is-ch1-mclk {
768 samsung,pins = "gpd7-1"; 757 samsung,pins = "gpd7-1";
769 samsung,pin-function = <2>; 758 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
770 samsung,pin-pud = <0>; 759 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
771 samsung,pin-drv = <0>; 760 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
772 }; 761 };
773 762
774 fimc_is_ch2_i2c: fimc-is-ch2-i2c { 763 fimc_is_ch2_i2c: fimc-is-ch2-i2c {
775 samsung,pins = "gpc2-5", "gpc2-4"; 764 samsung,pins = "gpc2-5", "gpc2-4";
776 samsung,pin-function = <2>; 765 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
777 samsung,pin-pud = <0>; 766 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
778 samsung,pin-drv = <0>; 767 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
779 }; 768 };
780 769
781 fimc_is_ch2_mclk: fimc-is-ch2-mclk { 770 fimc_is_ch2_mclk: fimc-is-ch2-mclk {
782 samsung,pins = "gpd7-2"; 771 samsung,pins = "gpd7-2";
783 samsung,pin-function = <2>; 772 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
784 samsung,pin-pud = <0>; 773 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
785 samsung,pin-drv = <0>; 774 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
786 }; 775 };
787}; 776};
788 777
@@ -797,8 +786,8 @@
797 786
798 hs_i2c5_bus: hs-i2c5-bus { 787 hs_i2c5_bus: hs-i2c5-bus {
799 samsung,pins = "gpj1-1", "gpj1-0"; 788 samsung,pins = "gpj1-1", "gpj1-0";
800 samsung,pin-function = <4>; 789 samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
801 samsung,pin-pud = <3>; 790 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
802 samsung,pin-drv = <0>; 791 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
803 }; 792 };
804}; 793};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
new file mode 100644
index 000000000000..098ad557fee3
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -0,0 +1,1191 @@
1/*
2 * SAMSUNG Exynos5433 TM2 board device tree source
3 *
4 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
5 *
6 * Common device tree source file for Samsung's TM2 and TM2E boards
7 * which are based on Samsung Exynos5433 SoC.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14/dts-v1/;
15#include "exynos5433.dtsi"
16#include <dt-bindings/clock/samsung,s2mps11.h>
17#include <dt-bindings/gpio/gpio.h>
18#include <dt-bindings/input/input.h>
19#include <dt-bindings/interrupt-controller/irq.h>
20
21/ {
22 aliases {
23 gsc0 = &gsc_0;
24 gsc1 = &gsc_1;
25 gsc2 = &gsc_2;
26 pinctrl0 = &pinctrl_alive;
27 pinctrl1 = &pinctrl_aud;
28 pinctrl2 = &pinctrl_cpif;
29 pinctrl3 = &pinctrl_ese;
30 pinctrl4 = &pinctrl_finger;
31 pinctrl5 = &pinctrl_fsys;
32 pinctrl6 = &pinctrl_imem;
33 pinctrl7 = &pinctrl_nfc;
34 pinctrl8 = &pinctrl_peric;
35 pinctrl9 = &pinctrl_touch;
36 serial0 = &serial_0;
37 serial1 = &serial_1;
38 serial2 = &serial_2;
39 serial3 = &serial_3;
40 spi0 = &spi_0;
41 spi1 = &spi_1;
42 spi2 = &spi_2;
43 spi3 = &spi_3;
44 spi4 = &spi_4;
45 mshc0 = &mshc_0;
46 mshc2 = &mshc_2;
47 };
48
49 chosen {
50 stdout-path = &serial_1;
51 };
52
53 memory@20000000 {
54 device_type = "memory";
55 reg = <0x0 0x20000000 0x0 0xc0000000>;
56 };
57
58 gpio-keys {
59 compatible = "gpio-keys";
60
61 power-key {
62 gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
63 linux,code = <KEY_POWER>;
64 label = "power key";
65 debounce-interval = <10>;
66 };
67
68 volume-up-key {
69 gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
70 linux,code = <KEY_VOLUMEUP>;
71 label = "volume-up key";
72 debounce-interval = <10>;
73 };
74
75 volume-down-key {
76 gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
77 linux,code = <KEY_VOLUMEDOWN>;
78 label = "volume-down key";
79 debounce-interval = <10>;
80 };
81
82 homepage-key {
83 gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
84 linux,code = <KEY_MENU>;
85 label = "homepage key";
86 debounce-interval = <10>;
87 };
88 };
89
90 i2c_max98504: i2c-gpio-0 {
91 compatible = "i2c-gpio";
92 gpios = <&gpd0 1 GPIO_ACTIVE_HIGH /* SPK_AMP_SDA */
93 &gpd0 0 GPIO_ACTIVE_HIGH /* SPK_AMP_SCL */ >;
94 i2c-gpio,delay-us = <2>;
95 #address-cells = <1>;
96 #size-cells = <0>;
97 status = "okay";
98
99 max98504: max98504@31 {
100 compatible = "maxim,max98504";
101 reg = <0x31>;
102 maxim,rx-path = <1>;
103 maxim,tx-path = <1>;
104 maxim,tx-channel-mask = <3>;
105 maxim,tx-channel-source = <2>;
106 };
107 };
108
109 sound {
110 compatible = "samsung,tm2-audio";
111 audio-codec = <&wm5110>;
112 i2s-controller = <&i2s0>;
113 audio-amplifier = <&max98504>;
114 mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
115 model = "wm5110";
116 samsung,audio-routing =
117 /* Headphone */
118 "HP", "HPOUT1L",
119 "HP", "HPOUT1R",
120
121 /* Speaker */
122 "SPK", "SPKOUT",
123 "SPKOUT", "HPOUT2L",
124 "SPKOUT", "HPOUT2R",
125
126 /* Receiver */
127 "RCV", "HPOUT3L",
128 "RCV", "HPOUT3R";
129 status = "okay";
130 };
131};
132
133&adc {
134 vdd-supply = <&ldo3_reg>;
135 status = "okay";
136
137 thermistor-ap {
138 compatible = "murata,ncp03wf104";
139 pullup-uv = <1800000>;
140 pullup-ohm = <100000>;
141 pulldown-ohm = <0>;
142 io-channels = <&adc 0>;
143 };
144
145 thermistor-battery {
146 compatible = "murata,ncp03wf104";
147 pullup-uv = <1800000>;
148 pullup-ohm = <100000>;
149 pulldown-ohm = <0>;
150 io-channels = <&adc 1>;
151 #thermal-sensor-cells = <0>;
152 };
153
154 thermistor-charger {
155 compatible = "murata,ncp03wf104";
156 pullup-uv = <1800000>;
157 pullup-ohm = <100000>;
158 pulldown-ohm = <0>;
159 io-channels = <&adc 2>;
160 };
161};
162
163&bus_g2d_400 {
164 devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>;
165 vdd-supply = <&buck4_reg>;
166 exynos,saturation-ratio = <10>;
167 status = "okay";
168};
169
170&bus_g2d_266 {
171 devfreq = <&bus_g2d_400>;
172 status = "okay";
173};
174
175&bus_gscl {
176 devfreq = <&bus_g2d_400>;
177 status = "okay";
178};
179
180&bus_hevc {
181 devfreq = <&bus_g2d_400>;
182 status = "okay";
183};
184
185&bus_jpeg {
186 devfreq = <&bus_g2d_400>;
187 status = "okay";
188};
189
190&bus_mfc {
191 devfreq = <&bus_g2d_400>;
192 status = "okay";
193};
194
195&bus_mscl {
196 devfreq = <&bus_g2d_400>;
197 status = "okay";
198};
199
200&bus_noc0 {
201 devfreq = <&bus_g2d_400>;
202 status = "okay";
203};
204
205&bus_noc1 {
206 devfreq = <&bus_g2d_400>;
207 status = "okay";
208};
209
210&bus_noc2 {
211 devfreq = <&bus_g2d_400>;
212 status = "okay";
213};
214
215&cmu_aud {
216 assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>;
217 assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
218};
219
220&cmu_fsys {
221 assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
222 <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
223 <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
224 <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
225 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
226 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
227 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
228 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
229 <&cmu_top CLK_DIV_SCLK_USBDRD30>,
230 <&cmu_top CLK_DIV_SCLK_USBHOST30>;
231 assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
232 <&cmu_top CLK_MOUT_BUS_PLL_USER>,
233 <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
234 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
235 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
236 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
237 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
238 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
239 assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
240 <66700000>, <66700000>;
241};
242
243&cmu_gscl {
244 assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>,
245 <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>;
246 assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
247 <&cmu_top CLK_ACLK_GSCL_333>;
248};
249
250&cmu_mfc {
251 assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>;
252 assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
253};
254
255&cmu_mscl {
256 assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
257 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
258 <&cmu_mscl CLK_MOUT_SCLK_JPEG>,
259 <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
260 assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
261 <&cmu_top CLK_SCLK_JPEG_MSCL>,
262 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
263 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
264};
265
266&cpu0 {
267 cpu-supply = <&buck3_reg>;
268};
269
270&cpu4 {
271 cpu-supply = <&buck2_reg>;
272};
273
274&decon {
275 status = "okay";
276
277 i80-if-timings {
278 };
279};
280
281&decon_tv {
282 status = "okay";
283
284 ports {
285 #address-cells = <1>;
286 #size-cells = <0>;
287
288 port@0 {
289 reg = <0>;
290 tv_to_hdmi: endpoint {
291 remote-endpoint = <&hdmi_to_tv>;
292 };
293 };
294 };
295};
296
297&dsi {
298 status = "okay";
299 vddcore-supply = <&ldo6_reg>;
300 vddio-supply = <&ldo7_reg>;
301 samsung,pll-clock-frequency = <24000000>;
302 pinctrl-names = "default";
303 pinctrl-0 = <&te_irq>;
304
305 ports {
306 #address-cells = <1>;
307 #size-cells = <0>;
308
309 port@1 {
310 reg = <1>;
311
312 dsi_out: endpoint {
313 samsung,burst-clock-frequency = <512000000>;
314 samsung,esc-clock-frequency = <16000000>;
315 };
316 };
317 };
318};
319
320&hdmi {
321 hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>;
322 status = "okay";
323 vdd-supply = <&ldo6_reg>;
324 vdd_osc-supply = <&ldo7_reg>;
325 vdd_pll-supply = <&ldo6_reg>;
326
327 ports {
328 #address-cells = <1>;
329 #size-cells = <0>;
330
331 port@0 {
332 reg = <0>;
333 hdmi_to_tv: endpoint {
334 remote-endpoint = <&tv_to_hdmi>;
335 };
336 };
337
338 port@1 {
339 reg = <1>;
340 hdmi_to_mhl: endpoint {
341 remote-endpoint = <&mhl_to_hdmi>;
342 };
343 };
344 };
345};
346
347&hsi2c_0 {
348 status = "okay";
349 clock-frequency = <2500000>;
350
351 s2mps13-pmic@66 {
352 compatible = "samsung,s2mps13-pmic";
353 interrupt-parent = <&gpa0>;
354 interrupts = <7 IRQ_TYPE_NONE>;
355 reg = <0x66>;
356 samsung,s2mps11-wrstbi-ground;
357
358 s2mps13_osc: clocks {
359 compatible = "samsung,s2mps13-clk";
360 #clock-cells = <1>;
361 clock-output-names = "s2mps13_ap", "s2mps13_cp",
362 "s2mps13_bt";
363 };
364
365 regulators {
366 ldo1_reg: LDO1 {
367 regulator-name = "VDD_ALIVE_0.9V_AP";
368 regulator-min-microvolt = <900000>;
369 regulator-max-microvolt = <900000>;
370 regulator-always-on;
371 };
372
373 ldo2_reg: LDO2 {
374 regulator-name = "VDDQ_MMC2_2.8V_AP";
375 regulator-min-microvolt = <2800000>;
376 regulator-max-microvolt = <2800000>;
377 regulator-always-on;
378 regulator-state-mem {
379 regulator-off-in-suspend;
380 };
381 };
382
383 ldo3_reg: LDO3 {
384 regulator-name = "VDD1_E_1.8V_AP";
385 regulator-min-microvolt = <1800000>;
386 regulator-max-microvolt = <1800000>;
387 regulator-always-on;
388 };
389
390 ldo4_reg: LDO4 {
391 regulator-name = "VDD10_MIF_PLL_1.0V_AP";
392 regulator-min-microvolt = <1300000>;
393 regulator-max-microvolt = <1300000>;
394 regulator-always-on;
395 regulator-state-mem {
396 regulator-off-in-suspend;
397 };
398 };
399
400 ldo5_reg: LDO5 {
401 regulator-name = "VDD10_DPLL_1.0V_AP";
402 regulator-min-microvolt = <1000000>;
403 regulator-max-microvolt = <1000000>;
404 regulator-always-on;
405 regulator-state-mem {
406 regulator-off-in-suspend;
407 };
408 };
409
410 ldo6_reg: LDO6 {
411 regulator-name = "VDD10_MIPI2L_1.0V_AP";
412 regulator-min-microvolt = <1000000>;
413 regulator-max-microvolt = <1000000>;
414 regulator-state-mem {
415 regulator-off-in-suspend;
416 };
417 };
418
419 ldo7_reg: LDO7 {
420 regulator-name = "VDD18_MIPI2L_1.8V_AP";
421 regulator-min-microvolt = <1800000>;
422 regulator-max-microvolt = <1800000>;
423 regulator-always-on;
424 regulator-state-mem {
425 regulator-off-in-suspend;
426 };
427 };
428
429 ldo8_reg: LDO8 {
430 regulator-name = "VDD18_LLI_1.8V_AP";
431 regulator-min-microvolt = <1800000>;
432 regulator-max-microvolt = <1800000>;
433 regulator-always-on;
434 regulator-state-mem {
435 regulator-off-in-suspend;
436 };
437 };
438
439 ldo9_reg: LDO9 {
440 regulator-name = "VDD18_ABB_ETC_1.8V_AP";
441 regulator-min-microvolt = <1800000>;
442 regulator-max-microvolt = <1800000>;
443 regulator-always-on;
444 regulator-state-mem {
445 regulator-off-in-suspend;
446 };
447 };
448
449 ldo10_reg: LDO10 {
450 regulator-name = "VDD33_USB30_3.0V_AP";
451 regulator-min-microvolt = <3000000>;
452 regulator-max-microvolt = <3000000>;
453 regulator-state-mem {
454 regulator-off-in-suspend;
455 };
456 };
457
458 ldo11_reg: LDO11 {
459 regulator-name = "VDD_INT_M_1.0V_AP";
460 regulator-min-microvolt = <1000000>;
461 regulator-max-microvolt = <1000000>;
462 regulator-always-on;
463 regulator-state-mem {
464 regulator-off-in-suspend;
465 };
466 };
467
468 ldo12_reg: LDO12 {
469 regulator-name = "VDD_KFC_M_1.1V_AP";
470 regulator-min-microvolt = <800000>;
471 regulator-max-microvolt = <1350000>;
472 regulator-always-on;
473 };
474
475 ldo13_reg: LDO13 {
476 regulator-name = "VDD_G3D_M_0.95V_AP";
477 regulator-min-microvolt = <950000>;
478 regulator-max-microvolt = <950000>;
479 regulator-always-on;
480 regulator-state-mem {
481 regulator-off-in-suspend;
482 };
483 };
484
485 ldo14_reg: LDO14 {
486 regulator-name = "VDDQ_M1_LDO_1.2V_AP";
487 regulator-min-microvolt = <1200000>;
488 regulator-max-microvolt = <1200000>;
489 regulator-always-on;
490 regulator-state-mem {
491 regulator-off-in-suspend;
492 };
493 };
494
495 ldo15_reg: LDO15 {
496 regulator-name = "VDDQ_M2_LDO_1.2V_AP";
497 regulator-min-microvolt = <1200000>;
498 regulator-max-microvolt = <1200000>;
499 regulator-always-on;
500 regulator-state-mem {
501 regulator-off-in-suspend;
502 };
503 };
504
505 ldo16_reg: LDO16 {
506 regulator-name = "VDDQ_EFUSE";
507 regulator-min-microvolt = <1400000>;
508 regulator-max-microvolt = <3400000>;
509 regulator-always-on;
510 };
511
512 ldo17_reg: LDO17 {
513 regulator-name = "V_TFLASH_2.8V_AP";
514 regulator-min-microvolt = <2800000>;
515 regulator-max-microvolt = <2800000>;
516 };
517
518 ldo18_reg: LDO18 {
519 regulator-name = "V_CODEC_1.8V_AP";
520 regulator-min-microvolt = <1800000>;
521 regulator-max-microvolt = <1800000>;
522 };
523
524 ldo19_reg: LDO19 {
525 regulator-name = "VDDA_1.8V_COMP";
526 regulator-min-microvolt = <1800000>;
527 regulator-max-microvolt = <1800000>;
528 regulator-always-on;
529 };
530
531 ldo20_reg: LDO20 {
532 regulator-name = "VCC_2.8V_AP";
533 regulator-min-microvolt = <2800000>;
534 regulator-max-microvolt = <2800000>;
535 regulator-always-on;
536 };
537
538 ldo21_reg: LDO21 {
539 regulator-name = "VT_CAM_1.8V";
540 regulator-min-microvolt = <1800000>;
541 regulator-max-microvolt = <1800000>;
542 };
543
544 ldo22_reg: LDO22 {
545 regulator-name = "CAM_IO_1.8V_AP";
546 regulator-min-microvolt = <1800000>;
547 regulator-max-microvolt = <1800000>;
548 };
549
550 ldo23_reg: LDO23 {
551 regulator-name = "CAM_SEN_CORE_1.05V_AP";
552 regulator-min-microvolt = <1050000>;
553 regulator-max-microvolt = <1050000>;
554 };
555
556 ldo24_reg: LDO24 {
557 regulator-name = "VT_CAM_1.2V";
558 regulator-min-microvolt = <1200000>;
559 regulator-max-microvolt = <1200000>;
560 };
561
562 ldo25_reg: LDO25 {
563 regulator-name = "UNUSED_LDO25";
564 regulator-min-microvolt = <2800000>;
565 regulator-max-microvolt = <2800000>;
566 };
567
568 ldo26_reg: LDO26 {
569 regulator-name = "CAM_AF_2.8V_AP";
570 regulator-min-microvolt = <2800000>;
571 regulator-max-microvolt = <2800000>;
572 };
573
574 ldo27_reg: LDO27 {
575 regulator-name = "VCC_3.0V_LCD_AP";
576 regulator-min-microvolt = <3000000>;
577 regulator-max-microvolt = <3000000>;
578 };
579
580 ldo28_reg: LDO28 {
581 regulator-name = "VCC_1.8V_LCD_AP";
582 regulator-min-microvolt = <1800000>;
583 regulator-max-microvolt = <1800000>;
584 };
585
586 ldo29_reg: LDO29 {
587 regulator-name = "VT_CAM_2.8V";
588 regulator-min-microvolt = <3000000>;
589 regulator-max-microvolt = <3000000>;
590 };
591
592 ldo30_reg: LDO30 {
593 regulator-name = "TSP_AVDD_3.3V_AP";
594 regulator-min-microvolt = <3300000>;
595 regulator-max-microvolt = <3300000>;
596 };
597
598 ldo31_reg: LDO31 {
599 /*
600 * LDO31 differs from target to target,
601 * its definition is in the .dts
602 */
603 };
604
605 ldo32_reg: LDO32 {
606 regulator-name = "VTOUCH_1.8V_AP";
607 regulator-min-microvolt = <1800000>;
608 regulator-max-microvolt = <1800000>;
609 };
610
611 ldo33_reg: LDO33 {
612 regulator-name = "VTOUCH_LED_3.3V";
613 regulator-min-microvolt = <2500000>;
614 regulator-max-microvolt = <3300000>;
615 regulator-ramp-delay = <12500>;
616 };
617
618 ldo34_reg: LDO34 {
619 regulator-name = "VCC_1.8V_MHL_AP";
620 regulator-min-microvolt = <1000000>;
621 regulator-max-microvolt = <2100000>;
622 };
623
624 ldo35_reg: LDO35 {
625 regulator-name = "OIS_VM_2.8V";
626 regulator-min-microvolt = <1800000>;
627 regulator-max-microvolt = <2800000>;
628 };
629
630 ldo36_reg: LDO36 {
631 regulator-name = "VSIL_1.0V";
632 regulator-min-microvolt = <1000000>;
633 regulator-max-microvolt = <1000000>;
634 };
635
636 ldo37_reg: LDO37 {
637 regulator-name = "VF_1.8V";
638 regulator-min-microvolt = <1800000>;
639 regulator-max-microvolt = <1800000>;
640 };
641
642 ldo38_reg: LDO38 {
643 /*
644 * LDO38 differs from target to target,
645 * its definition is in the .dts
646 */
647 };
648
649 ldo39_reg: LDO39 {
650 regulator-name = "V_HRM_1.8V";
651 regulator-min-microvolt = <1800000>;
652 regulator-max-microvolt = <1800000>;
653 };
654
655 ldo40_reg: LDO40 {
656 regulator-name = "V_HRM_3.3V";
657 regulator-min-microvolt = <3300000>;
658 regulator-max-microvolt = <3300000>;
659 };
660
661 buck1_reg: BUCK1 {
662 regulator-name = "VDD_MIF_0.9V_AP";
663 regulator-min-microvolt = <600000>;
664 regulator-max-microvolt = <1500000>;
665 regulator-always-on;
666 regulator-state-mem {
667 regulator-off-in-suspend;
668 };
669 };
670
671 buck2_reg: BUCK2 {
672 regulator-name = "VDD_EGL_1.0V_AP";
673 regulator-min-microvolt = <900000>;
674 regulator-max-microvolt = <1300000>;
675 regulator-always-on;
676 regulator-state-mem {
677 regulator-off-in-suspend;
678 };
679 };
680
681 buck3_reg: BUCK3 {
682 regulator-name = "VDD_KFC_1.0V_AP";
683 regulator-min-microvolt = <800000>;
684 regulator-max-microvolt = <1200000>;
685 regulator-always-on;
686 regulator-state-mem {
687 regulator-off-in-suspend;
688 };
689 };
690
691 buck4_reg: BUCK4 {
692 regulator-name = "VDD_INT_0.95V_AP";
693 regulator-min-microvolt = <600000>;
694 regulator-max-microvolt = <1500000>;
695 regulator-always-on;
696 regulator-state-mem {
697 regulator-off-in-suspend;
698 };
699 };
700
701 buck5_reg: BUCK5 {
702 regulator-name = "VDD_DISP_CAM0_0.9V_AP";
703 regulator-min-microvolt = <600000>;
704 regulator-max-microvolt = <1500000>;
705 regulator-always-on;
706 regulator-state-mem {
707 regulator-off-in-suspend;
708 };
709 };
710
711 buck6_reg: BUCK6 {
712 regulator-name = "VDD_G3D_0.9V_AP";
713 regulator-min-microvolt = <600000>;
714 regulator-max-microvolt = <1500000>;
715 regulator-always-on;
716 regulator-state-mem {
717 regulator-off-in-suspend;
718 };
719 };
720
721 buck7_reg: BUCK7 {
722 regulator-name = "VDD_MEM1_1.2V_AP";
723 regulator-min-microvolt = <1200000>;
724 regulator-max-microvolt = <1200000>;
725 regulator-always-on;
726 };
727
728 buck8_reg: BUCK8 {
729 regulator-name = "VDD_LLDO_1.35V_AP";
730 regulator-min-microvolt = <1350000>;
731 regulator-max-microvolt = <3300000>;
732 regulator-always-on;
733 };
734
735 buck9_reg: BUCK9 {
736 regulator-name = "VDD_MLDO_2.0V_AP";
737 regulator-min-microvolt = <1350000>;
738 regulator-max-microvolt = <3300000>;
739 regulator-always-on;
740 };
741
742 buck10_reg: BUCK10 {
743 regulator-name = "vdd_mem2";
744 regulator-min-microvolt = <550000>;
745 regulator-max-microvolt = <1500000>;
746 regulator-always-on;
747 };
748 };
749 };
750};
751
752&hsi2c_7 {
753 status = "okay";
754
755 sii8620@39 {
756 reg = <0x39>;
757 compatible = "sil,sii8620";
758 cvcc10-supply = <&ldo36_reg>;
759 iovcc18-supply = <&ldo34_reg>;
760 interrupt-parent = <&gpf0>;
761 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
762 reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>;
763 clocks = <&pmu_system_controller 0>;
764 clock-names = "xtal";
765
766 port {
767 mhl_to_hdmi: endpoint {
768 remote-endpoint = <&hdmi_to_mhl>;
769 };
770 };
771 };
772};
773
774&hsi2c_8 {
775 status = "okay";
776
777 max77843@66 {
778 compatible = "maxim,max77843";
779 interrupt-parent = <&gpa1>;
780 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
781 reg = <0x66>;
782
783 muic: max77843-muic {
784 compatible = "maxim,max77843-muic";
785 };
786
787 regulators {
788 compatible = "maxim,max77843-regulator";
789 safeout1_reg: SAFEOUT1 {
790 regulator-name = "SAFEOUT1";
791 regulator-min-microvolt = <3300000>;
792 regulator-max-microvolt = <4950000>;
793 };
794
795 safeout2_reg: SAFEOUT2 {
796 regulator-name = "SAFEOUT2";
797 regulator-min-microvolt = <3300000>;
798 regulator-max-microvolt = <4950000>;
799 };
800
801 charger_reg: CHARGER {
802 regulator-name = "CHARGER";
803 regulator-min-microamp = <100000>;
804 regulator-max-microamp = <3150000>;
805 };
806 };
807
808 haptic: max77843-haptic {
809 compatible = "maxim,max77843-haptic";
810 haptic-supply = <&ldo38_reg>;
811 pwms = <&pwm 0 33670 0>;
812 pwm-names = "haptic";
813 };
814 };
815};
816
817&hsi2c_11 {
818 status = "okay";
819};
820
821&i2s0 {
822 status = "okay";
823};
824
825&mshc_0 {
826 status = "okay";
827 num-slots = <1>;
828 mmc-hs200-1_8v;
829 mmc-hs400-1_8v;
830 cap-mmc-highspeed;
831 non-removable;
832 card-detect-delay = <200>;
833 samsung,dw-mshc-ciu-div = <3>;
834 samsung,dw-mshc-sdr-timing = <0 4>;
835 samsung,dw-mshc-ddr-timing = <0 2>;
836 samsung,dw-mshc-hs400-timing = <0 3>;
837 samsung,read-strobe-delay = <90>;
838 fifo-depth = <0x80>;
839 pinctrl-names = "default";
840 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
841 &sd0_bus8 &sd0_rdqs>;
842 bus-width = <8>;
843 assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
844 assigned-clock-rates = <800000000>;
845};
846
847&mshc_2 {
848 status = "okay";
849 num-slots = <1>;
850 cap-sd-highspeed;
851 disable-wp;
852 cd-gpios = <&gpa2 4 GPIO_ACTIVE_HIGH>;
853 cd-inverted;
854 card-detect-delay = <200>;
855 samsung,dw-mshc-ciu-div = <3>;
856 samsung,dw-mshc-sdr-timing = <0 4>;
857 samsung,dw-mshc-ddr-timing = <0 2>;
858 fifo-depth = <0x80>;
859 pinctrl-names = "default";
860 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
861 bus-width = <4>;
862};
863
864&ppmu_d0_general {
865 status = "okay";
866 events {
867 ppmu_event0_d0_general: ppmu-event0-d0-general {
868 event-name = "ppmu-event0-d0-general";
869 };
870 };
871};
872
873&ppmu_d1_general {
874 status = "okay";
875 events {
876 ppmu_event0_d1_general: ppmu-event0-d1-general {
877 event-name = "ppmu-event0-d1-general";
878 };
879 };
880};
881
882&pinctrl_alive {
883 pinctrl-names = "default";
884 pinctrl-0 = <&initial_alive>;
885
886 initial_alive: initial-state {
887 PIN(INPUT, gpa0-0, DOWN, FAST_SR1);
888 PIN(INPUT, gpa0-1, NONE, FAST_SR1);
889 PIN(INPUT, gpa0-2, DOWN, FAST_SR1);
890 PIN(INPUT, gpa0-3, NONE, FAST_SR1);
891 PIN(INPUT, gpa0-4, NONE, FAST_SR1);
892 PIN(INPUT, gpa0-5, DOWN, FAST_SR1);
893 PIN(INPUT, gpa0-6, NONE, FAST_SR1);
894 PIN(INPUT, gpa0-7, NONE, FAST_SR1);
895
896 PIN(INPUT, gpa1-0, UP, FAST_SR1);
897 PIN(INPUT, gpa1-1, NONE, FAST_SR1);
898 PIN(INPUT, gpa1-2, NONE, FAST_SR1);
899 PIN(INPUT, gpa1-3, DOWN, FAST_SR1);
900 PIN(INPUT, gpa1-4, DOWN, FAST_SR1);
901 PIN(INPUT, gpa1-5, NONE, FAST_SR1);
902 PIN(INPUT, gpa1-6, NONE, FAST_SR1);
903 PIN(INPUT, gpa1-7, NONE, FAST_SR1);
904
905 PIN(INPUT, gpa2-0, NONE, FAST_SR1);
906 PIN(INPUT, gpa2-1, NONE, FAST_SR1);
907 PIN(INPUT, gpa2-2, NONE, FAST_SR1);
908 PIN(INPUT, gpa2-3, DOWN, FAST_SR1);
909 PIN(INPUT, gpa2-4, NONE, FAST_SR1);
910 PIN(INPUT, gpa2-5, DOWN, FAST_SR1);
911 PIN(INPUT, gpa2-6, DOWN, FAST_SR1);
912 PIN(INPUT, gpa2-7, NONE, FAST_SR1);
913
914 PIN(INPUT, gpa3-0, DOWN, FAST_SR1);
915 PIN(INPUT, gpa3-1, DOWN, FAST_SR1);
916 PIN(INPUT, gpa3-2, NONE, FAST_SR1);
917 PIN(INPUT, gpa3-3, DOWN, FAST_SR1);
918 PIN(INPUT, gpa3-4, NONE, FAST_SR1);
919 PIN(INPUT, gpa3-5, DOWN, FAST_SR1);
920 PIN(INPUT, gpa3-6, DOWN, FAST_SR1);
921 PIN(INPUT, gpa3-7, DOWN, FAST_SR1);
922
923 PIN(INPUT, gpf1-0, NONE, FAST_SR1);
924 PIN(INPUT, gpf1-1, NONE, FAST_SR1);
925 PIN(INPUT, gpf1-2, DOWN, FAST_SR1);
926 PIN(INPUT, gpf1-4, UP, FAST_SR1);
927 PIN(OUTPUT, gpf1-5, NONE, FAST_SR1);
928 PIN(INPUT, gpf1-6, DOWN, FAST_SR1);
929 PIN(INPUT, gpf1-7, DOWN, FAST_SR1);
930
931 PIN(INPUT, gpf2-0, DOWN, FAST_SR1);
932 PIN(INPUT, gpf2-1, DOWN, FAST_SR1);
933 PIN(INPUT, gpf2-2, DOWN, FAST_SR1);
934 PIN(INPUT, gpf2-3, DOWN, FAST_SR1);
935
936 PIN(INPUT, gpf3-0, DOWN, FAST_SR1);
937 PIN(INPUT, gpf3-1, DOWN, FAST_SR1);
938 PIN(INPUT, gpf3-2, NONE, FAST_SR1);
939 PIN(INPUT, gpf3-3, DOWN, FAST_SR1);
940
941 PIN(INPUT, gpf4-0, DOWN, FAST_SR1);
942 PIN(INPUT, gpf4-1, DOWN, FAST_SR1);
943 PIN(INPUT, gpf4-2, DOWN, FAST_SR1);
944 PIN(INPUT, gpf4-3, DOWN, FAST_SR1);
945 PIN(INPUT, gpf4-4, DOWN, FAST_SR1);
946 PIN(INPUT, gpf4-5, DOWN, FAST_SR1);
947 PIN(INPUT, gpf4-6, DOWN, FAST_SR1);
948 PIN(INPUT, gpf4-7, DOWN, FAST_SR1);
949
950 PIN(INPUT, gpf5-0, DOWN, FAST_SR1);
951 PIN(INPUT, gpf5-1, DOWN, FAST_SR1);
952 PIN(INPUT, gpf5-2, DOWN, FAST_SR1);
953 PIN(INPUT, gpf5-3, DOWN, FAST_SR1);
954 PIN(OUTPUT, gpf5-4, NONE, FAST_SR1);
955 PIN(INPUT, gpf5-5, DOWN, FAST_SR1);
956 PIN(INPUT, gpf5-6, DOWN, FAST_SR1);
957 PIN(INPUT, gpf5-7, DOWN, FAST_SR1);
958 };
959
960 te_irq: te_irq {
961 samsung,pins = "gpf1-3";
962 samsung,pin-function = <0xf>;
963 };
964};
965
966&pinctrl_cpif {
967 pinctrl-names = "default";
968 pinctrl-0 = <&initial_cpif>;
969
970 initial_cpif: initial-state {
971 PIN(INPUT, gpv6-0, DOWN, FAST_SR1);
972 PIN(INPUT, gpv6-1, DOWN, FAST_SR1);
973 };
974};
975
976&pinctrl_ese {
977 pinctrl-names = "default";
978 pinctrl-0 = <&initial_ese>;
979
980 initial_ese: initial-state {
981 PIN(INPUT, gpj2-0, DOWN, FAST_SR1);
982 PIN(INPUT, gpj2-1, DOWN, FAST_SR1);
983 PIN(INPUT, gpj2-2, DOWN, FAST_SR1);
984 };
985};
986
987&pinctrl_fsys {
988 pinctrl-names = "default";
989 pinctrl-0 = <&initial_fsys>;
990
991 initial_fsys: initial-state {
992 PIN(INPUT, gpr3-0, NONE, FAST_SR1);
993 PIN(INPUT, gpr3-1, DOWN, FAST_SR1);
994 PIN(INPUT, gpr3-2, DOWN, FAST_SR1);
995 PIN(INPUT, gpr3-3, DOWN, FAST_SR1);
996 PIN(INPUT, gpr3-7, NONE, FAST_SR1);
997 };
998};
999
1000&pinctrl_imem {
1001 pinctrl-names = "default";
1002 pinctrl-0 = <&initial_imem>;
1003
1004 initial_imem: initial-state {
1005 PIN(INPUT, gpf0-0, UP, FAST_SR1);
1006 PIN(INPUT, gpf0-1, UP, FAST_SR1);
1007 PIN(INPUT, gpf0-2, DOWN, FAST_SR1);
1008 PIN(INPUT, gpf0-3, UP, FAST_SR1);
1009 PIN(INPUT, gpf0-4, DOWN, FAST_SR1);
1010 PIN(INPUT, gpf0-5, NONE, FAST_SR1);
1011 PIN(INPUT, gpf0-6, DOWN, FAST_SR1);
1012 PIN(INPUT, gpf0-7, UP, FAST_SR1);
1013 };
1014};
1015
1016&pinctrl_nfc {
1017 pinctrl-names = "default";
1018 pinctrl-0 = <&initial_nfc>;
1019
1020 initial_nfc: initial-state {
1021 PIN(INPUT, gpj0-2, DOWN, FAST_SR1);
1022 };
1023};
1024
1025&pinctrl_peric {
1026 pinctrl-names = "default";
1027 pinctrl-0 = <&initial_peric>;
1028
1029 initial_peric: initial-state {
1030 PIN(INPUT, gpv7-0, DOWN, FAST_SR1);
1031 PIN(INPUT, gpv7-1, DOWN, FAST_SR1);
1032 PIN(INPUT, gpv7-2, NONE, FAST_SR1);
1033 PIN(INPUT, gpv7-3, DOWN, FAST_SR1);
1034 PIN(INPUT, gpv7-4, DOWN, FAST_SR1);
1035 PIN(INPUT, gpv7-5, DOWN, FAST_SR1);
1036
1037 PIN(INPUT, gpb0-4, DOWN, FAST_SR1);
1038
1039 PIN(INPUT, gpc0-2, DOWN, FAST_SR1);
1040 PIN(INPUT, gpc0-5, DOWN, FAST_SR1);
1041 PIN(INPUT, gpc0-7, DOWN, FAST_SR1);
1042
1043 PIN(INPUT, gpc1-1, DOWN, FAST_SR1);
1044
1045 PIN(INPUT, gpc3-4, NONE, FAST_SR1);
1046 PIN(INPUT, gpc3-5, NONE, FAST_SR1);
1047 PIN(INPUT, gpc3-6, NONE, FAST_SR1);
1048 PIN(INPUT, gpc3-7, NONE, FAST_SR1);
1049
1050 PIN(OUTPUT, gpg0-0, NONE, FAST_SR1);
1051 PIN(2, gpg0-1, DOWN, FAST_SR1);
1052
1053 PIN(INPUT, gpd2-5, DOWN, FAST_SR1);
1054
1055 PIN(INPUT, gpd4-0, NONE, FAST_SR1);
1056 PIN(INPUT, gpd4-1, DOWN, FAST_SR1);
1057 PIN(INPUT, gpd4-2, DOWN, FAST_SR1);
1058 PIN(INPUT, gpd4-3, DOWN, FAST_SR1);
1059 PIN(INPUT, gpd4-4, DOWN, FAST_SR1);
1060
1061 PIN(INPUT, gpd6-3, DOWN, FAST_SR1);
1062
1063 PIN(INPUT, gpd8-1, UP, FAST_SR1);
1064
1065 PIN(INPUT, gpg1-0, DOWN, FAST_SR1);
1066 PIN(INPUT, gpg1-1, DOWN, FAST_SR1);
1067 PIN(INPUT, gpg1-2, DOWN, FAST_SR1);
1068 PIN(INPUT, gpg1-3, DOWN, FAST_SR1);
1069 PIN(INPUT, gpg1-4, DOWN, FAST_SR1);
1070
1071 PIN(INPUT, gpg2-0, DOWN, FAST_SR1);
1072 PIN(INPUT, gpg2-1, DOWN, FAST_SR1);
1073
1074 PIN(INPUT, gpg3-0, DOWN, FAST_SR1);
1075 PIN(INPUT, gpg3-1, DOWN, FAST_SR1);
1076 PIN(INPUT, gpg3-5, DOWN, FAST_SR1);
1077 PIN(INPUT, gpg3-7, DOWN, FAST_SR1);
1078 };
1079};
1080
1081&pinctrl_touch {
1082 pinctrl-names = "default";
1083 pinctrl-0 = <&initial_touch>;
1084
1085 initial_touch: initial-state {
1086 PIN(INPUT, gpj1-2, DOWN, FAST_SR1);
1087 };
1088};
1089
1090&pwm {
1091 pinctrl-0 = <&pwm0_out>;
1092 pinctrl-names = "default";
1093 status = "okay";
1094};
1095
1096&mic {
1097 status = "okay";
1098
1099 i80-if-timings {
1100 };
1101};
1102
1103&pmu_system_controller {
1104 assigned-clocks = <&pmu_system_controller 0>;
1105 assigned-clock-parents = <&xxti>;
1106};
1107
1108&serial_1 {
1109 status = "okay";
1110};
1111
1112&spi_1 {
1113 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
1114 status = "okay";
1115
1116 wm5110: wm5110-codec@0 {
1117 compatible = "wlf,wm5110";
1118 reg = <0x0>;
1119 spi-max-frequency = <20000000>;
1120 interrupt-parent = <&gpa0>;
1121 interrupts = <4 IRQ_TYPE_NONE>;
1122 clocks = <&pmu_system_controller 0>,
1123 <&s2mps13_osc S2MPS11_CLK_BT>;
1124 clock-names = "mclk1", "mclk2";
1125
1126 gpio-controller;
1127 #gpio-cells = <2>;
1128
1129 wlf,micd-detect-debounce = <300>;
1130 wlf,micd-bias-start-time = <0x1>;
1131 wlf,micd-rate = <0x7>;
1132 wlf,micd-dbtime = <0x1>;
1133 wlf,micd-force-micbias;
1134 wlf,micd-configs = <0x0 1 0>;
1135 wlf,hpdet-channel = <1>;
1136 wlf,gpsw = <0x1>;
1137 wlf,inmode = <2 0 2 0>;
1138
1139 wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
1140 wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
1141
1142 /* core supplies */
1143 AVDD-supply = <&ldo18_reg>;
1144 DBVDD1-supply = <&ldo18_reg>;
1145 CPVDD-supply = <&ldo18_reg>;
1146 DBVDD2-supply = <&ldo18_reg>;
1147 DBVDD3-supply = <&ldo18_reg>;
1148
1149 controller-data {
1150 samsung,spi-feedback-delay = <0>;
1151 };
1152 };
1153};
1154
1155&timer {
1156 clock-frequency = <24000000>;
1157};
1158
1159&tmu_atlas0 {
1160 vtmu-supply = <&ldo3_reg>;
1161 status = "okay";
1162};
1163
1164&tmu_apollo {
1165 vtmu-supply = <&ldo3_reg>;
1166 status = "okay";
1167};
1168
1169&tmu_g3d {
1170 vtmu-supply = <&ldo3_reg>;
1171 status = "okay";
1172};
1173
1174&usbdrd30 {
1175 vdd33-supply = <&ldo10_reg>;
1176 vdd10-supply = <&ldo6_reg>;
1177 status = "okay";
1178};
1179
1180&usbdrd_dwc3_0 {
1181 dr_mode = "otg";
1182};
1183
1184&usbdrd30_phy {
1185 vbus-supply = <&safeout1_reg>;
1186 status = "okay";
1187};
1188
1189&xxti {
1190 clock-frequency = <24000000>;
1191};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
index f21bdc2ff834..dea0a6f5bc18 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -11,1039 +11,68 @@
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13 13
14/dts-v1/; 14#include "exynos5433-tm2-common.dtsi"
15#include "exynos5433.dtsi"
16#include <dt-bindings/clock/samsung,s2mps11.h>
17#include <dt-bindings/gpio/gpio.h>
18#include <dt-bindings/input/input.h>
19#include <dt-bindings/interrupt-controller/irq.h>
20 15
21/ { 16/ {
22 model = "Samsung TM2 board"; 17 model = "Samsung TM2 board";
23 compatible = "samsung,tm2", "samsung,exynos5433"; 18 compatible = "samsung,tm2", "samsung,exynos5433";
24
25 aliases {
26 gsc0 = &gsc_0;
27 gsc1 = &gsc_1;
28 gsc2 = &gsc_2;
29 pinctrl0 = &pinctrl_alive;
30 pinctrl1 = &pinctrl_aud;
31 pinctrl2 = &pinctrl_cpif;
32 pinctrl3 = &pinctrl_ese;
33 pinctrl4 = &pinctrl_finger;
34 pinctrl5 = &pinctrl_fsys;
35 pinctrl6 = &pinctrl_imem;
36 pinctrl7 = &pinctrl_nfc;
37 pinctrl8 = &pinctrl_peric;
38 pinctrl9 = &pinctrl_touch;
39 serial0 = &serial_0;
40 serial1 = &serial_1;
41 serial2 = &serial_2;
42 serial3 = &serial_3;
43 spi0 = &spi_0;
44 spi1 = &spi_1;
45 spi2 = &spi_2;
46 spi3 = &spi_3;
47 spi4 = &spi_4;
48 mshc0 = &mshc_0;
49 mshc2 = &mshc_2;
50 };
51
52 chosen {
53 stdout-path = &serial_1;
54 };
55
56 memory@20000000 {
57 device_type = "memory";
58 reg = <0x0 0x20000000 0x0 0xc0000000>;
59 };
60
61 gpio-keys {
62 compatible = "gpio-keys";
63
64 power-key {
65 gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
66 linux,code = <KEY_POWER>;
67 label = "power key";
68 debounce-interval = <10>;
69 };
70
71 volume-up-key {
72 gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
73 linux,code = <KEY_VOLUMEUP>;
74 label = "volume-up key";
75 debounce-interval = <10>;
76 };
77
78 volume-down-key {
79 gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
80 linux,code = <KEY_VOLUMEDOWN>;
81 label = "volume-down key";
82 debounce-interval = <10>;
83 };
84
85 homepage-key {
86 gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
87 linux,code = <KEY_MENU>;
88 label = "homepage key";
89 debounce-interval = <10>;
90 };
91 };
92
93 i2c_max98504: i2c-gpio-0 {
94 compatible = "i2c-gpio";
95 gpios = <&gpd0 1 GPIO_ACTIVE_HIGH /* SPK_AMP_SDA */
96 &gpd0 0 GPIO_ACTIVE_HIGH /* SPK_AMP_SCL */ >;
97 i2c-gpio,delay-us = <2>;
98 #address-cells = <1>;
99 #size-cells = <0>;
100 status = "okay";
101
102 max98504: max98504@31 {
103 compatible = "maxim,max98504";
104 reg = <0x31>;
105 maxim,rx-path = <1>;
106 maxim,tx-path = <1>;
107 maxim,tx-channel-mask = <3>;
108 maxim,tx-channel-source = <2>;
109 };
110 };
111
112 sound {
113 compatible = "samsung,tm2-audio";
114 audio-codec = <&wm5110>;
115 i2s-controller = <&i2s0>;
116 audio-amplifier = <&max98504>;
117 mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
118 model = "wm5110";
119 samsung,audio-routing =
120 /* Headphone */
121 "HP", "HPOUT1L",
122 "HP", "HPOUT1R",
123
124 /* Speaker */
125 "SPK", "SPKOUT",
126 "SPKOUT", "HPOUT2L",
127 "SPKOUT", "HPOUT2R",
128
129 /* Receiver */
130 "RCV", "HPOUT3L",
131 "RCV", "HPOUT3R";
132 status = "okay";
133 };
134};
135
136&adc {
137 vdd-supply = <&ldo3_reg>;
138 status = "okay";
139
140 thermistor-ap {
141 compatible = "murata,ncp03wf104";
142 pullup-uv = <1800000>;
143 pullup-ohm = <100000>;
144 pulldown-ohm = <0>;
145 io-channels = <&adc 0>;
146 };
147
148 thermistor-battery {
149 compatible = "murata,ncp03wf104";
150 pullup-uv = <1800000>;
151 pullup-ohm = <100000>;
152 pulldown-ohm = <0>;
153 io-channels = <&adc 1>;
154 #thermal-sensor-cells = <0>;
155 };
156
157 thermistor-charger {
158 compatible = "murata,ncp03wf104";
159 pullup-uv = <1800000>;
160 pullup-ohm = <100000>;
161 pulldown-ohm = <0>;
162 io-channels = <&adc 2>;
163 };
164};
165
166&cmu_aud {
167 assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>;
168 assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
169};
170
171&cmu_fsys {
172 assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
173 <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
174 <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
175 <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
176 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
177 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
178 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
179 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
180 <&cmu_top CLK_DIV_SCLK_USBDRD30>,
181 <&cmu_top CLK_DIV_SCLK_USBHOST30>;
182 assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
183 <&cmu_top CLK_MOUT_BUS_PLL_USER>,
184 <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
185 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
186 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
187 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
188 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
189 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
190 assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
191 <66700000>, <66700000>;
192};
193
194&cmu_gscl {
195 assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>,
196 <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>;
197 assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
198 <&cmu_top CLK_ACLK_GSCL_333>;
199};
200
201&cmu_mfc {
202 assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>;
203 assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
204};
205
206&cmu_mscl {
207 assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
208 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
209 <&cmu_mscl CLK_MOUT_SCLK_JPEG>,
210 <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
211 assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
212 <&cmu_top CLK_SCLK_JPEG_MSCL>,
213 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
214 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
215};
216
217&cpu0 {
218 cpu-supply = <&buck3_reg>;
219};
220
221&cpu4 {
222 cpu-supply = <&buck2_reg>;
223};
224
225&decon {
226 status = "okay";
227
228 i80-if-timings {
229 };
230};
231
232&dsi {
233 status = "okay";
234 vddcore-supply = <&ldo6_reg>;
235 vddio-supply = <&ldo7_reg>;
236 samsung,pll-clock-frequency = <24000000>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&te_irq>;
239
240 ports {
241 #address-cells = <1>;
242 #size-cells = <0>;
243
244 port@1 {
245 reg = <1>;
246
247 dsi_out: endpoint {
248 samsung,burst-clock-frequency = <512000000>;
249 samsung,esc-clock-frequency = <16000000>;
250 };
251 };
252 };
253};
254
255&hsi2c_0 {
256 status = "okay";
257 clock-frequency = <2500000>;
258
259 s2mps13-pmic@66 {
260 compatible = "samsung,s2mps13-pmic";
261 interrupt-parent = <&gpa0>;
262 interrupts = <7 IRQ_TYPE_NONE>;
263 reg = <0x66>;
264 samsung,s2mps11-wrstbi-ground;
265
266 s2mps13_osc: clocks {
267 compatible = "samsung,s2mps13-clk";
268 #clock-cells = <1>;
269 clock-output-names = "s2mps13_ap", "s2mps13_cp",
270 "s2mps13_bt";
271 };
272
273 regulators {
274 ldo1_reg: LDO1 {
275 regulator-name = "VDD_ALIVE_0.9V_AP";
276 regulator-min-microvolt = <900000>;
277 regulator-max-microvolt = <900000>;
278 regulator-always-on;
279 };
280
281 ldo2_reg: LDO2 {
282 regulator-name = "VDDQ_MMC2_2.8V_AP";
283 regulator-min-microvolt = <2800000>;
284 regulator-max-microvolt = <2800000>;
285 regulator-always-on;
286 regulator-state-mem {
287 regulator-off-in-suspend;
288 };
289 };
290
291 ldo3_reg: LDO3 {
292 regulator-name = "VDD1_E_1.8V_AP";
293 regulator-min-microvolt = <1800000>;
294 regulator-max-microvolt = <1800000>;
295 regulator-always-on;
296 };
297
298 ldo4_reg: LDO4 {
299 regulator-name = "VDD10_MIF_PLL_1.0V_AP";
300 regulator-min-microvolt = <1300000>;
301 regulator-max-microvolt = <1300000>;
302 regulator-always-on;
303 regulator-state-mem {
304 regulator-off-in-suspend;
305 };
306 };
307
308 ldo5_reg: LDO5 {
309 regulator-name = "VDD10_DPLL_1.0V_AP";
310 regulator-min-microvolt = <1000000>;
311 regulator-max-microvolt = <1000000>;
312 regulator-always-on;
313 regulator-state-mem {
314 regulator-off-in-suspend;
315 };
316 };
317
318 ldo6_reg: LDO6 {
319 regulator-name = "VDD10_MIPI2L_1.0V_AP";
320 regulator-min-microvolt = <1000000>;
321 regulator-max-microvolt = <1000000>;
322 regulator-state-mem {
323 regulator-off-in-suspend;
324 };
325 };
326
327 ldo7_reg: LDO7 {
328 regulator-name = "VDD18_MIPI2L_1.8V_AP";
329 regulator-min-microvolt = <1800000>;
330 regulator-max-microvolt = <1800000>;
331 };
332
333 ldo8_reg: LDO8 {
334 regulator-name = "VDD18_LLI_1.8V_AP";
335 regulator-min-microvolt = <1800000>;
336 regulator-max-microvolt = <1800000>;
337 regulator-always-on;
338 regulator-state-mem {
339 regulator-off-in-suspend;
340 };
341 };
342
343 ldo9_reg: LDO9 {
344 regulator-name = "VDD18_ABB_ETC_1.8V_AP";
345 regulator-min-microvolt = <1800000>;
346 regulator-max-microvolt = <1800000>;
347 regulator-always-on;
348 regulator-state-mem {
349 regulator-off-in-suspend;
350 };
351 };
352
353 ldo10_reg: LDO10 {
354 regulator-name = "VDD33_USB30_3.0V_AP";
355 regulator-min-microvolt = <3000000>;
356 regulator-max-microvolt = <3000000>;
357 regulator-state-mem {
358 regulator-off-in-suspend;
359 };
360 };
361
362 ldo11_reg: LDO11 {
363 regulator-name = "VDD_INT_M_1.0V_AP";
364 regulator-min-microvolt = <1000000>;
365 regulator-max-microvolt = <1000000>;
366 regulator-always-on;
367 regulator-state-mem {
368 regulator-off-in-suspend;
369 };
370 };
371
372 ldo12_reg: LDO12 {
373 regulator-name = "VDD_KFC_M_1.1V_AP";
374 regulator-min-microvolt = <800000>;
375 regulator-max-microvolt = <1350000>;
376 regulator-always-on;
377 };
378
379 ldo13_reg: LDO13 {
380 regulator-name = "VDD_G3D_M_0.95V_AP";
381 regulator-min-microvolt = <950000>;
382 regulator-max-microvolt = <950000>;
383 regulator-always-on;
384 regulator-state-mem {
385 regulator-off-in-suspend;
386 };
387 };
388
389 ldo14_reg: LDO14 {
390 regulator-name = "VDDQ_M1_LDO_1.2V_AP";
391 regulator-min-microvolt = <1200000>;
392 regulator-max-microvolt = <1200000>;
393 regulator-always-on;
394 regulator-state-mem {
395 regulator-off-in-suspend;
396 };
397 };
398
399 ldo15_reg: LDO15 {
400 regulator-name = "VDDQ_M2_LDO_1.2V_AP";
401 regulator-min-microvolt = <1200000>;
402 regulator-max-microvolt = <1200000>;
403 regulator-always-on;
404 regulator-state-mem {
405 regulator-off-in-suspend;
406 };
407 };
408
409 ldo16_reg: LDO16 {
410 regulator-name = "VDDQ_EFUSE";
411 regulator-min-microvolt = <1400000>;
412 regulator-max-microvolt = <3400000>;
413 regulator-always-on;
414 };
415
416 ldo17_reg: LDO17 {
417 regulator-name = "V_TFLASH_2.8V_AP";
418 regulator-min-microvolt = <2800000>;
419 regulator-max-microvolt = <2800000>;
420 };
421
422 ldo18_reg: LDO18 {
423 regulator-name = "V_CODEC_1.8V_AP";
424 regulator-min-microvolt = <1800000>;
425 regulator-max-microvolt = <1800000>;
426 };
427
428 ldo19_reg: LDO19 {
429 regulator-name = "VDDA_1.8V_COMP";
430 regulator-min-microvolt = <1800000>;
431 regulator-max-microvolt = <1800000>;
432 regulator-always-on;
433 };
434
435 ldo20_reg: LDO20 {
436 regulator-name = "VCC_2.8V_AP";
437 regulator-min-microvolt = <2800000>;
438 regulator-max-microvolt = <2800000>;
439 regulator-always-on;
440 };
441
442 ldo21_reg: LDO21 {
443 regulator-name = "VT_CAM_1.8V";
444 regulator-min-microvolt = <1800000>;
445 regulator-max-microvolt = <1800000>;
446 };
447
448 ldo22_reg: LDO22 {
449 regulator-name = "CAM_IO_1.8V_AP";
450 regulator-min-microvolt = <1800000>;
451 regulator-max-microvolt = <1800000>;
452 };
453
454 ldo23_reg: LDO23 {
455 regulator-name = "CAM_SEN_CORE_1.2V_AP";
456 regulator-min-microvolt = <1050000>;
457 regulator-max-microvolt = <1200000>;
458 };
459
460 ldo24_reg: LDO24 {
461 regulator-name = "VT_CAM_1.2V";
462 regulator-min-microvolt = <1200000>;
463 regulator-max-microvolt = <1200000>;
464 };
465
466 ldo25_reg: LDO25 {
467 regulator-name = "CAM_SEN_A2.8V_AP";
468 regulator-min-microvolt = <2800000>;
469 regulator-max-microvolt = <2800000>;
470 };
471
472 ldo26_reg: LDO26 {
473 regulator-name = "CAM_AF_2.8V_AP";
474 regulator-min-microvolt = <2800000>;
475 regulator-max-microvolt = <2800000>;
476 };
477
478 ldo27_reg: LDO27 {
479 regulator-name = "VCC_3.0V_LCD_AP";
480 regulator-min-microvolt = <3000000>;
481 regulator-max-microvolt = <3000000>;
482 };
483
484 ldo28_reg: LDO28 {
485 regulator-name = "VCC_1.8V_LCD_AP";
486 regulator-min-microvolt = <1800000>;
487 regulator-max-microvolt = <1800000>;
488 };
489
490 ldo29_reg: LDO29 {
491 regulator-name = "VT_CAM_2.8V";
492 regulator-min-microvolt = <3000000>;
493 regulator-max-microvolt = <3000000>;
494 };
495
496 ldo30_reg: LDO30 {
497 regulator-name = "TSP_AVDD_3.3V_AP";
498 regulator-min-microvolt = <3300000>;
499 regulator-max-microvolt = <3300000>;
500 };
501
502 ldo31_reg: LDO31 {
503 regulator-name = "TSP_VDD_1.85V_AP";
504 regulator-min-microvolt = <1850000>;
505 regulator-max-microvolt = <1850000>;
506 };
507
508 ldo32_reg: LDO32 {
509 regulator-name = "VTOUCH_1.8V_AP";
510 regulator-min-microvolt = <1800000>;
511 regulator-max-microvolt = <1800000>;
512 };
513
514 ldo33_reg: LDO33 {
515 regulator-name = "VTOUCH_LED_3.3V";
516 regulator-min-microvolt = <2500000>;
517 regulator-max-microvolt = <3300000>;
518 regulator-ramp-delay = <12500>;
519 };
520
521 ldo34_reg: LDO34 {
522 regulator-name = "VCC_1.8V_MHL_AP";
523 regulator-min-microvolt = <1000000>;
524 regulator-max-microvolt = <2100000>;
525 };
526
527 ldo35_reg: LDO35 {
528 regulator-name = "OIS_VM_2.8V";
529 regulator-min-microvolt = <1800000>;
530 regulator-max-microvolt = <2800000>;
531 };
532
533 ldo36_reg: LDO36 {
534 regulator-name = "VSIL_1.0V";
535 regulator-min-microvolt = <1000000>;
536 regulator-max-microvolt = <1000000>;
537 };
538
539 ldo37_reg: LDO37 {
540 regulator-name = "VF_1.8V";
541 regulator-min-microvolt = <1800000>;
542 regulator-max-microvolt = <1800000>;
543 };
544
545 ldo38_reg: LDO38 {
546 regulator-name = "VCC_3.0V_MOTOR_AP";
547 regulator-min-microvolt = <3000000>;
548 regulator-max-microvolt = <3000000>;
549 };
550
551 ldo39_reg: LDO39 {
552 regulator-name = "V_HRM_1.8V";
553 regulator-min-microvolt = <1800000>;
554 regulator-max-microvolt = <1800000>;
555 };
556
557 ldo40_reg: LDO40 {
558 regulator-name = "V_HRM_3.3V";
559 regulator-min-microvolt = <3300000>;
560 regulator-max-microvolt = <3300000>;
561 };
562
563 buck1_reg: BUCK1 {
564 regulator-name = "VDD_MIF_0.9V_AP";
565 regulator-min-microvolt = <600000>;
566 regulator-max-microvolt = <1500000>;
567 regulator-always-on;
568 regulator-state-mem {
569 regulator-off-in-suspend;
570 };
571 };
572
573 buck2_reg: BUCK2 {
574 regulator-name = "VDD_EGL_1.0V_AP";
575 regulator-min-microvolt = <900000>;
576 regulator-max-microvolt = <1300000>;
577 regulator-always-on;
578 regulator-state-mem {
579 regulator-off-in-suspend;
580 };
581 };
582
583 buck3_reg: BUCK3 {
584 regulator-name = "VDD_KFC_1.0V_AP";
585 regulator-min-microvolt = <800000>;
586 regulator-max-microvolt = <1200000>;
587 regulator-always-on;
588 regulator-state-mem {
589 regulator-off-in-suspend;
590 };
591 };
592
593 buck4_reg: BUCK4 {
594 regulator-name = "VDD_INT_0.95V_AP";
595 regulator-min-microvolt = <600000>;
596 regulator-max-microvolt = <1500000>;
597 regulator-always-on;
598 regulator-state-mem {
599 regulator-off-in-suspend;
600 };
601 };
602
603 buck5_reg: BUCK5 {
604 regulator-name = "VDD_DISP_CAM0_0.9V_AP";
605 regulator-min-microvolt = <600000>;
606 regulator-max-microvolt = <1500000>;
607 regulator-always-on;
608 regulator-state-mem {
609 regulator-off-in-suspend;
610 };
611 };
612
613 buck6_reg: BUCK6 {
614 regulator-name = "VDD_G3D_0.9V_AP";
615 regulator-min-microvolt = <600000>;
616 regulator-max-microvolt = <1500000>;
617 regulator-always-on;
618 regulator-state-mem {
619 regulator-off-in-suspend;
620 };
621 };
622
623 buck7_reg: BUCK7 {
624 regulator-name = "VDD_MEM1_1.2V_AP";
625 regulator-min-microvolt = <1200000>;
626 regulator-max-microvolt = <1200000>;
627 regulator-always-on;
628 };
629
630 buck8_reg: BUCK8 {
631 regulator-name = "VDD_LLDO_1.35V_AP";
632 regulator-min-microvolt = <1350000>;
633 regulator-max-microvolt = <3300000>;
634 regulator-always-on;
635 };
636
637 buck9_reg: BUCK9 {
638 regulator-name = "VDD_MLDO_2.0V_AP";
639 regulator-min-microvolt = <1350000>;
640 regulator-max-microvolt = <3300000>;
641 regulator-always-on;
642 };
643
644 buck10_reg: BUCK10 {
645 regulator-name = "vdd_mem2";
646 regulator-min-microvolt = <550000>;
647 regulator-max-microvolt = <1500000>;
648 regulator-always-on;
649 };
650 };
651 };
652};
653
654&hsi2c_8 {
655 status = "okay";
656
657 max77843@66 {
658 compatible = "maxim,max77843";
659 interrupt-parent = <&gpa1>;
660 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
661 reg = <0x66>;
662
663 muic: max77843-muic {
664 compatible = "maxim,max77843-muic";
665 };
666
667 regulators {
668 compatible = "maxim,max77843-regulator";
669 safeout1_reg: SAFEOUT1 {
670 regulator-name = "SAFEOUT1";
671 regulator-min-microvolt = <3300000>;
672 regulator-max-microvolt = <4950000>;
673 };
674
675 safeout2_reg: SAFEOUT2 {
676 regulator-name = "SAFEOUT2";
677 regulator-min-microvolt = <3300000>;
678 regulator-max-microvolt = <4950000>;
679 };
680
681 charger_reg: CHARGER {
682 regulator-name = "CHARGER";
683 regulator-min-microamp = <100000>;
684 regulator-max-microamp = <3150000>;
685 };
686 };
687
688 haptic: max77843-haptic {
689 compatible = "maxim,max77843-haptic";
690 haptic-supply = <&ldo38_reg>;
691 pwms = <&pwm 0 33670 0>;
692 pwm-names = "haptic";
693 };
694 };
695};
696
697&i2s0 {
698 status = "okay";
699};
700
701&mshc_0 {
702 status = "okay";
703 num-slots = <1>;
704 mmc-hs200-1_8v;
705 mmc-hs400-1_8v;
706 cap-mmc-highspeed;
707 non-removable;
708 card-detect-delay = <200>;
709 samsung,dw-mshc-ciu-div = <3>;
710 samsung,dw-mshc-sdr-timing = <0 4>;
711 samsung,dw-mshc-ddr-timing = <0 2>;
712 samsung,dw-mshc-hs400-timing = <0 3>;
713 samsung,read-strobe-delay = <90>;
714 fifo-depth = <0x80>;
715 pinctrl-names = "default";
716 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
717 &sd0_bus8 &sd0_rdqs>;
718 bus-width = <8>;
719 assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
720 assigned-clock-rates = <800000000>;
721};
722
723&mshc_2 {
724 status = "okay";
725 num-slots = <1>;
726 cap-sd-highspeed;
727 disable-wp;
728 cd-gpios = <&gpa2 4 GPIO_ACTIVE_HIGH>;
729 cd-inverted;
730 card-detect-delay = <200>;
731 samsung,dw-mshc-ciu-div = <3>;
732 samsung,dw-mshc-sdr-timing = <0 4>;
733 samsung,dw-mshc-ddr-timing = <0 2>;
734 fifo-depth = <0x80>;
735 pinctrl-names = "default";
736 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
737 bus-width = <4>;
738};
739
740&pinctrl_alive {
741 pinctrl-names = "default";
742 pinctrl-0 = <&initial_alive>;
743
744 initial_alive: initial-state {
745 PIN(IN, gpa0-0, DOWN, LV1);
746 PIN(IN, gpa0-1, NONE, LV1);
747 PIN(IN, gpa0-2, DOWN, LV1);
748 PIN(IN, gpa0-3, NONE, LV1);
749 PIN(IN, gpa0-4, NONE, LV1);
750 PIN(IN, gpa0-5, DOWN, LV1);
751 PIN(IN, gpa0-6, NONE, LV1);
752 PIN(IN, gpa0-7, NONE, LV1);
753
754 PIN(IN, gpa1-0, UP, LV1);
755 PIN(IN, gpa1-1, NONE, LV1);
756 PIN(IN, gpa1-2, NONE, LV1);
757 PIN(IN, gpa1-3, DOWN, LV1);
758 PIN(IN, gpa1-4, DOWN, LV1);
759 PIN(IN, gpa1-5, NONE, LV1);
760 PIN(IN, gpa1-6, NONE, LV1);
761 PIN(IN, gpa1-7, NONE, LV1);
762
763 PIN(IN, gpa2-0, NONE, LV1);
764 PIN(IN, gpa2-1, NONE, LV1);
765 PIN(IN, gpa2-2, NONE, LV1);
766 PIN(IN, gpa2-3, DOWN, LV1);
767 PIN(IN, gpa2-4, NONE, LV1);
768 PIN(IN, gpa2-5, DOWN, LV1);
769 PIN(IN, gpa2-6, DOWN, LV1);
770 PIN(IN, gpa2-7, NONE, LV1);
771
772 PIN(IN, gpa3-0, DOWN, LV1);
773 PIN(IN, gpa3-1, DOWN, LV1);
774 PIN(IN, gpa3-2, NONE, LV1);
775 PIN(IN, gpa3-3, DOWN, LV1);
776 PIN(IN, gpa3-4, NONE, LV1);
777 PIN(IN, gpa3-5, DOWN, LV1);
778 PIN(IN, gpa3-6, DOWN, LV1);
779 PIN(IN, gpa3-7, DOWN, LV1);
780
781 PIN(IN, gpf1-0, NONE, LV1);
782 PIN(IN, gpf1-1, NONE, LV1);
783 PIN(IN, gpf1-2, DOWN, LV1);
784 PIN(IN, gpf1-4, UP, LV1);
785 PIN(OUT, gpf1-5, NONE, LV1);
786 PIN(IN, gpf1-6, DOWN, LV1);
787 PIN(IN, gpf1-7, DOWN, LV1);
788
789 PIN(IN, gpf2-0, DOWN, LV1);
790 PIN(IN, gpf2-1, DOWN, LV1);
791 PIN(IN, gpf2-2, DOWN, LV1);
792 PIN(IN, gpf2-3, DOWN, LV1);
793
794 PIN(IN, gpf3-0, DOWN, LV1);
795 PIN(IN, gpf3-1, DOWN, LV1);
796 PIN(IN, gpf3-2, NONE, LV1);
797 PIN(IN, gpf3-3, DOWN, LV1);
798
799 PIN(IN, gpf4-0, DOWN, LV1);
800 PIN(IN, gpf4-1, DOWN, LV1);
801 PIN(IN, gpf4-2, DOWN, LV1);
802 PIN(IN, gpf4-3, DOWN, LV1);
803 PIN(IN, gpf4-4, DOWN, LV1);
804 PIN(IN, gpf4-5, DOWN, LV1);
805 PIN(IN, gpf4-6, DOWN, LV1);
806 PIN(IN, gpf4-7, DOWN, LV1);
807
808 PIN(IN, gpf5-0, DOWN, LV1);
809 PIN(IN, gpf5-1, DOWN, LV1);
810 PIN(IN, gpf5-2, DOWN, LV1);
811 PIN(IN, gpf5-3, DOWN, LV1);
812 PIN(OUT, gpf5-4, NONE, LV1);
813 PIN(IN, gpf5-5, DOWN, LV1);
814 PIN(IN, gpf5-6, DOWN, LV1);
815 PIN(IN, gpf5-7, DOWN, LV1);
816 };
817
818 te_irq: te_irq {
819 samsung,pins = "gpf1-3";
820 samsung,pin-function = <0xf>;
821 };
822};
823
824&pinctrl_cpif {
825 pinctrl-names = "default";
826 pinctrl-0 = <&initial_cpif>;
827
828 initial_cpif: initial-state {
829 PIN(IN, gpv6-0, DOWN, LV1);
830 PIN(IN, gpv6-1, DOWN, LV1);
831 };
832};
833
834&pinctrl_ese {
835 pinctrl-names = "default";
836 pinctrl-0 = <&initial_ese>;
837
838 initial_ese: initial-state {
839 PIN(IN, gpj2-0, DOWN, LV1);
840 PIN(IN, gpj2-1, DOWN, LV1);
841 PIN(IN, gpj2-2, DOWN, LV1);
842 };
843};
844
845&pinctrl_fsys {
846 pinctrl-names = "default";
847 pinctrl-0 = <&initial_fsys>;
848
849 initial_fsys: initial-state {
850 PIN(IN, gpr3-0, NONE, LV1);
851 PIN(IN, gpr3-1, DOWN, LV1);
852 PIN(IN, gpr3-2, DOWN, LV1);
853 PIN(IN, gpr3-3, DOWN, LV1);
854 PIN(IN, gpr3-7, NONE, LV1);
855 };
856};
857
858&pinctrl_imem {
859 pinctrl-names = "default";
860 pinctrl-0 = <&initial_imem>;
861
862 initial_imem: initial-state {
863 PIN(IN, gpf0-0, UP, LV1);
864 PIN(IN, gpf0-1, UP, LV1);
865 PIN(IN, gpf0-2, DOWN, LV1);
866 PIN(IN, gpf0-3, UP, LV1);
867 PIN(IN, gpf0-4, DOWN, LV1);
868 PIN(IN, gpf0-5, NONE, LV1);
869 PIN(IN, gpf0-6, DOWN, LV1);
870 PIN(IN, gpf0-7, UP, LV1);
871 };
872};
873
874&pinctrl_nfc {
875 pinctrl-names = "default";
876 pinctrl-0 = <&initial_nfc>;
877
878 initial_nfc: initial-state {
879 PIN(IN, gpj0-2, DOWN, LV1);
880 };
881};
882
883&pinctrl_peric {
884 pinctrl-names = "default";
885 pinctrl-0 = <&initial_peric>;
886
887 initial_peric: initial-state {
888 PIN(IN, gpv7-0, DOWN, LV1);
889 PIN(IN, gpv7-1, DOWN, LV1);
890 PIN(IN, gpv7-2, NONE, LV1);
891 PIN(IN, gpv7-3, DOWN, LV1);
892 PIN(IN, gpv7-4, DOWN, LV1);
893 PIN(IN, gpv7-5, DOWN, LV1);
894
895 PIN(IN, gpb0-4, DOWN, LV1);
896
897 PIN(IN, gpc0-2, DOWN, LV1);
898 PIN(IN, gpc0-5, DOWN, LV1);
899 PIN(IN, gpc0-7, DOWN, LV1);
900
901 PIN(IN, gpc1-1, DOWN, LV1);
902
903 PIN(IN, gpc3-4, NONE, LV1);
904 PIN(IN, gpc3-5, NONE, LV1);
905 PIN(IN, gpc3-6, NONE, LV1);
906 PIN(IN, gpc3-7, NONE, LV1);
907
908 PIN(OUT, gpg0-0, NONE, LV1);
909 PIN(FUNC1, gpg0-1, DOWN, LV1);
910
911 PIN(IN, gpd2-5, DOWN, LV1);
912
913 PIN(IN, gpd4-0, NONE, LV1);
914 PIN(IN, gpd4-1, DOWN, LV1);
915 PIN(IN, gpd4-2, DOWN, LV1);
916 PIN(IN, gpd4-3, DOWN, LV1);
917 PIN(IN, gpd4-4, DOWN, LV1);
918
919 PIN(IN, gpd6-3, DOWN, LV1);
920
921 PIN(IN, gpd8-1, UP, LV1);
922
923 PIN(IN, gpg1-0, DOWN, LV1);
924 PIN(IN, gpg1-1, DOWN, LV1);
925 PIN(IN, gpg1-2, DOWN, LV1);
926 PIN(IN, gpg1-3, DOWN, LV1);
927 PIN(IN, gpg1-4, DOWN, LV1);
928
929 PIN(IN, gpg2-0, DOWN, LV1);
930 PIN(IN, gpg2-1, DOWN, LV1);
931
932 PIN(IN, gpg3-0, DOWN, LV1);
933 PIN(IN, gpg3-1, DOWN, LV1);
934 PIN(IN, gpg3-5, DOWN, LV1);
935 PIN(IN, gpg3-7, DOWN, LV1);
936 };
937};
938
939&pinctrl_touch {
940 pinctrl-names = "default";
941 pinctrl-0 = <&initial_touch>;
942
943 initial_touch: initial-state {
944 PIN(IN, gpj1-2, DOWN, LV1);
945 };
946};
947
948&pwm {
949 pinctrl-0 = <&pwm0_out>;
950 pinctrl-names = "default";
951 status = "okay";
952};
953
954&mic {
955 status = "okay";
956
957 i80-if-timings {
958 };
959};
960
961&pmu_system_controller {
962 assigned-clocks = <&pmu_system_controller 0>;
963 assigned-clock-parents = <&xxti>;
964};
965
966&serial_1 {
967 status = "okay";
968};
969
970&spi_1 {
971 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
972 status = "okay";
973
974 wm5110: wm5110-codec@0 {
975 compatible = "wlf,wm5110";
976 reg = <0x0>;
977 spi-max-frequency = <20000000>;
978 interrupt-parent = <&gpa0>;
979 interrupts = <4 IRQ_TYPE_NONE>;
980 clocks = <&pmu_system_controller 0>,
981 <&s2mps13_osc S2MPS11_CLK_BT>;
982 clock-names = "mclk1", "mclk2";
983
984 gpio-controller;
985 #gpio-cells = <2>;
986
987 wlf,micd-detect-debounce = <300>;
988 wlf,micd-bias-start-time = <0x1>;
989 wlf,micd-rate = <0x7>;
990 wlf,micd-dbtime = <0x1>;
991 wlf,micd-force-micbias;
992 wlf,micd-configs = <0x0 1 0>;
993 wlf,hpdet-channel = <1>;
994 wlf,gpsw = <0x1>;
995 wlf,inmode = <2 0 2 0>;
996
997 wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
998 wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
999
1000 /* core supplies */
1001 AVDD-supply = <&ldo18_reg>;
1002 DBVDD1-supply = <&ldo18_reg>;
1003 CPVDD-supply = <&ldo18_reg>;
1004 DBVDD2-supply = <&ldo18_reg>;
1005 DBVDD3-supply = <&ldo18_reg>;
1006
1007 controller-data {
1008 samsung,spi-feedback-delay = <0>;
1009 };
1010 };
1011};
1012
1013&timer {
1014 clock-frequency = <24000000>;
1015};
1016
1017&tmu_atlas0 {
1018 vtmu-supply = <&ldo3_reg>;
1019 status = "okay";
1020};
1021
1022&tmu_apollo {
1023 vtmu-supply = <&ldo3_reg>;
1024 status = "okay";
1025};
1026
1027&tmu_g3d {
1028 vtmu-supply = <&ldo3_reg>;
1029 status = "okay";
1030};
1031
1032&usbdrd30 {
1033 vdd33-supply = <&ldo10_reg>;
1034 vdd10-supply = <&ldo6_reg>;
1035 status = "okay";
1036};
1037
1038&usbdrd_dwc3_0 {
1039 dr_mode = "otg";
1040};
1041
1042&usbdrd30_phy {
1043 vbus-supply = <&safeout1_reg>;
1044 status = "okay";
1045}; 19};
1046 20
1047&xxti { 21&cmu_disp {
1048 clock-frequency = <24000000>; 22 /*
23 * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned
24 * clocks properties for DISP CMU for each board to keep them together
25 * for easier review and maintenance.
26 */
27 assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
28 <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
29 <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
30 <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
31 <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
32 <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
33 <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
34 <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
35 <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
36 <&cmu_disp CLK_MOUT_DISP_PLL>,
37 <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
38 <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
39 <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
40 assigned-clock-parents = <0>, <0>,
41 <&cmu_mif CLK_ACLK_DISP_333>,
42 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
43 <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
44 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
45 <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
46 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
47 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
48 <&cmu_disp CLK_FOUT_DISP_PLL>,
49 <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
50 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
51 <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
52 assigned-clock-rates = <250000000>, <400000000>;
53};
54
55&hsi2c_9 {
56 status = "okay";
57
58 touchkey@20 {
59 compatible = "cypress,tm2-touchkey";
60 reg = <0x20>;
61 interrupt-parent = <&gpa3>;
62 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
63 vcc-supply = <&ldo32_reg>;
64 vdd-supply = <&ldo33_reg>;
65 };
66};
67
68&ldo31_reg {
69 regulator-name = "TSP_VDD_1.85V_AP";
70 regulator-min-microvolt = <1850000>;
71 regulator-max-microvolt = <1850000>;
72};
73
74&ldo38_reg {
75 regulator-name = "VCC_3.0V_MOTOR_AP";
76 regulator-min-microvolt = <3000000>;
77 regulator-max-microvolt = <3000000>;
1049}; 78};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
index 1db4e7f363a9..7891a31adc17 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
@@ -11,21 +11,45 @@
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13 13
14#include "exynos5433-tm2.dts" 14#include "exynos5433-tm2-common.dtsi"
15 15
16/ { 16/ {
17 model = "Samsung TM2E board"; 17 model = "Samsung TM2E board";
18 compatible = "samsung,tm2e", "samsung,exynos5433"; 18 compatible = "samsung,tm2e", "samsung,exynos5433";
19}; 19};
20 20
21&ldo23_reg { 21&cmu_disp {
22 regulator-name = "CAM_SEN_CORE_1.025V_AP"; 22 /*
23 regulator-max-microvolt = <1050000>; 23 * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned
24}; 24 * clocks properties for DISP CMU for each board to keep them together
25 25 * for easier review and maintenance.
26&ldo25_reg { 26 */
27 regulator-name = "UNUSED_LDO25"; 27 assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
28 regulator-always-off; 28 <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
29 <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
30 <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
31 <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
32 <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
33 <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
34 <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
35 <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
36 <&cmu_disp CLK_MOUT_DISP_PLL>,
37 <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
38 <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
39 <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
40 assigned-clock-parents = <0>, <0>,
41 <&cmu_mif CLK_ACLK_DISP_333>,
42 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
43 <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
44 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
45 <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
46 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
47 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
48 <&cmu_disp CLK_FOUT_DISP_PLL>,
49 <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
50 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
51 <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
52 assigned-clock-rates = <278000000>, <400000000>;
29}; 53};
30 54
31&ldo31_reg { 55&ldo31_reg {
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 64226d5ae471..7b02fd6e33e1 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -299,7 +299,7 @@
299 #clock-cells = <1>; 299 #clock-cells = <1>;
300 }; 300 };
301 301
302 cmu_peris: clock-controller@0x10040000 { 302 cmu_peris: clock-controller@10040000 {
303 compatible = "samsung,exynos5433-cmu-peris"; 303 compatible = "samsung,exynos5433-cmu-peris";
304 reg = <0x10040000 0x1000>; 304 reg = <0x10040000 0x1000>;
305 #clock-cells = <1>; 305 #clock-cells = <1>;
@@ -599,6 +599,30 @@
599 clock-names = "fin_pll", "mct"; 599 clock-names = "fin_pll", "mct";
600 }; 600 };
601 601
602 ppmu_d0_cpu: ppmu@10480000 {
603 compatible = "samsung,exynos-ppmu-v2";
604 reg = <0x10480000 0x2000>;
605 status = "disabled";
606 };
607
608 ppmu_d0_general: ppmu@10490000 {
609 compatible = "samsung,exynos-ppmu-v2";
610 reg = <0x10490000 0x2000>;
611 status = "disabled";
612 };
613
614 ppmu_d1_cpu: ppmu@104b0000 {
615 compatible = "samsung,exynos-ppmu-v2";
616 reg = <0x104b0000 0x2000>;
617 status = "disabled";
618 };
619
620 ppmu_d1_general: ppmu@104c0000 {
621 compatible = "samsung,exynos-ppmu-v2";
622 reg = <0x104c0000 0x2000>;
623 status = "disabled";
624 };
625
602 pinctrl_alive: pinctrl@10580000 { 626 pinctrl_alive: pinctrl@10580000 {
603 compatible = "samsung,exynos5433-pinctrl"; 627 compatible = "samsung,exynos5433-pinctrl";
604 reg = <0x10580000 0x1a20>, <0x11090000 0x100>; 628 reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
@@ -682,7 +706,7 @@
682 interrupts = <GIC_PPI 9 0xf04>; 706 interrupts = <GIC_PPI 9 0xf04>;
683 }; 707 };
684 708
685 mipi_phy: video-phy@105c0710 { 709 mipi_phy: video-phy {
686 compatible = "samsung,exynos5433-mipi-video-phy"; 710 compatible = "samsung,exynos5433-mipi-video-phy";
687 #phy-cells = <1>; 711 #phy-cells = <1>;
688 samsung,pmu-syscon = <&pmu_system_controller>; 712 samsung,pmu-syscon = <&pmu_system_controller>;
@@ -727,6 +751,29 @@
727 }; 751 };
728 }; 752 };
729 753
754 decon_tv: decon@13880000 {
755 compatible = "samsung,exynos5433-decon-tv";
756 reg = <0x13880000 0x20b8>;
757 clocks = <&cmu_disp CLK_PCLK_DECON_TV>,
758 <&cmu_disp CLK_ACLK_DECON_TV>,
759 <&cmu_disp CLK_ACLK_SMMU_TV0X>,
760 <&cmu_disp CLK_ACLK_XIU_TV0X>,
761 <&cmu_disp CLK_PCLK_SMMU_TV0X>,
762 <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
763 <&cmu_disp CLK_SCLK_DECON_TV_ECLK>;
764 clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
765 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
766 "sclk_decon_vclk", "sclk_decon_eclk";
767 samsung,disp-sysreg = <&syscon_disp>;
768 interrupt-names = "fifo", "vsync", "lcd_sys";
769 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
772 status = "disabled";
773 iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>;
774 iommu-names = "m0", "m1";
775 };
776
730 dsi: dsi@13900000 { 777 dsi: dsi@13900000 {
731 compatible = "samsung,exynos5433-mipi-dsi"; 778 compatible = "samsung,exynos5433-mipi-dsi";
732 reg = <0x13900000 0xC0>; 779 reg = <0x13900000 0xC0>;
@@ -790,6 +837,35 @@
790 }; 837 };
791 }; 838 };
792 839
840 hdmi: hdmi@13970000 {
841 compatible = "samsung,exynos5433-hdmi";
842 reg = <0x13970000 0x70000>;
843 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&cmu_disp CLK_PCLK_HDMI>,
845 <&cmu_disp CLK_PCLK_HDMIPHY>,
846 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
847 <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
848 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
849 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
850 <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
851 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
852 <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>;
853 clock-names = "hdmi_pclk", "hdmi_i_pclk",
854 "i_tmds_clk", "i_pixel_clk",
855 "tmds_clko", "tmds_clko_user",
856 "pixel_clko", "pixel_clko_user",
857 "oscclk", "i_spdif_clk";
858 phy = <&hdmiphy>;
859 ddc = <&hsi2c_11>;
860 samsung,syscon-phandle = <&pmu_system_controller>;
861 samsung,sysreg-phandle = <&syscon_disp>;
862 status = "disabled";
863 };
864
865 hdmiphy: hdmiphy@13af0000 {
866 reg = <0x13af0000 0x80>;
867 };
868
793 syscon_disp: syscon@13b80000 { 869 syscon_disp: syscon@13b80000 {
794 compatible = "syscon"; 870 compatible = "syscon";
795 reg = <0x13b80000 0x1010>; 871 reg = <0x13b80000 0x1010>;
@@ -868,7 +944,7 @@
868 iommu-names = "left", "right"; 944 iommu-names = "left", "right";
869 }; 945 };
870 946
871 sysmmu_decon0x: sysmmu@0x13a00000 { 947 sysmmu_decon0x: sysmmu@13a00000 {
872 compatible = "samsung,exynos-sysmmu"; 948 compatible = "samsung,exynos-sysmmu";
873 reg = <0x13a00000 0x1000>; 949 reg = <0x13a00000 0x1000>;
874 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 950 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
@@ -878,7 +954,7 @@
878 #iommu-cells = <0>; 954 #iommu-cells = <0>;
879 }; 955 };
880 956
881 sysmmu_decon1x: sysmmu@0x13a10000 { 957 sysmmu_decon1x: sysmmu@13a10000 {
882 compatible = "samsung,exynos-sysmmu"; 958 compatible = "samsung,exynos-sysmmu";
883 reg = <0x13a10000 0x1000>; 959 reg = <0x13a10000 0x1000>;
884 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 960 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
@@ -888,7 +964,27 @@
888 #iommu-cells = <0>; 964 #iommu-cells = <0>;
889 }; 965 };
890 966
891 sysmmu_gscl0: sysmmu@0x13C80000 { 967 sysmmu_tv0x: sysmmu@13a20000 {
968 compatible = "samsung,exynos-sysmmu";
969 reg = <0x13a20000 0x1000>;
970 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
971 clock-names = "pclk", "aclk";
972 clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>,
973 <&cmu_disp CLK_ACLK_SMMU_TV0X>;
974 #iommu-cells = <0>;
975 };
976
977 sysmmu_tv1x: sysmmu@13a30000 {
978 compatible = "samsung,exynos-sysmmu";
979 reg = <0x13a30000 0x1000>;
980 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
981 clock-names = "pclk", "aclk";
982 clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>,
983 <&cmu_disp CLK_ACLK_SMMU_TV1X>;
984 #iommu-cells = <0>;
985 };
986
987 sysmmu_gscl0: sysmmu@13c80000 {
892 compatible = "samsung,exynos-sysmmu"; 988 compatible = "samsung,exynos-sysmmu";
893 reg = <0x13C80000 0x1000>; 989 reg = <0x13C80000 0x1000>;
894 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 990 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
@@ -898,7 +994,7 @@
898 #iommu-cells = <0>; 994 #iommu-cells = <0>;
899 }; 995 };
900 996
901 sysmmu_gscl1: sysmmu@0x13C90000 { 997 sysmmu_gscl1: sysmmu@13c90000 {
902 compatible = "samsung,exynos-sysmmu"; 998 compatible = "samsung,exynos-sysmmu";
903 reg = <0x13C90000 0x1000>; 999 reg = <0x13C90000 0x1000>;
904 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 1000 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
@@ -908,7 +1004,7 @@
908 #iommu-cells = <0>; 1004 #iommu-cells = <0>;
909 }; 1005 };
910 1006
911 sysmmu_gscl2: sysmmu@0x13CA0000 { 1007 sysmmu_gscl2: sysmmu@13ca0000 {
912 compatible = "samsung,exynos-sysmmu"; 1008 compatible = "samsung,exynos-sysmmu";
913 reg = <0x13CA0000 0x1000>; 1009 reg = <0x13CA0000 0x1000>;
914 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 1010 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
@@ -918,7 +1014,7 @@
918 #iommu-cells = <0>; 1014 #iommu-cells = <0>;
919 }; 1015 };
920 1016
921 sysmmu_jpeg: sysmmu@0x15060000 { 1017 sysmmu_jpeg: sysmmu@15060000 {
922 compatible = "samsung,exynos-sysmmu"; 1018 compatible = "samsung,exynos-sysmmu";
923 reg = <0x15060000 0x1000>; 1019 reg = <0x15060000 0x1000>;
924 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 1020 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
@@ -928,7 +1024,7 @@
928 #iommu-cells = <0>; 1024 #iommu-cells = <0>;
929 }; 1025 };
930 1026
931 sysmmu_mfc_0: sysmmu@0x15200000 { 1027 sysmmu_mfc_0: sysmmu@15200000 {
932 compatible = "samsung,exynos-sysmmu"; 1028 compatible = "samsung,exynos-sysmmu";
933 reg = <0x15200000 0x1000>; 1029 reg = <0x15200000 0x1000>;
934 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1030 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
@@ -938,7 +1034,7 @@
938 #iommu-cells = <0>; 1034 #iommu-cells = <0>;
939 }; 1035 };
940 1036
941 sysmmu_mfc_1: sysmmu@0x15210000 { 1037 sysmmu_mfc_1: sysmmu@15210000 {
942 compatible = "samsung,exynos-sysmmu"; 1038 compatible = "samsung,exynos-sysmmu";
943 reg = <0x15210000 0x1000>; 1039 reg = <0x15210000 0x1000>;
944 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1040 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
@@ -1261,7 +1357,7 @@
1261 status = "disabled"; 1357 status = "disabled";
1262 }; 1358 };
1263 1359
1264 usbdrd30: usb@15400000 { 1360 usbdrd30: usbdrd {
1265 compatible = "samsung,exynos5250-dwusb3"; 1361 compatible = "samsung,exynos5250-dwusb3";
1266 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, 1362 clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1267 <&cmu_fsys CLK_SCLK_USBDRD30>; 1363 <&cmu_fsys CLK_SCLK_USBDRD30>;
@@ -1308,7 +1404,7 @@
1308 status = "disabled"; 1404 status = "disabled";
1309 }; 1405 };
1310 1406
1311 usbhost30: usb@15a00000 { 1407 usbhost30: usbhost {
1312 compatible = "samsung,exynos5250-dwusb3"; 1408 compatible = "samsung,exynos5250-dwusb3";
1313 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, 1409 clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
1314 <&cmu_fsys CLK_SCLK_USBHOST30>; 1410 <&cmu_fsys CLK_SCLK_USBHOST30>;
@@ -1398,6 +1494,8 @@
1398 audio-subsystem@11400000 { 1494 audio-subsystem@11400000 {
1399 compatible = "samsung,exynos5433-lpass"; 1495 compatible = "samsung,exynos5433-lpass";
1400 reg = <0x11400000 0x100>, <0x11500000 0x08>; 1496 reg = <0x11400000 0x100>, <0x11500000 0x08>;
1497 clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
1498 clock-names = "sfr0_ctrl";
1401 samsung,pmu-syscon = <&pmu_system_controller>; 1499 samsung,pmu-syscon = <&pmu_system_controller>;
1402 #address-cells = <1>; 1500 #address-cells = <1>;
1403 #size-cells = <1>; 1501 #size-cells = <1>;
@@ -1458,5 +1556,6 @@
1458 }; 1556 };
1459}; 1557};
1460 1558
1559#include "exynos5433-bus.dtsi"
1461#include "exynos5433-pinctrl.dtsi" 1560#include "exynos5433-pinctrl.dtsi"
1462#include "exynos5433-tmu.dtsi" 1561#include "exynos5433-tmu.dtsi"
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
index c528dd52ba2d..e5892bb0ae6e 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -13,6 +13,7 @@
13#include "exynos7.dtsi" 13#include "exynos7.dtsi"
14#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/clock/samsung,s2mps11.h> 15#include <dt-bindings/clock/samsung,s2mps11.h>
16#include <dt-bindings/gpio/gpio.h>
16 17
17/ { 18/ {
18 model = "Samsung Exynos7 Espresso board based on EXYNOS7"; 19 model = "Samsung Exynos7 Espresso board based on EXYNOS7";
@@ -32,6 +33,29 @@
32 device_type = "memory"; 33 device_type = "memory";
33 reg = <0x0 0x40000000 0x0 0xC0000000>; 34 reg = <0x0 0x40000000 0x0 0xC0000000>;
34 }; 35 };
36
37 usb30_vbus_reg: regulator-usb30 {
38 compatible = "regulator-fixed";
39 regulator-name = "VBUS_5V";
40 regulator-min-microvolt = <5000000>;
41 regulator-max-microvolt = <5000000>;
42 gpio = <&gph1 1 GPIO_ACTIVE_HIGH>;
43 pinctrl-names = "default";
44 pinctrl-0 = <&usb30_vbus_en>;
45 enable-active-high;
46 };
47
48 usb3drd_boost_5v: regulator-usb3drd-boost {
49 compatible = "regulator-fixed";
50 regulator-name = "VUSB_VBUS_5V";
51 regulator-min-microvolt = <5000000>;
52 regulator-max-microvolt = <5000000>;
53 gpio = <&gpf4 1 GPIO_ACTIVE_HIGH>;
54 pinctrl-names = "default";
55 pinctrl-0 = <&usb3drd_boost_en>;
56 enable-active-high;
57 };
58
35}; 59};
36 60
37&fin_pll { 61&fin_pll {
@@ -328,8 +352,8 @@
328&pinctrl_alive { 352&pinctrl_alive {
329 pmic_irq: pmic-irq { 353 pmic_irq: pmic-irq {
330 samsung,pins = "gpa0-2"; 354 samsung,pins = "gpa0-2";
331 samsung,pin-pud = <3>; 355 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
332 samsung,pin-drv = <3>; 356 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
333 }; 357 };
334}; 358};
335 359
@@ -365,3 +389,24 @@
365 vqmmc-supply = <&ldo2_reg>; 389 vqmmc-supply = <&ldo2_reg>;
366 disable-wp; 390 disable-wp;
367}; 391};
392
393&pinctrl_bus1 {
394 usb30_vbus_en: usb30-vbus-en {
395 samsung,pins = "gph1-1";
396 samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
397 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
398 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
399 };
400
401 usb3drd_boost_en: usb3drd-boost-en {
402 samsung,pins = "gpf4-1";
403 samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
404 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
405 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
406 };
407};
408
409&usbdrd_phy {
410 vbus-supply = <&usb30_vbus_reg>;
411 vbus-boost-supply = <&usb3drd_boost_5v>;
412};
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
index 82321984e1fb..8f58850cd28c 100644
--- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -12,6 +12,8 @@
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13*/ 13*/
14 14
15#include <dt-bindings/pinctrl/samsung.h>
16
15&pinctrl_alive { 17&pinctrl_alive {
16 gpa0: gpa0 { 18 gpa0: gpa0 {
17 gpio-controller; 19 gpio-controller;
@@ -187,163 +189,163 @@
187 189
188 hs_i2c10_bus: hs-i2c10-bus { 190 hs_i2c10_bus: hs-i2c10-bus {
189 samsung,pins = "gpb0-1", "gpb0-0"; 191 samsung,pins = "gpb0-1", "gpb0-0";
190 samsung,pin-function = <2>; 192 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
191 samsung,pin-pud = <3>; 193 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
192 samsung,pin-drv = <0>; 194 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
193 }; 195 };
194 196
195 hs_i2c11_bus: hs-i2c11-bus { 197 hs_i2c11_bus: hs-i2c11-bus {
196 samsung,pins = "gpb0-3", "gpb0-2"; 198 samsung,pins = "gpb0-3", "gpb0-2";
197 samsung,pin-function = <2>; 199 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
198 samsung,pin-pud = <3>; 200 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
199 samsung,pin-drv = <0>; 201 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
200 }; 202 };
201 203
202 hs_i2c2_bus: hs-i2c2-bus { 204 hs_i2c2_bus: hs-i2c2-bus {
203 samsung,pins = "gpd0-3", "gpd0-2"; 205 samsung,pins = "gpd0-3", "gpd0-2";
204 samsung,pin-function = <3>; 206 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
205 samsung,pin-pud = <3>; 207 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
206 samsung,pin-drv = <0>; 208 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
207 }; 209 };
208 210
209 uart0_data: uart0-data { 211 uart0_data: uart0-data {
210 samsung,pins = "gpd0-0", "gpd0-1"; 212 samsung,pins = "gpd0-0", "gpd0-1";
211 samsung,pin-function = <2>; 213 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
212 samsung,pin-pud = <0>; 214 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
213 samsung,pin-drv = <0>; 215 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
214 }; 216 };
215 217
216 uart0_fctl: uart0-fctl { 218 uart0_fctl: uart0-fctl {
217 samsung,pins = "gpd0-2", "gpd0-3"; 219 samsung,pins = "gpd0-2", "gpd0-3";
218 samsung,pin-function = <2>; 220 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
219 samsung,pin-pud = <0>; 221 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
220 samsung,pin-drv = <0>; 222 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
221 }; 223 };
222 224
223 uart2_data: uart2-data { 225 uart2_data: uart2-data {
224 samsung,pins = "gpd1-4", "gpd1-5"; 226 samsung,pins = "gpd1-4", "gpd1-5";
225 samsung,pin-function = <2>; 227 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
226 samsung,pin-pud = <0>; 228 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
227 samsung,pin-drv = <0>; 229 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
228 }; 230 };
229 231
230 hs_i2c3_bus: hs-i2c3-bus { 232 hs_i2c3_bus: hs-i2c3-bus {
231 samsung,pins = "gpd1-3", "gpd1-2"; 233 samsung,pins = "gpd1-3", "gpd1-2";
232 samsung,pin-function = <3>; 234 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
233 samsung,pin-pud = <3>; 235 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
234 samsung,pin-drv = <0>; 236 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
235 }; 237 };
236 238
237 uart1_data: uart1-data { 239 uart1_data: uart1-data {
238 samsung,pins = "gpd1-0", "gpd1-1"; 240 samsung,pins = "gpd1-0", "gpd1-1";
239 samsung,pin-function = <2>; 241 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
240 samsung,pin-pud = <0>; 242 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
241 samsung,pin-drv = <0>; 243 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
242 }; 244 };
243 245
244 uart1_fctl: uart1-fctl { 246 uart1_fctl: uart1-fctl {
245 samsung,pins = "gpd1-2", "gpd1-3"; 247 samsung,pins = "gpd1-2", "gpd1-3";
246 samsung,pin-function = <2>; 248 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
247 samsung,pin-pud = <0>; 249 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
248 samsung,pin-drv = <0>; 250 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
249 }; 251 };
250 252
251 hs_i2c0_bus: hs-i2c0-bus { 253 hs_i2c0_bus: hs-i2c0-bus {
252 samsung,pins = "gpd2-1", "gpd2-0"; 254 samsung,pins = "gpd2-1", "gpd2-0";
253 samsung,pin-function = <2>; 255 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
254 samsung,pin-pud = <3>; 256 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
255 samsung,pin-drv = <0>; 257 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
256 }; 258 };
257 259
258 hs_i2c1_bus: hs-i2c1-bus { 260 hs_i2c1_bus: hs-i2c1-bus {
259 samsung,pins = "gpd2-3", "gpd2-2"; 261 samsung,pins = "gpd2-3", "gpd2-2";
260 samsung,pin-function = <2>; 262 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
261 samsung,pin-pud = <3>; 263 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
262 samsung,pin-drv = <0>; 264 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
263 }; 265 };
264 266
265 hs_i2c9_bus: hs-i2c9-bus { 267 hs_i2c9_bus: hs-i2c9-bus {
266 samsung,pins = "gpd2-7", "gpd2-6"; 268 samsung,pins = "gpd2-7", "gpd2-6";
267 samsung,pin-function = <3>; 269 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
268 samsung,pin-pud = <3>; 270 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
269 samsung,pin-drv = <0>; 271 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
270 }; 272 };
271 273
272 pwm0_out: pwm0-out { 274 pwm0_out: pwm0-out {
273 samsung,pins = "gpd2-4"; 275 samsung,pins = "gpd2-4";
274 samsung,pin-function = <2>; 276 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
275 samsung,pin-pud = <0>; 277 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
276 samsung,pin-drv = <0>; 278 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
277 }; 279 };
278 280
279 pwm1_out: pwm1-out { 281 pwm1_out: pwm1-out {
280 samsung,pins = "gpd2-5"; 282 samsung,pins = "gpd2-5";
281 samsung,pin-function = <2>; 283 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
282 samsung,pin-pud = <0>; 284 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
283 samsung,pin-drv = <0>; 285 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
284 }; 286 };
285 287
286 pwm2_out: pwm2-out { 288 pwm2_out: pwm2-out {
287 samsung,pins = "gpd2-6"; 289 samsung,pins = "gpd2-6";
288 samsung,pin-function = <2>; 290 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
289 samsung,pin-pud = <0>; 291 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
290 samsung,pin-drv = <0>; 292 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
291 }; 293 };
292 294
293 pwm3_out: pwm3-out { 295 pwm3_out: pwm3-out {
294 samsung,pins = "gpd2-7"; 296 samsung,pins = "gpd2-7";
295 samsung,pin-function = <2>; 297 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
296 samsung,pin-pud = <0>; 298 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
297 samsung,pin-drv = <0>; 299 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
298 }; 300 };
299 301
300 hs_i2c8_bus: hs-i2c8-bus { 302 hs_i2c8_bus: hs-i2c8-bus {
301 samsung,pins = "gpd5-3", "gpd5-2"; 303 samsung,pins = "gpd5-3", "gpd5-2";
302 samsung,pin-function = <3>; 304 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
303 samsung,pin-pud = <3>; 305 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
304 samsung,pin-drv = <0>; 306 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
305 }; 307 };
306 308
307 uart3_data: uart3-data { 309 uart3_data: uart3-data {
308 samsung,pins = "gpd5-0", "gpd5-1"; 310 samsung,pins = "gpd5-0", "gpd5-1";
309 samsung,pin-function = <3>; 311 samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
310 samsung,pin-pud = <0>; 312 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
311 samsung,pin-drv = <0>; 313 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
312 }; 314 };
313 315
314 spi2_bus: spi2-bus { 316 spi2_bus: spi2-bus {
315 samsung,pins = "gpd5-0", "gpd5-1", "gpd5-2", "gpd5-3"; 317 samsung,pins = "gpd5-0", "gpd5-1", "gpd5-2", "gpd5-3";
316 samsung,pin-function = <2>; 318 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
317 samsung,pin-pud = <3>; 319 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
318 samsung,pin-drv = <0>; 320 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
319 }; 321 };
320 322
321 spi1_bus: spi1-bus { 323 spi1_bus: spi1-bus {
322 samsung,pins = "gpd6-2", "gpd6-3", "gpd6-4", "gpd6-5"; 324 samsung,pins = "gpd6-2", "gpd6-3", "gpd6-4", "gpd6-5";
323 samsung,pin-function = <2>; 325 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
324 samsung,pin-pud = <3>; 326 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
325 samsung,pin-drv = <0>; 327 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
326 }; 328 };
327 329
328 spi0_bus: spi0-bus { 330 spi0_bus: spi0-bus {
329 samsung,pins = "gpd8-0", "gpd8-1", "gpd6-0", "gpd6-1"; 331 samsung,pins = "gpd8-0", "gpd8-1", "gpd6-0", "gpd6-1";
330 samsung,pin-function = <2>; 332 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
331 samsung,pin-pud = <3>; 333 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
332 samsung,pin-drv = <0>; 334 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
333 }; 335 };
334 336
335 hs_i2c4_bus: hs-i2c4-bus { 337 hs_i2c4_bus: hs-i2c4-bus {
336 samsung,pins = "gpg3-1", "gpg3-0"; 338 samsung,pins = "gpg3-1", "gpg3-0";
337 samsung,pin-function = <2>; 339 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
338 samsung,pin-pud = <3>; 340 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
339 samsung,pin-drv = <0>; 341 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
340 }; 342 };
341 343
342 hs_i2c5_bus: hs-i2c5-bus { 344 hs_i2c5_bus: hs-i2c5-bus {
343 samsung,pins = "gpg3-3", "gpg3-2"; 345 samsung,pins = "gpg3-3", "gpg3-2";
344 samsung,pin-function = <2>; 346 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
345 samsung,pin-pud = <3>; 347 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
346 samsung,pin-drv = <0>; 348 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
347 }; 349 };
348}; 350};
349 351
@@ -358,9 +360,9 @@
358 360
359 hs_i2c6_bus: hs-i2c6-bus { 361 hs_i2c6_bus: hs-i2c6-bus {
360 samsung,pins = "gpj0-1", "gpj0-0"; 362 samsung,pins = "gpj0-1", "gpj0-0";
361 samsung,pin-function = <2>; 363 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
362 samsung,pin-pud = <3>; 364 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
363 samsung,pin-drv = <0>; 365 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
364 }; 366 };
365}; 367};
366 368
@@ -375,9 +377,9 @@
375 377
376 hs_i2c7_bus: hs-i2c7-bus { 378 hs_i2c7_bus: hs-i2c7-bus {
377 samsung,pins = "gpj1-1", "gpj1-0"; 379 samsung,pins = "gpj1-1", "gpj1-0";
378 samsung,pin-function = <2>; 380 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
379 samsung,pin-pud = <3>; 381 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
380 samsung,pin-drv = <0>; 382 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
381 }; 383 };
382}; 384};
383 385
@@ -392,9 +394,9 @@
392 394
393 spi3_bus: spi3-bus { 395 spi3_bus: spi3-bus {
394 samsung,pins = "gpg4-0", "gpg4-1", "gpg4-2", "gpg4-3"; 396 samsung,pins = "gpg4-0", "gpg4-1", "gpg4-2", "gpg4-3";
395 samsung,pin-function = <2>; 397 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
396 samsung,pin-pud = <3>; 398 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
397 samsung,pin-drv = <0>; 399 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
398 }; 400 };
399}; 401};
400 402
@@ -409,9 +411,9 @@
409 411
410 spi4_bus: spi4-bus { 412 spi4_bus: spi4-bus {
411 samsung,pins = "gpv7-0", "gpv7-1", "gpv7-2", "gpv7-3"; 413 samsung,pins = "gpv7-0", "gpv7-1", "gpv7-2", "gpv7-3";
412 samsung,pin-function = <2>; 414 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
413 samsung,pin-pud = <3>; 415 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
414 samsung,pin-drv = <0>; 416 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
415 }; 417 };
416}; 418};
417 419
@@ -426,37 +428,37 @@
426 428
427 sd2_clk: sd2-clk { 429 sd2_clk: sd2-clk {
428 samsung,pins = "gpr4-0"; 430 samsung,pins = "gpr4-0";
429 samsung,pin-function = <2>; 431 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
430 samsung,pin-pud = <0>; 432 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
431 samsung,pin-drv = <3>; 433 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
432 }; 434 };
433 435
434 sd2_cmd: sd2-cmd { 436 sd2_cmd: sd2-cmd {
435 samsung,pins = "gpr4-1"; 437 samsung,pins = "gpr4-1";
436 samsung,pin-function = <2>; 438 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
437 samsung,pin-pud = <0>; 439 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
438 samsung,pin-drv = <3>; 440 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
439 }; 441 };
440 442
441 sd2_cd: sd2-cd { 443 sd2_cd: sd2-cd {
442 samsung,pins = "gpr4-2"; 444 samsung,pins = "gpr4-2";
443 samsung,pin-function = <2>; 445 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
444 samsung,pin-pud = <3>; 446 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
445 samsung,pin-drv = <3>; 447 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
446 }; 448 };
447 449
448 sd2_bus1: sd2-bus-width1 { 450 sd2_bus1: sd2-bus-width1 {
449 samsung,pins = "gpr4-3"; 451 samsung,pins = "gpr4-3";
450 samsung,pin-function = <2>; 452 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
451 samsung,pin-pud = <3>; 453 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
452 samsung,pin-drv = <3>; 454 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
453 }; 455 };
454 456
455 sd2_bus4: sd2-bus-width4 { 457 sd2_bus4: sd2-bus-width4 {
456 samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6"; 458 samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6";
457 samsung,pin-function = <2>; 459 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
458 samsung,pin-pud = <3>; 460 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
459 samsung,pin-drv = <3>; 461 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
460 }; 462 };
461}; 463};
462 464
@@ -495,107 +497,107 @@
495 497
496 sd0_clk: sd0-clk { 498 sd0_clk: sd0-clk {
497 samsung,pins = "gpr0-0"; 499 samsung,pins = "gpr0-0";
498 samsung,pin-function = <2>; 500 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
499 samsung,pin-pud = <0>; 501 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
500 samsung,pin-drv = <3>; 502 samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>;
501 }; 503 };
502 504
503 sd0_cmd: sd0-cmd { 505 sd0_cmd: sd0-cmd {
504 samsung,pins = "gpr0-1"; 506 samsung,pins = "gpr0-1";
505 samsung,pin-function = <2>; 507 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
506 samsung,pin-pud = <3>; 508 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
507 samsung,pin-drv = <3>; 509 samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>;
508 }; 510 };
509 511
510 sd0_ds: sd0-ds { 512 sd0_ds: sd0-ds {
511 samsung,pins = "gpr0-2"; 513 samsung,pins = "gpr0-2";
512 samsung,pin-function = <2>; 514 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
513 samsung,pin-pud = <1>; 515 samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
514 samsung,pin-drv = <3>; 516 samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>;
515 }; 517 };
516 518
517 sd0_qrdy: sd0-qrdy { 519 sd0_qrdy: sd0-qrdy {
518 samsung,pins = "gpr0-3"; 520 samsung,pins = "gpr0-3";
519 samsung,pin-function = <2>; 521 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
520 samsung,pin-pud = <1>; 522 samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
521 samsung,pin-drv = <3>; 523 samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>;
522 }; 524 };
523 525
524 sd0_bus1: sd0-bus-width1 { 526 sd0_bus1: sd0-bus-width1 {
525 samsung,pins = "gpr1-0"; 527 samsung,pins = "gpr1-0";
526 samsung,pin-function = <2>; 528 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
527 samsung,pin-pud = <3>; 529 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
528 samsung,pin-drv = <3>; 530 samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>;
529 }; 531 };
530 532
531 sd0_bus4: sd0-bus-width4 { 533 sd0_bus4: sd0-bus-width4 {
532 samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3"; 534 samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3";
533 samsung,pin-function = <2>; 535 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
534 samsung,pin-pud = <3>; 536 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
535 samsung,pin-drv = <3>; 537 samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>;
536 }; 538 };
537 539
538 sd0_bus8: sd0-bus-width8 { 540 sd0_bus8: sd0-bus-width8 {
539 samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7"; 541 samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7";
540 samsung,pin-function = <2>; 542 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
541 samsung,pin-pud = <3>; 543 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
542 samsung,pin-drv = <3>; 544 samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV2>;
543 }; 545 };
544 546
545 sd1_clk: sd1-clk { 547 sd1_clk: sd1-clk {
546 samsung,pins = "gpr2-0"; 548 samsung,pins = "gpr2-0";
547 samsung,pin-function = <2>; 549 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
548 samsung,pin-pud = <0>; 550 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
549 samsung,pin-drv = <2>; 551 samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV3>;
550 }; 552 };
551 553
552 sd1_cmd: sd1-cmd { 554 sd1_cmd: sd1-cmd {
553 samsung,pins = "gpr2-1"; 555 samsung,pins = "gpr2-1";
554 samsung,pin-function = <2>; 556 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
555 samsung,pin-pud = <0>; 557 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
556 samsung,pin-drv = <2>; 558 samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV3>;
557 }; 559 };
558 560
559 sd1_ds: sd1-ds { 561 sd1_ds: sd1-ds {
560 samsung,pins = "gpr2-2"; 562 samsung,pins = "gpr2-2";
561 samsung,pin-function = <2>; 563 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
562 samsung,pin-pud = <1>; 564 samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
563 samsung,pin-drv = <6>; 565 samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV4>;
564 }; 566 };
565 567
566 sd1_qrdy: sd1-qrdy { 568 sd1_qrdy: sd1-qrdy {
567 samsung,pins = "gpr2-3"; 569 samsung,pins = "gpr2-3";
568 samsung,pin-function = <2>; 570 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
569 samsung,pin-pud = <1>; 571 samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
570 samsung,pin-drv = <6>; 572 samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV4>;
571 }; 573 };
572 574
573 sd1_int: sd1-int { 575 sd1_int: sd1-int {
574 samsung,pins = "gpr2-4"; 576 samsung,pins = "gpr2-4";
575 samsung,pin-function = <2>; 577 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
576 samsung,pin-pud = <1>; 578 samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
577 samsung,pin-drv = <6>; 579 samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV4>;
578 }; 580 };
579 581
580 sd1_bus1: sd1-bus-width1 { 582 sd1_bus1: sd1-bus-width1 {
581 samsung,pins = "gpr3-0"; 583 samsung,pins = "gpr3-0";
582 samsung,pin-function = <2>; 584 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
583 samsung,pin-pud = <3>; 585 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
584 samsung,pin-drv = <2>; 586 samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV3>;
585 }; 587 };
586 588
587 sd1_bus4: sd1-bus-width4 { 589 sd1_bus4: sd1-bus-width4 {
588 samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3"; 590 samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3";
589 samsung,pin-function = <2>; 591 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
590 samsung,pin-pud = <3>; 592 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
591 samsung,pin-drv = <2>; 593 samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV3>;
592 }; 594 };
593 595
594 sd1_bus8: sd1-bus-width8 { 596 sd1_bus8: sd1-bus-width8 {
595 samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; 597 samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
596 samsung,pin-function = <2>; 598 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
597 samsung,pin-pud = <3>; 599 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
598 samsung,pin-drv = <2>; 600 samsung,pin-drv = <EXYNOS7_FSYS1_PIN_DRV_LV3>;
599 }; 601 };
600}; 602};
601 603
@@ -682,22 +684,22 @@
682 684
683 spi5_bus: spi5-bus { 685 spi5_bus: spi5-bus {
684 samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3"; 686 samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3";
685 samsung,pin-function = <2>; 687 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
686 samsung,pin-pud = <3>; 688 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
687 samsung,pin-drv = <0>; 689 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
688 }; 690 };
689 691
690 ufs_refclk_out: ufs-refclk-out { 692 ufs_refclk_out: ufs-refclk-out {
691 samsung,pins = "gpg2-4"; 693 samsung,pins = "gpg2-4";
692 samsung,pin-function = <2>; 694 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
693 samsung,pin-pud = <0>; 695 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
694 samsung,pin-drv = <2>; 696 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV2>;
695 }; 697 };
696 698
697 ufs_rst_n: ufs-rst-n { 699 ufs_rst_n: ufs-rst-n {
698 samsung,pins = "gph1-5"; 700 samsung,pins = "gph1-5";
699 samsung,pin-function = <2>; 701 samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
700 samsung,pin-pud = <3>; 702 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
701 samsung,pin-drv = <0>; 703 samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
702 }; 704 };
703}; 705};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi
index 80aa60e38237..9a3fbed1765a 100644
--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -603,6 +603,40 @@
603 #include "exynos7-trip-points.dtsi" 603 #include "exynos7-trip-points.dtsi"
604 }; 604 };
605 }; 605 };
606
607 usbdrd_phy: phy@15500000 {
608 compatible = "samsung,exynos7-usbdrd-phy";
609 reg = <0x15500000 0x100>;
610 clocks = <&clock_fsys0 ACLK_USBDRD300>,
611 <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>,
612 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>,
613 <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>,
614 <&clock_fsys0 SCLK_USBDRD300_REFCLK>;
615 clock-names = "phy", "ref", "phy_pipe",
616 "phy_utmi", "itp";
617 samsung,pmu-syscon = <&pmu_system_controller>;
618 #phy-cells = <1>;
619 };
620
621 usbdrd3 {
622 compatible = "samsung,exynos7-dwusb3";
623 clocks = <&clock_fsys0 ACLK_USBDRD300>,
624 <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>,
625 <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>;
626 clock-names = "usbdrd30", "usbdrd30_susp_clk",
627 "usbdrd30_axius_clk";
628 #address-cells = <1>;
629 #size-cells = <1>;
630 ranges;
631
632 dwc3@15400000 {
633 compatible = "snps,dwc3";
634 reg = <0x15400000 0x10000>;
635 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
636 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
637 phy-names = "usb2-phy", "usb3-phy";
638 };
639 };
606 }; 640 };
607}; 641};
608 642
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index f096bd7df40c..3feaea8be40e 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -739,7 +739,9 @@ static const struct samsung_pll_rate_table exynos5443_pll_rates[] __initconst =
739 PLL_35XX_RATE(350000000U, 350, 6, 2), 739 PLL_35XX_RATE(350000000U, 350, 6, 2),
740 PLL_35XX_RATE(333000000U, 222, 4, 2), 740 PLL_35XX_RATE(333000000U, 222, 4, 2),
741 PLL_35XX_RATE(300000000U, 500, 5, 3), 741 PLL_35XX_RATE(300000000U, 500, 5, 3),
742 PLL_35XX_RATE(278000000U, 556, 6, 3),
742 PLL_35XX_RATE(266000000U, 532, 6, 3), 743 PLL_35XX_RATE(266000000U, 532, 6, 3),
744 PLL_35XX_RATE(250000000U, 500, 6, 3),
743 PLL_35XX_RATE(200000000U, 400, 6, 3), 745 PLL_35XX_RATE(200000000U, 400, 6, 3),
744 PLL_35XX_RATE(166000000U, 332, 6, 3), 746 PLL_35XX_RATE(166000000U, 332, 6, 3),
745 PLL_35XX_RATE(160000000U, 320, 6, 3), 747 PLL_35XX_RATE(160000000U, 320, 6, 3),
@@ -2559,8 +2561,10 @@ static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = {
2559 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000), 2561 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
2560 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000), 2562 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
2561 /* PHY clocks from MIPI_DPHY0 */ 2563 /* PHY clocks from MIPI_DPHY0 */
2562 FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, 0, 188000000), 2564 FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy",
2563 FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, 0, 100000000), 2565 NULL, 0, 188000000),
2566 FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy",
2567 NULL, 0, 100000000),
2564 /* PHY clocks from HDMI_PHY */ 2568 /* PHY clocks from HDMI_PHY */
2565 FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy", 2569 FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
2566 NULL, 0, 300000000), 2570 NULL, 0, 300000000),
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 4fa6bb2136e3..be39d23e6a32 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -771,7 +771,10 @@
771 771
772#define CLK_PCLK_DECON 113 772#define CLK_PCLK_DECON 113
773 773
774#define DISP_NR_CLK 114 774#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114
775#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115
776
777#define DISP_NR_CLK 116
775 778
776/* CMU_AUD */ 779/* CMU_AUD */
777#define CLK_MOUT_AUD_PLL_USER 1 780#define CLK_MOUT_AUD_PLL_USER 1
diff --git a/include/dt-bindings/pinctrl/samsung.h b/include/dt-bindings/pinctrl/samsung.h
index 6276eb785e2b..b7aa3646208b 100644
--- a/include/dt-bindings/pinctrl/samsung.h
+++ b/include/dt-bindings/pinctrl/samsung.h
@@ -45,6 +45,20 @@
45#define EXYNOS5420_PIN_DRV_LV3 2 45#define EXYNOS5420_PIN_DRV_LV3 2
46#define EXYNOS5420_PIN_DRV_LV4 3 46#define EXYNOS5420_PIN_DRV_LV4 3
47 47
48/* Drive strengths for Exynos5433 */
49#define EXYNOS5433_PIN_DRV_FAST_SR1 0
50#define EXYNOS5433_PIN_DRV_FAST_SR2 1
51#define EXYNOS5433_PIN_DRV_FAST_SR3 2
52#define EXYNOS5433_PIN_DRV_FAST_SR4 3
53#define EXYNOS5433_PIN_DRV_FAST_SR5 4
54#define EXYNOS5433_PIN_DRV_FAST_SR6 5
55#define EXYNOS5433_PIN_DRV_SLOW_SR1 8
56#define EXYNOS5433_PIN_DRV_SLOW_SR2 9
57#define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa
58#define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb
59#define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc
60#define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf
61
48#define EXYNOS_PIN_FUNC_INPUT 0 62#define EXYNOS_PIN_FUNC_INPUT 0
49#define EXYNOS_PIN_FUNC_OUTPUT 1 63#define EXYNOS_PIN_FUNC_OUTPUT 1
50#define EXYNOS_PIN_FUNC_2 2 64#define EXYNOS_PIN_FUNC_2 2
@@ -54,4 +68,12 @@
54#define EXYNOS_PIN_FUNC_6 6 68#define EXYNOS_PIN_FUNC_6 6
55#define EXYNOS_PIN_FUNC_F 0xf 69#define EXYNOS_PIN_FUNC_F 0xf
56 70
71/* Drive strengths for Exynos7 FSYS1 block */
72#define EXYNOS7_FSYS1_PIN_DRV_LV1 0
73#define EXYNOS7_FSYS1_PIN_DRV_LV2 4
74#define EXYNOS7_FSYS1_PIN_DRV_LV3 2
75#define EXYNOS7_FSYS1_PIN_DRV_LV4 6
76#define EXYNOS7_FSYS1_PIN_DRV_LV5 1
77#define EXYNOS7_FSYS1_PIN_DRV_LV6 5
78
57#endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */ 79#endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-30 23:54:26 -0500