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-rw-r--r--drivers/gpu/drm/amd/amdgpu/Makefile3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c327
-rw-r--r--drivers/gpu/drm/amd/include/cgs_common.h563
-rw-r--r--drivers/gpu/drm/amd/include/cgs_linux.h135
5 files changed, 1036 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 908360584e4d..ccdbb3579bd8 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -77,6 +77,9 @@ amdgpu-y += \
77 amdgpu_amdkfd_gfx_v7.o \ 77 amdgpu_amdkfd_gfx_v7.o \
78 amdgpu_amdkfd_gfx_v8.o 78 amdgpu_amdkfd_gfx_v8.o
79 79
80# add cgs
81amdgpu-y += amdgpu_cgs.o
82
80amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o 83amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o
81amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o 84amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o
82amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o 85amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index baefa635169a..548e2bb72d99 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -42,6 +42,7 @@
42#include <ttm/ttm_module.h> 42#include <ttm/ttm_module.h>
43#include <ttm/ttm_execbuf_util.h> 43#include <ttm/ttm_execbuf_util.h>
44 44
45#include <drm/drmP.h>
45#include <drm/drm_gem.h> 46#include <drm/drm_gem.h>
46#include <drm/amdgpu_drm.h> 47#include <drm/amdgpu_drm.h>
47 48
@@ -1862,6 +1863,13 @@ extern int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1862 struct drm_file *filp); 1863 struct drm_file *filp);
1863 1864
1864/* 1865/*
1866 * CGS
1867 */
1868void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1869void amdgpu_cgs_destroy_device(void *cgs_device);
1870
1871
1872/*
1865 * Core structure, functions and helpers. 1873 * Core structure, functions and helpers.
1866 */ 1874 */
1867typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1875typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
new file mode 100644
index 000000000000..aea264a15d9b
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -0,0 +1,327 @@
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#include "amdgpu.h"
25#include "cgs_linux.h"
26
27struct amdgpu_cgs_device {
28 struct cgs_device base;
29 struct amdgpu_device *adev;
30};
31
32#define CGS_FUNC_ADEV \
33 struct amdgpu_device *adev = \
34 ((struct amdgpu_cgs_device *)cgs_device)->adev
35
36static int amdgpu_cgs_gpu_mem_info(void *cgs_device, enum cgs_gpu_mem_type type,
37 uint64_t *mc_start, uint64_t *mc_size,
38 uint64_t *mem_size)
39{
40 return 0;
41}
42
43static int amdgpu_cgs_gmap_kmem(void *cgs_device, void *kmem,
44 uint64_t size,
45 uint64_t min_offset, uint64_t max_offset,
46 cgs_handle_t *kmem_handle, uint64_t *mcaddr)
47{
48 return 0;
49}
50
51static int amdgpu_cgs_gunmap_kmem(void *cgs_device, cgs_handle_t kmem_handle)
52{
53 return 0;
54}
55
56static int amdgpu_cgs_alloc_gpu_mem(void *cgs_device,
57 enum cgs_gpu_mem_type type,
58 uint64_t size, uint64_t align,
59 uint64_t min_offset, uint64_t max_offset,
60 cgs_handle_t *handle)
61{
62 return 0;
63}
64
65static int amdgpu_cgs_import_gpu_mem(void *cgs_device, int dmabuf_fd,
66 cgs_handle_t *handle)
67{
68 /* TODO */
69 return 0;
70}
71
72static int amdgpu_cgs_free_gpu_mem(void *cgs_device, cgs_handle_t handle)
73{
74 /* TODO */
75 return 0;
76}
77
78static int amdgpu_cgs_gmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
79 uint64_t *mcaddr)
80{
81 /* TODO */
82 return 0;
83}
84
85static int amdgpu_cgs_gunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
86{
87 /* TODO */
88 return 0;
89}
90
91static int amdgpu_cgs_kmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
92 void **map)
93{
94 /* TODO */
95 return 0;
96}
97
98static int amdgpu_cgs_kunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
99{
100 /* TODO */
101 return 0;
102}
103
104static uint32_t amdgpu_cgs_read_register(void *cgs_device, unsigned offset)
105{
106 /* TODO */
107 return 0;
108}
109
110static void amdgpu_cgs_write_register(void *cgs_device, unsigned offset,
111 uint32_t value)
112{
113 /* TODO */
114 return;
115}
116
117static uint32_t amdgpu_cgs_read_ind_register(void *cgs_device,
118 enum cgs_ind_reg space,
119 unsigned index)
120{
121 /* TODO */
122 return 0;
123}
124
125static void amdgpu_cgs_write_ind_register(void *cgs_device,
126 enum cgs_ind_reg space,
127 unsigned index, uint32_t value)
128{
129 /* TODO */
130 return;
131}
132
133static uint8_t amdgpu_cgs_read_pci_config_byte(void *cgs_device, unsigned addr)
134{
135 /* TODO */
136 return 0;
137}
138
139static uint16_t amdgpu_cgs_read_pci_config_word(void *cgs_device, unsigned addr)
140{
141 /* TODO */
142 return 0;
143}
144
145static uint32_t amdgpu_cgs_read_pci_config_dword(void *cgs_device,
146 unsigned addr)
147{
148 /* TODO */
149 return 0;
150}
151
152static void amdgpu_cgs_write_pci_config_byte(void *cgs_device, unsigned addr,
153 uint8_t value)
154{
155 /* TODO */
156 return;
157}
158
159static void amdgpu_cgs_write_pci_config_word(void *cgs_device, unsigned addr,
160 uint16_t value)
161{
162 /* TODO */
163 return;
164}
165
166static void amdgpu_cgs_write_pci_config_dword(void *cgs_device, unsigned addr,
167 uint32_t value)
168{
169 /* TODO */
170 return;
171}
172
173static const void *amdgpu_cgs_atom_get_data_table(void *cgs_device,
174 unsigned table, uint16_t *size,
175 uint8_t *frev, uint8_t *crev)
176{
177 /* TODO */
178 return NULL;
179}
180
181static int amdgpu_cgs_atom_get_cmd_table_revs(void *cgs_device, unsigned table,
182 uint8_t *frev, uint8_t *crev)
183{
184 /* TODO */
185 return 0;
186}
187
188static int amdgpu_cgs_atom_exec_cmd_table(void *cgs_device, unsigned table,
189 void *args)
190{
191 /* TODO */
192 return 0;
193}
194
195
196static int amdgpu_cgs_create_pm_request(void *cgs_device, cgs_handle_t *request)
197{
198 /* TODO */
199 return 0;
200}
201
202static int amdgpu_cgs_destroy_pm_request(void *cgs_device, cgs_handle_t request)
203{
204 /* TODO */
205 return 0;
206}
207
208static int amdgpu_cgs_set_pm_request(void *cgs_device, cgs_handle_t request,
209 int active)
210{
211 /* TODO */
212 return 0;
213}
214
215static int amdgpu_cgs_pm_request_clock(void *cgs_device, cgs_handle_t request,
216 enum cgs_clock clock, unsigned freq)
217{
218 /* TODO */
219 return 0;
220}
221
222static int amdgpu_cgs_pm_request_engine(void *cgs_device, cgs_handle_t request,
223 enum cgs_engine engine, int powered)
224{
225 /* TODO */
226 return 0;
227}
228
229
230
231static int amdgpu_cgs_pm_query_clock_limits(void *cgs_device,
232 enum cgs_clock clock,
233 struct cgs_clock_limits *limits)
234{
235 /* TODO */
236 return 0;
237}
238
239static int amdgpu_cgs_set_camera_voltages(void *cgs_device, uint32_t mask,
240 const uint32_t *voltages)
241{
242 DRM_ERROR("not implemented");
243 return -EPERM;
244}
245
246static int amdgpu_cgs_add_irq_source(void *cgs_device, unsigned src_id,
247 unsigned num_types,
248 cgs_irq_source_set_func_t set,
249 cgs_irq_handler_func_t handler,
250 void *private_data)
251{
252 /* TODO */
253 return 0;
254}
255
256static int amdgpu_cgs_irq_get(void *cgs_device, unsigned src_id, unsigned type)
257{
258 /* TODO */
259 return 0;
260}
261
262static int amdgpu_cgs_irq_put(void *cgs_device, unsigned src_id, unsigned type)
263{
264 /* TODO */
265 return 0;
266}
267
268static const struct cgs_ops amdgpu_cgs_ops = {
269 amdgpu_cgs_gpu_mem_info,
270 amdgpu_cgs_gmap_kmem,
271 amdgpu_cgs_gunmap_kmem,
272 amdgpu_cgs_alloc_gpu_mem,
273 amdgpu_cgs_free_gpu_mem,
274 amdgpu_cgs_gmap_gpu_mem,
275 amdgpu_cgs_gunmap_gpu_mem,
276 amdgpu_cgs_kmap_gpu_mem,
277 amdgpu_cgs_kunmap_gpu_mem,
278 amdgpu_cgs_read_register,
279 amdgpu_cgs_write_register,
280 amdgpu_cgs_read_ind_register,
281 amdgpu_cgs_write_ind_register,
282 amdgpu_cgs_read_pci_config_byte,
283 amdgpu_cgs_read_pci_config_word,
284 amdgpu_cgs_read_pci_config_dword,
285 amdgpu_cgs_write_pci_config_byte,
286 amdgpu_cgs_write_pci_config_word,
287 amdgpu_cgs_write_pci_config_dword,
288 amdgpu_cgs_atom_get_data_table,
289 amdgpu_cgs_atom_get_cmd_table_revs,
290 amdgpu_cgs_atom_exec_cmd_table,
291 amdgpu_cgs_create_pm_request,
292 amdgpu_cgs_destroy_pm_request,
293 amdgpu_cgs_set_pm_request,
294 amdgpu_cgs_pm_request_clock,
295 amdgpu_cgs_pm_request_engine,
296 amdgpu_cgs_pm_query_clock_limits,
297 amdgpu_cgs_set_camera_voltages
298};
299
300static const struct cgs_os_ops amdgpu_cgs_os_ops = {
301 amdgpu_cgs_import_gpu_mem,
302 amdgpu_cgs_add_irq_source,
303 amdgpu_cgs_irq_get,
304 amdgpu_cgs_irq_put
305};
306
307void *amdgpu_cgs_create_device(struct amdgpu_device *adev)
308{
309 struct amdgpu_cgs_device *cgs_device =
310 kmalloc(sizeof(*cgs_device), GFP_KERNEL);
311
312 if (!cgs_device) {
313 DRM_ERROR("Couldn't allocate CGS device structure\n");
314 return NULL;
315 }
316
317 cgs_device->base.ops = &amdgpu_cgs_ops;
318 cgs_device->base.os_ops = &amdgpu_cgs_os_ops;
319 cgs_device->adev = adev;
320
321 return cgs_device;
322}
323
324void amdgpu_cgs_destroy_device(void *cgs_device)
325{
326 kfree(cgs_device);
327}
diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
new file mode 100644
index 000000000000..f8cdb8875d89
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/cgs_common.h
@@ -0,0 +1,563 @@
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#ifndef _CGS_COMMON_H
25#define _CGS_COMMON_H
26
27/**
28 * enum cgs_gpu_mem_type - GPU memory types
29 */
30enum cgs_gpu_mem_type {
31 CGS_GPU_MEM_TYPE__VISIBLE_FB,
32 CGS_GPU_MEM_TYPE__INVISIBLE_FB,
33 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
34 CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB,
35 CGS_GPU_MEM_TYPE__GART_CACHEABLE,
36 CGS_GPU_MEM_TYPE__GART_WRITECOMBINE
37};
38
39/**
40 * enum cgs_ind_reg - Indirect register spaces
41 */
42enum cgs_ind_reg {
43 CGS_IND_REG__MMIO,
44 CGS_IND_REG__PCIE,
45 CGS_IND_REG__SMC,
46 CGS_IND_REG__UVD_CTX,
47 CGS_IND_REG__DIDT,
48 CGS_IND_REG__AUDIO_ENDPT
49};
50
51/**
52 * enum cgs_clock - Clocks controlled by the SMU
53 */
54enum cgs_clock {
55 CGS_CLOCK__SCLK,
56 CGS_CLOCK__MCLK,
57 CGS_CLOCK__VCLK,
58 CGS_CLOCK__DCLK,
59 CGS_CLOCK__ECLK,
60 CGS_CLOCK__ACLK,
61 CGS_CLOCK__ICLK,
62 /* ... */
63};
64
65/**
66 * enum cgs_engine - Engines that can be statically power-gated
67 */
68enum cgs_engine {
69 CGS_ENGINE__UVD,
70 CGS_ENGINE__VCE,
71 CGS_ENGINE__VP8,
72 CGS_ENGINE__ACP_DMA,
73 CGS_ENGINE__ACP_DSP0,
74 CGS_ENGINE__ACP_DSP1,
75 CGS_ENGINE__ISP,
76 /* ... */
77};
78
79/**
80 * enum cgs_voltage_planes - Voltage planes for external camera HW
81 */
82enum cgs_voltage_planes {
83 CGS_VOLTAGE_PLANE__SENSOR0,
84 CGS_VOLTAGE_PLANE__SENSOR1,
85 /* ... */
86};
87
88/**
89 * struct cgs_clock_limits - Clock limits
90 *
91 * Clocks are specified in 10KHz units.
92 */
93struct cgs_clock_limits {
94 unsigned min; /**< Minimum supported frequency */
95 unsigned max; /**< Maxumim supported frequency */
96 unsigned sustainable; /**< Thermally sustainable frequency */
97};
98
99typedef unsigned long cgs_handle_t;
100
101/**
102 * cgs_gpu_mem_info() - Return information about memory heaps
103 * @cgs_device: opaque device handle
104 * @type: memory type
105 * @mc_start: Start MC address of the heap (output)
106 * @mc_size: MC address space size (output)
107 * @mem_size: maximum amount of memory available for allocation (output)
108 *
109 * This function returns information about memory heaps. The type
110 * parameter is used to select the memory heap. The mc_start and
111 * mc_size for GART heaps may be bigger than the memory available for
112 * allocation.
113 *
114 * mc_start and mc_size are undefined for non-contiguous FB memory
115 * types, since buffers allocated with these types may or may not be
116 * GART mapped.
117 *
118 * Return: 0 on success, -errno otherwise
119 */
120typedef int (*cgs_gpu_mem_info_t)(void *cgs_device, enum cgs_gpu_mem_type type,
121 uint64_t *mc_start, uint64_t *mc_size,
122 uint64_t *mem_size);
123
124/**
125 * cgs_gmap_kmem() - map kernel memory to GART aperture
126 * @cgs_device: opaque device handle
127 * @kmem: pointer to kernel memory
128 * @size: size to map
129 * @min_offset: minimum offset from start of GART aperture
130 * @max_offset: maximum offset from start of GART aperture
131 * @kmem_handle: kernel memory handle (output)
132 * @mcaddr: MC address (output)
133 *
134 * Return: 0 on success, -errno otherwise
135 */
136typedef int (*cgs_gmap_kmem_t)(void *cgs_device, void *kmem, uint64_t size,
137 uint64_t min_offset, uint64_t max_offset,
138 cgs_handle_t *kmem_handle, uint64_t *mcaddr);
139
140/**
141 * cgs_gunmap_kmem() - unmap kernel memory
142 * @cgs_device: opaque device handle
143 * @kmem_handle: kernel memory handle returned by gmap_kmem
144 *
145 * Return: 0 on success, -errno otherwise
146 */
147typedef int (*cgs_gunmap_kmem_t)(void *cgs_device, cgs_handle_t kmem_handle);
148
149/**
150 * cgs_alloc_gpu_mem() - Allocate GPU memory
151 * @cgs_device: opaque device handle
152 * @type: memory type
153 * @size: size in bytes
154 * @align: alignment in bytes
155 * @min_offset: minimum offset from start of heap
156 * @max_offset: maximum offset from start of heap
157 * @handle: memory handle (output)
158 *
159 * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous
160 * memory allocation. This guarantees that the MC address returned by
161 * cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous
162 * FB memory types may be GART mapped depending on memory
163 * fragmentation and memory allocator policies.
164 *
165 * If min/max_offset are non-0, the allocation will be forced to
166 * reside between these offsets in its respective memory heap. The
167 * base address that the offset relates to, depends on the memory
168 * type.
169 *
170 * - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address
171 * - CGS_GPU_MEM_TYPE__GART_*: GART aperture base address
172 * - others: undefined, don't use with max_offset
173 *
174 * Return: 0 on success, -errno otherwise
175 */
176typedef int (*cgs_alloc_gpu_mem_t)(void *cgs_device, enum cgs_gpu_mem_type type,
177 uint64_t size, uint64_t align,
178 uint64_t min_offset, uint64_t max_offset,
179 cgs_handle_t *handle);
180
181/**
182 * cgs_free_gpu_mem() - Free GPU memory
183 * @cgs_device: opaque device handle
184 * @handle: memory handle returned by alloc or import
185 *
186 * Return: 0 on success, -errno otherwise
187 */
188typedef int (*cgs_free_gpu_mem_t)(void *cgs_device, cgs_handle_t handle);
189
190/**
191 * cgs_gmap_gpu_mem() - GPU-map GPU memory
192 * @cgs_device: opaque device handle
193 * @handle: memory handle returned by alloc or import
194 * @mcaddr: MC address (output)
195 *
196 * Ensures that a buffer is GPU accessible and returns its MC address.
197 *
198 * Return: 0 on success, -errno otherwise
199 */
200typedef int (*cgs_gmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle,
201 uint64_t *mcaddr);
202
203/**
204 * cgs_gunmap_gpu_mem() - GPU-unmap GPU memory
205 * @cgs_device: opaque device handle
206 * @handle: memory handle returned by alloc or import
207 *
208 * Allows the buffer to be migrated while it's not used by the GPU.
209 *
210 * Return: 0 on success, -errno otherwise
211 */
212typedef int (*cgs_gunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle);
213
214/**
215 * cgs_kmap_gpu_mem() - Kernel-map GPU memory
216 *
217 * @cgs_device: opaque device handle
218 * @handle: memory handle returned by alloc or import
219 * @map: Kernel virtual address the memory was mapped to (output)
220 *
221 * Return: 0 on success, -errno otherwise
222 */
223typedef int (*cgs_kmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle,
224 void **map);
225
226/**
227 * cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory
228 * @cgs_device: opaque device handle
229 * @handle: memory handle returned by alloc or import
230 *
231 * Return: 0 on success, -errno otherwise
232 */
233typedef int (*cgs_kunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle);
234
235/**
236 * cgs_read_register() - Read an MMIO register
237 * @cgs_device: opaque device handle
238 * @offset: register offset
239 *
240 * Return: register value
241 */
242typedef uint32_t (*cgs_read_register_t)(void *cgs_device, unsigned offset);
243
244/**
245 * cgs_write_register() - Write an MMIO register
246 * @cgs_device: opaque device handle
247 * @offset: register offset
248 * @value: register value
249 */
250typedef void (*cgs_write_register_t)(void *cgs_device, unsigned offset,
251 uint32_t value);
252
253/**
254 * cgs_read_ind_register() - Read an indirect register
255 * @cgs_device: opaque device handle
256 * @offset: register offset
257 *
258 * Return: register value
259 */
260typedef uint32_t (*cgs_read_ind_register_t)(void *cgs_device, enum cgs_ind_reg space,
261 unsigned index);
262
263/**
264 * cgs_write_ind_register() - Write an indirect register
265 * @cgs_device: opaque device handle
266 * @offset: register offset
267 * @value: register value
268 */
269typedef void (*cgs_write_ind_register_t)(void *cgs_device, enum cgs_ind_reg space,
270 unsigned index, uint32_t value);
271
272/**
273 * cgs_read_pci_config_byte() - Read byte from PCI configuration space
274 * @cgs_device: opaque device handle
275 * @addr: address
276 *
277 * Return: Value read
278 */
279typedef uint8_t (*cgs_read_pci_config_byte_t)(void *cgs_device, unsigned addr);
280
281/**
282 * cgs_read_pci_config_word() - Read word from PCI configuration space
283 * @cgs_device: opaque device handle
284 * @addr: address, must be word-aligned
285 *
286 * Return: Value read
287 */
288typedef uint16_t (*cgs_read_pci_config_word_t)(void *cgs_device, unsigned addr);
289
290/**
291 * cgs_read_pci_config_dword() - Read dword from PCI configuration space
292 * @cgs_device: opaque device handle
293 * @addr: address, must be dword-aligned
294 *
295 * Return: Value read
296 */
297typedef uint32_t (*cgs_read_pci_config_dword_t)(void *cgs_device,
298 unsigned addr);
299
300/**
301 * cgs_write_pci_config_byte() - Write byte to PCI configuration space
302 * @cgs_device: opaque device handle
303 * @addr: address
304 * @value: value to write
305 */
306typedef void (*cgs_write_pci_config_byte_t)(void *cgs_device, unsigned addr,
307 uint8_t value);
308
309/**
310 * cgs_write_pci_config_word() - Write byte to PCI configuration space
311 * @cgs_device: opaque device handle
312 * @addr: address, must be word-aligned
313 * @value: value to write
314 */
315typedef void (*cgs_write_pci_config_word_t)(void *cgs_device, unsigned addr,
316 uint16_t value);
317
318/**
319 * cgs_write_pci_config_dword() - Write byte to PCI configuration space
320 * @cgs_device: opaque device handle
321 * @addr: address, must be dword-aligned
322 * @value: value to write
323 */
324typedef void (*cgs_write_pci_config_dword_t)(void *cgs_device, unsigned addr,
325 uint32_t value);
326
327/**
328 * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table
329 * @cgs_device: opaque device handle
330 * @table: data table index
331 * @size: size of the table (output, may be NULL)
332 * @frev: table format revision (output, may be NULL)
333 * @crev: table content revision (output, may be NULL)
334 *
335 * Return: Pointer to start of the table, or NULL on failure
336 */
337typedef const void *(*cgs_atom_get_data_table_t)(
338 void *cgs_device, unsigned table,
339 uint16_t *size, uint8_t *frev, uint8_t *crev);
340
341/**
342 * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions
343 * @cgs_device: opaque device handle
344 * @table: data table index
345 * @frev: table format revision (output, may be NULL)
346 * @crev: table content revision (output, may be NULL)
347 *
348 * Return: 0 on success, -errno otherwise
349 */
350typedef int (*cgs_atom_get_cmd_table_revs_t)(void *cgs_device, unsigned table,
351 uint8_t *frev, uint8_t *crev);
352
353/**
354 * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table
355 * @cgs_device: opaque device handle
356 * @table: command table index
357 * @args: arguments
358 *
359 * Return: 0 on success, -errno otherwise
360 */
361typedef int (*cgs_atom_exec_cmd_table_t)(void *cgs_device,
362 unsigned table, void *args);
363
364/**
365 * cgs_create_pm_request() - Create a power management request
366 * @cgs_device: opaque device handle
367 * @request: handle of created PM request (output)
368 *
369 * Return: 0 on success, -errno otherwise
370 */
371typedef int (*cgs_create_pm_request_t)(void *cgs_device, cgs_handle_t *request);
372
373/**
374 * cgs_destroy_pm_request() - Destroy a power management request
375 * @cgs_device: opaque device handle
376 * @request: handle of created PM request
377 *
378 * Return: 0 on success, -errno otherwise
379 */
380typedef int (*cgs_destroy_pm_request_t)(void *cgs_device, cgs_handle_t request);
381
382/**
383 * cgs_set_pm_request() - Activate or deactiveate a PM request
384 * @cgs_device: opaque device handle
385 * @request: PM request handle
386 * @active: 0 = deactivate, non-0 = activate
387 *
388 * While a PM request is active, its minimum clock requests are taken
389 * into account as the requested engines are powered up. When the
390 * request is inactive, the engines may be powered down and clocks may
391 * be lower, depending on other PM requests by other driver
392 * components.
393 *
394 * Return: 0 on success, -errno otherwise
395 */
396typedef int (*cgs_set_pm_request_t)(void *cgs_device, cgs_handle_t request,
397 int active);
398
399/**
400 * cgs_pm_request_clock() - Request a minimum frequency for a specific clock
401 * @cgs_device: opaque device handle
402 * @request: PM request handle
403 * @clock: which clock?
404 * @freq: requested min. frequency in 10KHz units (0 to clear request)
405 *
406 * Return: 0 on success, -errno otherwise
407 */
408typedef int (*cgs_pm_request_clock_t)(void *cgs_device, cgs_handle_t request,
409 enum cgs_clock clock, unsigned freq);
410
411/**
412 * cgs_pm_request_engine() - Request an engine to be powered up
413 * @cgs_device: opaque device handle
414 * @request: PM request handle
415 * @engine: which engine?
416 * @powered: 0 = powered down, non-0 = powered up
417 *
418 * Return: 0 on success, -errno otherwise
419 */
420typedef int (*cgs_pm_request_engine_t)(void *cgs_device, cgs_handle_t request,
421 enum cgs_engine engine, int powered);
422
423/**
424 * cgs_pm_query_clock_limits() - Query clock frequency limits
425 * @cgs_device: opaque device handle
426 * @clock: which clock?
427 * @limits: clock limits
428 *
429 * Return: 0 on success, -errno otherwise
430 */
431typedef int (*cgs_pm_query_clock_limits_t)(void *cgs_device,
432 enum cgs_clock clock,
433 struct cgs_clock_limits *limits);
434
435/**
436 * cgs_set_camera_voltages() - Apply specific voltages to PMIC voltage planes
437 * @cgs_device: opaque device handle
438 * @mask: bitmask of voltages to change (1<<CGS_VOLTAGE_PLANE__xyz|...)
439 * @voltages: pointer to array of voltage values in 1mV units
440 *
441 * Return: 0 on success, -errno otherwise
442 */
443typedef int (*cgs_set_camera_voltages_t)(void *cgs_device, uint32_t mask,
444 const uint32_t *voltages);
445
446struct cgs_ops {
447 /* memory management calls (similar to KFD interface) */
448 cgs_gpu_mem_info_t gpu_mem_info;
449 cgs_gmap_kmem_t gmap_kmem;
450 cgs_gunmap_kmem_t gunmap_kmem;
451 cgs_alloc_gpu_mem_t alloc_gpu_mem;
452 cgs_free_gpu_mem_t free_gpu_mem;
453 cgs_gmap_gpu_mem_t gmap_gpu_mem;
454 cgs_gunmap_gpu_mem_t gunmap_gpu_mem;
455 cgs_kmap_gpu_mem_t kmap_gpu_mem;
456 cgs_kunmap_gpu_mem_t kunmap_gpu_mem;
457 /* MMIO access */
458 cgs_read_register_t read_register;
459 cgs_write_register_t write_register;
460 cgs_read_ind_register_t read_ind_register;
461 cgs_write_ind_register_t write_ind_register;
462 /* PCI configuration space access */
463 cgs_read_pci_config_byte_t read_pci_config_byte;
464 cgs_read_pci_config_word_t read_pci_config_word;
465 cgs_read_pci_config_dword_t read_pci_config_dword;
466 cgs_write_pci_config_byte_t write_pci_config_byte;
467 cgs_write_pci_config_word_t write_pci_config_word;
468 cgs_write_pci_config_dword_t write_pci_config_dword;
469 /* ATOM BIOS */
470 cgs_atom_get_data_table_t atom_get_data_table;
471 cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs;
472 cgs_atom_exec_cmd_table_t atom_exec_cmd_table;
473 /* Power management */
474 cgs_create_pm_request_t create_pm_request;
475 cgs_destroy_pm_request_t destroy_pm_request;
476 cgs_set_pm_request_t set_pm_request;
477 cgs_pm_request_clock_t pm_request_clock;
478 cgs_pm_request_engine_t pm_request_engine;
479 cgs_pm_query_clock_limits_t pm_query_clock_limits;
480 cgs_set_camera_voltages_t set_camera_voltages;
481 /* ACPI (TODO) */
482};
483
484struct cgs_os_ops; /* To be define in OS-specific CGS header */
485
486struct cgs_device
487{
488 const struct cgs_ops *ops;
489 const struct cgs_os_ops *os_ops;
490 /* to be embedded at the start of driver private structure */
491};
492
493/* Convenience macros that make CGS indirect function calls look like
494 * normal function calls */
495#define CGS_CALL(func,dev,...) \
496 (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__))
497#define CGS_OS_CALL(func,dev,...) \
498 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__))
499
500#define cgs_gpu_mem_info(dev,type,mc_start,mc_size,mem_size) \
501 CGS_CALL(gpu_mem_info,dev,type,mc_start,mc_size,mem_size)
502#define cgs_gmap_kmem(dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) \
503 CGS_CALL(gmap_kmem,dev,kmem,size,min_off,max_off,kmem_handle,mcaddr)
504#define cgs_gummap_kmem(dev,kmem_handle) \
505 CGS_CALL(gunmap_kmem,dev,keme_handle)
506#define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) \
507 CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle)
508#define cgs_free_gpu_mem(dev,handle) \
509 CGS_CALL(free_gpu_mem,dev,handle)
510#define cgs_gmap_gpu_mem(dev,handle,mcaddr) \
511 CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr)
512#define cgs_gummap_gpu_mem(dev,handle) \
513 CGS_CALL(gunmap_gpu_mem,dev,handle)
514#define cgs_kmap_gpu_mem(dev,handle,map) \
515 CGS_CALL(kmap_gpu_mem,dev,handle,map)
516#define cgs_kunmap_gpu_mem(dev,handle) \
517 CGS_CALL(kunmap_gpu_mem,dev,handle)
518
519#define cgs_read_register(dev,offset) \
520 CGS_CALL(read_register,dev,offset)
521#define cgs_write_register(dev,offset,value) \
522 CGS_CALL(write_register,dev,offset,value)
523#define cgs_read_ind_register(dev,space,index) \
524 CGS_CALL(read_ind_register,dev,space,index)
525#define cgs_write_ind_register(dev,space,index,value) \
526 CGS_CALL(write_ind_register,dev,space,index,value)
527
528#define cgs_read_pci_config_byte(dev,addr) \
529 CGS_CALL(read_pci_config_byte,dev,addr)
530#define cgs_read_pci_config_word(dev,addr) \
531 CGS_CALL(read_pci_config_word,dev,addr)
532#define cgs_read_pci_config_dword(dev,addr) \
533 CGS_CALL(read_pci_config_dword,dev,addr)
534#define cgs_write_pci_config_byte(dev,addr,value) \
535 CGS_CALL(write_pci_config_byte,dev,addr,value)
536#define cgs_write_pci_config_word(dev,addr,value) \
537 CGS_CALL(write_pci_config_word,dev,addr,value)
538#define cgs_write_pci_config_dword(dev,addr,value) \
539 CGS_CALL(write_pci_config_dword,dev,addr,value)
540
541#define cgs_atom_get_data_table(dev,table,size,frev,crev) \
542 CGS_CALL(atom_get_data_table,dev,table,size,frev,crev)
543#define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \
544 CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev)
545#define cgs_atom_exec_cmd_table(dev,table,args) \
546 CGS_CALL(atom_exec_cmd_table,dev,table,args)
547
548#define cgs_create_pm_request(dev,request) \
549 CGS_CALL(create_pm_request,dev,request)
550#define cgs_destroy_pm_request(dev,request) \
551 CGS_CALL(destroy_pm_request,dev,request)
552#define cgs_set_pm_request(dev,request,active) \
553 CGS_CALL(set_pm_request,dev,request,active)
554#define cgs_pm_request_clock(dev,request,clock,freq) \
555 CGS_CALL(pm_request_clock,dev,request,clock,freq)
556#define cgs_pm_request_engine(dev,request,engine,powered) \
557 CGS_CALL(pm_request_engine,dev,request,engine,powered)
558#define cgs_pm_query_clock_limits(dev,clock,limits) \
559 CGS_CALL(pm_query_clock_limits,dev,clock,limits)
560#define cgs_set_camera_voltages(dev,mask,voltages) \
561 CGS_CALL(set_camera_voltages,dev,mask,voltages)
562
563#endif /* _CGS_COMMON_H */
diff --git a/drivers/gpu/drm/amd/include/cgs_linux.h b/drivers/gpu/drm/amd/include/cgs_linux.h
new file mode 100644
index 000000000000..488642f08267
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/cgs_linux.h
@@ -0,0 +1,135 @@
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#ifndef _CGS_LINUX_H
25#define _CGS_LINUX_H
26
27#include "cgs_common.h"
28
29/**
30 * cgs_import_gpu_mem() - Import dmabuf handle
31 * @cgs_device: opaque device handle
32 * @dmabuf_fd: DMABuf file descriptor
33 * @handle: memory handle (output)
34 *
35 * Must be called in the process context that dmabuf_fd belongs to.
36 *
37 * Return: 0 on success, -errno otherwise
38 */
39typedef int (*cgs_import_gpu_mem_t)(void *cgs_device, int dmabuf_fd,
40 cgs_handle_t *handle);
41
42/**
43 * cgs_irq_source_set_func() - Callback for enabling/disabling interrupt sources
44 * @private_data: private data provided to cgs_add_irq_source
45 * @src_id: interrupt source ID
46 * @type: interrupt type
47 * @enabled: 0 = disable source, non-0 = enable source
48 *
49 * Return: 0 on success, -errno otherwise
50 */
51typedef int (*cgs_irq_source_set_func_t)(void *private_data,
52 unsigned src_id, unsigned type,
53 int enabled);
54
55/**
56 * cgs_irq_handler_func() - Interrupt handler callback
57 * @private_data: private data provided to cgs_add_irq_source
58 * @src_id: interrupt source ID
59 * @iv_entry: pointer to raw ih ring entry
60 *
61 * This callback runs in interrupt context.
62 *
63 * Return: 0 on success, -errno otherwise
64 */
65typedef int (*cgs_irq_handler_func_t)(void *private_data,
66 unsigned src_id, const uint32_t *iv_entry);
67
68/**
69 * cgs_add_irq_source() - Add an IRQ source
70 * @cgs_device: opaque device handle
71 * @src_id: interrupt source ID
72 * @num_types: number of interrupt types that can be independently enabled
73 * @set: callback function to enable/disable an interrupt type
74 * @handler: interrupt handler callback
75 * @private_data: private data to pass to callback functions
76 *
77 * The same IRQ source can be added only once. Adding an IRQ source
78 * indicates ownership of that IRQ source and all its IRQ types.
79 *
80 * Return: 0 on success, -errno otherwise
81 */
82typedef int (*cgs_add_irq_source_t)(void *cgs_device, unsigned src_id,
83 unsigned num_types,
84 cgs_irq_source_set_func_t set,
85 cgs_irq_handler_func_t handler,
86 void *private_data);
87
88/**
89 * cgs_irq_get() - Request enabling an IRQ source and type
90 * @cgs_device: opaque device handle
91 * @src_id: interrupt source ID
92 * @type: interrupt type
93 *
94 * cgs_irq_get and cgs_irq_put calls must be balanced. They count
95 * "references" to IRQ sources.
96 *
97 * Return: 0 on success, -errno otherwise
98 */
99typedef int (*cgs_irq_get_t)(void *cgs_device, unsigned src_id, unsigned type);
100
101/**
102 * cgs_irq_put() - Indicate IRQ source is no longer needed
103 * @cgs_device: opaque device handle
104 * @src_id: interrupt source ID
105 * @type: interrupt type
106 *
107 * cgs_irq_get and cgs_irq_put calls must be balanced. They count
108 * "references" to IRQ sources. Even after cgs_irq_put is called, the
109 * IRQ handler may still be called if there are more refecences to
110 * the IRQ source.
111 *
112 * Return: 0 on success, -errno otherwise
113 */
114typedef int (*cgs_irq_put_t)(void *cgs_device, unsigned src_id, unsigned type);
115
116struct cgs_os_ops {
117 cgs_import_gpu_mem_t import_gpu_mem;
118
119 /* IRQ handling */
120 cgs_add_irq_source_t add_irq_source;
121 cgs_irq_get_t irq_get;
122 cgs_irq_put_t irq_put;
123};
124
125#define cgs_import_gpu_mem(dev,dmabuf_fd,handle) \
126 CGS_OS_CALL(import_gpu_mem,dev,dmabuf_fd,handle)
127#define cgs_add_irq_source(dev,src_id,num_types,set,handler,private_data) \
128 CGS_OS_CALL(add_irq_source,dev,src_id,num_types,set,handler, \
129 private_data)
130#define cgs_irq_get(dev,src_id,type) \
131 CGS_OS_CALL(irq_get,dev,src_id,type)
132#define cgs_irq_put(dev,src_id,type) \
133 CGS_OS_CALL(irq_put,dev,src_id,type)
134
135#endif /* _CGS_LINUX_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-31 20:09:29 -0400