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-rw-r--r--Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt48
-rw-r--r--Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt (renamed from Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt)61
-rw-r--r--Documentation/devicetree/bindings/thermal/armada-thermal.txt5
-rw-r--r--Documentation/devicetree/bindings/thermal/qcom-tsens.txt31
-rw-r--r--drivers/thermal/armada_thermal.c534
-rw-r--r--drivers/thermal/imx_thermal.c5
-rw-r--r--drivers/thermal/qcom/Makefile2
-rw-r--r--drivers/thermal/qcom/tsens-8996.c84
-rw-r--r--drivers/thermal/qcom/tsens-common.c29
-rw-r--r--drivers/thermal/qcom/tsens-v2.c77
-rw-r--r--drivers/thermal/qcom/tsens.c3
-rw-r--r--drivers/thermal/qcom/tsens.h8
-rw-r--r--drivers/thermal/rcar_thermal.c2
-rw-r--r--drivers/thermal/samsung/exynos_tmu.c5
-rw-r--r--drivers/thermal/thermal_hwmon.c3
-rw-r--r--drivers/thermal/ti-soc-thermal/dra752-bandgap.h68
-rw-r--r--drivers/thermal/ti-soc-thermal/dra752-thermal-data.c65
-rw-r--r--drivers/thermal/ti-soc-thermal/omap3-thermal-data.c6
-rw-r--r--drivers/thermal/ti-soc-thermal/omap4-thermal-data.c10
-rw-r--r--drivers/thermal/ti-soc-thermal/omap4xxx-bandgap.h10
-rw-r--r--drivers/thermal/ti-soc-thermal/omap5-thermal-data.c46
-rw-r--r--drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h41
-rw-r--r--drivers/thermal/ti-soc-thermal/ti-bandgap.c370
-rw-r--r--drivers/thermal/ti-soc-thermal/ti-bandgap.h43
24 files changed, 649 insertions, 907 deletions
diff --git a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
index 0b887440e08a..3fd21bb7cb37 100644
--- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
@@ -2,14 +2,17 @@ Marvell Armada AP806 System Controller
2====================================== 2======================================
3 3
4The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K 4The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K
5SoCs. It contains a system controller, which provides a number 5SoCs. It contains system controllers, which provide several registers
6registers giving access to numerous features: clocks, pin-muxing and 6giving access to numerous features: clocks, pin-muxing and many other
7many other SoC configuration items. This DT binding allows to describe 7SoC configuration items. This DT binding allows to describe these
8this system controller. 8system controllers.
9 9
10For the top level node: 10For the top level node:
11 - compatible: must be: "syscon", "simple-mfd"; 11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP806 system controller 12 - reg: register area of the AP806 system controller
13
14SYSTEM CONTROLLER 0
15===================
13 16
14Clocks: 17Clocks:
15------- 18-------
@@ -98,3 +101,38 @@ ap_syscon: system-controller@6f4000 {
98 gpio-ranges = <&ap_pinctrl 0 0 19>; 101 gpio-ranges = <&ap_pinctrl 0 0 19>;
99 }; 102 };
100}; 103};
104
105SYSTEM CONTROLLER 1
106===================
107
108Thermal:
109--------
110
111For common binding part and usage, refer to
112Documentation/devicetree/bindings/thermal/thermal.txt
113
114The thermal IP can probe the temperature all around the processor. It
115may feature several channels, each of them wired to one sensor.
116
117Required properties:
118- compatible: must be one of:
119 * marvell,armada-ap806-thermal
120- reg: register range associated with the thermal functions.
121
122Optional properties:
123- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
124 to this IP and represents the channel ID. There is one sensor per
125 channel. O refers to the thermal IP internal channel, while positive
126 IDs refer to each CPU.
127
128Example:
129ap_syscon1: system-controller@6f8000 {
130 compatible = "syscon", "simple-mfd";
131 reg = <0x6f8000 0x1000>;
132
133 ap_thermal: thermal-sensor@80 {
134 compatible = "marvell,armada-ap806-thermal";
135 reg = <0x80 0x10>;
136 #thermal-sensor-cells = <1>;
137 };
138};
diff --git a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt
index 29cdbae6c5ac..81ce742d2760 100644
--- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt
@@ -1,15 +1,18 @@
1Marvell Armada CP110 System Controller 0 1Marvell Armada CP110 System Controller
2======================================== 2======================================
3 3
4The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K 4The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K
5SoCs. It contains two sets of system control registers, System 5SoCs. It contains system controllers, which provide several registers
6Controller 0 and System Controller 1. This Device Tree binding allows 6giving access to numerous features: clocks, pin-muxing and many other
7to describe the first system controller, which provides registers to 7SoC configuration items. This DT binding allows to describe these
8configure various aspects of the SoC. 8system controllers.
9 9
10For the top level node: 10For the top level node:
11 - compatible: must be: "syscon", "simple-mfd"; 11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the CP110 system controller 0 12 - reg: register area of the CP110 system controller
13
14SYSTEM CONTROLLER 0
15===================
13 16
14Clocks: 17Clocks:
15------- 18-------
@@ -163,26 +166,60 @@ Required properties:
163 166
164Example: 167Example:
165 168
166cpm_syscon0: system-controller@440000 { 169CP110_LABEL(syscon0): system-controller@440000 {
167 compatible = "syscon", "simple-mfd"; 170 compatible = "syscon", "simple-mfd";
168 reg = <0x440000 0x1000>; 171 reg = <0x440000 0x1000>;
169 172
170 cpm_clk: clock { 173 CP110_LABEL(clk): clock {
171 compatible = "marvell,cp110-clock"; 174 compatible = "marvell,cp110-clock";
172 #clock-cells = <2>; 175 #clock-cells = <2>;
173 }; 176 };
174 177
175 cpm_pinctrl: pinctrl { 178 CP110_LABEL(pinctrl): pinctrl {
176 compatible = "marvell,armada-8k-cpm-pinctrl"; 179 compatible = "marvell,armada-8k-cpm-pinctrl";
177 }; 180 };
178 181
179 cpm_gpio1: gpio@100 { 182 CP110_LABEL(gpio1): gpio@100 {
180 compatible = "marvell,armada-8k-gpio"; 183 compatible = "marvell,armada-8k-gpio";
181 offset = <0x100>; 184 offset = <0x100>;
182 ngpios = <32>; 185 ngpios = <32>;
183 gpio-controller; 186 gpio-controller;
184 #gpio-cells = <2>; 187 #gpio-cells = <2>;
185 gpio-ranges = <&cpm_pinctrl 0 0 32>; 188 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
186 }; 189 };
187 190
188}; 191};
192
193SYSTEM CONTROLLER 1
194===================
195
196Thermal:
197--------
198
199The thermal IP can probe the temperature all around the processor. It
200may feature several channels, each of them wired to one sensor.
201
202For common binding part and usage, refer to
203Documentation/devicetree/bindings/thermal/thermal.txt
204
205Required properties:
206- compatible: must be one of:
207 * marvell,armada-cp110-thermal
208- reg: register range associated with the thermal functions.
209
210Optional properties:
211- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer
212 to this IP and represents the channel ID. There is one sensor per
213 channel. O refers to the thermal IP internal channel.
214
215Example:
216CP110_LABEL(syscon1): system-controller@6f8000 {
217 compatible = "syscon", "simple-mfd";
218 reg = <0x6f8000 0x1000>;
219
220 CP110_LABEL(thermal): thermal-sensor@70 {
221 compatible = "marvell,armada-cp110-thermal";
222 reg = <0x70 0x10>;
223 #thermal-sensor-cells = <1>;
224 };
225};
diff --git a/Documentation/devicetree/bindings/thermal/armada-thermal.txt b/Documentation/devicetree/bindings/thermal/armada-thermal.txt
index e0d013a2e66d..f3b441100890 100644
--- a/Documentation/devicetree/bindings/thermal/armada-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/armada-thermal.txt
@@ -10,6 +10,11 @@ Required properties:
10 * marvell,armada-ap806-thermal 10 * marvell,armada-ap806-thermal
11 * marvell,armada-cp110-thermal 11 * marvell,armada-cp110-thermal
12 12
13Note: these bindings are deprecated for AP806/CP110 and should instead
14follow the rules described in:
15Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
16Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt
17
13- reg: Device's register space. 18- reg: Device's register space.
14 Two entries are expected, see the examples below. The first one points 19 Two entries are expected, see the examples below. The first one points
15 to the status register (4B). The second one points to the control 20 to the status register (4B). The second one points to the control
diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt
index 06195e8f35e2..1d9e8cf61018 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt
+++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt
@@ -1,18 +1,28 @@
1* QCOM SoC Temperature Sensor (TSENS) 1* QCOM SoC Temperature Sensor (TSENS)
2 2
3Required properties: 3Required properties:
4- compatible : 4- compatible:
5 - "qcom,msm8916-tsens" : For 8916 Family of SoCs 5 Must be one of the following:
6 - "qcom,msm8974-tsens" : For 8974 Family of SoCs 6 - "qcom,msm8916-tsens" (MSM8916)
7 - "qcom,msm8996-tsens" : For 8996 Family of SoCs 7 - "qcom,msm8974-tsens" (MSM8974)
8 - "qcom,msm8996-tsens" (MSM8996)
9 - "qcom,msm8998-tsens", "qcom,tsens-v2" (MSM8998)
10 - "qcom,sdm845-tsens", "qcom,tsens-v2" (SDM845)
11 The generic "qcom,tsens-v2" property must be used as a fallback for any SoC
12 with version 2 of the TSENS IP. MSM8996 is the only exception because the
13 generic property did not exist when support was added.
14
15- reg: Address range of the thermal registers.
16 New platforms containing v2.x.y of the TSENS IP must specify the SROT and TM
17 register spaces separately, with order being TM before SROT.
18 See Example 2, below.
8 19
9- reg: Address range of the thermal registers
10- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description. 20- #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description.
11- #qcom,sensors: Number of sensors in tsens block 21- #qcom,sensors: Number of sensors in tsens block
12- Refer to Documentation/devicetree/bindings/nvmem/nvmem.txt to know how to specify 22- Refer to Documentation/devicetree/bindings/nvmem/nvmem.txt to know how to specify
13nvmem cells 23nvmem cells
14 24
15Example: 25Example 1 (legacy support before a fallback tsens-v2 property was introduced):
16tsens: thermal-sensor@900000 { 26tsens: thermal-sensor@900000 {
17 compatible = "qcom,msm8916-tsens"; 27 compatible = "qcom,msm8916-tsens";
18 reg = <0x4a8000 0x2000>; 28 reg = <0x4a8000 0x2000>;
@@ -20,3 +30,12 @@ tsens: thermal-sensor@900000 {
20 nvmem-cell-names = "caldata", "calsel"; 30 nvmem-cell-names = "caldata", "calsel";
21 #thermal-sensor-cells = <1>; 31 #thermal-sensor-cells = <1>;
22 }; 32 };
33
34Example 2 (for any platform containing v2 of the TSENS IP):
35tsens0: thermal-sensor@c263000 {
36 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
37 reg = <0xc263000 0x1ff>, /* TM */
38 <0xc222000 0x1ff>; /* SROT */
39 #qcom,sensors = <13>;
40 #thermal-sensor-cells = <1>;
41 };
diff --git a/drivers/thermal/armada_thermal.c b/drivers/thermal/armada_thermal.c
index 4c275ec10ac5..2c2f6d93034e 100644
--- a/drivers/thermal/armada_thermal.c
+++ b/drivers/thermal/armada_thermal.c
@@ -24,6 +24,8 @@
24#include <linux/of_device.h> 24#include <linux/of_device.h>
25#include <linux/thermal.h> 25#include <linux/thermal.h>
26#include <linux/iopoll.h> 26#include <linux/iopoll.h>
27#include <linux/mfd/syscon.h>
28#include <linux/regmap.h>
27 29
28/* Thermal Manager Control and Status Register */ 30/* Thermal Manager Control and Status Register */
29#define PMU_TDC0_SW_RST_MASK (0x1 << 1) 31#define PMU_TDC0_SW_RST_MASK (0x1 << 1)
@@ -39,24 +41,24 @@
39#define A375_READOUT_INVERT BIT(15) 41#define A375_READOUT_INVERT BIT(15)
40#define A375_HW_RESETn BIT(8) 42#define A375_HW_RESETn BIT(8)
41 43
42/* Legacy bindings */
43#define LEGACY_CONTROL_MEM_LEN 0x4
44
45/* Current bindings with the 2 control registers under the same memory area */
46#define LEGACY_CONTROL1_OFFSET 0x0
47#define CONTROL0_OFFSET 0x0
48#define CONTROL1_OFFSET 0x4
49
50/* Errata fields */ 44/* Errata fields */
51#define CONTROL0_TSEN_TC_TRIM_MASK 0x7 45#define CONTROL0_TSEN_TC_TRIM_MASK 0x7
52#define CONTROL0_TSEN_TC_TRIM_VAL 0x3 46#define CONTROL0_TSEN_TC_TRIM_VAL 0x3
53 47
54/* TSEN refers to the temperature sensors within the AP */
55#define CONTROL0_TSEN_START BIT(0) 48#define CONTROL0_TSEN_START BIT(0)
56#define CONTROL0_TSEN_RESET BIT(1) 49#define CONTROL0_TSEN_RESET BIT(1)
57#define CONTROL0_TSEN_ENABLE BIT(2) 50#define CONTROL0_TSEN_ENABLE BIT(2)
58 51#define CONTROL0_TSEN_AVG_BYPASS BIT(6)
59/* EXT_TSEN refers to the external temperature sensors, out of the AP */ 52#define CONTROL0_TSEN_CHAN_SHIFT 13
53#define CONTROL0_TSEN_CHAN_MASK 0xF
54#define CONTROL0_TSEN_OSR_SHIFT 24
55#define CONTROL0_TSEN_OSR_MAX 0x3
56#define CONTROL0_TSEN_MODE_SHIFT 30
57#define CONTROL0_TSEN_MODE_EXTERNAL 0x2
58#define CONTROL0_TSEN_MODE_MASK 0x3
59
60#define CONTROL1_TSEN_AVG_SHIFT 0
61#define CONTROL1_TSEN_AVG_MASK 0x7
60#define CONTROL1_EXT_TSEN_SW_RESET BIT(7) 62#define CONTROL1_EXT_TSEN_SW_RESET BIT(7)
61#define CONTROL1_EXT_TSEN_HW_RESETn BIT(8) 63#define CONTROL1_EXT_TSEN_HW_RESETn BIT(8)
62 64
@@ -67,19 +69,19 @@ struct armada_thermal_data;
67 69
68/* Marvell EBU Thermal Sensor Dev Structure */ 70/* Marvell EBU Thermal Sensor Dev Structure */
69struct armada_thermal_priv { 71struct armada_thermal_priv {
70 void __iomem *status; 72 struct device *dev;
71 void __iomem *control0; 73 struct regmap *syscon;
72 void __iomem *control1; 74 char zone_name[THERMAL_NAME_LENGTH];
75 /* serialize temperature reads/updates */
76 struct mutex update_lock;
73 struct armada_thermal_data *data; 77 struct armada_thermal_data *data;
78 int current_channel;
74}; 79};
75 80
76struct armada_thermal_data { 81struct armada_thermal_data {
77 /* Initialize the sensor */ 82 /* Initialize the thermal IC */
78 void (*init_sensor)(struct platform_device *pdev, 83 void (*init)(struct platform_device *pdev,
79 struct armada_thermal_priv *); 84 struct armada_thermal_priv *priv);
80
81 /* Test for a valid sensor value (optional) */
82 bool (*is_valid)(struct armada_thermal_priv *);
83 85
84 /* Formula coeficients: temp = (b - m * reg) / div */ 86 /* Formula coeficients: temp = (b - m * reg) / div */
85 s64 coef_b; 87 s64 coef_b;
@@ -92,141 +94,242 @@ struct armada_thermal_data {
92 unsigned int temp_shift; 94 unsigned int temp_shift;
93 unsigned int temp_mask; 95 unsigned int temp_mask;
94 u32 is_valid_bit; 96 u32 is_valid_bit;
95 bool needs_control0; 97
98 /* Syscon access */
99 unsigned int syscon_control0_off;
100 unsigned int syscon_control1_off;
101 unsigned int syscon_status_off;
102
103 /* One sensor is in the thermal IC, the others are in the CPUs if any */
104 unsigned int cpu_nr;
96}; 105};
97 106
98static void armadaxp_init_sensor(struct platform_device *pdev, 107struct armada_drvdata {
99 struct armada_thermal_priv *priv) 108 enum drvtype {
109 LEGACY,
110 SYSCON
111 } type;
112 union {
113 struct armada_thermal_priv *priv;
114 struct thermal_zone_device *tz;
115 } data;
116};
117
118/*
119 * struct armada_thermal_sensor - hold the information of one thermal sensor
120 * @thermal: pointer to the local private structure
121 * @tzd: pointer to the thermal zone device
122 * @id: identifier of the thermal sensor
123 */
124struct armada_thermal_sensor {
125 struct armada_thermal_priv *priv;
126 int id;
127};
128
129static void armadaxp_init(struct platform_device *pdev,
130 struct armada_thermal_priv *priv)
100{ 131{
132 struct armada_thermal_data *data = priv->data;
101 u32 reg; 133 u32 reg;
102 134
103 reg = readl_relaxed(priv->control1); 135 regmap_read(priv->syscon, data->syscon_control1_off, &reg);
104 reg |= PMU_TDC0_OTF_CAL_MASK; 136 reg |= PMU_TDC0_OTF_CAL_MASK;
105 writel(reg, priv->control1);
106 137
107 /* Reference calibration value */ 138 /* Reference calibration value */
108 reg &= ~PMU_TDC0_REF_CAL_CNT_MASK; 139 reg &= ~PMU_TDC0_REF_CAL_CNT_MASK;
109 reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS); 140 reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS);
110 writel(reg, priv->control1);
111 141
112 /* Reset the sensor */ 142 /* Reset the sensor */
113 reg = readl_relaxed(priv->control1); 143 reg |= PMU_TDC0_SW_RST_MASK;
114 writel((reg | PMU_TDC0_SW_RST_MASK), priv->control1);
115 144
116 writel(reg, priv->control1); 145 regmap_write(priv->syscon, data->syscon_control1_off, reg);
117 146
118 /* Enable the sensor */ 147 /* Enable the sensor */
119 reg = readl_relaxed(priv->status); 148 regmap_read(priv->syscon, data->syscon_status_off, &reg);
120 reg &= ~PMU_TM_DISABLE_MASK; 149 reg &= ~PMU_TM_DISABLE_MASK;
121 writel(reg, priv->status); 150 regmap_write(priv->syscon, data->syscon_status_off, reg);
122} 151}
123 152
124static void armada370_init_sensor(struct platform_device *pdev, 153static void armada370_init(struct platform_device *pdev,
125 struct armada_thermal_priv *priv) 154 struct armada_thermal_priv *priv)
126{ 155{
156 struct armada_thermal_data *data = priv->data;
127 u32 reg; 157 u32 reg;
128 158
129 reg = readl_relaxed(priv->control1); 159 regmap_read(priv->syscon, data->syscon_control1_off, &reg);
130 reg |= PMU_TDC0_OTF_CAL_MASK; 160 reg |= PMU_TDC0_OTF_CAL_MASK;
131 writel(reg, priv->control1);
132 161
133 /* Reference calibration value */ 162 /* Reference calibration value */
134 reg &= ~PMU_TDC0_REF_CAL_CNT_MASK; 163 reg &= ~PMU_TDC0_REF_CAL_CNT_MASK;
135 reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS); 164 reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS);
136 writel(reg, priv->control1);
137 165
166 /* Reset the sensor */
138 reg &= ~PMU_TDC0_START_CAL_MASK; 167 reg &= ~PMU_TDC0_START_CAL_MASK;
139 writel(reg, priv->control1); 168
169 regmap_write(priv->syscon, data->syscon_control1_off, reg);
140 170
141 msleep(10); 171 msleep(10);
142} 172}
143 173
144static void armada375_init_sensor(struct platform_device *pdev, 174static void armada375_init(struct platform_device *pdev,
145 struct armada_thermal_priv *priv) 175 struct armada_thermal_priv *priv)
146{ 176{
177 struct armada_thermal_data *data = priv->data;
147 u32 reg; 178 u32 reg;
148 179
149 reg = readl(priv->control1); 180 regmap_read(priv->syscon, data->syscon_control1_off, &reg);
150 reg &= ~(A375_UNIT_CONTROL_MASK << A375_UNIT_CONTROL_SHIFT); 181 reg &= ~(A375_UNIT_CONTROL_MASK << A375_UNIT_CONTROL_SHIFT);
151 reg &= ~A375_READOUT_INVERT; 182 reg &= ~A375_READOUT_INVERT;
152 reg &= ~A375_HW_RESETn; 183 reg &= ~A375_HW_RESETn;
184 regmap_write(priv->syscon, data->syscon_control1_off, reg);
153 185
154 writel(reg, priv->control1);
155 msleep(20); 186 msleep(20);
156 187
157 reg |= A375_HW_RESETn; 188 reg |= A375_HW_RESETn;
158 writel(reg, priv->control1); 189 regmap_write(priv->syscon, data->syscon_control1_off, reg);
190
159 msleep(50); 191 msleep(50);
160} 192}
161 193
162static void armada_wait_sensor_validity(struct armada_thermal_priv *priv) 194static int armada_wait_sensor_validity(struct armada_thermal_priv *priv)
163{ 195{
164 u32 reg; 196 u32 reg;
165 197
166 readl_relaxed_poll_timeout(priv->status, reg, 198 return regmap_read_poll_timeout(priv->syscon,
167 reg & priv->data->is_valid_bit, 199 priv->data->syscon_status_off, reg,
168 STATUS_POLL_PERIOD_US, 200 reg & priv->data->is_valid_bit,
169 STATUS_POLL_TIMEOUT_US); 201 STATUS_POLL_PERIOD_US,
202 STATUS_POLL_TIMEOUT_US);
170} 203}
171 204
172static void armada380_init_sensor(struct platform_device *pdev, 205static void armada380_init(struct platform_device *pdev,
173 struct armada_thermal_priv *priv) 206 struct armada_thermal_priv *priv)
174{ 207{
175 u32 reg = readl_relaxed(priv->control1); 208 struct armada_thermal_data *data = priv->data;
209 u32 reg;
176 210
177 /* Disable the HW/SW reset */ 211 /* Disable the HW/SW reset */
212 regmap_read(priv->syscon, data->syscon_control1_off, &reg);
178 reg |= CONTROL1_EXT_TSEN_HW_RESETn; 213 reg |= CONTROL1_EXT_TSEN_HW_RESETn;
179 reg &= ~CONTROL1_EXT_TSEN_SW_RESET; 214 reg &= ~CONTROL1_EXT_TSEN_SW_RESET;
180 writel(reg, priv->control1); 215 regmap_write(priv->syscon, data->syscon_control1_off, reg);
181 216
182 /* Set Tsen Tc Trim to correct default value (errata #132698) */ 217 /* Set Tsen Tc Trim to correct default value (errata #132698) */
183 if (priv->control0) { 218 regmap_read(priv->syscon, data->syscon_control0_off, &reg);
184 reg = readl_relaxed(priv->control0); 219 reg &= ~CONTROL0_TSEN_TC_TRIM_MASK;
185 reg &= ~CONTROL0_TSEN_TC_TRIM_MASK; 220 reg |= CONTROL0_TSEN_TC_TRIM_VAL;
186 reg |= CONTROL0_TSEN_TC_TRIM_VAL; 221 regmap_write(priv->syscon, data->syscon_control0_off, reg);
187 writel(reg, priv->control0);
188 }
189
190 /* Wait the sensors to be valid or the core will warn the user */
191 armada_wait_sensor_validity(priv);
192} 222}
193 223
194static void armada_ap806_init_sensor(struct platform_device *pdev, 224static void armada_ap806_init(struct platform_device *pdev,
195 struct armada_thermal_priv *priv) 225 struct armada_thermal_priv *priv)
196{ 226{
227 struct armada_thermal_data *data = priv->data;
197 u32 reg; 228 u32 reg;
198 229
199 reg = readl_relaxed(priv->control0); 230 regmap_read(priv->syscon, data->syscon_control0_off, &reg);
200 reg &= ~CONTROL0_TSEN_RESET; 231 reg &= ~CONTROL0_TSEN_RESET;
201 reg |= CONTROL0_TSEN_START | CONTROL0_TSEN_ENABLE; 232 reg |= CONTROL0_TSEN_START | CONTROL0_TSEN_ENABLE;
202 writel(reg, priv->control0);
203 233
204 /* Wait the sensors to be valid or the core will warn the user */ 234 /* Sample every ~2ms */
205 armada_wait_sensor_validity(priv); 235 reg |= CONTROL0_TSEN_OSR_MAX << CONTROL0_TSEN_OSR_SHIFT;
236
237 /* Enable average (2 samples by default) */
238 reg &= ~CONTROL0_TSEN_AVG_BYPASS;
239
240 regmap_write(priv->syscon, data->syscon_control0_off, reg);
241}
242
243static void armada_cp110_init(struct platform_device *pdev,
244 struct armada_thermal_priv *priv)
245{
246 struct armada_thermal_data *data = priv->data;
247 u32 reg;
248
249 armada380_init(pdev, priv);
250
251 /* Sample every ~2ms */
252 regmap_read(priv->syscon, data->syscon_control0_off, &reg);
253 reg |= CONTROL0_TSEN_OSR_MAX << CONTROL0_TSEN_OSR_SHIFT;
254 regmap_write(priv->syscon, data->syscon_control0_off, reg);
255
256 /* Average the output value over 2^1 = 2 samples */
257 regmap_read(priv->syscon, data->syscon_control1_off, &reg);
258 reg &= ~CONTROL1_TSEN_AVG_MASK << CONTROL1_TSEN_AVG_SHIFT;
259 reg |= 1 << CONTROL1_TSEN_AVG_SHIFT;
260 regmap_write(priv->syscon, data->syscon_control1_off, reg);
206} 261}
207 262
208static bool armada_is_valid(struct armada_thermal_priv *priv) 263static bool armada_is_valid(struct armada_thermal_priv *priv)
209{ 264{
210 u32 reg = readl_relaxed(priv->status); 265 u32 reg;
266
267 if (!priv->data->is_valid_bit)
268 return true;
269
270 regmap_read(priv->syscon, priv->data->syscon_status_off, &reg);
211 271
212 return reg & priv->data->is_valid_bit; 272 return reg & priv->data->is_valid_bit;
213} 273}
214 274
215static int armada_get_temp(struct thermal_zone_device *thermal, 275/* There is currently no board with more than one sensor per channel */
216 int *temp) 276static int armada_select_channel(struct armada_thermal_priv *priv, int channel)
217{ 277{
218 struct armada_thermal_priv *priv = thermal->devdata; 278 struct armada_thermal_data *data = priv->data;
219 u32 reg, div; 279 u32 ctrl0;
220 s64 sample, b, m; 280
281 if (channel < 0 || channel > priv->data->cpu_nr)
282 return -EINVAL;
283
284 if (priv->current_channel == channel)
285 return 0;
286
287 /* Stop the measurements */
288 regmap_read(priv->syscon, data->syscon_control0_off, &ctrl0);
289 ctrl0 &= ~CONTROL0_TSEN_START;
290 regmap_write(priv->syscon, data->syscon_control0_off, ctrl0);
291
292 /* Reset the mode, internal sensor will be automatically selected */
293 ctrl0 &= ~(CONTROL0_TSEN_MODE_MASK << CONTROL0_TSEN_MODE_SHIFT);
294
295 /* Other channels are external and should be selected accordingly */
296 if (channel) {
297 /* Change the mode to external */
298 ctrl0 |= CONTROL0_TSEN_MODE_EXTERNAL <<
299 CONTROL0_TSEN_MODE_SHIFT;
300 /* Select the sensor */
301 ctrl0 &= ~(CONTROL0_TSEN_CHAN_MASK << CONTROL0_TSEN_CHAN_SHIFT);
302 ctrl0 |= (channel - 1) << CONTROL0_TSEN_CHAN_SHIFT;
303 }
221 304
222 /* Valid check */ 305 /* Actually set the mode/channel */
223 if (priv->data->is_valid && !priv->data->is_valid(priv)) { 306 regmap_write(priv->syscon, data->syscon_control0_off, ctrl0);
224 dev_err(&thermal->device, 307 priv->current_channel = channel;
308
309 /* Re-start the measurements */
310 ctrl0 |= CONTROL0_TSEN_START;
311 regmap_write(priv->syscon, data->syscon_control0_off, ctrl0);
312
313 /*
314 * The IP has a latency of ~15ms, so after updating the selected source,
315 * we must absolutely wait for the sensor validity bit to ensure we read
316 * actual data.
317 */
318 if (armada_wait_sensor_validity(priv)) {
319 dev_err(priv->dev,
225 "Temperature sensor reading not valid\n"); 320 "Temperature sensor reading not valid\n");
226 return -EIO; 321 return -EIO;
227 } 322 }
228 323
229 reg = readl_relaxed(priv->status); 324 return 0;
325}
326
327static int armada_read_sensor(struct armada_thermal_priv *priv, int *temp)
328{
329 u32 reg, div;
330 s64 sample, b, m;
331
332 regmap_read(priv->syscon, priv->data->syscon_status_off, &reg);
230 reg = (reg >> priv->data->temp_shift) & priv->data->temp_mask; 333 reg = (reg >> priv->data->temp_shift) & priv->data->temp_mask;
231 if (priv->data->signed_sample) 334 if (priv->data->signed_sample)
232 /* The most significant bit is the sign bit */ 335 /* The most significant bit is the sign bit */
@@ -247,45 +350,93 @@ static int armada_get_temp(struct thermal_zone_device *thermal,
247 return 0; 350 return 0;
248} 351}
249 352
250static struct thermal_zone_device_ops ops = { 353static int armada_get_temp_legacy(struct thermal_zone_device *thermal,
354 int *temp)
355{
356 struct armada_thermal_priv *priv = thermal->devdata;
357 int ret;
358
359 /* Valid check */
360 if (armada_is_valid(priv)) {
361 dev_err(priv->dev,
362 "Temperature sensor reading not valid\n");
363 return -EIO;
364 }
365
366 /* Do the actual reading */
367 ret = armada_read_sensor(priv, temp);
368
369 return ret;
370}
371
372static struct thermal_zone_device_ops legacy_ops = {
373 .get_temp = armada_get_temp_legacy,
374};
375
376static int armada_get_temp(void *_sensor, int *temp)
377{
378 struct armada_thermal_sensor *sensor = _sensor;
379 struct armada_thermal_priv *priv = sensor->priv;
380 int ret;
381
382 mutex_lock(&priv->update_lock);
383
384 /* Select the desired channel */
385 ret = armada_select_channel(priv, sensor->id);
386 if (ret)
387 goto unlock_mutex;
388
389 /* Do the actual reading */
390 ret = armada_read_sensor(priv, temp);
391
392unlock_mutex:
393 mutex_unlock(&priv->update_lock);
394
395 return ret;
396}
397
398static struct thermal_zone_of_device_ops of_ops = {
251 .get_temp = armada_get_temp, 399 .get_temp = armada_get_temp,
252}; 400};
253 401
254static const struct armada_thermal_data armadaxp_data = { 402static const struct armada_thermal_data armadaxp_data = {
255 .init_sensor = armadaxp_init_sensor, 403 .init = armadaxp_init,
256 .temp_shift = 10, 404 .temp_shift = 10,
257 .temp_mask = 0x1ff, 405 .temp_mask = 0x1ff,
258 .coef_b = 3153000000ULL, 406 .coef_b = 3153000000ULL,
259 .coef_m = 10000000ULL, 407 .coef_m = 10000000ULL,
260 .coef_div = 13825, 408 .coef_div = 13825,
409 .syscon_status_off = 0xb0,
410 .syscon_control1_off = 0xd0,
261}; 411};
262 412
263static const struct armada_thermal_data armada370_data = { 413static const struct armada_thermal_data armada370_data = {
264 .is_valid = armada_is_valid, 414 .init = armada370_init,
265 .init_sensor = armada370_init_sensor,
266 .is_valid_bit = BIT(9), 415 .is_valid_bit = BIT(9),
267 .temp_shift = 10, 416 .temp_shift = 10,
268 .temp_mask = 0x1ff, 417 .temp_mask = 0x1ff,
269 .coef_b = 3153000000ULL, 418 .coef_b = 3153000000ULL,
270 .coef_m = 10000000ULL, 419 .coef_m = 10000000ULL,
271 .coef_div = 13825, 420 .coef_div = 13825,
421 .syscon_status_off = 0x0,
422 .syscon_control1_off = 0x4,
272}; 423};
273 424
274static const struct armada_thermal_data armada375_data = { 425static const struct armada_thermal_data armada375_data = {
275 .is_valid = armada_is_valid, 426 .init = armada375_init,
276 .init_sensor = armada375_init_sensor,
277 .is_valid_bit = BIT(10), 427 .is_valid_bit = BIT(10),
278 .temp_shift = 0, 428 .temp_shift = 0,
279 .temp_mask = 0x1ff, 429 .temp_mask = 0x1ff,
280 .coef_b = 3171900000ULL, 430 .coef_b = 3171900000ULL,
281 .coef_m = 10000000ULL, 431 .coef_m = 10000000ULL,
282 .coef_div = 13616, 432 .coef_div = 13616,
283 .needs_control0 = true, 433 .syscon_status_off = 0x78,
434 .syscon_control0_off = 0x7c,
435 .syscon_control1_off = 0x80,
284}; 436};
285 437
286static const struct armada_thermal_data armada380_data = { 438static const struct armada_thermal_data armada380_data = {
287 .is_valid = armada_is_valid, 439 .init = armada380_init,
288 .init_sensor = armada380_init_sensor,
289 .is_valid_bit = BIT(10), 440 .is_valid_bit = BIT(10),
290 .temp_shift = 0, 441 .temp_shift = 0,
291 .temp_mask = 0x3ff, 442 .temp_mask = 0x3ff,
@@ -293,11 +444,13 @@ static const struct armada_thermal_data armada380_data = {
293 .coef_m = 2000096ULL, 444 .coef_m = 2000096ULL,
294 .coef_div = 4201, 445 .coef_div = 4201,
295 .inverted = true, 446 .inverted = true,
447 .syscon_control0_off = 0x70,
448 .syscon_control1_off = 0x74,
449 .syscon_status_off = 0x78,
296}; 450};
297 451
298static const struct armada_thermal_data armada_ap806_data = { 452static const struct armada_thermal_data armada_ap806_data = {
299 .is_valid = armada_is_valid, 453 .init = armada_ap806_init,
300 .init_sensor = armada_ap806_init_sensor,
301 .is_valid_bit = BIT(16), 454 .is_valid_bit = BIT(16),
302 .temp_shift = 0, 455 .temp_shift = 0,
303 .temp_mask = 0x3ff, 456 .temp_mask = 0x3ff,
@@ -306,12 +459,14 @@ static const struct armada_thermal_data armada_ap806_data = {
306 .coef_div = 1, 459 .coef_div = 1,
307 .inverted = true, 460 .inverted = true,
308 .signed_sample = true, 461 .signed_sample = true,
309 .needs_control0 = true, 462 .syscon_control0_off = 0x84,
463 .syscon_control1_off = 0x88,
464 .syscon_status_off = 0x8C,
465 .cpu_nr = 4,
310}; 466};
311 467
312static const struct armada_thermal_data armada_cp110_data = { 468static const struct armada_thermal_data armada_cp110_data = {
313 .is_valid = armada_is_valid, 469 .init = armada_cp110_init,
314 .init_sensor = armada380_init_sensor,
315 .is_valid_bit = BIT(10), 470 .is_valid_bit = BIT(10),
316 .temp_shift = 0, 471 .temp_shift = 0,
317 .temp_mask = 0x3ff, 472 .temp_mask = 0x3ff,
@@ -319,7 +474,9 @@ static const struct armada_thermal_data armada_cp110_data = {
319 .coef_m = 2000096ULL, 474 .coef_m = 2000096ULL,
320 .coef_div = 4201, 475 .coef_div = 4201,
321 .inverted = true, 476 .inverted = true,
322 .needs_control0 = true, 477 .syscon_control0_off = 0x70,
478 .syscon_control1_off = 0x74,
479 .syscon_status_off = 0x78,
323}; 480};
324 481
325static const struct of_device_id armada_thermal_id_table[] = { 482static const struct of_device_id armada_thermal_id_table[] = {
@@ -353,13 +510,97 @@ static const struct of_device_id armada_thermal_id_table[] = {
353}; 510};
354MODULE_DEVICE_TABLE(of, armada_thermal_id_table); 511MODULE_DEVICE_TABLE(of, armada_thermal_id_table);
355 512
513static const struct regmap_config armada_thermal_regmap_config = {
514 .reg_bits = 32,
515 .reg_stride = 4,
516 .val_bits = 32,
517 .fast_io = true,
518};
519
520static int armada_thermal_probe_legacy(struct platform_device *pdev,
521 struct armada_thermal_priv *priv)
522{
523 struct armada_thermal_data *data = priv->data;
524 struct resource *res;
525 void __iomem *base;
526
527 /* First memory region points towards the status register */
528 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
529 if (IS_ERR(res))
530 return PTR_ERR(res);
531
532 /*
533 * Edit the resource start address and length to map over all the
534 * registers, instead of pointing at them one by one.
535 */
536 res->start -= data->syscon_status_off;
537 res->end = res->start + max(data->syscon_status_off,
538 max(data->syscon_control0_off,
539 data->syscon_control1_off)) +
540 sizeof(unsigned int) - 1;
541
542 base = devm_ioremap_resource(&pdev->dev, res);
543 if (IS_ERR(base))
544 return PTR_ERR(base);
545
546 priv->syscon = devm_regmap_init_mmio(&pdev->dev, base,
547 &armada_thermal_regmap_config);
548 if (IS_ERR(priv->syscon))
549 return PTR_ERR(priv->syscon);
550
551 return 0;
552}
553
554static int armada_thermal_probe_syscon(struct platform_device *pdev,
555 struct armada_thermal_priv *priv)
556{
557 priv->syscon = syscon_node_to_regmap(pdev->dev.parent->of_node);
558 if (IS_ERR(priv->syscon))
559 return PTR_ERR(priv->syscon);
560
561 return 0;
562}
563
564static void armada_set_sane_name(struct platform_device *pdev,
565 struct armada_thermal_priv *priv)
566{
567 const char *name = dev_name(&pdev->dev);
568 char *insane_char;
569
570 if (strlen(name) > THERMAL_NAME_LENGTH) {
571 /*
572 * When inside a system controller, the device name has the
573 * form: f06f8000.system-controller:ap-thermal so stripping
574 * after the ':' should give us a shorter but meaningful name.
575 */
576 name = strrchr(name, ':');
577 if (!name)
578 name = "armada_thermal";
579 else
580 name++;
581 }
582
583 /* Save the name locally */
584 strncpy(priv->zone_name, name, THERMAL_NAME_LENGTH - 1);
585 priv->zone_name[THERMAL_NAME_LENGTH - 1] = '\0';
586
587 /* Then check there are no '-' or hwmon core will complain */
588 do {
589 insane_char = strpbrk(priv->zone_name, "-");
590 if (insane_char)
591 *insane_char = '_';
592 } while (insane_char);
593}
594
356static int armada_thermal_probe(struct platform_device *pdev) 595static int armada_thermal_probe(struct platform_device *pdev)
357{ 596{
358 void __iomem *control = NULL; 597 struct thermal_zone_device *tz;
359 struct thermal_zone_device *thermal; 598 struct armada_thermal_sensor *sensor;
599 struct armada_drvdata *drvdata;
360 const struct of_device_id *match; 600 const struct of_device_id *match;
361 struct armada_thermal_priv *priv; 601 struct armada_thermal_priv *priv;
362 struct resource *res; 602 int sensor_id;
603 int ret;
363 604
364 match = of_match_device(armada_thermal_id_table, &pdev->dev); 605 match = of_match_device(armada_thermal_id_table, &pdev->dev);
365 if (!match) 606 if (!match)
@@ -369,58 +610,99 @@ static int armada_thermal_probe(struct platform_device *pdev)
369 if (!priv) 610 if (!priv)
370 return -ENOMEM; 611 return -ENOMEM;
371 612
372 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 613 drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
373 priv->status = devm_ioremap_resource(&pdev->dev, res); 614 if (!drvdata)
374 if (IS_ERR(priv->status)) 615 return -ENOMEM;
375 return PTR_ERR(priv->status);
376
377 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
378 control = devm_ioremap_resource(&pdev->dev, res);
379 if (IS_ERR(control))
380 return PTR_ERR(control);
381 616
617 priv->dev = &pdev->dev;
382 priv->data = (struct armada_thermal_data *)match->data; 618 priv->data = (struct armada_thermal_data *)match->data;
383 619
620 mutex_init(&priv->update_lock);
621
384 /* 622 /*
385 * Legacy DT bindings only described "control1" register (also referred 623 * Legacy DT bindings only described "control1" register (also referred
386 * as "control MSB" on old documentation). New bindings cover 624 * as "control MSB" on old documentation). Then, bindings moved to cover
387 * "control0/control LSB" and "control1/control MSB" registers within 625 * "control0/control LSB" and "control1/control MSB" registers within
388 * the same resource, which is then of size 8 instead of 4. 626 * the same resource, which was then of size 8 instead of 4.
627 *
628 * The logic of defining sporadic registers is broken. For instance, it
629 * blocked the addition of the overheat interrupt feature that needed
630 * another resource somewhere else in the same memory area. One solution
631 * is to define an overall system controller and put the thermal node
632 * into it, which requires the use of regmaps across all the driver.
389 */ 633 */
390 if (resource_size(res) == LEGACY_CONTROL_MEM_LEN) { 634 if (IS_ERR(syscon_node_to_regmap(pdev->dev.parent->of_node))) {
391 /* ->control0 unavailable in this configuration */ 635 /* Ensure device name is correct for the thermal core */
392 if (priv->data->needs_control0) { 636 armada_set_sane_name(pdev, priv);
393 dev_err(&pdev->dev, "No access to control0 register\n"); 637
394 return -EINVAL; 638 ret = armada_thermal_probe_legacy(pdev, priv);
639 if (ret)
640 return ret;
641
642 priv->data->init(pdev, priv);
643
644 /* Wait the sensors to be valid */
645 armada_wait_sensor_validity(priv);
646
647 tz = thermal_zone_device_register(priv->zone_name, 0, 0, priv,
648 &legacy_ops, NULL, 0, 0);
649 if (IS_ERR(tz)) {
650 dev_err(&pdev->dev,
651 "Failed to register thermal zone device\n");
652 return PTR_ERR(tz);
395 } 653 }
396 654
397 priv->control1 = control + LEGACY_CONTROL1_OFFSET; 655 drvdata->type = LEGACY;
398 } else { 656 drvdata->data.tz = tz;
399 priv->control0 = control + CONTROL0_OFFSET; 657 platform_set_drvdata(pdev, drvdata);
400 priv->control1 = control + CONTROL1_OFFSET; 658
659 return 0;
401 } 660 }
402 661
403 priv->data->init_sensor(pdev, priv); 662 ret = armada_thermal_probe_syscon(pdev, priv);
663 if (ret)
664 return ret;
404 665
405 thermal = thermal_zone_device_register(dev_name(&pdev->dev), 0, 0, priv, 666 priv->current_channel = -1;
406 &ops, NULL, 0, 0); 667 priv->data->init(pdev, priv);
407 if (IS_ERR(thermal)) { 668 drvdata->type = SYSCON;
408 dev_err(&pdev->dev, 669 drvdata->data.priv = priv;
409 "Failed to register thermal zone device\n"); 670 platform_set_drvdata(pdev, drvdata);
410 return PTR_ERR(thermal);
411 }
412 671
413 platform_set_drvdata(pdev, thermal); 672 /*
673 * There is one channel for the IC and one per CPU (if any), each
674 * channel has one sensor.
675 */
676 for (sensor_id = 0; sensor_id <= priv->data->cpu_nr; sensor_id++) {
677 sensor = devm_kzalloc(&pdev->dev,
678 sizeof(struct armada_thermal_sensor),
679 GFP_KERNEL);
680 if (!sensor)
681 return -ENOMEM;
682
683 /* Register the sensor */
684 sensor->priv = priv;
685 sensor->id = sensor_id;
686 tz = devm_thermal_zone_of_sensor_register(&pdev->dev,
687 sensor->id, sensor,
688 &of_ops);
689 if (IS_ERR(tz)) {
690 dev_info(&pdev->dev, "Thermal sensor %d unavailable\n",
691 sensor_id);
692 devm_kfree(&pdev->dev, sensor);
693 continue;
694 }
695 }
414 696
415 return 0; 697 return 0;
416} 698}
417 699
418static int armada_thermal_exit(struct platform_device *pdev) 700static int armada_thermal_exit(struct platform_device *pdev)
419{ 701{
420 struct thermal_zone_device *armada_thermal = 702 struct armada_drvdata *drvdata = platform_get_drvdata(pdev);
421 platform_get_drvdata(pdev);
422 703
423 thermal_zone_device_unregister(armada_thermal); 704 if (drvdata->type == LEGACY)
705 thermal_zone_device_unregister(drvdata->data.tz);
424 706
425 return 0; 707 return 0;
426} 708}
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index cbfcca828cd7..aa452acb60b6 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -605,7 +605,10 @@ static int imx_init_from_nvmem_cells(struct platform_device *pdev)
605 ret = nvmem_cell_read_u32(&pdev->dev, "calib", &val); 605 ret = nvmem_cell_read_u32(&pdev->dev, "calib", &val);
606 if (ret) 606 if (ret)
607 return ret; 607 return ret;
608 imx_init_calib(pdev, val); 608
609 ret = imx_init_calib(pdev, val);
610 if (ret)
611 return ret;
609 612
610 ret = nvmem_cell_read_u32(&pdev->dev, "temp_grade", &val); 613 ret = nvmem_cell_read_u32(&pdev->dev, "temp_grade", &val);
611 if (ret) 614 if (ret)
diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile
index 2cc2193637e7..a821929ede0b 100644
--- a/drivers/thermal/qcom/Makefile
+++ b/drivers/thermal/qcom/Makefile
@@ -1,2 +1,2 @@
1obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o 1obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o
2qcom_tsens-y += tsens.o tsens-common.o tsens-8916.o tsens-8974.o tsens-8960.o tsens-8996.o 2qcom_tsens-y += tsens.o tsens-common.o tsens-8916.o tsens-8974.o tsens-8960.o tsens-v2.o
diff --git a/drivers/thermal/qcom/tsens-8996.c b/drivers/thermal/qcom/tsens-8996.c
deleted file mode 100644
index e1f77818d8fa..000000000000
--- a/drivers/thermal/qcom/tsens-8996.c
+++ /dev/null
@@ -1,84 +0,0 @@
1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#include <linux/platform_device.h>
16#include <linux/regmap.h>
17#include "tsens.h"
18
19#define STATUS_OFFSET 0x10a0
20#define LAST_TEMP_MASK 0xfff
21#define STATUS_VALID_BIT BIT(21)
22#define CODE_SIGN_BIT BIT(11)
23
24static int get_temp_8996(struct tsens_device *tmdev, int id, int *temp)
25{
26 struct tsens_sensor *s = &tmdev->sensor[id];
27 u32 code;
28 unsigned int sensor_addr;
29 int last_temp = 0, last_temp2 = 0, last_temp3 = 0, ret;
30
31 sensor_addr = STATUS_OFFSET + s->hw_id * 4;
32 ret = regmap_read(tmdev->map, sensor_addr, &code);
33 if (ret)
34 return ret;
35 last_temp = code & LAST_TEMP_MASK;
36 if (code & STATUS_VALID_BIT)
37 goto done;
38
39 /* Try a second time */
40 ret = regmap_read(tmdev->map, sensor_addr, &code);
41 if (ret)
42 return ret;
43 if (code & STATUS_VALID_BIT) {
44 last_temp = code & LAST_TEMP_MASK;
45 goto done;
46 } else {
47 last_temp2 = code & LAST_TEMP_MASK;
48 }
49
50 /* Try a third/last time */
51 ret = regmap_read(tmdev->map, sensor_addr, &code);
52 if (ret)
53 return ret;
54 if (code & STATUS_VALID_BIT) {
55 last_temp = code & LAST_TEMP_MASK;
56 goto done;
57 } else {
58 last_temp3 = code & LAST_TEMP_MASK;
59 }
60
61 if (last_temp == last_temp2)
62 last_temp = last_temp2;
63 else if (last_temp2 == last_temp3)
64 last_temp = last_temp3;
65done:
66 /* Code sign bit is the sign extension for a negative value */
67 if (last_temp & CODE_SIGN_BIT)
68 last_temp |= ~CODE_SIGN_BIT;
69
70 /* Temperatures are in deciCelicius */
71 *temp = last_temp * 100;
72
73 return 0;
74}
75
76static const struct tsens_ops ops_8996 = {
77 .init = init_common,
78 .get_temp = get_temp_8996,
79};
80
81const struct tsens_data data_8996 = {
82 .num_sensors = 13,
83 .ops = &ops_8996,
84};
diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c
index b1449ad67fc0..6207d8d92351 100644
--- a/drivers/thermal/qcom/tsens-common.c
+++ b/drivers/thermal/qcom/tsens-common.c
@@ -16,6 +16,7 @@
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/nvmem-consumer.h> 17#include <linux/nvmem-consumer.h>
18#include <linux/of_address.h> 18#include <linux/of_address.h>
19#include <linux/of_platform.h>
19#include <linux/platform_device.h> 20#include <linux/platform_device.h>
20#include <linux/regmap.h> 21#include <linux/regmap.h>
21#include "tsens.h" 22#include "tsens.h"
@@ -103,11 +104,11 @@ int get_temp_common(struct tsens_device *tmdev, int id, int *temp)
103{ 104{
104 struct tsens_sensor *s = &tmdev->sensor[id]; 105 struct tsens_sensor *s = &tmdev->sensor[id];
105 u32 code; 106 u32 code;
106 unsigned int sensor_addr; 107 unsigned int status_reg;
107 int last_temp = 0, ret; 108 int last_temp = 0, ret;
108 109
109 sensor_addr = S0_ST_ADDR + s->hw_id * SN_ADDR_OFFSET; 110 status_reg = S0_ST_ADDR + s->hw_id * SN_ADDR_OFFSET;
110 ret = regmap_read(tmdev->map, sensor_addr, &code); 111 ret = regmap_read(tmdev->map, status_reg, &code);
111 if (ret) 112 if (ret)
112 return ret; 113 return ret;
113 last_temp = code & SN_ST_TEMP_MASK; 114 last_temp = code & SN_ST_TEMP_MASK;
@@ -126,16 +127,28 @@ static const struct regmap_config tsens_config = {
126int __init init_common(struct tsens_device *tmdev) 127int __init init_common(struct tsens_device *tmdev)
127{ 128{
128 void __iomem *base; 129 void __iomem *base;
130 struct resource *res;
131 struct platform_device *op = of_find_device_by_node(tmdev->dev->of_node);
129 132
130 base = of_iomap(tmdev->dev->of_node, 0); 133 if (!op)
131 if (!base)
132 return -EINVAL; 134 return -EINVAL;
133 135
136 /* The driver only uses the TM register address space for now */
137 if (op->num_resources > 1) {
138 tmdev->tm_offset = 0;
139 } else {
140 /* old DTs where SROT and TM were in a contiguous 2K block */
141 tmdev->tm_offset = 0x1000;
142 }
143
144 res = platform_get_resource(op, IORESOURCE_MEM, 0);
145 base = devm_ioremap_resource(&op->dev, res);
146 if (IS_ERR(base))
147 return PTR_ERR(base);
148
134 tmdev->map = devm_regmap_init_mmio(tmdev->dev, base, &tsens_config); 149 tmdev->map = devm_regmap_init_mmio(tmdev->dev, base, &tsens_config);
135 if (IS_ERR(tmdev->map)) { 150 if (IS_ERR(tmdev->map))
136 iounmap(base);
137 return PTR_ERR(tmdev->map); 151 return PTR_ERR(tmdev->map);
138 }
139 152
140 return 0; 153 return 0;
141} 154}
diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c
new file mode 100644
index 000000000000..44da02f594ac
--- /dev/null
+++ b/drivers/thermal/qcom/tsens-v2.c
@@ -0,0 +1,77 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2018, Linaro Limited
5 */
6
7#include <linux/regmap.h>
8#include <linux/bitops.h>
9#include "tsens.h"
10
11#define STATUS_OFFSET 0xa0
12#define LAST_TEMP_MASK 0xfff
13#define STATUS_VALID_BIT BIT(21)
14
15static int get_temp_tsens_v2(struct tsens_device *tmdev, int id, int *temp)
16{
17 struct tsens_sensor *s = &tmdev->sensor[id];
18 u32 code;
19 unsigned int status_reg;
20 u32 last_temp = 0, last_temp2 = 0, last_temp3 = 0;
21 int ret;
22
23 status_reg = tmdev->tm_offset + STATUS_OFFSET + s->hw_id * 4;
24 ret = regmap_read(tmdev->map, status_reg, &code);
25 if (ret)
26 return ret;
27 last_temp = code & LAST_TEMP_MASK;
28 if (code & STATUS_VALID_BIT)
29 goto done;
30
31 /* Try a second time */
32 ret = regmap_read(tmdev->map, status_reg, &code);
33 if (ret)
34 return ret;
35 if (code & STATUS_VALID_BIT) {
36 last_temp = code & LAST_TEMP_MASK;
37 goto done;
38 } else {
39 last_temp2 = code & LAST_TEMP_MASK;
40 }
41
42 /* Try a third/last time */
43 ret = regmap_read(tmdev->map, status_reg, &code);
44 if (ret)
45 return ret;
46 if (code & STATUS_VALID_BIT) {
47 last_temp = code & LAST_TEMP_MASK;
48 goto done;
49 } else {
50 last_temp3 = code & LAST_TEMP_MASK;
51 }
52
53 if (last_temp == last_temp2)
54 last_temp = last_temp2;
55 else if (last_temp2 == last_temp3)
56 last_temp = last_temp3;
57done:
58 /* Convert temperature from deciCelsius to milliCelsius */
59 *temp = sign_extend32(last_temp, fls(LAST_TEMP_MASK) - 1) * 100;
60
61 return 0;
62}
63
64static const struct tsens_ops ops_generic_v2 = {
65 .init = init_common,
66 .get_temp = get_temp_tsens_v2,
67};
68
69const struct tsens_data data_tsens_v2 = {
70 .ops = &ops_generic_v2,
71};
72
73/* Kept around for backward compatibility with old msm8996.dtsi */
74const struct tsens_data data_8996 = {
75 .num_sensors = 13,
76 .ops = &ops_generic_v2,
77};
diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c
index 3440166c2ae9..a2c9bfae3d86 100644
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -72,6 +72,9 @@ static const struct of_device_id tsens_table[] = {
72 }, { 72 }, {
73 .compatible = "qcom,msm8996-tsens", 73 .compatible = "qcom,msm8996-tsens",
74 .data = &data_8996, 74 .data = &data_8996,
75 }, {
76 .compatible = "qcom,tsens-v2",
77 .data = &data_tsens_v2,
75 }, 78 },
76 {} 79 {}
77}; 80};
diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h
index 911c1978892b..14331eb45a86 100644
--- a/drivers/thermal/qcom/tsens.h
+++ b/drivers/thermal/qcom/tsens.h
@@ -77,9 +77,8 @@ struct tsens_device {
77 struct device *dev; 77 struct device *dev;
78 u32 num_sensors; 78 u32 num_sensors;
79 struct regmap *map; 79 struct regmap *map;
80 struct regmap_field *status_field; 80 u32 tm_offset;
81 struct tsens_context ctx; 81 struct tsens_context ctx;
82 bool trdy;
83 const struct tsens_ops *ops; 82 const struct tsens_ops *ops;
84 struct tsens_sensor sensor[0]; 83 struct tsens_sensor sensor[0];
85}; 84};
@@ -89,6 +88,9 @@ void compute_intercept_slope(struct tsens_device *, u32 *, u32 *, u32);
89int init_common(struct tsens_device *); 88int init_common(struct tsens_device *);
90int get_temp_common(struct tsens_device *, int, int *); 89int get_temp_common(struct tsens_device *, int, int *);
91 90
92extern const struct tsens_data data_8916, data_8974, data_8960, data_8996; 91/* TSENS v1 targets */
92extern const struct tsens_data data_8916, data_8974, data_8960;
93/* TSENS v2 targets */
94extern const struct tsens_data data_8996, data_tsens_v2;
93 95
94#endif /* __QCOM_TSENS_H__ */ 96#endif /* __QCOM_TSENS_H__ */
diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c
index 45fb284d4c11..e77e63070e99 100644
--- a/drivers/thermal/rcar_thermal.c
+++ b/drivers/thermal/rcar_thermal.c
@@ -598,7 +598,7 @@ static int rcar_thermal_probe(struct platform_device *pdev)
598 enr_bits |= 3 << (i * 8); 598 enr_bits |= 3 << (i * 8);
599 } 599 }
600 600
601 if (enr_bits) 601 if (common->base && enr_bits)
602 rcar_thermal_common_write(common, ENR, enr_bits); 602 rcar_thermal_common_write(common, ENR, enr_bits);
603 603
604 dev_info(dev, "%d sensor probed\n", i); 604 dev_info(dev, "%d sensor probed\n", i);
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index a992e51ef065..48eef552cba4 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -789,11 +789,6 @@ static void exynos_tmu_work(struct work_struct *work)
789 struct exynos_tmu_data *data = container_of(work, 789 struct exynos_tmu_data *data = container_of(work,
790 struct exynos_tmu_data, irq_work); 790 struct exynos_tmu_data, irq_work);
791 791
792 if (!IS_ERR(data->clk_sec))
793 clk_enable(data->clk_sec);
794 if (!IS_ERR(data->clk_sec))
795 clk_disable(data->clk_sec);
796
797 thermal_zone_device_update(data->tzd, THERMAL_EVENT_UNSPECIFIED); 792 thermal_zone_device_update(data->tzd, THERMAL_EVENT_UNSPECIFIED);
798 793
799 mutex_lock(&data->lock); 794 mutex_lock(&data->lock);
diff --git a/drivers/thermal/thermal_hwmon.c b/drivers/thermal/thermal_hwmon.c
index 11278836ed12..40c69a533b24 100644
--- a/drivers/thermal/thermal_hwmon.c
+++ b/drivers/thermal/thermal_hwmon.c
@@ -142,7 +142,8 @@ int thermal_add_hwmon_sysfs(struct thermal_zone_device *tz)
142 142
143 INIT_LIST_HEAD(&hwmon->tz_list); 143 INIT_LIST_HEAD(&hwmon->tz_list);
144 strlcpy(hwmon->type, tz->type, THERMAL_NAME_LENGTH); 144 strlcpy(hwmon->type, tz->type, THERMAL_NAME_LENGTH);
145 hwmon->device = hwmon_device_register_with_info(NULL, hwmon->type, 145 strreplace(hwmon->type, '-', '_');
146 hwmon->device = hwmon_device_register_with_info(&tz->device, hwmon->type,
146 hwmon, NULL, NULL); 147 hwmon, NULL, NULL);
147 if (IS_ERR(hwmon->device)) { 148 if (IS_ERR(hwmon->device)) {
148 result = PTR_ERR(hwmon->device); 149 result = PTR_ERR(hwmon->device);
diff --git a/drivers/thermal/ti-soc-thermal/dra752-bandgap.h b/drivers/thermal/ti-soc-thermal/dra752-bandgap.h
index a31e4b5e82cd..9490cd63fa6a 100644
--- a/drivers/thermal/ti-soc-thermal/dra752-bandgap.h
+++ b/drivers/thermal/ti-soc-thermal/dra752-bandgap.h
@@ -54,56 +54,36 @@
54#define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET 0x8 54#define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET 0x8
55#define DRA752_TEMP_SENSOR_CORE_OFFSET 0x154 55#define DRA752_TEMP_SENSOR_CORE_OFFSET 0x154
56#define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET 0x1ac 56#define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET 0x1ac
57#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET 0x1c4
58#define DRA752_DTEMP_CORE_0_OFFSET 0x208
59#define DRA752_DTEMP_CORE_1_OFFSET 0x20c 57#define DRA752_DTEMP_CORE_1_OFFSET 0x20c
60#define DRA752_DTEMP_CORE_2_OFFSET 0x210 58#define DRA752_DTEMP_CORE_2_OFFSET 0x210
61#define DRA752_DTEMP_CORE_3_OFFSET 0x214
62#define DRA752_DTEMP_CORE_4_OFFSET 0x218
63 59
64/* DRA752.iva register offsets */ 60/* DRA752.iva register offsets */
65#define DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET 0x388 61#define DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET 0x388
66#define DRA752_TEMP_SENSOR_IVA_OFFSET 0x398 62#define DRA752_TEMP_SENSOR_IVA_OFFSET 0x398
67#define DRA752_BANDGAP_THRESHOLD_IVA_OFFSET 0x3a4 63#define DRA752_BANDGAP_THRESHOLD_IVA_OFFSET 0x3a4
68#define DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET 0x3b4
69#define DRA752_DTEMP_IVA_0_OFFSET 0x3d0
70#define DRA752_DTEMP_IVA_1_OFFSET 0x3d4 64#define DRA752_DTEMP_IVA_1_OFFSET 0x3d4
71#define DRA752_DTEMP_IVA_2_OFFSET 0x3d8 65#define DRA752_DTEMP_IVA_2_OFFSET 0x3d8
72#define DRA752_DTEMP_IVA_3_OFFSET 0x3dc
73#define DRA752_DTEMP_IVA_4_OFFSET 0x3e0
74 66
75/* DRA752.mpu register offsets */ 67/* DRA752.mpu register offsets */
76#define DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET 0x4 68#define DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET 0x4
77#define DRA752_TEMP_SENSOR_MPU_OFFSET 0x14c 69#define DRA752_TEMP_SENSOR_MPU_OFFSET 0x14c
78#define DRA752_BANDGAP_THRESHOLD_MPU_OFFSET 0x1a4 70#define DRA752_BANDGAP_THRESHOLD_MPU_OFFSET 0x1a4
79#define DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET 0x1bc
80#define DRA752_DTEMP_MPU_0_OFFSET 0x1e0
81#define DRA752_DTEMP_MPU_1_OFFSET 0x1e4 71#define DRA752_DTEMP_MPU_1_OFFSET 0x1e4
82#define DRA752_DTEMP_MPU_2_OFFSET 0x1e8 72#define DRA752_DTEMP_MPU_2_OFFSET 0x1e8
83#define DRA752_DTEMP_MPU_3_OFFSET 0x1ec
84#define DRA752_DTEMP_MPU_4_OFFSET 0x1f0
85 73
86/* DRA752.dspeve register offsets */ 74/* DRA752.dspeve register offsets */
87#define DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET 0x384 75#define DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET 0x384
88#define DRA752_TEMP_SENSOR_DSPEVE_OFFSET 0x394 76#define DRA752_TEMP_SENSOR_DSPEVE_OFFSET 0x394
89#define DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET 0x3a0 77#define DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET 0x3a0
90#define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET 0x3b0
91#define DRA752_DTEMP_DSPEVE_0_OFFSET 0x3bc
92#define DRA752_DTEMP_DSPEVE_1_OFFSET 0x3c0 78#define DRA752_DTEMP_DSPEVE_1_OFFSET 0x3c0
93#define DRA752_DTEMP_DSPEVE_2_OFFSET 0x3c4 79#define DRA752_DTEMP_DSPEVE_2_OFFSET 0x3c4
94#define DRA752_DTEMP_DSPEVE_3_OFFSET 0x3c8
95#define DRA752_DTEMP_DSPEVE_4_OFFSET 0x3cc
96 80
97/* DRA752.gpu register offsets */ 81/* DRA752.gpu register offsets */
98#define DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET 0x0 82#define DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET 0x0
99#define DRA752_TEMP_SENSOR_GPU_OFFSET 0x150 83#define DRA752_TEMP_SENSOR_GPU_OFFSET 0x150
100#define DRA752_BANDGAP_THRESHOLD_GPU_OFFSET 0x1a8 84#define DRA752_BANDGAP_THRESHOLD_GPU_OFFSET 0x1a8
101#define DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET 0x1c0
102#define DRA752_DTEMP_GPU_0_OFFSET 0x1f4
103#define DRA752_DTEMP_GPU_1_OFFSET 0x1f8 85#define DRA752_DTEMP_GPU_1_OFFSET 0x1f8
104#define DRA752_DTEMP_GPU_2_OFFSET 0x1fc 86#define DRA752_DTEMP_GPU_2_OFFSET 0x1fc
105#define DRA752_DTEMP_GPU_3_OFFSET 0x200
106#define DRA752_DTEMP_GPU_4_OFFSET 0x204
107 87
108/** 88/**
109 * Register bitfields for DRA752 89 * Register bitfields for DRA752
@@ -114,7 +94,6 @@
114 */ 94 */
115 95
116/* DRA752.BANDGAP_STATUS_1 */ 96/* DRA752.BANDGAP_STATUS_1 */
117#define DRA752_BANDGAP_STATUS_1_ALERT_MASK BIT(31)
118#define DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK BIT(5) 97#define DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK BIT(5)
119#define DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK BIT(4) 98#define DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK BIT(4)
120#define DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK BIT(3) 99#define DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK BIT(3)
@@ -125,10 +104,6 @@
125/* DRA752.BANDGAP_CTRL_2 */ 104/* DRA752.BANDGAP_CTRL_2 */
126#define DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK BIT(22) 105#define DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK BIT(22)
127#define DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK BIT(21) 106#define DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK BIT(21)
128#define DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK BIT(19)
129#define DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK BIT(18)
130#define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK BIT(16)
131#define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK BIT(15)
132#define DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK BIT(3) 107#define DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK BIT(3)
133#define DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK BIT(2) 108#define DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK BIT(2)
134#define DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK BIT(1) 109#define DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK BIT(1)
@@ -141,17 +116,10 @@
141#define DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK BIT(0) 116#define DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK BIT(0)
142 117
143/* DRA752.BANDGAP_CTRL_1 */ 118/* DRA752.BANDGAP_CTRL_1 */
144#define DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK (0x3 << 30)
145#define DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK (0x7 << 27) 119#define DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK (0x7 << 27)
146#define DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK BIT(23) 120#define DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK BIT(23)
147#define DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK BIT(22) 121#define DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK BIT(22)
148#define DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK BIT(21) 122#define DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK BIT(21)
149#define DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK BIT(20)
150#define DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK BIT(19)
151#define DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK BIT(18)
152#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK BIT(17)
153#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK BIT(16)
154#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK BIT(15)
155#define DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK BIT(5) 123#define DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK BIT(5)
156#define DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK BIT(4) 124#define DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK BIT(4)
157#define DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK BIT(3) 125#define DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK BIT(3)
@@ -168,22 +136,6 @@
168#define DRA752_BANDGAP_THRESHOLD_HOT_MASK (0x3ff << 16) 136#define DRA752_BANDGAP_THRESHOLD_HOT_MASK (0x3ff << 16)
169#define DRA752_BANDGAP_THRESHOLD_COLD_MASK (0x3ff << 0) 137#define DRA752_BANDGAP_THRESHOLD_COLD_MASK (0x3ff << 0)
170 138
171
172/* DRA752.BANDGAP_CUMUL_DTEMP_CORE */
173#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_MASK (0xffffffff << 0)
174
175/* DRA752.BANDGAP_CUMUL_DTEMP_IVA */
176#define DRA752_BANDGAP_CUMUL_DTEMP_IVA_MASK (0xffffffff << 0)
177
178/* DRA752.BANDGAP_CUMUL_DTEMP_MPU */
179#define DRA752_BANDGAP_CUMUL_DTEMP_MPU_MASK (0xffffffff << 0)
180
181/* DRA752.BANDGAP_CUMUL_DTEMP_DSPEVE */
182#define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_MASK (0xffffffff << 0)
183
184/* DRA752.BANDGAP_CUMUL_DTEMP_GPU */
185#define DRA752_BANDGAP_CUMUL_DTEMP_GPU_MASK (0xffffffff << 0)
186
187/** 139/**
188 * Temperature limits and thresholds for DRA752 140 * Temperature limits and thresholds for DRA752
189 * 141 *
@@ -202,10 +154,6 @@
202/* bandgap clock limits */ 154/* bandgap clock limits */
203#define DRA752_GPU_MAX_FREQ 1500000 155#define DRA752_GPU_MAX_FREQ 1500000
204#define DRA752_GPU_MIN_FREQ 1000000 156#define DRA752_GPU_MIN_FREQ 1000000
205/* sensor limits */
206#define DRA752_GPU_MIN_TEMP -40000
207#define DRA752_GPU_MAX_TEMP 125000
208#define DRA752_GPU_HYST_VAL 5000
209/* interrupts thresholds */ 157/* interrupts thresholds */
210#define DRA752_GPU_T_HOT 800 158#define DRA752_GPU_T_HOT 800
211#define DRA752_GPU_T_COLD 795 159#define DRA752_GPU_T_COLD 795
@@ -214,10 +162,6 @@
214/* bandgap clock limits */ 162/* bandgap clock limits */
215#define DRA752_MPU_MAX_FREQ 1500000 163#define DRA752_MPU_MAX_FREQ 1500000
216#define DRA752_MPU_MIN_FREQ 1000000 164#define DRA752_MPU_MIN_FREQ 1000000
217/* sensor limits */
218#define DRA752_MPU_MIN_TEMP -40000
219#define DRA752_MPU_MAX_TEMP 125000
220#define DRA752_MPU_HYST_VAL 5000
221/* interrupts thresholds */ 165/* interrupts thresholds */
222#define DRA752_MPU_T_HOT 800 166#define DRA752_MPU_T_HOT 800
223#define DRA752_MPU_T_COLD 795 167#define DRA752_MPU_T_COLD 795
@@ -226,10 +170,6 @@
226/* bandgap clock limits */ 170/* bandgap clock limits */
227#define DRA752_CORE_MAX_FREQ 1500000 171#define DRA752_CORE_MAX_FREQ 1500000
228#define DRA752_CORE_MIN_FREQ 1000000 172#define DRA752_CORE_MIN_FREQ 1000000
229/* sensor limits */
230#define DRA752_CORE_MIN_TEMP -40000
231#define DRA752_CORE_MAX_TEMP 125000
232#define DRA752_CORE_HYST_VAL 5000
233/* interrupts thresholds */ 173/* interrupts thresholds */
234#define DRA752_CORE_T_HOT 800 174#define DRA752_CORE_T_HOT 800
235#define DRA752_CORE_T_COLD 795 175#define DRA752_CORE_T_COLD 795
@@ -238,10 +178,6 @@
238/* bandgap clock limits */ 178/* bandgap clock limits */
239#define DRA752_DSPEVE_MAX_FREQ 1500000 179#define DRA752_DSPEVE_MAX_FREQ 1500000
240#define DRA752_DSPEVE_MIN_FREQ 1000000 180#define DRA752_DSPEVE_MIN_FREQ 1000000
241/* sensor limits */
242#define DRA752_DSPEVE_MIN_TEMP -40000
243#define DRA752_DSPEVE_MAX_TEMP 125000
244#define DRA752_DSPEVE_HYST_VAL 5000
245/* interrupts thresholds */ 181/* interrupts thresholds */
246#define DRA752_DSPEVE_T_HOT 800 182#define DRA752_DSPEVE_T_HOT 800
247#define DRA752_DSPEVE_T_COLD 795 183#define DRA752_DSPEVE_T_COLD 795
@@ -250,10 +186,6 @@
250/* bandgap clock limits */ 186/* bandgap clock limits */
251#define DRA752_IVA_MAX_FREQ 1500000 187#define DRA752_IVA_MAX_FREQ 1500000
252#define DRA752_IVA_MIN_FREQ 1000000 188#define DRA752_IVA_MIN_FREQ 1000000
253/* sensor limits */
254#define DRA752_IVA_MIN_TEMP -40000
255#define DRA752_IVA_MAX_TEMP 125000
256#define DRA752_IVA_HYST_VAL 5000
257/* interrupts thresholds */ 189/* interrupts thresholds */
258#define DRA752_IVA_T_HOT 800 190#define DRA752_IVA_T_HOT 800
259#define DRA752_IVA_T_COLD 795 191#define DRA752_IVA_T_COLD 795
diff --git a/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c b/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c
index 4167373327d9..33a3030aa3c0 100644
--- a/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c
+++ b/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c
@@ -41,24 +41,16 @@ dra752_core_temp_sensor_registers = {
41 .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET, 41 .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
42 .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK, 42 .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK,
43 .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK, 43 .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK,
44 .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
45 .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, 44 .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
46 .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK, 45 .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK,
47 .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK,
48 .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK,
49 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_CORE_OFFSET, 46 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_CORE_OFFSET,
50 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, 47 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
51 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, 48 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
52 .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET, 49 .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
53 .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
54 .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK, 50 .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK,
55 .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK, 51 .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK,
56 .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET,
57 .ctrl_dtemp_0 = DRA752_DTEMP_CORE_0_OFFSET,
58 .ctrl_dtemp_1 = DRA752_DTEMP_CORE_1_OFFSET, 52 .ctrl_dtemp_1 = DRA752_DTEMP_CORE_1_OFFSET,
59 .ctrl_dtemp_2 = DRA752_DTEMP_CORE_2_OFFSET, 53 .ctrl_dtemp_2 = DRA752_DTEMP_CORE_2_OFFSET,
60 .ctrl_dtemp_3 = DRA752_DTEMP_CORE_3_OFFSET,
61 .ctrl_dtemp_4 = DRA752_DTEMP_CORE_4_OFFSET,
62 .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET, 54 .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET,
63}; 55};
64 56
@@ -74,24 +66,16 @@ dra752_iva_temp_sensor_registers = {
74 .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET, 66 .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
75 .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK, 67 .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK,
76 .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK, 68 .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK,
77 .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
78 .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, 69 .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
79 .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK, 70 .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK,
80 .mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK,
81 .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK,
82 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_IVA_OFFSET, 71 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_IVA_OFFSET,
83 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, 72 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
84 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, 73 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
85 .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET, 74 .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
86 .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
87 .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK, 75 .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK,
88 .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK, 76 .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK,
89 .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET,
90 .ctrl_dtemp_0 = DRA752_DTEMP_IVA_0_OFFSET,
91 .ctrl_dtemp_1 = DRA752_DTEMP_IVA_1_OFFSET, 77 .ctrl_dtemp_1 = DRA752_DTEMP_IVA_1_OFFSET,
92 .ctrl_dtemp_2 = DRA752_DTEMP_IVA_2_OFFSET, 78 .ctrl_dtemp_2 = DRA752_DTEMP_IVA_2_OFFSET,
93 .ctrl_dtemp_3 = DRA752_DTEMP_IVA_3_OFFSET,
94 .ctrl_dtemp_4 = DRA752_DTEMP_IVA_4_OFFSET,
95 .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET, 79 .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET,
96}; 80};
97 81
@@ -107,24 +91,16 @@ dra752_mpu_temp_sensor_registers = {
107 .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET, 91 .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
108 .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK, 92 .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK,
109 .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK, 93 .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK,
110 .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
111 .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, 94 .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
112 .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK, 95 .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK,
113 .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK,
114 .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK,
115 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_MPU_OFFSET, 96 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_MPU_OFFSET,
116 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, 97 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
117 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, 98 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
118 .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET, 99 .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
119 .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
120 .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK, 100 .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK,
121 .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK, 101 .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK,
122 .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET,
123 .ctrl_dtemp_0 = DRA752_DTEMP_MPU_0_OFFSET,
124 .ctrl_dtemp_1 = DRA752_DTEMP_MPU_1_OFFSET, 102 .ctrl_dtemp_1 = DRA752_DTEMP_MPU_1_OFFSET,
125 .ctrl_dtemp_2 = DRA752_DTEMP_MPU_2_OFFSET, 103 .ctrl_dtemp_2 = DRA752_DTEMP_MPU_2_OFFSET,
126 .ctrl_dtemp_3 = DRA752_DTEMP_MPU_3_OFFSET,
127 .ctrl_dtemp_4 = DRA752_DTEMP_MPU_4_OFFSET,
128 .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET, 104 .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET,
129}; 105};
130 106
@@ -140,24 +116,16 @@ dra752_dspeve_temp_sensor_registers = {
140 .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET, 116 .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
141 .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK, 117 .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK,
142 .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK, 118 .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK,
143 .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
144 .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, 119 .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
145 .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK, 120 .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK,
146 .mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK,
147 .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK,
148 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET, 121 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET,
149 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, 122 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
150 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, 123 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
151 .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET, 124 .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
152 .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
153 .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK, 125 .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK,
154 .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK, 126 .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK,
155 .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET,
156 .ctrl_dtemp_0 = DRA752_DTEMP_DSPEVE_0_OFFSET,
157 .ctrl_dtemp_1 = DRA752_DTEMP_DSPEVE_1_OFFSET, 127 .ctrl_dtemp_1 = DRA752_DTEMP_DSPEVE_1_OFFSET,
158 .ctrl_dtemp_2 = DRA752_DTEMP_DSPEVE_2_OFFSET, 128 .ctrl_dtemp_2 = DRA752_DTEMP_DSPEVE_2_OFFSET,
159 .ctrl_dtemp_3 = DRA752_DTEMP_DSPEVE_3_OFFSET,
160 .ctrl_dtemp_4 = DRA752_DTEMP_DSPEVE_4_OFFSET,
161 .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET, 129 .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET,
162}; 130};
163 131
@@ -173,24 +141,16 @@ dra752_gpu_temp_sensor_registers = {
173 .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET, 141 .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
174 .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK, 142 .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK,
175 .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK, 143 .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK,
176 .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
177 .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, 144 .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
178 .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK, 145 .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK,
179 .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK,
180 .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK,
181 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_GPU_OFFSET, 146 .bgap_threshold = DRA752_BANDGAP_THRESHOLD_GPU_OFFSET,
182 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK, 147 .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
183 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK, 148 .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
184 .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET, 149 .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
185 .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
186 .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK, 150 .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK,
187 .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK, 151 .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK,
188 .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET,
189 .ctrl_dtemp_0 = DRA752_DTEMP_GPU_0_OFFSET,
190 .ctrl_dtemp_1 = DRA752_DTEMP_GPU_1_OFFSET, 152 .ctrl_dtemp_1 = DRA752_DTEMP_GPU_1_OFFSET,
191 .ctrl_dtemp_2 = DRA752_DTEMP_GPU_2_OFFSET, 153 .ctrl_dtemp_2 = DRA752_DTEMP_GPU_2_OFFSET,
192 .ctrl_dtemp_3 = DRA752_DTEMP_GPU_3_OFFSET,
193 .ctrl_dtemp_4 = DRA752_DTEMP_GPU_4_OFFSET,
194 .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET, 154 .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET,
195}; 155};
196 156
@@ -200,11 +160,6 @@ static struct temp_sensor_data dra752_mpu_temp_sensor_data = {
200 .t_cold = DRA752_MPU_T_COLD, 160 .t_cold = DRA752_MPU_T_COLD,
201 .min_freq = DRA752_MPU_MIN_FREQ, 161 .min_freq = DRA752_MPU_MIN_FREQ,
202 .max_freq = DRA752_MPU_MAX_FREQ, 162 .max_freq = DRA752_MPU_MAX_FREQ,
203 .max_temp = DRA752_MPU_MAX_TEMP,
204 .min_temp = DRA752_MPU_MIN_TEMP,
205 .hyst_val = DRA752_MPU_HYST_VAL,
206 .update_int1 = 1000,
207 .update_int2 = 2000,
208}; 163};
209 164
210/* Thresholds and limits for DRA752 GPU temperature sensor */ 165/* Thresholds and limits for DRA752 GPU temperature sensor */
@@ -213,11 +168,6 @@ static struct temp_sensor_data dra752_gpu_temp_sensor_data = {
213 .t_cold = DRA752_GPU_T_COLD, 168 .t_cold = DRA752_GPU_T_COLD,
214 .min_freq = DRA752_GPU_MIN_FREQ, 169 .min_freq = DRA752_GPU_MIN_FREQ,
215 .max_freq = DRA752_GPU_MAX_FREQ, 170 .max_freq = DRA752_GPU_MAX_FREQ,
216 .max_temp = DRA752_GPU_MAX_TEMP,
217 .min_temp = DRA752_GPU_MIN_TEMP,
218 .hyst_val = DRA752_GPU_HYST_VAL,
219 .update_int1 = 1000,
220 .update_int2 = 2000,
221}; 171};
222 172
223/* Thresholds and limits for DRA752 CORE temperature sensor */ 173/* Thresholds and limits for DRA752 CORE temperature sensor */
@@ -226,11 +176,6 @@ static struct temp_sensor_data dra752_core_temp_sensor_data = {
226 .t_cold = DRA752_CORE_T_COLD, 176 .t_cold = DRA752_CORE_T_COLD,
227 .min_freq = DRA752_CORE_MIN_FREQ, 177 .min_freq = DRA752_CORE_MIN_FREQ,
228 .max_freq = DRA752_CORE_MAX_FREQ, 178 .max_freq = DRA752_CORE_MAX_FREQ,
229 .max_temp = DRA752_CORE_MAX_TEMP,
230 .min_temp = DRA752_CORE_MIN_TEMP,
231 .hyst_val = DRA752_CORE_HYST_VAL,
232 .update_int1 = 1000,
233 .update_int2 = 2000,
234}; 179};
235 180
236/* Thresholds and limits for DRA752 DSPEVE temperature sensor */ 181/* Thresholds and limits for DRA752 DSPEVE temperature sensor */
@@ -239,11 +184,6 @@ static struct temp_sensor_data dra752_dspeve_temp_sensor_data = {
239 .t_cold = DRA752_DSPEVE_T_COLD, 184 .t_cold = DRA752_DSPEVE_T_COLD,
240 .min_freq = DRA752_DSPEVE_MIN_FREQ, 185 .min_freq = DRA752_DSPEVE_MIN_FREQ,
241 .max_freq = DRA752_DSPEVE_MAX_FREQ, 186 .max_freq = DRA752_DSPEVE_MAX_FREQ,
242 .max_temp = DRA752_DSPEVE_MAX_TEMP,
243 .min_temp = DRA752_DSPEVE_MIN_TEMP,
244 .hyst_val = DRA752_DSPEVE_HYST_VAL,
245 .update_int1 = 1000,
246 .update_int2 = 2000,
247}; 187};
248 188
249/* Thresholds and limits for DRA752 IVA temperature sensor */ 189/* Thresholds and limits for DRA752 IVA temperature sensor */
@@ -252,11 +192,6 @@ static struct temp_sensor_data dra752_iva_temp_sensor_data = {
252 .t_cold = DRA752_IVA_T_COLD, 192 .t_cold = DRA752_IVA_T_COLD,
253 .min_freq = DRA752_IVA_MIN_FREQ, 193 .min_freq = DRA752_IVA_MIN_FREQ,
254 .max_freq = DRA752_IVA_MAX_FREQ, 194 .max_freq = DRA752_IVA_MAX_FREQ,
255 .max_temp = DRA752_IVA_MAX_TEMP,
256 .min_temp = DRA752_IVA_MIN_TEMP,
257 .hyst_val = DRA752_IVA_HYST_VAL,
258 .update_int1 = 1000,
259 .update_int2 = 2000,
260}; 195};
261 196
262/* 197/*
diff --git a/drivers/thermal/ti-soc-thermal/omap3-thermal-data.c b/drivers/thermal/ti-soc-thermal/omap3-thermal-data.c
index c6d217913dd1..f5366807daf0 100644
--- a/drivers/thermal/ti-soc-thermal/omap3-thermal-data.c
+++ b/drivers/thermal/ti-soc-thermal/omap3-thermal-data.c
@@ -48,9 +48,6 @@ omap34xx_mpu_temp_sensor_registers = {
48static struct temp_sensor_data omap34xx_mpu_temp_sensor_data = { 48static struct temp_sensor_data omap34xx_mpu_temp_sensor_data = {
49 .min_freq = 32768, 49 .min_freq = 32768,
50 .max_freq = 32768, 50 .max_freq = 32768,
51 .max_temp = 125000,
52 .min_temp = -40000,
53 .hyst_val = 5000,
54}; 51};
55 52
56/* 53/*
@@ -119,9 +116,6 @@ omap36xx_mpu_temp_sensor_registers = {
119static struct temp_sensor_data omap36xx_mpu_temp_sensor_data = { 116static struct temp_sensor_data omap36xx_mpu_temp_sensor_data = {
120 .min_freq = 32768, 117 .min_freq = 32768,
121 .max_freq = 32768, 118 .max_freq = 32768,
122 .max_temp = 125000,
123 .min_temp = -40000,
124 .hyst_val = 5000,
125}; 119};
126 120
127/* 121/*
diff --git a/drivers/thermal/ti-soc-thermal/omap4-thermal-data.c b/drivers/thermal/ti-soc-thermal/omap4-thermal-data.c
index fd1113360603..c12211eaaac4 100644
--- a/drivers/thermal/ti-soc-thermal/omap4-thermal-data.c
+++ b/drivers/thermal/ti-soc-thermal/omap4-thermal-data.c
@@ -42,9 +42,6 @@ omap4430_mpu_temp_sensor_registers = {
42static struct temp_sensor_data omap4430_mpu_temp_sensor_data = { 42static struct temp_sensor_data omap4430_mpu_temp_sensor_data = {
43 .min_freq = OMAP4430_MIN_FREQ, 43 .min_freq = OMAP4430_MIN_FREQ,
44 .max_freq = OMAP4430_MAX_FREQ, 44 .max_freq = OMAP4430_MAX_FREQ,
45 .max_temp = OMAP4430_MAX_TEMP,
46 .min_temp = OMAP4430_MIN_TEMP,
47 .hyst_val = OMAP4430_HYST_VAL,
48}; 45};
49 46
50/* 47/*
@@ -121,8 +118,6 @@ omap4460_mpu_temp_sensor_registers = {
121 .tshut_cold_mask = OMAP4460_TSHUT_COLD_MASK, 118 .tshut_cold_mask = OMAP4460_TSHUT_COLD_MASK,
122 119
123 .bgap_status = OMAP4460_BGAP_STATUS_OFFSET, 120 .bgap_status = OMAP4460_BGAP_STATUS_OFFSET,
124 .status_clean_stop_mask = OMAP4460_CLEAN_STOP_MASK,
125 .status_bgap_alert_mask = OMAP4460_BGAP_ALERT_MASK,
126 .status_hot_mask = OMAP4460_HOT_FLAG_MASK, 121 .status_hot_mask = OMAP4460_HOT_FLAG_MASK,
127 .status_cold_mask = OMAP4460_COLD_FLAG_MASK, 122 .status_cold_mask = OMAP4460_COLD_FLAG_MASK,
128 123
@@ -137,11 +132,6 @@ static struct temp_sensor_data omap4460_mpu_temp_sensor_data = {
137 .t_cold = OMAP4460_T_COLD, 132 .t_cold = OMAP4460_T_COLD,
138 .min_freq = OMAP4460_MIN_FREQ, 133 .min_freq = OMAP4460_MIN_FREQ,
139 .max_freq = OMAP4460_MAX_FREQ, 134 .max_freq = OMAP4460_MAX_FREQ,
140 .max_temp = OMAP4460_MAX_TEMP,
141 .min_temp = OMAP4460_MIN_TEMP,
142 .hyst_val = OMAP4460_HYST_VAL,
143 .update_int1 = 1000,
144 .update_int2 = 2000,
145}; 135};
146 136
147/* 137/*
diff --git a/drivers/thermal/ti-soc-thermal/omap4xxx-bandgap.h b/drivers/thermal/ti-soc-thermal/omap4xxx-bandgap.h
index 6f2de3a3356d..b87c8659ec60 100644
--- a/drivers/thermal/ti-soc-thermal/omap4xxx-bandgap.h
+++ b/drivers/thermal/ti-soc-thermal/omap4xxx-bandgap.h
@@ -73,10 +73,6 @@
73/* bandgap clock limits (no control on 4430) */ 73/* bandgap clock limits (no control on 4430) */
74#define OMAP4430_MAX_FREQ 32768 74#define OMAP4430_MAX_FREQ 32768
75#define OMAP4430_MIN_FREQ 32768 75#define OMAP4430_MIN_FREQ 32768
76/* sensor limits */
77#define OMAP4430_MIN_TEMP -40000
78#define OMAP4430_MAX_TEMP 125000
79#define OMAP4430_HYST_VAL 5000
80 76
81/** 77/**
82 * *** OMAP4460 *** Applicable for OMAP4470 78 * *** OMAP4460 *** Applicable for OMAP4470
@@ -143,8 +139,6 @@
143#define OMAP4460_TSHUT_COLD_MASK (0x3ff << 0) 139#define OMAP4460_TSHUT_COLD_MASK (0x3ff << 0)
144 140
145/* OMAP4460.BANDGAP_STATUS bits */ 141/* OMAP4460.BANDGAP_STATUS bits */
146#define OMAP4460_CLEAN_STOP_MASK BIT(3)
147#define OMAP4460_BGAP_ALERT_MASK BIT(2)
148#define OMAP4460_HOT_FLAG_MASK BIT(1) 142#define OMAP4460_HOT_FLAG_MASK BIT(1)
149#define OMAP4460_COLD_FLAG_MASK BIT(0) 143#define OMAP4460_COLD_FLAG_MASK BIT(0)
150 144
@@ -162,10 +156,6 @@
162/* bandgap clock limits */ 156/* bandgap clock limits */
163#define OMAP4460_MAX_FREQ 1500000 157#define OMAP4460_MAX_FREQ 1500000
164#define OMAP4460_MIN_FREQ 1000000 158#define OMAP4460_MIN_FREQ 1000000
165/* sensor limits */
166#define OMAP4460_MIN_TEMP -40000
167#define OMAP4460_MAX_TEMP 123000
168#define OMAP4460_HYST_VAL 5000
169/* interrupts thresholds */ 159/* interrupts thresholds */
170#define OMAP4460_TSHUT_HOT 900 /* 122 deg C */ 160#define OMAP4460_TSHUT_HOT 900 /* 122 deg C */
171#define OMAP4460_TSHUT_COLD 895 /* 100 deg C */ 161#define OMAP4460_TSHUT_COLD 895 /* 100 deg C */
diff --git a/drivers/thermal/ti-soc-thermal/omap5-thermal-data.c b/drivers/thermal/ti-soc-thermal/omap5-thermal-data.c
index 6ac037098b52..8191bae834de 100644
--- a/drivers/thermal/ti-soc-thermal/omap5-thermal-data.c
+++ b/drivers/thermal/ti-soc-thermal/omap5-thermal-data.c
@@ -38,12 +38,8 @@ omap5430_mpu_temp_sensor_registers = {
38 .bgap_mask_ctrl = OMAP5430_BGAP_CTRL_OFFSET, 38 .bgap_mask_ctrl = OMAP5430_BGAP_CTRL_OFFSET,
39 .mask_hot_mask = OMAP5430_MASK_HOT_MPU_MASK, 39 .mask_hot_mask = OMAP5430_MASK_HOT_MPU_MASK,
40 .mask_cold_mask = OMAP5430_MASK_COLD_MPU_MASK, 40 .mask_cold_mask = OMAP5430_MASK_COLD_MPU_MASK,
41 .mask_sidlemode_mask = OMAP5430_MASK_SIDLEMODE_MASK,
42 .mask_counter_delay_mask = OMAP5430_MASK_COUNTER_DELAY_MASK, 41 .mask_counter_delay_mask = OMAP5430_MASK_COUNTER_DELAY_MASK,
43 .mask_freeze_mask = OMAP5430_MASK_FREEZE_MPU_MASK, 42 .mask_freeze_mask = OMAP5430_MASK_FREEZE_MPU_MASK,
44 .mask_clear_mask = OMAP5430_MASK_CLEAR_MPU_MASK,
45 .mask_clear_accum_mask = OMAP5430_MASK_CLEAR_ACCUM_MPU_MASK,
46
47 43
48 .bgap_counter = OMAP5430_BGAP_CTRL_OFFSET, 44 .bgap_counter = OMAP5430_BGAP_CTRL_OFFSET,
49 .counter_mask = OMAP5430_COUNTER_MASK, 45 .counter_mask = OMAP5430_COUNTER_MASK,
@@ -57,17 +53,11 @@ omap5430_mpu_temp_sensor_registers = {
57 .tshut_cold_mask = OMAP5430_TSHUT_COLD_MASK, 53 .tshut_cold_mask = OMAP5430_TSHUT_COLD_MASK,
58 54
59 .bgap_status = OMAP5430_BGAP_STATUS_OFFSET, 55 .bgap_status = OMAP5430_BGAP_STATUS_OFFSET,
60 .status_clean_stop_mask = 0x0,
61 .status_bgap_alert_mask = OMAP5430_BGAP_ALERT_MASK,
62 .status_hot_mask = OMAP5430_HOT_MPU_FLAG_MASK, 56 .status_hot_mask = OMAP5430_HOT_MPU_FLAG_MASK,
63 .status_cold_mask = OMAP5430_COLD_MPU_FLAG_MASK, 57 .status_cold_mask = OMAP5430_COLD_MPU_FLAG_MASK,
64 58
65 .bgap_cumul_dtemp = OMAP5430_BGAP_CUMUL_DTEMP_MPU_OFFSET,
66 .ctrl_dtemp_0 = OMAP5430_BGAP_DTEMP_MPU_0_OFFSET,
67 .ctrl_dtemp_1 = OMAP5430_BGAP_DTEMP_MPU_1_OFFSET, 59 .ctrl_dtemp_1 = OMAP5430_BGAP_DTEMP_MPU_1_OFFSET,
68 .ctrl_dtemp_2 = OMAP5430_BGAP_DTEMP_MPU_2_OFFSET, 60 .ctrl_dtemp_2 = OMAP5430_BGAP_DTEMP_MPU_2_OFFSET,
69 .ctrl_dtemp_3 = OMAP5430_BGAP_DTEMP_MPU_3_OFFSET,
70 .ctrl_dtemp_4 = OMAP5430_BGAP_DTEMP_MPU_4_OFFSET,
71 .bgap_efuse = OMAP5430_FUSE_OPP_BGAP_MPU, 61 .bgap_efuse = OMAP5430_FUSE_OPP_BGAP_MPU,
72}; 62};
73 63
@@ -84,11 +74,8 @@ omap5430_gpu_temp_sensor_registers = {
84 .bgap_mask_ctrl = OMAP5430_BGAP_CTRL_OFFSET, 74 .bgap_mask_ctrl = OMAP5430_BGAP_CTRL_OFFSET,
85 .mask_hot_mask = OMAP5430_MASK_HOT_GPU_MASK, 75 .mask_hot_mask = OMAP5430_MASK_HOT_GPU_MASK,
86 .mask_cold_mask = OMAP5430_MASK_COLD_GPU_MASK, 76 .mask_cold_mask = OMAP5430_MASK_COLD_GPU_MASK,
87 .mask_sidlemode_mask = OMAP5430_MASK_SIDLEMODE_MASK,
88 .mask_counter_delay_mask = OMAP5430_MASK_COUNTER_DELAY_MASK, 77 .mask_counter_delay_mask = OMAP5430_MASK_COUNTER_DELAY_MASK,
89 .mask_freeze_mask = OMAP5430_MASK_FREEZE_GPU_MASK, 78 .mask_freeze_mask = OMAP5430_MASK_FREEZE_GPU_MASK,
90 .mask_clear_mask = OMAP5430_MASK_CLEAR_GPU_MASK,
91 .mask_clear_accum_mask = OMAP5430_MASK_CLEAR_ACCUM_GPU_MASK,
92 79
93 .bgap_counter = OMAP5430_BGAP_CTRL_OFFSET, 80 .bgap_counter = OMAP5430_BGAP_CTRL_OFFSET,
94 .counter_mask = OMAP5430_COUNTER_MASK, 81 .counter_mask = OMAP5430_COUNTER_MASK,
@@ -102,17 +89,11 @@ omap5430_gpu_temp_sensor_registers = {
102 .tshut_cold_mask = OMAP5430_TSHUT_COLD_MASK, 89 .tshut_cold_mask = OMAP5430_TSHUT_COLD_MASK,
103 90
104 .bgap_status = OMAP5430_BGAP_STATUS_OFFSET, 91 .bgap_status = OMAP5430_BGAP_STATUS_OFFSET,
105 .status_clean_stop_mask = 0x0,
106 .status_bgap_alert_mask = OMAP5430_BGAP_ALERT_MASK,
107 .status_hot_mask = OMAP5430_HOT_GPU_FLAG_MASK, 92 .status_hot_mask = OMAP5430_HOT_GPU_FLAG_MASK,
108 .status_cold_mask = OMAP5430_COLD_GPU_FLAG_MASK, 93 .status_cold_mask = OMAP5430_COLD_GPU_FLAG_MASK,
109 94
110 .bgap_cumul_dtemp = OMAP5430_BGAP_CUMUL_DTEMP_GPU_OFFSET,
111 .ctrl_dtemp_0 = OMAP5430_BGAP_DTEMP_GPU_0_OFFSET,
112 .ctrl_dtemp_1 = OMAP5430_BGAP_DTEMP_GPU_1_OFFSET, 95 .ctrl_dtemp_1 = OMAP5430_BGAP_DTEMP_GPU_1_OFFSET,
113 .ctrl_dtemp_2 = OMAP5430_BGAP_DTEMP_GPU_2_OFFSET, 96 .ctrl_dtemp_2 = OMAP5430_BGAP_DTEMP_GPU_2_OFFSET,
114 .ctrl_dtemp_3 = OMAP5430_BGAP_DTEMP_GPU_3_OFFSET,
115 .ctrl_dtemp_4 = OMAP5430_BGAP_DTEMP_GPU_4_OFFSET,
116 97
117 .bgap_efuse = OMAP5430_FUSE_OPP_BGAP_GPU, 98 .bgap_efuse = OMAP5430_FUSE_OPP_BGAP_GPU,
118}; 99};
@@ -130,11 +111,8 @@ omap5430_core_temp_sensor_registers = {
130 .bgap_mask_ctrl = OMAP5430_BGAP_CTRL_OFFSET, 111 .bgap_mask_ctrl = OMAP5430_BGAP_CTRL_OFFSET,
131 .mask_hot_mask = OMAP5430_MASK_HOT_CORE_MASK, 112 .mask_hot_mask = OMAP5430_MASK_HOT_CORE_MASK,
132 .mask_cold_mask = OMAP5430_MASK_COLD_CORE_MASK, 113 .mask_cold_mask = OMAP5430_MASK_COLD_CORE_MASK,
133 .mask_sidlemode_mask = OMAP5430_MASK_SIDLEMODE_MASK,
134 .mask_counter_delay_mask = OMAP5430_MASK_COUNTER_DELAY_MASK, 114 .mask_counter_delay_mask = OMAP5430_MASK_COUNTER_DELAY_MASK,
135 .mask_freeze_mask = OMAP5430_MASK_FREEZE_CORE_MASK, 115 .mask_freeze_mask = OMAP5430_MASK_FREEZE_CORE_MASK,
136 .mask_clear_mask = OMAP5430_MASK_CLEAR_CORE_MASK,
137 .mask_clear_accum_mask = OMAP5430_MASK_CLEAR_ACCUM_CORE_MASK,
138 116
139 .bgap_counter = OMAP5430_BGAP_CTRL_OFFSET, 117 .bgap_counter = OMAP5430_BGAP_CTRL_OFFSET,
140 .counter_mask = OMAP5430_COUNTER_MASK, 118 .counter_mask = OMAP5430_COUNTER_MASK,
@@ -148,17 +126,11 @@ omap5430_core_temp_sensor_registers = {
148 .tshut_cold_mask = OMAP5430_TSHUT_COLD_MASK, 126 .tshut_cold_mask = OMAP5430_TSHUT_COLD_MASK,
149 127
150 .bgap_status = OMAP5430_BGAP_STATUS_OFFSET, 128 .bgap_status = OMAP5430_BGAP_STATUS_OFFSET,
151 .status_clean_stop_mask = 0x0,
152 .status_bgap_alert_mask = OMAP5430_BGAP_ALERT_MASK,
153 .status_hot_mask = OMAP5430_HOT_CORE_FLAG_MASK, 129 .status_hot_mask = OMAP5430_HOT_CORE_FLAG_MASK,
154 .status_cold_mask = OMAP5430_COLD_CORE_FLAG_MASK, 130 .status_cold_mask = OMAP5430_COLD_CORE_FLAG_MASK,
155 131
156 .bgap_cumul_dtemp = OMAP5430_BGAP_CUMUL_DTEMP_CORE_OFFSET,
157 .ctrl_dtemp_0 = OMAP5430_BGAP_DTEMP_CORE_0_OFFSET,
158 .ctrl_dtemp_1 = OMAP5430_BGAP_DTEMP_CORE_1_OFFSET, 132 .ctrl_dtemp_1 = OMAP5430_BGAP_DTEMP_CORE_1_OFFSET,
159 .ctrl_dtemp_2 = OMAP5430_BGAP_DTEMP_CORE_2_OFFSET, 133 .ctrl_dtemp_2 = OMAP5430_BGAP_DTEMP_CORE_2_OFFSET,
160 .ctrl_dtemp_3 = OMAP5430_BGAP_DTEMP_CORE_3_OFFSET,
161 .ctrl_dtemp_4 = OMAP5430_BGAP_DTEMP_CORE_4_OFFSET,
162 134
163 .bgap_efuse = OMAP5430_FUSE_OPP_BGAP_CORE, 135 .bgap_efuse = OMAP5430_FUSE_OPP_BGAP_CORE,
164}; 136};
@@ -171,11 +143,6 @@ static struct temp_sensor_data omap5430_mpu_temp_sensor_data = {
171 .t_cold = OMAP5430_MPU_T_COLD, 143 .t_cold = OMAP5430_MPU_T_COLD,
172 .min_freq = OMAP5430_MPU_MIN_FREQ, 144 .min_freq = OMAP5430_MPU_MIN_FREQ,
173 .max_freq = OMAP5430_MPU_MAX_FREQ, 145 .max_freq = OMAP5430_MPU_MAX_FREQ,
174 .max_temp = OMAP5430_MPU_MAX_TEMP,
175 .min_temp = OMAP5430_MPU_MIN_TEMP,
176 .hyst_val = OMAP5430_MPU_HYST_VAL,
177 .update_int1 = 1000,
178 .update_int2 = 2000,
179}; 146};
180 147
181/* Thresholds and limits for OMAP5430 GPU temperature sensor */ 148/* Thresholds and limits for OMAP5430 GPU temperature sensor */
@@ -186,11 +153,6 @@ static struct temp_sensor_data omap5430_gpu_temp_sensor_data = {
186 .t_cold = OMAP5430_GPU_T_COLD, 153 .t_cold = OMAP5430_GPU_T_COLD,
187 .min_freq = OMAP5430_GPU_MIN_FREQ, 154 .min_freq = OMAP5430_GPU_MIN_FREQ,
188 .max_freq = OMAP5430_GPU_MAX_FREQ, 155 .max_freq = OMAP5430_GPU_MAX_FREQ,
189 .max_temp = OMAP5430_GPU_MAX_TEMP,
190 .min_temp = OMAP5430_GPU_MIN_TEMP,
191 .hyst_val = OMAP5430_GPU_HYST_VAL,
192 .update_int1 = 1000,
193 .update_int2 = 2000,
194}; 156};
195 157
196/* Thresholds and limits for OMAP5430 CORE temperature sensor */ 158/* Thresholds and limits for OMAP5430 CORE temperature sensor */
@@ -201,11 +163,6 @@ static struct temp_sensor_data omap5430_core_temp_sensor_data = {
201 .t_cold = OMAP5430_CORE_T_COLD, 163 .t_cold = OMAP5430_CORE_T_COLD,
202 .min_freq = OMAP5430_CORE_MIN_FREQ, 164 .min_freq = OMAP5430_CORE_MIN_FREQ,
203 .max_freq = OMAP5430_CORE_MAX_FREQ, 165 .max_freq = OMAP5430_CORE_MAX_FREQ,
204 .max_temp = OMAP5430_CORE_MAX_TEMP,
205 .min_temp = OMAP5430_CORE_MIN_TEMP,
206 .hyst_val = OMAP5430_CORE_HYST_VAL,
207 .update_int1 = 1000,
208 .update_int2 = 2000,
209}; 166};
210 167
211/* 168/*
@@ -319,8 +276,7 @@ const struct ti_bandgap_data omap5430_data = {
319 TI_BANDGAP_FEATURE_FREEZE_BIT | 276 TI_BANDGAP_FEATURE_FREEZE_BIT |
320 TI_BANDGAP_FEATURE_TALERT | 277 TI_BANDGAP_FEATURE_TALERT |
321 TI_BANDGAP_FEATURE_COUNTER_DELAY | 278 TI_BANDGAP_FEATURE_COUNTER_DELAY |
322 TI_BANDGAP_FEATURE_HISTORY_BUFFER | 279 TI_BANDGAP_FEATURE_HISTORY_BUFFER,
323 TI_BANDGAP_FEATURE_ERRATA_813,
324 .fclock_name = "l3instr_ts_gclk_div", 280 .fclock_name = "l3instr_ts_gclk_div",
325 .div_ck_name = "l3instr_ts_gclk_div", 281 .div_ck_name = "l3instr_ts_gclk_div",
326 .conv_table = omap5430_adc_to_temp, 282 .conv_table = omap5430_adc_to_temp,
diff --git a/drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h b/drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h
index 400b55dffadd..9096403b74b0 100644
--- a/drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h
+++ b/drivers/thermal/ti-soc-thermal/omap5xxx-bandgap.h
@@ -44,36 +44,24 @@
44#define OMAP5430_TEMP_SENSOR_GPU_OFFSET 0x150 44#define OMAP5430_TEMP_SENSOR_GPU_OFFSET 0x150
45#define OMAP5430_BGAP_THRESHOLD_GPU_OFFSET 0x1A8 45#define OMAP5430_BGAP_THRESHOLD_GPU_OFFSET 0x1A8
46#define OMAP5430_BGAP_TSHUT_GPU_OFFSET 0x1B4 46#define OMAP5430_BGAP_TSHUT_GPU_OFFSET 0x1B4
47#define OMAP5430_BGAP_CUMUL_DTEMP_GPU_OFFSET 0x1C0
48#define OMAP5430_BGAP_DTEMP_GPU_0_OFFSET 0x1F4
49#define OMAP5430_BGAP_DTEMP_GPU_1_OFFSET 0x1F8 47#define OMAP5430_BGAP_DTEMP_GPU_1_OFFSET 0x1F8
50#define OMAP5430_BGAP_DTEMP_GPU_2_OFFSET 0x1FC 48#define OMAP5430_BGAP_DTEMP_GPU_2_OFFSET 0x1FC
51#define OMAP5430_BGAP_DTEMP_GPU_3_OFFSET 0x200
52#define OMAP5430_BGAP_DTEMP_GPU_4_OFFSET 0x204
53 49
54/* OMAP5430.MPU register offsets */ 50/* OMAP5430.MPU register offsets */
55#define OMAP5430_FUSE_OPP_BGAP_MPU 0x4 51#define OMAP5430_FUSE_OPP_BGAP_MPU 0x4
56#define OMAP5430_TEMP_SENSOR_MPU_OFFSET 0x14C 52#define OMAP5430_TEMP_SENSOR_MPU_OFFSET 0x14C
57#define OMAP5430_BGAP_THRESHOLD_MPU_OFFSET 0x1A4 53#define OMAP5430_BGAP_THRESHOLD_MPU_OFFSET 0x1A4
58#define OMAP5430_BGAP_TSHUT_MPU_OFFSET 0x1B0 54#define OMAP5430_BGAP_TSHUT_MPU_OFFSET 0x1B0
59#define OMAP5430_BGAP_CUMUL_DTEMP_MPU_OFFSET 0x1BC
60#define OMAP5430_BGAP_DTEMP_MPU_0_OFFSET 0x1E0
61#define OMAP5430_BGAP_DTEMP_MPU_1_OFFSET 0x1E4 55#define OMAP5430_BGAP_DTEMP_MPU_1_OFFSET 0x1E4
62#define OMAP5430_BGAP_DTEMP_MPU_2_OFFSET 0x1E8 56#define OMAP5430_BGAP_DTEMP_MPU_2_OFFSET 0x1E8
63#define OMAP5430_BGAP_DTEMP_MPU_3_OFFSET 0x1EC
64#define OMAP5430_BGAP_DTEMP_MPU_4_OFFSET 0x1F0
65 57
66/* OMAP5430.MPU register offsets */ 58/* OMAP5430.MPU register offsets */
67#define OMAP5430_FUSE_OPP_BGAP_CORE 0x8 59#define OMAP5430_FUSE_OPP_BGAP_CORE 0x8
68#define OMAP5430_TEMP_SENSOR_CORE_OFFSET 0x154 60#define OMAP5430_TEMP_SENSOR_CORE_OFFSET 0x154
69#define OMAP5430_BGAP_THRESHOLD_CORE_OFFSET 0x1AC 61#define OMAP5430_BGAP_THRESHOLD_CORE_OFFSET 0x1AC
70#define OMAP5430_BGAP_TSHUT_CORE_OFFSET 0x1B8 62#define OMAP5430_BGAP_TSHUT_CORE_OFFSET 0x1B8
71#define OMAP5430_BGAP_CUMUL_DTEMP_CORE_OFFSET 0x1C4
72#define OMAP5430_BGAP_DTEMP_CORE_0_OFFSET 0x208
73#define OMAP5430_BGAP_DTEMP_CORE_1_OFFSET 0x20C 63#define OMAP5430_BGAP_DTEMP_CORE_1_OFFSET 0x20C
74#define OMAP5430_BGAP_DTEMP_CORE_2_OFFSET 0x210 64#define OMAP5430_BGAP_DTEMP_CORE_2_OFFSET 0x210
75#define OMAP5430_BGAP_DTEMP_CORE_3_OFFSET 0x214
76#define OMAP5430_BGAP_DTEMP_CORE_4_OFFSET 0x218
77 65
78/* OMAP5430.common register offsets */ 66/* OMAP5430.common register offsets */
79#define OMAP5430_BGAP_CTRL_OFFSET 0x1A0 67#define OMAP5430_BGAP_CTRL_OFFSET 0x1A0
@@ -94,17 +82,10 @@
94#define OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0) 82#define OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0)
95 83
96/* OMAP5430.BANDGAP_CTRL */ 84/* OMAP5430.BANDGAP_CTRL */
97#define OMAP5430_MASK_SIDLEMODE_MASK (0x3 << 30)
98#define OMAP5430_MASK_COUNTER_DELAY_MASK (0x7 << 27) 85#define OMAP5430_MASK_COUNTER_DELAY_MASK (0x7 << 27)
99#define OMAP5430_MASK_FREEZE_CORE_MASK BIT(23) 86#define OMAP5430_MASK_FREEZE_CORE_MASK BIT(23)
100#define OMAP5430_MASK_FREEZE_GPU_MASK BIT(22) 87#define OMAP5430_MASK_FREEZE_GPU_MASK BIT(22)
101#define OMAP5430_MASK_FREEZE_MPU_MASK BIT(21) 88#define OMAP5430_MASK_FREEZE_MPU_MASK BIT(21)
102#define OMAP5430_MASK_CLEAR_CORE_MASK BIT(20)
103#define OMAP5430_MASK_CLEAR_GPU_MASK BIT(19)
104#define OMAP5430_MASK_CLEAR_MPU_MASK BIT(18)
105#define OMAP5430_MASK_CLEAR_ACCUM_CORE_MASK BIT(17)
106#define OMAP5430_MASK_CLEAR_ACCUM_GPU_MASK BIT(16)
107#define OMAP5430_MASK_CLEAR_ACCUM_MPU_MASK BIT(15)
108#define OMAP5430_MASK_HOT_CORE_MASK BIT(5) 89#define OMAP5430_MASK_HOT_CORE_MASK BIT(5)
109#define OMAP5430_MASK_COLD_CORE_MASK BIT(4) 90#define OMAP5430_MASK_COLD_CORE_MASK BIT(4)
110#define OMAP5430_MASK_HOT_GPU_MASK BIT(3) 91#define OMAP5430_MASK_HOT_GPU_MASK BIT(3)
@@ -123,17 +104,7 @@
123#define OMAP5430_TSHUT_HOT_MASK (0x3ff << 16) 104#define OMAP5430_TSHUT_HOT_MASK (0x3ff << 16)
124#define OMAP5430_TSHUT_COLD_MASK (0x3ff << 0) 105#define OMAP5430_TSHUT_COLD_MASK (0x3ff << 0)
125 106
126/* OMAP5430.BANDGAP_CUMUL_DTEMP_MPU */
127#define OMAP5430_CUMUL_DTEMP_MPU_MASK (0xffffffff << 0)
128
129/* OMAP5430.BANDGAP_CUMUL_DTEMP_GPU */
130#define OMAP5430_CUMUL_DTEMP_GPU_MASK (0xffffffff << 0)
131
132/* OMAP5430.BANDGAP_CUMUL_DTEMP_CORE */
133#define OMAP5430_CUMUL_DTEMP_CORE_MASK (0xffffffff << 0)
134
135/* OMAP5430.BANDGAP_STATUS */ 107/* OMAP5430.BANDGAP_STATUS */
136#define OMAP5430_BGAP_ALERT_MASK BIT(31)
137#define OMAP5430_HOT_CORE_FLAG_MASK BIT(5) 108#define OMAP5430_HOT_CORE_FLAG_MASK BIT(5)
138#define OMAP5430_COLD_CORE_FLAG_MASK BIT(4) 109#define OMAP5430_COLD_CORE_FLAG_MASK BIT(4)
139#define OMAP5430_HOT_GPU_FLAG_MASK BIT(3) 110#define OMAP5430_HOT_GPU_FLAG_MASK BIT(3)
@@ -159,10 +130,6 @@
159/* bandgap clock limits */ 130/* bandgap clock limits */
160#define OMAP5430_GPU_MAX_FREQ 1500000 131#define OMAP5430_GPU_MAX_FREQ 1500000
161#define OMAP5430_GPU_MIN_FREQ 1000000 132#define OMAP5430_GPU_MIN_FREQ 1000000
162/* sensor limits */
163#define OMAP5430_GPU_MIN_TEMP -40000
164#define OMAP5430_GPU_MAX_TEMP 125000
165#define OMAP5430_GPU_HYST_VAL 5000
166/* interrupts thresholds */ 133/* interrupts thresholds */
167#define OMAP5430_GPU_TSHUT_HOT 915 134#define OMAP5430_GPU_TSHUT_HOT 915
168#define OMAP5430_GPU_TSHUT_COLD 900 135#define OMAP5430_GPU_TSHUT_COLD 900
@@ -173,10 +140,6 @@
173/* bandgap clock limits */ 140/* bandgap clock limits */
174#define OMAP5430_MPU_MAX_FREQ 1500000 141#define OMAP5430_MPU_MAX_FREQ 1500000
175#define OMAP5430_MPU_MIN_FREQ 1000000 142#define OMAP5430_MPU_MIN_FREQ 1000000
176/* sensor limits */
177#define OMAP5430_MPU_MIN_TEMP -40000
178#define OMAP5430_MPU_MAX_TEMP 125000
179#define OMAP5430_MPU_HYST_VAL 5000
180/* interrupts thresholds */ 143/* interrupts thresholds */
181#define OMAP5430_MPU_TSHUT_HOT 915 144#define OMAP5430_MPU_TSHUT_HOT 915
182#define OMAP5430_MPU_TSHUT_COLD 900 145#define OMAP5430_MPU_TSHUT_COLD 900
@@ -187,10 +150,6 @@
187/* bandgap clock limits */ 150/* bandgap clock limits */
188#define OMAP5430_CORE_MAX_FREQ 1500000 151#define OMAP5430_CORE_MAX_FREQ 1500000
189#define OMAP5430_CORE_MIN_FREQ 1000000 152#define OMAP5430_CORE_MIN_FREQ 1000000
190/* sensor limits */
191#define OMAP5430_CORE_MIN_TEMP -40000
192#define OMAP5430_CORE_MAX_TEMP 125000
193#define OMAP5430_CORE_HYST_VAL 5000
194/* interrupts thresholds */ 153/* interrupts thresholds */
195#define OMAP5430_CORE_TSHUT_HOT 915 154#define OMAP5430_CORE_TSHUT_HOT 915
196#define OMAP5430_CORE_TSHUT_COLD 900 155#define OMAP5430_CORE_TSHUT_COLD 900
diff --git a/drivers/thermal/ti-soc-thermal/ti-bandgap.c b/drivers/thermal/ti-soc-thermal/ti-bandgap.c
index 696ab3046b87..097328d8e943 100644
--- a/drivers/thermal/ti-soc-thermal/ti-bandgap.c
+++ b/drivers/thermal/ti-soc-thermal/ti-bandgap.c
@@ -306,217 +306,6 @@ int ti_bandgap_adc_to_mcelsius(struct ti_bandgap *bgp, int adc_val, int *t)
306} 306}
307 307
308/** 308/**
309 * ti_bandgap_mcelsius_to_adc() - converts a mCelsius value to ADC scale
310 * @bgp: struct ti_bandgap pointer
311 * @temp: value in mCelsius
312 * @adc: address where to write the resulting temperature in ADC representation
313 *
314 * Simple conversion from mCelsius to ADC values. In case the temp value
315 * is out of the ADC conv table range, it returns -ERANGE, 0 on success.
316 * The conversion table is indexed by the ADC values.
317 *
318 * Return: 0 if conversion was successful, else -ERANGE in case the @temp
319 * argument is out of the ADC conv table range.
320 */
321static
322int ti_bandgap_mcelsius_to_adc(struct ti_bandgap *bgp, long temp, int *adc)
323{
324 const struct ti_bandgap_data *conf = bgp->conf;
325 const int *conv_table = bgp->conf->conv_table;
326 int high, low, mid;
327
328 low = 0;
329 high = conf->adc_end_val - conf->adc_start_val;
330 mid = (high + low) / 2;
331
332 if (temp < conv_table[low] || temp > conv_table[high])
333 return -ERANGE;
334
335 while (low < high) {
336 if (temp < conv_table[mid])
337 high = mid - 1;
338 else
339 low = mid + 1;
340 mid = (low + high) / 2;
341 }
342
343 *adc = conf->adc_start_val + low;
344 return 0;
345}
346
347/**
348 * ti_bandgap_add_hyst() - add hysteresis (in mCelsius) to an ADC value
349 * @bgp: struct ti_bandgap pointer
350 * @adc_val: temperature value in ADC representation
351 * @hyst_val: hysteresis value in mCelsius
352 * @sum: address where to write the resulting temperature (in ADC scale)
353 *
354 * Adds an hysteresis value (in mCelsius) to a ADC temperature value.
355 *
356 * Return: 0 on success, -ERANGE otherwise.
357 */
358static
359int ti_bandgap_add_hyst(struct ti_bandgap *bgp, int adc_val, int hyst_val,
360 u32 *sum)
361{
362 int temp, ret;
363
364 /*
365 * Need to add in the mcelsius domain, so we have a temperature
366 * the conv_table range
367 */
368 ret = ti_bandgap_adc_to_mcelsius(bgp, adc_val, &temp);
369 if (ret < 0)
370 return ret;
371
372 temp += hyst_val;
373
374 ret = ti_bandgap_mcelsius_to_adc(bgp, temp, sum);
375 return ret;
376}
377
378/*** Helper functions handling device Alert/Shutdown signals ***/
379
380/**
381 * ti_bandgap_unmask_interrupts() - unmasks the events of thot & tcold
382 * @bgp: struct ti_bandgap pointer
383 * @id: bandgap sensor id
384 * @t_hot: hot temperature value to trigger alert signal
385 * @t_cold: cold temperature value to trigger alert signal
386 *
387 * Checks the requested t_hot and t_cold values and configures the IRQ event
388 * masks accordingly. Call this function only if bandgap features HAS(TALERT).
389 */
390static void ti_bandgap_unmask_interrupts(struct ti_bandgap *bgp, int id,
391 u32 t_hot, u32 t_cold)
392{
393 struct temp_sensor_registers *tsr;
394 u32 temp, reg_val;
395
396 /* Read the current on die temperature */
397 temp = ti_bandgap_read_temp(bgp, id);
398
399 tsr = bgp->conf->sensors[id].registers;
400 reg_val = ti_bandgap_readl(bgp, tsr->bgap_mask_ctrl);
401
402 if (temp < t_hot)
403 reg_val |= tsr->mask_hot_mask;
404 else
405 reg_val &= ~tsr->mask_hot_mask;
406
407 if (t_cold < temp)
408 reg_val |= tsr->mask_cold_mask;
409 else
410 reg_val &= ~tsr->mask_cold_mask;
411 ti_bandgap_writel(bgp, reg_val, tsr->bgap_mask_ctrl);
412}
413
414/**
415 * ti_bandgap_update_alert_threshold() - sequence to update thresholds
416 * @bgp: struct ti_bandgap pointer
417 * @id: bandgap sensor id
418 * @val: value (ADC) of a new threshold
419 * @hot: desired threshold to be updated. true if threshold hot, false if
420 * threshold cold
421 *
422 * It will program the required thresholds (hot and cold) for TALERT signal.
423 * This function can be used to update t_hot or t_cold, depending on @hot value.
424 * It checks the resulting t_hot and t_cold values, based on the new passed @val
425 * and configures the thresholds so that t_hot is always greater than t_cold.
426 * Call this function only if bandgap features HAS(TALERT).
427 *
428 * Return: 0 if no error, else corresponding error
429 */
430static int ti_bandgap_update_alert_threshold(struct ti_bandgap *bgp, int id,
431 int val, bool hot)
432{
433 struct temp_sensor_data *ts_data = bgp->conf->sensors[id].ts_data;
434 struct temp_sensor_registers *tsr;
435 u32 thresh_val, reg_val, t_hot, t_cold, ctrl;
436 int err = 0;
437
438 tsr = bgp->conf->sensors[id].registers;
439
440 /* obtain the current value */
441 thresh_val = ti_bandgap_readl(bgp, tsr->bgap_threshold);
442 t_cold = (thresh_val & tsr->threshold_tcold_mask) >>
443 __ffs(tsr->threshold_tcold_mask);
444 t_hot = (thresh_val & tsr->threshold_thot_mask) >>
445 __ffs(tsr->threshold_thot_mask);
446 if (hot)
447 t_hot = val;
448 else
449 t_cold = val;
450
451 if (t_cold > t_hot) {
452 if (hot)
453 err = ti_bandgap_add_hyst(bgp, t_hot,
454 -ts_data->hyst_val,
455 &t_cold);
456 else
457 err = ti_bandgap_add_hyst(bgp, t_cold,
458 ts_data->hyst_val,
459 &t_hot);
460 }
461
462 /* write the new threshold values */
463 reg_val = thresh_val &
464 ~(tsr->threshold_thot_mask | tsr->threshold_tcold_mask);
465 reg_val |= (t_hot << __ffs(tsr->threshold_thot_mask)) |
466 (t_cold << __ffs(tsr->threshold_tcold_mask));
467
468 /**
469 * Errata i813:
470 * Spurious Thermal Alert: Talert can happen randomly while the device
471 * remains under the temperature limit defined for this event to trig.
472 * This spurious event is caused by a incorrect re-synchronization
473 * between clock domains. The comparison between configured threshold
474 * and current temperature value can happen while the value is
475 * transitioning (metastable), thus causing inappropriate event
476 * generation. No spurious event occurs as long as the threshold value
477 * stays unchanged. Spurious event can be generated while a thermal
478 * alert threshold is modified in
479 * CONTROL_BANDGAP_THRESHOLD_MPU/GPU/CORE/DSPEVE/IVA_n.
480 */
481
482 if (TI_BANDGAP_HAS(bgp, ERRATA_813)) {
483 /* Mask t_hot and t_cold events at the IP Level */
484 ctrl = ti_bandgap_readl(bgp, tsr->bgap_mask_ctrl);
485
486 if (hot)
487 ctrl &= ~tsr->mask_hot_mask;
488 else
489 ctrl &= ~tsr->mask_cold_mask;
490
491 ti_bandgap_writel(bgp, ctrl, tsr->bgap_mask_ctrl);
492 }
493
494 /* Write the threshold value */
495 ti_bandgap_writel(bgp, reg_val, tsr->bgap_threshold);
496
497 if (TI_BANDGAP_HAS(bgp, ERRATA_813)) {
498 /* Unmask t_hot and t_cold events at the IP Level */
499 ctrl = ti_bandgap_readl(bgp, tsr->bgap_mask_ctrl);
500 if (hot)
501 ctrl |= tsr->mask_hot_mask;
502 else
503 ctrl |= tsr->mask_cold_mask;
504
505 ti_bandgap_writel(bgp, ctrl, tsr->bgap_mask_ctrl);
506 }
507
508 if (err) {
509 dev_err(bgp->dev, "failed to reprogram thot threshold\n");
510 err = -EIO;
511 goto exit;
512 }
513
514 ti_bandgap_unmask_interrupts(bgp, id, t_hot, t_cold);
515exit:
516 return err;
517}
518
519/**
520 * ti_bandgap_validate() - helper to check the sanity of a struct ti_bandgap 309 * ti_bandgap_validate() - helper to check the sanity of a struct ti_bandgap
521 * @bgp: struct ti_bandgap pointer 310 * @bgp: struct ti_bandgap pointer
522 * @id: bandgap sensor id 311 * @id: bandgap sensor id
@@ -544,165 +333,6 @@ static inline int ti_bandgap_validate(struct ti_bandgap *bgp, int id)
544} 333}
545 334
546/** 335/**
547 * _ti_bandgap_write_threshold() - helper to update TALERT t_cold or t_hot
548 * @bgp: struct ti_bandgap pointer
549 * @id: bandgap sensor id
550 * @val: value (mCelsius) of a new threshold
551 * @hot: desired threshold to be updated. true if threshold hot, false if
552 * threshold cold
553 *
554 * It will update the required thresholds (hot and cold) for TALERT signal.
555 * This function can be used to update t_hot or t_cold, depending on @hot value.
556 * Validates the mCelsius range and update the requested threshold.
557 * Call this function only if bandgap features HAS(TALERT).
558 *
559 * Return: 0 if no error, else corresponding error value.
560 */
561static int _ti_bandgap_write_threshold(struct ti_bandgap *bgp, int id, int val,
562 bool hot)
563{
564 struct temp_sensor_data *ts_data;
565 struct temp_sensor_registers *tsr;
566 u32 adc_val;
567 int ret;
568
569 ret = ti_bandgap_validate(bgp, id);
570 if (ret)
571 return ret;
572
573 if (!TI_BANDGAP_HAS(bgp, TALERT))
574 return -ENOTSUPP;
575
576 ts_data = bgp->conf->sensors[id].ts_data;
577 tsr = bgp->conf->sensors[id].registers;
578 if (hot) {
579 if (val < ts_data->min_temp + ts_data->hyst_val)
580 ret = -EINVAL;
581 } else {
582 if (val > ts_data->max_temp + ts_data->hyst_val)
583 ret = -EINVAL;
584 }
585
586 if (ret)
587 return ret;
588
589 ret = ti_bandgap_mcelsius_to_adc(bgp, val, &adc_val);
590 if (ret < 0)
591 return ret;
592
593 spin_lock(&bgp->lock);
594 ret = ti_bandgap_update_alert_threshold(bgp, id, adc_val, hot);
595 spin_unlock(&bgp->lock);
596 return ret;
597}
598
599/**
600 * _ti_bandgap_read_threshold() - helper to read TALERT t_cold or t_hot
601 * @bgp: struct ti_bandgap pointer
602 * @id: bandgap sensor id
603 * @val: value (mCelsius) of a threshold
604 * @hot: desired threshold to be read. true if threshold hot, false if
605 * threshold cold
606 *
607 * It will fetch the required thresholds (hot and cold) for TALERT signal.
608 * This function can be used to read t_hot or t_cold, depending on @hot value.
609 * Call this function only if bandgap features HAS(TALERT).
610 *
611 * Return: 0 if no error, -ENOTSUPP if it has no TALERT support, or the
612 * corresponding error value if some operation fails.
613 */
614static int _ti_bandgap_read_threshold(struct ti_bandgap *bgp, int id,
615 int *val, bool hot)
616{
617 struct temp_sensor_registers *tsr;
618 u32 temp, mask;
619 int ret = 0;
620
621 ret = ti_bandgap_validate(bgp, id);
622 if (ret)
623 goto exit;
624
625 if (!TI_BANDGAP_HAS(bgp, TALERT)) {
626 ret = -ENOTSUPP;
627 goto exit;
628 }
629
630 tsr = bgp->conf->sensors[id].registers;
631 if (hot)
632 mask = tsr->threshold_thot_mask;
633 else
634 mask = tsr->threshold_tcold_mask;
635
636 temp = ti_bandgap_readl(bgp, tsr->bgap_threshold);
637 temp = (temp & mask) >> __ffs(mask);
638 ret = ti_bandgap_adc_to_mcelsius(bgp, temp, &temp);
639 if (ret) {
640 dev_err(bgp->dev, "failed to read thot\n");
641 ret = -EIO;
642 goto exit;
643 }
644
645 *val = temp;
646
647exit:
648 return ret;
649}
650
651/*** Exposed APIs ***/
652
653/**
654 * ti_bandgap_read_thot() - reads sensor current thot
655 * @bgp: pointer to bandgap instance
656 * @id: sensor id
657 * @thot: resulting current thot value
658 *
659 * Return: 0 on success or the proper error code
660 */
661int ti_bandgap_read_thot(struct ti_bandgap *bgp, int id, int *thot)
662{
663 return _ti_bandgap_read_threshold(bgp, id, thot, true);
664}
665
666/**
667 * ti_bandgap_write_thot() - sets sensor current thot
668 * @bgp: pointer to bandgap instance
669 * @id: sensor id
670 * @val: desired thot value
671 *
672 * Return: 0 on success or the proper error code
673 */
674int ti_bandgap_write_thot(struct ti_bandgap *bgp, int id, int val)
675{
676 return _ti_bandgap_write_threshold(bgp, id, val, true);
677}
678
679/**
680 * ti_bandgap_read_tcold() - reads sensor current tcold
681 * @bgp: pointer to bandgap instance
682 * @id: sensor id
683 * @tcold: resulting current tcold value
684 *
685 * Return: 0 on success or the proper error code
686 */
687int ti_bandgap_read_tcold(struct ti_bandgap *bgp, int id, int *tcold)
688{
689 return _ti_bandgap_read_threshold(bgp, id, tcold, false);
690}
691
692/**
693 * ti_bandgap_write_tcold() - sets the sensor tcold
694 * @bgp: pointer to bandgap instance
695 * @id: sensor id
696 * @val: desired tcold value
697 *
698 * Return: 0 on success or the proper error code
699 */
700int ti_bandgap_write_tcold(struct ti_bandgap *bgp, int id, int val)
701{
702 return _ti_bandgap_write_threshold(bgp, id, val, false);
703}
704
705/**
706 * ti_bandgap_read_counter() - read the sensor counter 336 * ti_bandgap_read_counter() - read the sensor counter
707 * @bgp: pointer to bandgap instance 337 * @bgp: pointer to bandgap instance
708 * @id: sensor id 338 * @id: sensor id
diff --git a/drivers/thermal/ti-soc-thermal/ti-bandgap.h b/drivers/thermal/ti-soc-thermal/ti-bandgap.h
index 209c664c2823..68d39ad43241 100644
--- a/drivers/thermal/ti-soc-thermal/ti-bandgap.h
+++ b/drivers/thermal/ti-soc-thermal/ti-bandgap.h
@@ -78,11 +78,8 @@
78 * @bgap_mask_ctrl: BANDGAP_MASK_CTRL register offset 78 * @bgap_mask_ctrl: BANDGAP_MASK_CTRL register offset
79 * @mask_hot_mask: mask to bandgap_mask_ctrl.mask_hot 79 * @mask_hot_mask: mask to bandgap_mask_ctrl.mask_hot
80 * @mask_cold_mask: mask to bandgap_mask_ctrl.mask_cold 80 * @mask_cold_mask: mask to bandgap_mask_ctrl.mask_cold
81 * @mask_sidlemode_mask: mask to bandgap_mask_ctrl.mask_sidlemode
82 * @mask_counter_delay_mask: mask to bandgap_mask_ctrl.mask_counter_delay 81 * @mask_counter_delay_mask: mask to bandgap_mask_ctrl.mask_counter_delay
83 * @mask_freeze_mask: mask to bandgap_mask_ctrl.mask_free 82 * @mask_freeze_mask: mask to bandgap_mask_ctrl.mask_free
84 * @mask_clear_mask: mask to bandgap_mask_ctrl.mask_clear
85 * @mask_clear_accum_mask: mask to bandgap_mask_ctrl.mask_clear_accum
86 * @bgap_mode_ctrl: BANDGAP_MODE_CTRL register offset 83 * @bgap_mode_ctrl: BANDGAP_MODE_CTRL register offset
87 * @mode_ctrl_mask: mask to bandgap_mode_ctrl.mode_ctrl 84 * @mode_ctrl_mask: mask to bandgap_mode_ctrl.mode_ctrl
88 * @bgap_counter: BANDGAP_COUNTER register offset 85 * @bgap_counter: BANDGAP_COUNTER register offset
@@ -91,21 +88,13 @@
91 * @threshold_thot_mask: mask to bandgap_threhold.thot 88 * @threshold_thot_mask: mask to bandgap_threhold.thot
92 * @threshold_tcold_mask: mask to bandgap_threhold.tcold 89 * @threshold_tcold_mask: mask to bandgap_threhold.tcold
93 * @tshut_threshold: TSHUT_THRESHOLD register offset (TSHUT thresholds) 90 * @tshut_threshold: TSHUT_THRESHOLD register offset (TSHUT thresholds)
94 * @tshut_efuse_mask: mask to tshut_threshold.tshut_efuse
95 * @tshut_efuse_shift: shift to tshut_threshold.tshut_efuse
96 * @tshut_hot_mask: mask to tshut_threhold.thot 91 * @tshut_hot_mask: mask to tshut_threhold.thot
97 * @tshut_cold_mask: mask to tshut_threhold.thot 92 * @tshut_cold_mask: mask to tshut_threhold.thot
98 * @bgap_status: BANDGAP_STATUS register offset 93 * @bgap_status: BANDGAP_STATUS register offset
99 * @status_clean_stop_mask: mask to bandgap_status.clean_stop
100 * @status_bgap_alert_mask: mask to bandgap_status.bandgap_alert
101 * @status_hot_mask: mask to bandgap_status.hot 94 * @status_hot_mask: mask to bandgap_status.hot
102 * @status_cold_mask: mask to bandgap_status.cold 95 * @status_cold_mask: mask to bandgap_status.cold
103 * @bgap_cumul_dtemp: BANDGAP_CUMUL_DTEMP register offset
104 * @ctrl_dtemp_0: CTRL_DTEMP0 register offset
105 * @ctrl_dtemp_1: CTRL_DTEMP1 register offset 96 * @ctrl_dtemp_1: CTRL_DTEMP1 register offset
106 * @ctrl_dtemp_2: CTRL_DTEMP2 register offset 97 * @ctrl_dtemp_2: CTRL_DTEMP2 register offset
107 * @ctrl_dtemp_3: CTRL_DTEMP3 register offset
108 * @ctrl_dtemp_4: CTRL_DTEMP4 register offset
109 * @bgap_efuse: BANDGAP_EFUSE register offset 98 * @bgap_efuse: BANDGAP_EFUSE register offset
110 * 99 *
111 * The register offsets and bitfields might change across 100 * The register offsets and bitfields might change across
@@ -121,17 +110,14 @@ struct temp_sensor_registers {
121 u32 temp_sensor_ctrl; 110 u32 temp_sensor_ctrl;
122 u32 bgap_tempsoff_mask; 111 u32 bgap_tempsoff_mask;
123 u32 bgap_soc_mask; 112 u32 bgap_soc_mask;
124 u32 bgap_eocz_mask; /* not used: but needs revisit */ 113 u32 bgap_eocz_mask;
125 u32 bgap_dtemp_mask; 114 u32 bgap_dtemp_mask;
126 115
127 u32 bgap_mask_ctrl; 116 u32 bgap_mask_ctrl;
128 u32 mask_hot_mask; 117 u32 mask_hot_mask;
129 u32 mask_cold_mask; 118 u32 mask_cold_mask;
130 u32 mask_sidlemode_mask; /* not used: but may be needed for pm */
131 u32 mask_counter_delay_mask; 119 u32 mask_counter_delay_mask;
132 u32 mask_freeze_mask; 120 u32 mask_freeze_mask;
133 u32 mask_clear_mask; /* not used: but needed for trending */
134 u32 mask_clear_accum_mask; /* not used: but needed for trending */
135 121
136 u32 bgap_mode_ctrl; 122 u32 bgap_mode_ctrl;
137 u32 mode_ctrl_mask; 123 u32 mode_ctrl_mask;
@@ -144,23 +130,15 @@ struct temp_sensor_registers {
144 u32 threshold_tcold_mask; 130 u32 threshold_tcold_mask;
145 131
146 u32 tshut_threshold; 132 u32 tshut_threshold;
147 u32 tshut_efuse_mask; /* not used */
148 u32 tshut_efuse_shift; /* not used */
149 u32 tshut_hot_mask; 133 u32 tshut_hot_mask;
150 u32 tshut_cold_mask; 134 u32 tshut_cold_mask;
151 135
152 u32 bgap_status; 136 u32 bgap_status;
153 u32 status_clean_stop_mask; /* not used: but needed for trending */
154 u32 status_bgap_alert_mask; /* not used */
155 u32 status_hot_mask; 137 u32 status_hot_mask;
156 u32 status_cold_mask; 138 u32 status_cold_mask;
157 139
158 u32 bgap_cumul_dtemp; /* not used: but needed for trending */ 140 u32 ctrl_dtemp_1;
159 u32 ctrl_dtemp_0; /* not used: but needed for trending */ 141 u32 ctrl_dtemp_2;
160 u32 ctrl_dtemp_1; /* not used: but needed for trending */
161 u32 ctrl_dtemp_2; /* not used: but needed for trending */
162 u32 ctrl_dtemp_3; /* not used: but needed for trending */
163 u32 ctrl_dtemp_4; /* not used: but needed for trending */
164 u32 bgap_efuse; 142 u32 bgap_efuse;
165}; 143};
166 144
@@ -172,11 +150,6 @@ struct temp_sensor_registers {
172 * @t_cold: temperature to trigger a thermal alert (low initial value) 150 * @t_cold: temperature to trigger a thermal alert (low initial value)
173 * @min_freq: sensor minimum clock rate 151 * @min_freq: sensor minimum clock rate
174 * @max_freq: sensor maximum clock rate 152 * @max_freq: sensor maximum clock rate
175 * @max_temp: sensor maximum temperature
176 * @min_temp: sensor minimum temperature
177 * @hyst_val: temperature hysteresis considered while converting ADC values
178 * @update_int1: update interval
179 * @update_int2: update interval
180 * 153 *
181 * This data structure will hold the required thresholds and temperature limits 154 * This data structure will hold the required thresholds and temperature limits
182 * for a specific temperature sensor, like shutdown temperature, alert 155 * for a specific temperature sensor, like shutdown temperature, alert
@@ -189,11 +162,6 @@ struct temp_sensor_data {
189 u32 t_cold; 162 u32 t_cold;
190 u32 min_freq; 163 u32 min_freq;
191 u32 max_freq; 164 u32 max_freq;
192 int max_temp;
193 int min_temp;
194 int hyst_val;
195 u32 update_int1; /* not used */
196 u32 update_int2; /* not used */
197}; 165};
198 166
199struct ti_bandgap_data; 167struct ti_bandgap_data;
@@ -316,8 +284,6 @@ struct ti_temp_sensor {
316 * 284 *
317 * TI_BANDGAP_FEATURE_ERRATA_814 - used to workaorund when the bandgap device 285 * TI_BANDGAP_FEATURE_ERRATA_814 - used to workaorund when the bandgap device
318 * has Errata 814 286 * has Errata 814
319 * TI_BANDGAP_FEATURE_ERRATA_813 - used to workaorund when the bandgap device
320 * has Errata 813
321 * TI_BANDGAP_FEATURE_UNRELIABLE - used when the sensor readings are too 287 * TI_BANDGAP_FEATURE_UNRELIABLE - used when the sensor readings are too
322 * inaccurate. 288 * inaccurate.
323 * TI_BANDGAP_HAS(b, f) - macro to check if a bandgap device is capable of a 289 * TI_BANDGAP_HAS(b, f) - macro to check if a bandgap device is capable of a
@@ -334,8 +300,7 @@ struct ti_temp_sensor {
334#define TI_BANDGAP_FEATURE_COUNTER_DELAY BIT(8) 300#define TI_BANDGAP_FEATURE_COUNTER_DELAY BIT(8)
335#define TI_BANDGAP_FEATURE_HISTORY_BUFFER BIT(9) 301#define TI_BANDGAP_FEATURE_HISTORY_BUFFER BIT(9)
336#define TI_BANDGAP_FEATURE_ERRATA_814 BIT(10) 302#define TI_BANDGAP_FEATURE_ERRATA_814 BIT(10)
337#define TI_BANDGAP_FEATURE_ERRATA_813 BIT(11) 303#define TI_BANDGAP_FEATURE_UNRELIABLE BIT(11)
338#define TI_BANDGAP_FEATURE_UNRELIABLE BIT(12)
339#define TI_BANDGAP_HAS(b, f) \ 304#define TI_BANDGAP_HAS(b, f) \
340 ((b)->conf->features & TI_BANDGAP_FEATURE_ ## f) 305 ((b)->conf->features & TI_BANDGAP_FEATURE_ ## f)
341 306
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-31 05:59:39 -0500