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-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c16
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h1
-rw-r--r--include/uapi/drm/amdgpu_drm.h22
4 files changed, 40 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index dca4be970d13..1dbe76c3c366 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -948,6 +948,7 @@ void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
948const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 948const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
949 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 949 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
950 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 950 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
951 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
951 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 952 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
952 /* KMS */ 953 /* KMS */
953 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 954 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 8ecf82c5fe74..e4e2bacdb230 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2322,3 +2322,19 @@ void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2322 } 2322 }
2323 } 2323 }
2324} 2324}
2325
2326int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
2327{
2328 union drm_amdgpu_vm *args = data;
2329
2330 switch (args->in.op) {
2331 case AMDGPU_VM_OP_RESERVE_VMID:
2332 case AMDGPU_VM_OP_UNRESERVE_VMID:
2333 return -EINVAL;
2334 break;
2335 default:
2336 return -EINVAL;
2337 }
2338
2339 return 0;
2340}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index e1d951ece433..b10ce2d08685 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -239,5 +239,6 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
239void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 239void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
240 struct amdgpu_bo_va *bo_va); 240 struct amdgpu_bo_va *bo_va);
241void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size); 241void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size);
242int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
242 243
243#endif 244#endif
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 6c249e5cfb09..56ceb3daaba5 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -51,6 +51,7 @@ extern "C" {
51#define DRM_AMDGPU_GEM_OP 0x10 51#define DRM_AMDGPU_GEM_OP 0x10
52#define DRM_AMDGPU_GEM_USERPTR 0x11 52#define DRM_AMDGPU_GEM_USERPTR 0x11
53#define DRM_AMDGPU_WAIT_FENCES 0x12 53#define DRM_AMDGPU_WAIT_FENCES 0x12
54#define DRM_AMDGPU_VM 0x13
54 55
55#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 56#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
56#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 57#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -65,6 +66,7 @@ extern "C" {
65#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 66#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
66#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 67#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
67#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 68#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
69#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
68 70
69#define AMDGPU_GEM_DOMAIN_CPU 0x1 71#define AMDGPU_GEM_DOMAIN_CPU 0x1
70#define AMDGPU_GEM_DOMAIN_GTT 0x2 72#define AMDGPU_GEM_DOMAIN_GTT 0x2
@@ -190,6 +192,26 @@ union drm_amdgpu_ctx {
190 union drm_amdgpu_ctx_out out; 192 union drm_amdgpu_ctx_out out;
191}; 193};
192 194
195/* vm ioctl */
196#define AMDGPU_VM_OP_RESERVE_VMID 1
197#define AMDGPU_VM_OP_UNRESERVE_VMID 2
198
199struct drm_amdgpu_vm_in {
200 /** AMDGPU_VM_OP_* */
201 __u32 op;
202 __u32 flags;
203};
204
205struct drm_amdgpu_vm_out {
206 /** For future use, no flags defined so far */
207 __u64 flags;
208};
209
210union drm_amdgpu_vm {
211 struct drm_amdgpu_vm_in in;
212 struct drm_amdgpu_vm_out out;
213};
214
193/* 215/*
194 * This is not a reliable API and you should expect it to fail for any 216 * This is not a reliable API and you should expect it to fail for any
195 * number of reasons and have fallback path that do not use userptr to 217 * number of reasons and have fallback path that do not use userptr to