diff options
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 47 |
1 files changed, 34 insertions, 13 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c index 47d1c132ac40..1e3e9be7d77e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | |||
| @@ -379,29 +379,50 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd) | |||
| 379 | { | 379 | { |
| 380 | struct amdgpu_device *adev = get_amdgpu_device(kgd); | 380 | struct amdgpu_device *adev = get_amdgpu_device(kgd); |
| 381 | struct cik_sdma_rlc_registers *m; | 381 | struct cik_sdma_rlc_registers *m; |
| 382 | unsigned long end_jiffies; | ||
| 382 | uint32_t sdma_base_addr; | 383 | uint32_t sdma_base_addr; |
| 384 | uint32_t data; | ||
| 383 | 385 | ||
| 384 | m = get_sdma_mqd(mqd); | 386 | m = get_sdma_mqd(mqd); |
| 385 | sdma_base_addr = get_sdma_base_addr(m); | 387 | sdma_base_addr = get_sdma_base_addr(m); |
| 386 | 388 | ||
| 387 | WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR, | 389 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, |
| 388 | m->sdma_rlc_virtual_addr); | 390 | m->sdma_rlc_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); |
| 389 | 391 | ||
| 390 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, | 392 | end_jiffies = msecs_to_jiffies(2000) + jiffies; |
| 391 | m->sdma_rlc_rb_base); | 393 | while (true) { |
| 394 | data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); | ||
| 395 | if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) | ||
| 396 | break; | ||
| 397 | if (time_after(jiffies, end_jiffies)) | ||
| 398 | return -ETIME; | ||
| 399 | usleep_range(500, 1000); | ||
| 400 | } | ||
| 401 | if (m->sdma_engine_id) { | ||
| 402 | data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL); | ||
| 403 | data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL, | ||
| 404 | RESUME_CTX, 0); | ||
| 405 | WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data); | ||
| 406 | } else { | ||
| 407 | data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL); | ||
| 408 | data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL, | ||
| 409 | RESUME_CTX, 0); | ||
| 410 | WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data); | ||
| 411 | } | ||
| 392 | 412 | ||
| 413 | WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, | ||
| 414 | m->sdma_rlc_doorbell); | ||
| 415 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0); | ||
| 416 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0); | ||
| 417 | WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR, | ||
| 418 | m->sdma_rlc_virtual_addr); | ||
| 419 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base); | ||
| 393 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, | 420 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, |
| 394 | m->sdma_rlc_rb_base_hi); | 421 | m->sdma_rlc_rb_base_hi); |
| 395 | |||
| 396 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, | 422 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, |
| 397 | m->sdma_rlc_rb_rptr_addr_lo); | 423 | m->sdma_rlc_rb_rptr_addr_lo); |
| 398 | |||
| 399 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, | 424 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, |
| 400 | m->sdma_rlc_rb_rptr_addr_hi); | 425 | m->sdma_rlc_rb_rptr_addr_hi); |
| 401 | |||
| 402 | WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, | ||
| 403 | m->sdma_rlc_doorbell); | ||
| 404 | |||
| 405 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, | 426 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, |
| 406 | m->sdma_rlc_rb_cntl); | 427 | m->sdma_rlc_rb_cntl); |
| 407 | 428 | ||
| @@ -574,9 +595,9 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, | |||
| 574 | } | 595 | } |
| 575 | 596 | ||
| 576 | WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); | 597 | WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); |
| 577 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0); | 598 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, |
| 578 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0); | 599 | RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) | |
| 579 | WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, 0); | 600 | SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); |
| 580 | 601 | ||
| 581 | return 0; | 602 | return 0; |
| 582 | } | 603 | } |
