diff options
| -rw-r--r-- | arch/powerpc/platforms/512x/clock-commonclk.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c index b3097fe6441b..af265ae40a61 100644 --- a/arch/powerpc/platforms/512x/clock-commonclk.c +++ b/arch/powerpc/platforms/512x/clock-commonclk.c | |||
| @@ -239,6 +239,7 @@ static inline struct clk *mpc512x_clk_divider( | |||
| 239 | const char *name, const char *parent_name, u8 clkflags, | 239 | const char *name, const char *parent_name, u8 clkflags, |
| 240 | u32 __iomem *reg, u8 pos, u8 len, int divflags) | 240 | u32 __iomem *reg, u8 pos, u8 len, int divflags) |
| 241 | { | 241 | { |
| 242 | divflags |= CLK_DIVIDER_BIG_ENDIAN; | ||
| 242 | return clk_register_divider(NULL, name, parent_name, clkflags, | 243 | return clk_register_divider(NULL, name, parent_name, clkflags, |
| 243 | reg, pos, len, divflags, &clklock); | 244 | reg, pos, len, divflags, &clklock); |
| 244 | } | 245 | } |
| @@ -250,7 +251,7 @@ static inline struct clk *mpc512x_clk_divtable( | |||
| 250 | { | 251 | { |
| 251 | u8 divflags; | 252 | u8 divflags; |
| 252 | 253 | ||
| 253 | divflags = 0; | 254 | divflags = CLK_DIVIDER_BIG_ENDIAN; |
| 254 | return clk_register_divider_table(NULL, name, parent_name, 0, | 255 | return clk_register_divider_table(NULL, name, parent_name, 0, |
| 255 | reg, pos, len, divflags, | 256 | reg, pos, len, divflags, |
| 256 | divtab, &clklock); | 257 | divtab, &clklock); |
| @@ -261,10 +262,12 @@ static inline struct clk *mpc512x_clk_gated( | |||
| 261 | u32 __iomem *reg, u8 pos) | 262 | u32 __iomem *reg, u8 pos) |
| 262 | { | 263 | { |
| 263 | int clkflags; | 264 | int clkflags; |
| 265 | u8 gateflags; | ||
| 264 | 266 | ||
| 265 | clkflags = CLK_SET_RATE_PARENT; | 267 | clkflags = CLK_SET_RATE_PARENT; |
| 268 | gateflags = CLK_GATE_BIG_ENDIAN; | ||
| 266 | return clk_register_gate(NULL, name, parent_name, clkflags, | 269 | return clk_register_gate(NULL, name, parent_name, clkflags, |
| 267 | reg, pos, 0, &clklock); | 270 | reg, pos, gateflags, &clklock); |
| 268 | } | 271 | } |
| 269 | 272 | ||
| 270 | static inline struct clk *mpc512x_clk_muxed(const char *name, | 273 | static inline struct clk *mpc512x_clk_muxed(const char *name, |
| @@ -275,7 +278,7 @@ static inline struct clk *mpc512x_clk_muxed(const char *name, | |||
| 275 | u8 muxflags; | 278 | u8 muxflags; |
| 276 | 279 | ||
| 277 | clkflags = CLK_SET_RATE_PARENT; | 280 | clkflags = CLK_SET_RATE_PARENT; |
| 278 | muxflags = 0; | 281 | muxflags = CLK_MUX_BIG_ENDIAN; |
| 279 | return clk_register_mux(NULL, name, | 282 | return clk_register_mux(NULL, name, |
| 280 | parent_names, parent_count, clkflags, | 283 | parent_names, parent_count, clkflags, |
| 281 | reg, pos, len, muxflags, &clklock); | 284 | reg, pos, len, muxflags, &clklock); |
