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-rw-r--r--drivers/clk/meson/meson8b.c203
1 files changed, 197 insertions, 6 deletions
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 950d0e548c75..0b9353d8d4fd 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -1659,6 +1659,185 @@ static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
1659static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2); 1659static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
1660static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3); 1660static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
1661 1661
1662static struct clk_hw_onecell_data meson8_hw_onecell_data = {
1663 .hws = {
1664 [CLKID_XTAL] = &meson8b_xtal.hw,
1665 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
1666 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
1667 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
1668 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
1669 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
1670 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
1671 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
1672 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
1673 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
1674 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
1675 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
1676 [CLKID_CLK81] = &meson8b_clk81.hw,
1677 [CLKID_DDR] = &meson8b_ddr.hw,
1678 [CLKID_DOS] = &meson8b_dos.hw,
1679 [CLKID_ISA] = &meson8b_isa.hw,
1680 [CLKID_PL301] = &meson8b_pl301.hw,
1681 [CLKID_PERIPHS] = &meson8b_periphs.hw,
1682 [CLKID_SPICC] = &meson8b_spicc.hw,
1683 [CLKID_I2C] = &meson8b_i2c.hw,
1684 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
1685 [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
1686 [CLKID_RNG0] = &meson8b_rng0.hw,
1687 [CLKID_UART0] = &meson8b_uart0.hw,
1688 [CLKID_SDHC] = &meson8b_sdhc.hw,
1689 [CLKID_STREAM] = &meson8b_stream.hw,
1690 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
1691 [CLKID_SDIO] = &meson8b_sdio.hw,
1692 [CLKID_ABUF] = &meson8b_abuf.hw,
1693 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
1694 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
1695 [CLKID_SPI] = &meson8b_spi.hw,
1696 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
1697 [CLKID_ETH] = &meson8b_eth.hw,
1698 [CLKID_DEMUX] = &meson8b_demux.hw,
1699 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
1700 [CLKID_IEC958] = &meson8b_iec958.hw,
1701 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
1702 [CLKID_AMCLK] = &meson8b_amclk.hw,
1703 [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
1704 [CLKID_MIXER] = &meson8b_mixer.hw,
1705 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
1706 [CLKID_ADC] = &meson8b_adc.hw,
1707 [CLKID_BLKMV] = &meson8b_blkmv.hw,
1708 [CLKID_AIU] = &meson8b_aiu.hw,
1709 [CLKID_UART1] = &meson8b_uart1.hw,
1710 [CLKID_G2D] = &meson8b_g2d.hw,
1711 [CLKID_USB0] = &meson8b_usb0.hw,
1712 [CLKID_USB1] = &meson8b_usb1.hw,
1713 [CLKID_RESET] = &meson8b_reset.hw,
1714 [CLKID_NAND] = &meson8b_nand.hw,
1715 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
1716 [CLKID_USB] = &meson8b_usb.hw,
1717 [CLKID_VDIN1] = &meson8b_vdin1.hw,
1718 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
1719 [CLKID_EFUSE] = &meson8b_efuse.hw,
1720 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
1721 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
1722 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
1723 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
1724 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
1725 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
1726 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
1727 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
1728 [CLKID_DVIN] = &meson8b_dvin.hw,
1729 [CLKID_UART2] = &meson8b_uart2.hw,
1730 [CLKID_SANA] = &meson8b_sana.hw,
1731 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
1732 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
1733 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
1734 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
1735 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
1736 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
1737 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
1738 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
1739 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
1740 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
1741 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
1742 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
1743 [CLKID_ENC480P] = &meson8b_enc480p.hw,
1744 [CLKID_RNG1] = &meson8b_rng1.hw,
1745 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
1746 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
1747 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
1748 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
1749 [CLKID_EDP] = &meson8b_edp.hw,
1750 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
1751 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
1752 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
1753 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
1754 [CLKID_MPLL0] = &meson8b_mpll0.hw,
1755 [CLKID_MPLL1] = &meson8b_mpll1.hw,
1756 [CLKID_MPLL2] = &meson8b_mpll2.hw,
1757 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
1758 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
1759 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
1760 [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
1761 [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
1762 [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
1763 [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
1764 [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
1765 [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
1766 [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
1767 [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
1768 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
1769 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
1770 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
1771 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
1772 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
1773 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
1774 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
1775 [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
1776 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
1777 [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
1778 [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
1779 [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
1780 [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
1781 [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
1782 [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
1783 [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
1784 [CLKID_ABP_SEL] = &meson8b_abp_clk_sel.hw,
1785 [CLKID_ABP] = &meson8b_abp_clk_gate.hw,
1786 [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
1787 [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
1788 [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
1789 [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
1790 [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
1791 [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
1792 [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
1793 [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
1794 [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
1795 [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
1796 [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
1797 [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
1798 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
1799 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
1800 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
1801 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
1802 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
1803 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
1804 [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
1805 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
1806 [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
1807 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
1808 [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
1809 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
1810 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
1811 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
1812 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
1813 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
1814 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
1815 [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
1816 [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
1817 [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
1818 [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
1819 [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
1820 [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
1821 [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
1822 [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
1823 [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
1824 [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
1825 [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
1826 [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
1827 [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
1828 [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
1829 [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
1830 [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
1831 [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
1832 [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
1833 [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
1834 [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
1835 [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
1836 [CLK_NR_CLKS] = NULL,
1837 },
1838 .num = CLK_NR_CLKS,
1839};
1840
1662static struct clk_hw_onecell_data meson8b_hw_onecell_data = { 1841static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
1663 .hws = { 1842 .hws = {
1664 [CLKID_XTAL] = &meson8b_xtal.hw, 1843 [CLKID_XTAL] = &meson8b_xtal.hw,
@@ -2132,7 +2311,6 @@ static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb,
2132 2311
2133static struct meson8b_nb_data meson8b_cpu_nb_data = { 2312static struct meson8b_nb_data meson8b_cpu_nb_data = {
2134 .nb.notifier_call = meson8b_cpu_clk_notifier_cb, 2313 .nb.notifier_call = meson8b_cpu_clk_notifier_cb,
2135 .onecell_data = &meson8b_hw_onecell_data,
2136}; 2314};
2137 2315
2138static const struct regmap_config clkc_regmap_config = { 2316static const struct regmap_config clkc_regmap_config = {
@@ -2141,7 +2319,8 @@ static const struct regmap_config clkc_regmap_config = {
2141 .reg_stride = 4, 2319 .reg_stride = 4,
2142}; 2320};
2143 2321
2144static void __init meson8b_clkc_init(struct device_node *np) 2322static void __init meson8b_clkc_init_common(struct device_node *np,
2323 struct clk_hw_onecell_data *clk_hw_onecell_data)
2145{ 2324{
2146 struct meson8b_clk_reset *rstc; 2325 struct meson8b_clk_reset *rstc;
2147 const char *notifier_clk_name; 2326 const char *notifier_clk_name;
@@ -2192,14 +2371,16 @@ static void __init meson8b_clkc_init(struct device_node *np)
2192 */ 2371 */
2193 for (i = CLKID_XTAL; i < CLK_NR_CLKS; i++) { 2372 for (i = CLKID_XTAL; i < CLK_NR_CLKS; i++) {
2194 /* array might be sparse */ 2373 /* array might be sparse */
2195 if (!meson8b_hw_onecell_data.hws[i]) 2374 if (!clk_hw_onecell_data->hws[i])
2196 continue; 2375 continue;
2197 2376
2198 ret = clk_hw_register(NULL, meson8b_hw_onecell_data.hws[i]); 2377 ret = clk_hw_register(NULL, clk_hw_onecell_data->hws[i]);
2199 if (ret) 2378 if (ret)
2200 return; 2379 return;
2201 } 2380 }
2202 2381
2382 meson8b_cpu_nb_data.onecell_data = clk_hw_onecell_data;
2383
2203 /* 2384 /*
2204 * FIXME we shouldn't program the muxes in notifier handlers. The 2385 * FIXME we shouldn't program the muxes in notifier handlers. The
2205 * tricky programming sequence will be handled by the forthcoming 2386 * tricky programming sequence will be handled by the forthcoming
@@ -2215,13 +2396,23 @@ static void __init meson8b_clkc_init(struct device_node *np)
2215 } 2396 }
2216 2397
2217 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, 2398 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
2218 &meson8b_hw_onecell_data); 2399 clk_hw_onecell_data);
2219 if (ret) 2400 if (ret)
2220 pr_err("%s: failed to register clock provider\n", __func__); 2401 pr_err("%s: failed to register clock provider\n", __func__);
2221} 2402}
2222 2403
2404static void __init meson8_clkc_init(struct device_node *np)
2405{
2406 return meson8b_clkc_init_common(np, &meson8_hw_onecell_data);
2407}
2408
2409static void __init meson8b_clkc_init(struct device_node *np)
2410{
2411 return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data);
2412}
2413
2223CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc", 2414CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
2224 meson8b_clkc_init); 2415 meson8_clkc_init);
2225CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc", 2416CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
2226 meson8b_clkc_init); 2417 meson8b_clkc_init);
2227CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc", 2418CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-24 09:59:17 -0500