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-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c63
1 files changed, 34 insertions, 29 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 0ea715c747bb..fd5646c11bb2 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -111,7 +111,8 @@ amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
111 111
112static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 112static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
113 struct drm_plane *plane, 113 struct drm_plane *plane,
114 unsigned long possible_crtcs); 114 unsigned long possible_crtcs,
115 const struct dc_plane_cap *plane_cap);
115static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, 116static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
116 struct drm_plane *plane, 117 struct drm_plane *plane,
117 uint32_t link_index); 118 uint32_t link_index);
@@ -1961,7 +1962,8 @@ amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
1961 1962
1962static int initialize_plane(struct amdgpu_display_manager *dm, 1963static int initialize_plane(struct amdgpu_display_manager *dm,
1963 struct amdgpu_mode_info *mode_info, int plane_id, 1964 struct amdgpu_mode_info *mode_info, int plane_id,
1964 enum drm_plane_type plane_type) 1965 enum drm_plane_type plane_type,
1966 const struct dc_plane_cap *plane_cap)
1965{ 1967{
1966 struct drm_plane *plane; 1968 struct drm_plane *plane;
1967 unsigned long possible_crtcs; 1969 unsigned long possible_crtcs;
@@ -1984,7 +1986,7 @@ static int initialize_plane(struct amdgpu_display_manager *dm,
1984 if (plane_id >= dm->dc->caps.max_streams) 1986 if (plane_id >= dm->dc->caps.max_streams)
1985 possible_crtcs = 0xff; 1987 possible_crtcs = 0xff;
1986 1988
1987 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs); 1989 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
1988 1990
1989 if (ret) { 1991 if (ret) {
1990 DRM_ERROR("KMS: Failed to initialize plane\n"); 1992 DRM_ERROR("KMS: Failed to initialize plane\n");
@@ -2037,8 +2039,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
2037 struct amdgpu_encoder *aencoder = NULL; 2039 struct amdgpu_encoder *aencoder = NULL;
2038 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2040 struct amdgpu_mode_info *mode_info = &adev->mode_info;
2039 uint32_t link_cnt; 2041 uint32_t link_cnt;
2040 int32_t overlay_planes, primary_planes; 2042 int32_t primary_planes;
2041 enum dc_connection_type new_connection_type = dc_connection_none; 2043 enum dc_connection_type new_connection_type = dc_connection_none;
2044 const struct dc_plane_cap *plane;
2042 2045
2043 link_cnt = dm->dc->caps.max_links; 2046 link_cnt = dm->dc->caps.max_links;
2044 if (amdgpu_dm_mode_config_init(dm->adev)) { 2047 if (amdgpu_dm_mode_config_init(dm->adev)) {
@@ -2046,24 +2049,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
2046 return -EINVAL; 2049 return -EINVAL;
2047 } 2050 }
2048 2051
2049 /*
2050 * Determine the number of overlay planes supported.
2051 * Only support DCN for now, and cap so we don't encourage
2052 * userspace to use up all the planes.
2053 */
2054 overlay_planes = 0;
2055
2056 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
2057 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
2058
2059 if (plane->type == DC_PLANE_TYPE_DCN_UNIVERSAL &&
2060 plane->blends_with_above && plane->blends_with_below &&
2061 plane->supports_argb8888)
2062 overlay_planes += 1;
2063 }
2064
2065 overlay_planes = min(overlay_planes, 1);
2066
2067 /* There is one primary plane per CRTC */ 2052 /* There is one primary plane per CRTC */
2068 primary_planes = dm->dc->caps.max_streams; 2053 primary_planes = dm->dc->caps.max_streams;
2069 ASSERT(primary_planes <= AMDGPU_MAX_PLANES); 2054 ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
@@ -2073,8 +2058,10 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
2073 * Order is reversed to match iteration order in atomic check. 2058 * Order is reversed to match iteration order in atomic check.
2074 */ 2059 */
2075 for (i = (primary_planes - 1); i >= 0; i--) { 2060 for (i = (primary_planes - 1); i >= 0; i--) {
2061 plane = &dm->dc->caps.planes[i];
2062
2076 if (initialize_plane(dm, mode_info, i, 2063 if (initialize_plane(dm, mode_info, i,
2077 DRM_PLANE_TYPE_PRIMARY)) { 2064 DRM_PLANE_TYPE_PRIMARY, plane)) {
2078 DRM_ERROR("KMS: Failed to initialize primary plane\n"); 2065 DRM_ERROR("KMS: Failed to initialize primary plane\n");
2079 goto fail; 2066 goto fail;
2080 } 2067 }
@@ -2085,13 +2072,30 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
2085 * These planes have a higher DRM index than the primary planes since 2072 * These planes have a higher DRM index than the primary planes since
2086 * they should be considered as having a higher z-order. 2073 * they should be considered as having a higher z-order.
2087 * Order is reversed to match iteration order in atomic check. 2074 * Order is reversed to match iteration order in atomic check.
2075 *
2076 * Only support DCN for now, and only expose one so we don't encourage
2077 * userspace to use up all the pipes.
2088 */ 2078 */
2089 for (i = (overlay_planes - 1); i >= 0; i--) { 2079 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
2080 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
2081
2082 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
2083 continue;
2084
2085 if (!plane->blends_with_above || !plane->blends_with_below)
2086 continue;
2087
2088 if (!plane->supports_argb8888)
2089 continue;
2090
2090 if (initialize_plane(dm, NULL, primary_planes + i, 2091 if (initialize_plane(dm, NULL, primary_planes + i,
2091 DRM_PLANE_TYPE_OVERLAY)) { 2092 DRM_PLANE_TYPE_OVERLAY, plane)) {
2092 DRM_ERROR("KMS: Failed to initialize overlay plane\n"); 2093 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
2093 goto fail; 2094 goto fail;
2094 } 2095 }
2096
2097 /* Only create one overlay plane. */
2098 break;
2095 } 2099 }
2096 2100
2097 for (i = 0; i < dm->dc->caps.max_streams; i++) 2101 for (i = 0; i < dm->dc->caps.max_streams; i++)
@@ -4119,7 +4123,8 @@ static const u32 cursor_formats[] = {
4119 4123
4120static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, 4124static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
4121 struct drm_plane *plane, 4125 struct drm_plane *plane,
4122 unsigned long possible_crtcs) 4126 unsigned long possible_crtcs,
4127 const struct dc_plane_cap *plane_cap)
4123{ 4128{
4124 int res = -EPERM; 4129 int res = -EPERM;
4125 4130
@@ -4156,8 +4161,8 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
4156 break; 4161 break;
4157 } 4162 }
4158 4163
4159 /* TODO: Check DC plane caps explicitly here for adding propertes */ 4164 if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
4160 if (plane->type == DRM_PLANE_TYPE_OVERLAY) { 4165 plane_cap && plane_cap->per_pixel_alpha) {
4161 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) | 4166 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
4162 BIT(DRM_MODE_BLEND_PREMULTI); 4167 BIT(DRM_MODE_BLEND_PREMULTI);
4163 4168
@@ -4189,7 +4194,7 @@ static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
4189 goto fail; 4194 goto fail;
4190 4195
4191 cursor_plane->type = DRM_PLANE_TYPE_CURSOR; 4196 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
4192 res = amdgpu_dm_plane_init(dm, cursor_plane, 0); 4197 res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
4193 4198
4194 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); 4199 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
4195 if (!acrtc) 4200 if (!acrtc)