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-rw-r--r--arch/mips/Kconfig42
-rw-r--r--arch/mips/Makefile11
-rw-r--r--arch/mips/bcm47xx/workarounds.c8
-rw-r--r--arch/mips/bmips/setup.c9
-rw-r--r--arch/mips/boot/dts/lantiq/danube.dtsi42
-rw-r--r--arch/mips/boot/dts/lantiq/easy50712.dts14
-rw-r--r--arch/mips/boot/dts/mscc/Makefile2
-rw-r--r--arch/mips/boot/dts/mscc/ocelot.dtsi19
-rw-r--r--arch/mips/boot/dts/mscc/ocelot_pcb120.dts107
-rw-r--r--arch/mips/boot/dts/mscc/ocelot_pcb123.dts6
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c16
-rw-r--r--arch/mips/cavium-octeon/setup.c9
-rw-r--r--arch/mips/cavium-octeon/smp.c7
-rw-r--r--arch/mips/configs/generic/board-ocelot.config10
-rw-r--r--arch/mips/generic/Kconfig6
-rw-r--r--arch/mips/generic/Makefile1
-rw-r--r--arch/mips/generic/Platform2
-rw-r--r--arch/mips/generic/board-ocelot.its.S (renamed from arch/mips/generic/board-ocelot_pcb123.its.S)17
-rw-r--r--arch/mips/generic/kexec.c44
-rw-r--r--arch/mips/include/asm/asm-eva.h6
-rw-r--r--arch/mips/include/asm/asm.h116
-rw-r--r--arch/mips/include/asm/io.h129
-rw-r--r--arch/mips/include/asm/kexec.h11
-rw-r--r--arch/mips/include/asm/mach-loongson64/irq.h2
-rw-r--r--arch/mips/include/asm/mach-loongson64/kernel-entry-init.h16
-rw-r--r--arch/mips/include/asm/mipsregs.h20
-rw-r--r--arch/mips/include/asm/r4kcache.h73
-rw-r--r--arch/mips/include/asm/smp-ops.h3
-rw-r--r--arch/mips/include/asm/smp.h16
-rw-r--r--arch/mips/kernel/Makefile18
-rw-r--r--arch/mips/kernel/crash.c7
-rw-r--r--arch/mips/kernel/head.S18
-rw-r--r--arch/mips/kernel/machine_kexec.c143
-rw-r--r--arch/mips/kernel/mips-mt.c59
-rw-r--r--arch/mips/kernel/relocate.c2
-rw-r--r--arch/mips/kernel/setup.c144
-rw-r--r--arch/mips/kernel/smp-bmips.c7
-rw-r--r--arch/mips/kernel/smp-cps.c80
-rw-r--r--arch/mips/kernel/traps.c5
-rw-r--r--arch/mips/kernel/unaligned.c47
-rw-r--r--arch/mips/lib/Makefile2
-rw-r--r--arch/mips/lib/iomap-pci.c7
-rw-r--r--arch/mips/lib/iomap.c227
-rw-r--r--arch/mips/lib/memcpy.S22
-rw-r--r--arch/mips/lib/memset.S60
-rw-r--r--arch/mips/loongson64/common/Makefile1
-rw-r--r--arch/mips/loongson64/fuloong-2e/Makefile2
-rw-r--r--arch/mips/loongson64/fuloong-2e/dma.c12
-rw-r--r--arch/mips/loongson64/lemote-2f/Makefile2
-rw-r--r--arch/mips/loongson64/lemote-2f/dma.c (renamed from arch/mips/loongson64/common/dma.c)4
-rw-r--r--arch/mips/loongson64/loongson-3/irq.c56
-rw-r--r--arch/mips/loongson64/loongson-3/numa.c34
-rw-r--r--arch/mips/loongson64/loongson-3/smp.c14
-rw-r--r--arch/mips/mm/init.c7
-rw-r--r--arch/mips/netlogic/common/irq.c14
-rw-r--r--arch/mips/pci/ops-loongson3.c34
-rw-r--r--arch/mips/pci/pci-legacy.c4
-rw-r--r--arch/mips/pci/pci-rt2880.c2
-rw-r--r--arch/mips/pmcs-msp71xx/msp_usb.c4
-rw-r--r--arch/mips/ralink/cevt-rt3352.c6
-rw-r--r--arch/mips/ralink/ill_acc.c2
-rw-r--r--arch/mips/ralink/rt305x.c5
-rw-r--r--arch/mips/sgi-ip22/ip28-berr.c2
-rw-r--r--arch/mips/sgi-ip27/ip27-memory.c11
-rw-r--r--arch/mips/tools/.gitignore1
-rw-r--r--arch/mips/tools/Makefile5
-rw-r--r--arch/mips/tools/elf-entry.c96
-rw-r--r--arch/mips/txx9/generic/setup.c5
68 files changed, 918 insertions, 1017 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 77c022e56e6e..53e75ddbba1c 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -21,6 +21,7 @@ config MIPS
21 select GENERIC_CLOCKEVENTS 21 select GENERIC_CLOCKEVENTS
22 select GENERIC_CMOS_UPDATE 22 select GENERIC_CMOS_UPDATE
23 select GENERIC_CPU_AUTOPROBE 23 select GENERIC_CPU_AUTOPROBE
24 select GENERIC_IOMAP
24 select GENERIC_IRQ_PROBE 25 select GENERIC_IRQ_PROBE
25 select GENERIC_IRQ_SHOW 26 select GENERIC_IRQ_SHOW
26 select GENERIC_LIB_ASHLDI3 27 select GENERIC_LIB_ASHLDI3
@@ -28,7 +29,6 @@ config MIPS
28 select GENERIC_LIB_CMPDI2 29 select GENERIC_LIB_CMPDI2
29 select GENERIC_LIB_LSHRDI3 30 select GENERIC_LIB_LSHRDI3
30 select GENERIC_LIB_UCMPDI2 31 select GENERIC_LIB_UCMPDI2
31 select GENERIC_PCI_IOMAP
32 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC 32 select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
33 select GENERIC_SMP_IDLE_THREAD 33 select GENERIC_SMP_IDLE_THREAD
34 select GENERIC_TIME_VSYSCALL 34 select GENERIC_TIME_VSYSCALL
@@ -78,6 +78,7 @@ config MIPS
78 select RTC_LIB if !MACH_LOONGSON64 78 select RTC_LIB if !MACH_LOONGSON64
79 select SYSCTL_EXCEPTION_TRACE 79 select SYSCTL_EXCEPTION_TRACE
80 select VIRT_TO_BUS 80 select VIRT_TO_BUS
81 select NO_BOOTMEM
81 82
82menu "Machine selection" 83menu "Machine selection"
83 84
@@ -132,6 +133,7 @@ config MIPS_GENERIC
132 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN 133 select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
133 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN 134 select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
134 select USE_OF 135 select USE_OF
136 select UHI_BOOT
135 help 137 help
136 Select this to build a kernel which aims to support multiple boards, 138 Select this to build a kernel which aims to support multiple boards,
137 generally using a flattened device tree passed from the bootloader 139 generally using a flattened device tree passed from the bootloader
@@ -1149,6 +1151,7 @@ config NO_IOPORT_MAP
1149 1151
1150config GENERIC_CSUM 1152config GENERIC_CSUM
1151 bool 1153 bool
1154 default y if !CPU_HAS_LOAD_STORE_LR
1152 1155
1153config GENERIC_ISA_DMA 1156config GENERIC_ISA_DMA
1154 bool 1157 bool
@@ -1367,6 +1370,7 @@ config CPU_LOONGSON3
1367 select CPU_SUPPORTS_64BIT_KERNEL 1370 select CPU_SUPPORTS_64BIT_KERNEL
1368 select CPU_SUPPORTS_HIGHMEM 1371 select CPU_SUPPORTS_HIGHMEM
1369 select CPU_SUPPORTS_HUGEPAGES 1372 select CPU_SUPPORTS_HUGEPAGES
1373 select CPU_HAS_LOAD_STORE_LR
1370 select WEAK_ORDERING 1374 select WEAK_ORDERING
1371 select WEAK_REORDERING_BEYOND_LLSC 1375 select WEAK_REORDERING_BEYOND_LLSC
1372 select MIPS_PGD_C0_CONTEXT 1376 select MIPS_PGD_C0_CONTEXT
@@ -1443,6 +1447,7 @@ config CPU_MIPS32_R1
1443 bool "MIPS32 Release 1" 1447 bool "MIPS32 Release 1"
1444 depends on SYS_HAS_CPU_MIPS32_R1 1448 depends on SYS_HAS_CPU_MIPS32_R1
1445 select CPU_HAS_PREFETCH 1449 select CPU_HAS_PREFETCH
1450 select CPU_HAS_LOAD_STORE_LR
1446 select CPU_SUPPORTS_32BIT_KERNEL 1451 select CPU_SUPPORTS_32BIT_KERNEL
1447 select CPU_SUPPORTS_HIGHMEM 1452 select CPU_SUPPORTS_HIGHMEM
1448 help 1453 help
@@ -1460,6 +1465,7 @@ config CPU_MIPS32_R2
1460 bool "MIPS32 Release 2" 1465 bool "MIPS32 Release 2"
1461 depends on SYS_HAS_CPU_MIPS32_R2 1466 depends on SYS_HAS_CPU_MIPS32_R2
1462 select CPU_HAS_PREFETCH 1467 select CPU_HAS_PREFETCH
1468 select CPU_HAS_LOAD_STORE_LR
1463 select CPU_SUPPORTS_32BIT_KERNEL 1469 select CPU_SUPPORTS_32BIT_KERNEL
1464 select CPU_SUPPORTS_HIGHMEM 1470 select CPU_SUPPORTS_HIGHMEM
1465 select CPU_SUPPORTS_MSA 1471 select CPU_SUPPORTS_MSA
@@ -1478,7 +1484,6 @@ config CPU_MIPS32_R6
1478 select CPU_SUPPORTS_32BIT_KERNEL 1484 select CPU_SUPPORTS_32BIT_KERNEL
1479 select CPU_SUPPORTS_HIGHMEM 1485 select CPU_SUPPORTS_HIGHMEM
1480 select CPU_SUPPORTS_MSA 1486 select CPU_SUPPORTS_MSA
1481 select GENERIC_CSUM
1482 select HAVE_KVM 1487 select HAVE_KVM
1483 select MIPS_O32_FP64_SUPPORT 1488 select MIPS_O32_FP64_SUPPORT
1484 help 1489 help
@@ -1491,6 +1496,7 @@ config CPU_MIPS64_R1
1491 bool "MIPS64 Release 1" 1496 bool "MIPS64 Release 1"
1492 depends on SYS_HAS_CPU_MIPS64_R1 1497 depends on SYS_HAS_CPU_MIPS64_R1
1493 select CPU_HAS_PREFETCH 1498 select CPU_HAS_PREFETCH
1499 select CPU_HAS_LOAD_STORE_LR
1494 select CPU_SUPPORTS_32BIT_KERNEL 1500 select CPU_SUPPORTS_32BIT_KERNEL
1495 select CPU_SUPPORTS_64BIT_KERNEL 1501 select CPU_SUPPORTS_64BIT_KERNEL
1496 select CPU_SUPPORTS_HIGHMEM 1502 select CPU_SUPPORTS_HIGHMEM
@@ -1510,6 +1516,7 @@ config CPU_MIPS64_R2
1510 bool "MIPS64 Release 2" 1516 bool "MIPS64 Release 2"
1511 depends on SYS_HAS_CPU_MIPS64_R2 1517 depends on SYS_HAS_CPU_MIPS64_R2
1512 select CPU_HAS_PREFETCH 1518 select CPU_HAS_PREFETCH
1519 select CPU_HAS_LOAD_STORE_LR
1513 select CPU_SUPPORTS_32BIT_KERNEL 1520 select CPU_SUPPORTS_32BIT_KERNEL
1514 select CPU_SUPPORTS_64BIT_KERNEL 1521 select CPU_SUPPORTS_64BIT_KERNEL
1515 select CPU_SUPPORTS_HIGHMEM 1522 select CPU_SUPPORTS_HIGHMEM
@@ -1531,7 +1538,6 @@ config CPU_MIPS64_R6
1531 select CPU_SUPPORTS_64BIT_KERNEL 1538 select CPU_SUPPORTS_64BIT_KERNEL
1532 select CPU_SUPPORTS_HIGHMEM 1539 select CPU_SUPPORTS_HIGHMEM
1533 select CPU_SUPPORTS_MSA 1540 select CPU_SUPPORTS_MSA
1534 select GENERIC_CSUM
1535 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32 1541 select MIPS_O32_FP64_SUPPORT if 32BIT || MIPS32_O32
1536 select HAVE_KVM 1542 select HAVE_KVM
1537 help 1543 help
@@ -1544,6 +1550,7 @@ config CPU_R3000
1544 bool "R3000" 1550 bool "R3000"
1545 depends on SYS_HAS_CPU_R3000 1551 depends on SYS_HAS_CPU_R3000
1546 select CPU_HAS_WB 1552 select CPU_HAS_WB
1553 select CPU_HAS_LOAD_STORE_LR
1547 select CPU_SUPPORTS_32BIT_KERNEL 1554 select CPU_SUPPORTS_32BIT_KERNEL
1548 select CPU_SUPPORTS_HIGHMEM 1555 select CPU_SUPPORTS_HIGHMEM
1549 help 1556 help
@@ -1558,12 +1565,14 @@ config CPU_TX39XX
1558 bool "R39XX" 1565 bool "R39XX"
1559 depends on SYS_HAS_CPU_TX39XX 1566 depends on SYS_HAS_CPU_TX39XX
1560 select CPU_SUPPORTS_32BIT_KERNEL 1567 select CPU_SUPPORTS_32BIT_KERNEL
1568 select CPU_HAS_LOAD_STORE_LR
1561 1569
1562config CPU_VR41XX 1570config CPU_VR41XX
1563 bool "R41xx" 1571 bool "R41xx"
1564 depends on SYS_HAS_CPU_VR41XX 1572 depends on SYS_HAS_CPU_VR41XX
1565 select CPU_SUPPORTS_32BIT_KERNEL 1573 select CPU_SUPPORTS_32BIT_KERNEL
1566 select CPU_SUPPORTS_64BIT_KERNEL 1574 select CPU_SUPPORTS_64BIT_KERNEL
1575 select CPU_HAS_LOAD_STORE_LR
1567 help 1576 help
1568 The options selects support for the NEC VR4100 series of processors. 1577 The options selects support for the NEC VR4100 series of processors.
1569 Only choose this option if you have one of these processors as a 1578 Only choose this option if you have one of these processors as a
@@ -1575,6 +1584,7 @@ config CPU_R4300
1575 depends on SYS_HAS_CPU_R4300 1584 depends on SYS_HAS_CPU_R4300
1576 select CPU_SUPPORTS_32BIT_KERNEL 1585 select CPU_SUPPORTS_32BIT_KERNEL
1577 select CPU_SUPPORTS_64BIT_KERNEL 1586 select CPU_SUPPORTS_64BIT_KERNEL
1587 select CPU_HAS_LOAD_STORE_LR
1578 help 1588 help
1579 MIPS Technologies R4300-series processors. 1589 MIPS Technologies R4300-series processors.
1580 1590
@@ -1584,6 +1594,7 @@ config CPU_R4X00
1584 select CPU_SUPPORTS_32BIT_KERNEL 1594 select CPU_SUPPORTS_32BIT_KERNEL
1585 select CPU_SUPPORTS_64BIT_KERNEL 1595 select CPU_SUPPORTS_64BIT_KERNEL
1586 select CPU_SUPPORTS_HUGEPAGES 1596 select CPU_SUPPORTS_HUGEPAGES
1597 select CPU_HAS_LOAD_STORE_LR
1587 help 1598 help
1588 MIPS Technologies R4000-series processors other than 4300, including 1599 MIPS Technologies R4000-series processors other than 4300, including
1589 the R4000, R4400, R4600, and 4700. 1600 the R4000, R4400, R4600, and 4700.
@@ -1592,6 +1603,7 @@ config CPU_TX49XX
1592 bool "R49XX" 1603 bool "R49XX"
1593 depends on SYS_HAS_CPU_TX49XX 1604 depends on SYS_HAS_CPU_TX49XX
1594 select CPU_HAS_PREFETCH 1605 select CPU_HAS_PREFETCH
1606 select CPU_HAS_LOAD_STORE_LR
1595 select CPU_SUPPORTS_32BIT_KERNEL 1607 select CPU_SUPPORTS_32BIT_KERNEL
1596 select CPU_SUPPORTS_64BIT_KERNEL 1608 select CPU_SUPPORTS_64BIT_KERNEL
1597 select CPU_SUPPORTS_HUGEPAGES 1609 select CPU_SUPPORTS_HUGEPAGES
@@ -1602,6 +1614,7 @@ config CPU_R5000
1602 select CPU_SUPPORTS_32BIT_KERNEL 1614 select CPU_SUPPORTS_32BIT_KERNEL
1603 select CPU_SUPPORTS_64BIT_KERNEL 1615 select CPU_SUPPORTS_64BIT_KERNEL
1604 select CPU_SUPPORTS_HUGEPAGES 1616 select CPU_SUPPORTS_HUGEPAGES
1617 select CPU_HAS_LOAD_STORE_LR
1605 help 1618 help
1606 MIPS Technologies R5000-series processors other than the Nevada. 1619 MIPS Technologies R5000-series processors other than the Nevada.
1607 1620
@@ -1611,6 +1624,7 @@ config CPU_R5432
1611 select CPU_SUPPORTS_32BIT_KERNEL 1624 select CPU_SUPPORTS_32BIT_KERNEL
1612 select CPU_SUPPORTS_64BIT_KERNEL 1625 select CPU_SUPPORTS_64BIT_KERNEL
1613 select CPU_SUPPORTS_HUGEPAGES 1626 select CPU_SUPPORTS_HUGEPAGES
1627 select CPU_HAS_LOAD_STORE_LR
1614 1628
1615config CPU_R5500 1629config CPU_R5500
1616 bool "R5500" 1630 bool "R5500"
@@ -1618,6 +1632,7 @@ config CPU_R5500
1618 select CPU_SUPPORTS_32BIT_KERNEL 1632 select CPU_SUPPORTS_32BIT_KERNEL
1619 select CPU_SUPPORTS_64BIT_KERNEL 1633 select CPU_SUPPORTS_64BIT_KERNEL
1620 select CPU_SUPPORTS_HUGEPAGES 1634 select CPU_SUPPORTS_HUGEPAGES
1635 select CPU_HAS_LOAD_STORE_LR
1621 help 1636 help
1622 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV 1637 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
1623 instruction set. 1638 instruction set.
@@ -1628,6 +1643,7 @@ config CPU_NEVADA
1628 select CPU_SUPPORTS_32BIT_KERNEL 1643 select CPU_SUPPORTS_32BIT_KERNEL
1629 select CPU_SUPPORTS_64BIT_KERNEL 1644 select CPU_SUPPORTS_64BIT_KERNEL
1630 select CPU_SUPPORTS_HUGEPAGES 1645 select CPU_SUPPORTS_HUGEPAGES
1646 select CPU_HAS_LOAD_STORE_LR
1631 help 1647 help
1632 QED / PMC-Sierra RM52xx-series ("Nevada") processors. 1648 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
1633 1649
@@ -1635,6 +1651,7 @@ config CPU_R8000
1635 bool "R8000" 1651 bool "R8000"
1636 depends on SYS_HAS_CPU_R8000 1652 depends on SYS_HAS_CPU_R8000
1637 select CPU_HAS_PREFETCH 1653 select CPU_HAS_PREFETCH
1654 select CPU_HAS_LOAD_STORE_LR
1638 select CPU_SUPPORTS_64BIT_KERNEL 1655 select CPU_SUPPORTS_64BIT_KERNEL
1639 help 1656 help
1640 MIPS Technologies R8000 processors. Note these processors are 1657 MIPS Technologies R8000 processors. Note these processors are
@@ -1644,6 +1661,7 @@ config CPU_R10000
1644 bool "R10000" 1661 bool "R10000"
1645 depends on SYS_HAS_CPU_R10000 1662 depends on SYS_HAS_CPU_R10000
1646 select CPU_HAS_PREFETCH 1663 select CPU_HAS_PREFETCH
1664 select CPU_HAS_LOAD_STORE_LR
1647 select CPU_SUPPORTS_32BIT_KERNEL 1665 select CPU_SUPPORTS_32BIT_KERNEL
1648 select CPU_SUPPORTS_64BIT_KERNEL 1666 select CPU_SUPPORTS_64BIT_KERNEL
1649 select CPU_SUPPORTS_HIGHMEM 1667 select CPU_SUPPORTS_HIGHMEM
@@ -1655,6 +1673,7 @@ config CPU_RM7000
1655 bool "RM7000" 1673 bool "RM7000"
1656 depends on SYS_HAS_CPU_RM7000 1674 depends on SYS_HAS_CPU_RM7000
1657 select CPU_HAS_PREFETCH 1675 select CPU_HAS_PREFETCH
1676 select CPU_HAS_LOAD_STORE_LR
1658 select CPU_SUPPORTS_32BIT_KERNEL 1677 select CPU_SUPPORTS_32BIT_KERNEL
1659 select CPU_SUPPORTS_64BIT_KERNEL 1678 select CPU_SUPPORTS_64BIT_KERNEL
1660 select CPU_SUPPORTS_HIGHMEM 1679 select CPU_SUPPORTS_HIGHMEM
@@ -1663,6 +1682,7 @@ config CPU_RM7000
1663config CPU_SB1 1682config CPU_SB1
1664 bool "SB1" 1683 bool "SB1"
1665 depends on SYS_HAS_CPU_SB1 1684 depends on SYS_HAS_CPU_SB1
1685 select CPU_HAS_LOAD_STORE_LR
1666 select CPU_SUPPORTS_32BIT_KERNEL 1686 select CPU_SUPPORTS_32BIT_KERNEL
1667 select CPU_SUPPORTS_64BIT_KERNEL 1687 select CPU_SUPPORTS_64BIT_KERNEL
1668 select CPU_SUPPORTS_HIGHMEM 1688 select CPU_SUPPORTS_HIGHMEM
@@ -1673,6 +1693,7 @@ config CPU_CAVIUM_OCTEON
1673 bool "Cavium Octeon processor" 1693 bool "Cavium Octeon processor"
1674 depends on SYS_HAS_CPU_CAVIUM_OCTEON 1694 depends on SYS_HAS_CPU_CAVIUM_OCTEON
1675 select CPU_HAS_PREFETCH 1695 select CPU_HAS_PREFETCH
1696 select CPU_HAS_LOAD_STORE_LR
1676 select CPU_SUPPORTS_64BIT_KERNEL 1697 select CPU_SUPPORTS_64BIT_KERNEL
1677 select WEAK_ORDERING 1698 select WEAK_ORDERING
1678 select CPU_SUPPORTS_HIGHMEM 1699 select CPU_SUPPORTS_HIGHMEM
@@ -1702,6 +1723,7 @@ config CPU_BMIPS
1702 select WEAK_ORDERING 1723 select WEAK_ORDERING
1703 select CPU_SUPPORTS_HIGHMEM 1724 select CPU_SUPPORTS_HIGHMEM
1704 select CPU_HAS_PREFETCH 1725 select CPU_HAS_PREFETCH
1726 select CPU_HAS_LOAD_STORE_LR
1705 select CPU_SUPPORTS_CPUFREQ 1727 select CPU_SUPPORTS_CPUFREQ
1706 select MIPS_EXTERNAL_TIMER 1728 select MIPS_EXTERNAL_TIMER
1707 help 1729 help
@@ -1710,6 +1732,7 @@ config CPU_BMIPS
1710config CPU_XLR 1732config CPU_XLR
1711 bool "Netlogic XLR SoC" 1733 bool "Netlogic XLR SoC"
1712 depends on SYS_HAS_CPU_XLR 1734 depends on SYS_HAS_CPU_XLR
1735 select CPU_HAS_LOAD_STORE_LR
1713 select CPU_SUPPORTS_32BIT_KERNEL 1736 select CPU_SUPPORTS_32BIT_KERNEL
1714 select CPU_SUPPORTS_64BIT_KERNEL 1737 select CPU_SUPPORTS_64BIT_KERNEL
1715 select CPU_SUPPORTS_HIGHMEM 1738 select CPU_SUPPORTS_HIGHMEM
@@ -1728,6 +1751,7 @@ config CPU_XLP
1728 select WEAK_ORDERING 1751 select WEAK_ORDERING
1729 select WEAK_REORDERING_BEYOND_LLSC 1752 select WEAK_REORDERING_BEYOND_LLSC
1730 select CPU_HAS_PREFETCH 1753 select CPU_HAS_PREFETCH
1754 select CPU_HAS_LOAD_STORE_LR
1731 select CPU_MIPSR2 1755 select CPU_MIPSR2
1732 select CPU_SUPPORTS_HUGEPAGES 1756 select CPU_SUPPORTS_HUGEPAGES
1733 select MIPS_ASID_BITS_VARIABLE 1757 select MIPS_ASID_BITS_VARIABLE
@@ -1833,12 +1857,14 @@ config CPU_LOONGSON2
1833 select CPU_SUPPORTS_HIGHMEM 1857 select CPU_SUPPORTS_HIGHMEM
1834 select CPU_SUPPORTS_HUGEPAGES 1858 select CPU_SUPPORTS_HUGEPAGES
1835 select ARCH_HAS_PHYS_TO_DMA 1859 select ARCH_HAS_PHYS_TO_DMA
1860 select CPU_HAS_LOAD_STORE_LR
1836 1861
1837config CPU_LOONGSON1 1862config CPU_LOONGSON1
1838 bool 1863 bool
1839 select CPU_MIPS32 1864 select CPU_MIPS32
1840 select CPU_MIPSR1 1865 select CPU_MIPSR1
1841 select CPU_HAS_PREFETCH 1866 select CPU_HAS_PREFETCH
1867 select CPU_HAS_LOAD_STORE_LR
1842 select CPU_SUPPORTS_32BIT_KERNEL 1868 select CPU_SUPPORTS_32BIT_KERNEL
1843 select CPU_SUPPORTS_HIGHMEM 1869 select CPU_SUPPORTS_HIGHMEM
1844 select CPU_SUPPORTS_CPUFREQ 1870 select CPU_SUPPORTS_CPUFREQ
@@ -2452,6 +2478,13 @@ config XKS01
2452config CPU_HAS_RIXI 2478config CPU_HAS_RIXI
2453 bool 2479 bool
2454 2480
2481config CPU_HAS_LOAD_STORE_LR
2482 bool
2483 help
2484 CPU has support for unaligned load and store instructions:
2485 LWL, LWR, SWL, SWR (Load/store word left/right).
2486 LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit systems).
2487
2455# 2488#
2456# Vectored interrupt mode is an R2 feature 2489# Vectored interrupt mode is an R2 feature
2457# 2490#
@@ -2899,6 +2932,9 @@ config USE_OF
2899 select OF_EARLY_FLATTREE 2932 select OF_EARLY_FLATTREE
2900 select IRQ_DOMAIN 2933 select IRQ_DOMAIN
2901 2934
2935config UHI_BOOT
2936 bool
2937
2902config BUILTIN_DTB 2938config BUILTIN_DTB
2903 bool 2939 bool
2904 2940
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index d43eeaa6d75b..15a84cfd0719 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -13,6 +13,7 @@
13# 13#
14 14
15archscripts: scripts_basic 15archscripts: scripts_basic
16 $(Q)$(MAKE) $(build)=arch/mips/tools elf-entry
16 $(Q)$(MAKE) $(build)=arch/mips/boot/tools relocs 17 $(Q)$(MAKE) $(build)=arch/mips/boot/tools relocs
17 18
18KBUILD_DEFCONFIG := 32r2el_defconfig 19KBUILD_DEFCONFIG := 32r2el_defconfig
@@ -230,6 +231,8 @@ toolchain-xpa := $(call cc-option-yn,$(xpa-cflags-y) -mxpa)
230cflags-$(toolchain-xpa) += -DTOOLCHAIN_SUPPORTS_XPA 231cflags-$(toolchain-xpa) += -DTOOLCHAIN_SUPPORTS_XPA
231toolchain-crc := $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mcrc) 232toolchain-crc := $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mcrc)
232cflags-$(toolchain-crc) += -DTOOLCHAIN_SUPPORTS_CRC 233cflags-$(toolchain-crc) += -DTOOLCHAIN_SUPPORTS_CRC
234toolchain-dsp := $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mdsp)
235cflags-$(toolchain-dsp) += -DTOOLCHAIN_SUPPORTS_DSP
233 236
234# 237#
235# Firmware support 238# Firmware support
@@ -257,13 +260,7 @@ ifdef CONFIG_PHYSICAL_START
257load-y = $(CONFIG_PHYSICAL_START) 260load-y = $(CONFIG_PHYSICAL_START)
258endif 261endif
259 262
260# Sign-extend the entry point to 64 bits if retrieved as a 32-bit number. 263entry-y = $(shell $(objtree)/arch/mips/tools/elf-entry vmlinux)
261entry-y = $(shell $(OBJDUMP) -f vmlinux 2>/dev/null \
262 | sed -n '/^start address / { \
263 s/^.* //; \
264 s/0x\([0-7].......\)$$/0x00000000\1/; \
265 s/0x\(........\)$$/0xffffffff\1/; p }')
266
267cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic 264cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
268drivers-$(CONFIG_PCI) += arch/mips/pci/ 265drivers-$(CONFIG_PCI) += arch/mips/pci/
269 266
diff --git a/arch/mips/bcm47xx/workarounds.c b/arch/mips/bcm47xx/workarounds.c
index 1a8a07e7a563..46eddbec8d9f 100644
--- a/arch/mips/bcm47xx/workarounds.c
+++ b/arch/mips/bcm47xx/workarounds.c
@@ -5,9 +5,8 @@
5#include <bcm47xx_board.h> 5#include <bcm47xx_board.h>
6#include <bcm47xx.h> 6#include <bcm47xx.h>
7 7
8static void __init bcm47xx_workarounds_netgear_wnr3500l(void) 8static void __init bcm47xx_workarounds_enable_usb_power(int usb_power)
9{ 9{
10 const int usb_power = 12;
11 int err; 10 int err;
12 11
13 err = gpio_request_one(usb_power, GPIOF_OUT_INIT_HIGH, "usb_power"); 12 err = gpio_request_one(usb_power, GPIOF_OUT_INIT_HIGH, "usb_power");
@@ -23,7 +22,10 @@ void __init bcm47xx_workarounds(void)
23 22
24 switch (board) { 23 switch (board) {
25 case BCM47XX_BOARD_NETGEAR_WNR3500L: 24 case BCM47XX_BOARD_NETGEAR_WNR3500L:
26 bcm47xx_workarounds_netgear_wnr3500l(); 25 bcm47xx_workarounds_enable_usb_power(12);
26 break;
27 case BCM47XX_BOARD_NETGEAR_WNDR3400_V3:
28 bcm47xx_workarounds_enable_usb_power(21);
27 break; 29 break;
28 default: 30 default:
29 /* No workaround(s) needed */ 31 /* No workaround(s) needed */
diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c
index 231fc5ce375e..6329c5f780d6 100644
--- a/arch/mips/bmips/setup.c
+++ b/arch/mips/bmips/setup.c
@@ -153,8 +153,6 @@ void __init plat_time_init(void)
153 mips_hpt_frequency = freq; 153 mips_hpt_frequency = freq;
154} 154}
155 155
156extern const char __appended_dtb;
157
158void __init plat_mem_setup(void) 156void __init plat_mem_setup(void)
159{ 157{
160 void *dtb; 158 void *dtb;
@@ -164,15 +162,10 @@ void __init plat_mem_setup(void)
164 ioport_resource.start = 0; 162 ioport_resource.start = 0;
165 ioport_resource.end = ~0; 163 ioport_resource.end = ~0;
166 164
167#ifdef CONFIG_MIPS_ELF_APPENDED_DTB
168 if (!fdt_check_header(&__appended_dtb))
169 dtb = (void *)&__appended_dtb;
170 else
171#endif
172 /* intended to somewhat resemble ARM; see Documentation/arm/Booting */ 165 /* intended to somewhat resemble ARM; see Documentation/arm/Booting */
173 if (fw_arg0 == 0 && fw_arg1 == 0xffffffff) 166 if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
174 dtb = phys_to_virt(fw_arg2); 167 dtb = phys_to_virt(fw_arg2);
175 else if (fw_passed_dtb) /* UHI interface */ 168 else if (fw_passed_dtb) /* UHI interface or appended dtb */
176 dtb = (void *)fw_passed_dtb; 169 dtb = (void *)fw_passed_dtb;
177 else if (__dtb_start != __dtb_end) 170 else if (__dtb_start != __dtb_end)
178 dtb = (void *)__dtb_start; 171 dtb = (void *)__dtb_start;
diff --git a/arch/mips/boot/dts/lantiq/danube.dtsi b/arch/mips/boot/dts/lantiq/danube.dtsi
index 2dd950181f8a..510be63c8bdf 100644
--- a/arch/mips/boot/dts/lantiq/danube.dtsi
+++ b/arch/mips/boot/dts/lantiq/danube.dtsi
@@ -10,12 +10,12 @@
10 }; 10 };
11 }; 11 };
12 12
13 biu@1F800000 { 13 biu@1f800000 {
14 #address-cells = <1>; 14 #address-cells = <1>;
15 #size-cells = <1>; 15 #size-cells = <1>;
16 compatible = "lantiq,biu", "simple-bus"; 16 compatible = "lantiq,biu", "simple-bus";
17 reg = <0x1F800000 0x800000>; 17 reg = <0x1f800000 0x800000>;
18 ranges = <0x0 0x1F800000 0x7FFFFF>; 18 ranges = <0x0 0x1f800000 0x7fffff>;
19 19
20 icu0: icu@80200 { 20 icu0: icu@80200 {
21 #interrupt-cells = <1>; 21 #interrupt-cells = <1>;
@@ -24,18 +24,18 @@
24 reg = <0x80200 0x120>; 24 reg = <0x80200 0x120>;
25 }; 25 };
26 26
27 watchdog@803F0 { 27 watchdog@803f0 {
28 compatible = "lantiq,wdt"; 28 compatible = "lantiq,wdt";
29 reg = <0x803F0 0x10>; 29 reg = <0x803f0 0x10>;
30 }; 30 };
31 }; 31 };
32 32
33 sram@1F000000 { 33 sram@1f000000 {
34 #address-cells = <1>; 34 #address-cells = <1>;
35 #size-cells = <1>; 35 #size-cells = <1>;
36 compatible = "lantiq,sram"; 36 compatible = "lantiq,sram";
37 reg = <0x1F000000 0x800000>; 37 reg = <0x1f000000 0x800000>;
38 ranges = <0x0 0x1F000000 0x7FFFFF>; 38 ranges = <0x0 0x1f000000 0x7fffff>;
39 39
40 eiu0: eiu@101000 { 40 eiu0: eiu@101000 {
41 #interrupt-cells = <1>; 41 #interrupt-cells = <1>;
@@ -66,41 +66,41 @@
66 #address-cells = <1>; 66 #address-cells = <1>;
67 #size-cells = <1>; 67 #size-cells = <1>;
68 compatible = "lantiq,fpi", "simple-bus"; 68 compatible = "lantiq,fpi", "simple-bus";
69 ranges = <0x0 0x10000000 0xEEFFFFF>; 69 ranges = <0x0 0x10000000 0xeefffff>;
70 reg = <0x10000000 0xEF00000>; 70 reg = <0x10000000 0xef00000>;
71 71
72 gptu@E100A00 { 72 gptu@e100a00 {
73 compatible = "lantiq,gptu-xway"; 73 compatible = "lantiq,gptu-xway";
74 reg = <0xE100A00 0x100>; 74 reg = <0xe100a00 0x100>;
75 }; 75 };
76 76
77 serial@E100C00 { 77 serial@e100c00 {
78 compatible = "lantiq,asc"; 78 compatible = "lantiq,asc";
79 reg = <0xE100C00 0x400>; 79 reg = <0xe100c00 0x400>;
80 interrupt-parent = <&icu0>; 80 interrupt-parent = <&icu0>;
81 interrupts = <112 113 114>; 81 interrupts = <112 113 114>;
82 }; 82 };
83 83
84 dma0: dma@E104100 { 84 dma0: dma@e104100 {
85 compatible = "lantiq,dma-xway"; 85 compatible = "lantiq,dma-xway";
86 reg = <0xE104100 0x800>; 86 reg = <0xe104100 0x800>;
87 }; 87 };
88 88
89 ebu0: ebu@E105300 { 89 ebu0: ebu@e105300 {
90 compatible = "lantiq,ebu-xway"; 90 compatible = "lantiq,ebu-xway";
91 reg = <0xE105300 0x100>; 91 reg = <0xe105300 0x100>;
92 }; 92 };
93 93
94 pci0: pci@E105400 { 94 pci0: pci@e105400 {
95 #address-cells = <3>; 95 #address-cells = <3>;
96 #size-cells = <2>; 96 #size-cells = <2>;
97 #interrupt-cells = <1>; 97 #interrupt-cells = <1>;
98 compatible = "lantiq,pci-xway"; 98 compatible = "lantiq,pci-xway";
99 bus-range = <0x0 0x0>; 99 bus-range = <0x0 0x0>;
100 ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */ 100 ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
101 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */ 101 0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */
102 reg = <0x7000000 0x8000 /* config space */ 102 reg = <0x7000000 0x8000 /* config space */
103 0xE105400 0x400>; /* pci bridge */ 103 0xe105400 0x400>; /* pci bridge */
104 }; 104 };
105 }; 105 };
106}; 106};
diff --git a/arch/mips/boot/dts/lantiq/easy50712.dts b/arch/mips/boot/dts/lantiq/easy50712.dts
index c37a33962f28..1ce20b7d05cb 100644
--- a/arch/mips/boot/dts/lantiq/easy50712.dts
+++ b/arch/mips/boot/dts/lantiq/easy50712.dts
@@ -52,14 +52,14 @@
52 }; 52 };
53 }; 53 };
54 54
55 gpio: pinmux@E100B10 { 55 gpio: pinmux@e100b10 {
56 compatible = "lantiq,danube-pinctrl"; 56 compatible = "lantiq,danube-pinctrl";
57 pinctrl-names = "default"; 57 pinctrl-names = "default";
58 pinctrl-0 = <&state_default>; 58 pinctrl-0 = <&state_default>;
59 59
60 #gpio-cells = <2>; 60 #gpio-cells = <2>;
61 gpio-controller; 61 gpio-controller;
62 reg = <0xE100B10 0xA0>; 62 reg = <0xe100b10 0xa0>;
63 63
64 state_default: pinmux { 64 state_default: pinmux {
65 stp { 65 stp {
@@ -82,26 +82,26 @@
82 }; 82 };
83 }; 83 };
84 84
85 etop@E180000 { 85 etop@e180000 {
86 compatible = "lantiq,etop-xway"; 86 compatible = "lantiq,etop-xway";
87 reg = <0xE180000 0x40000>; 87 reg = <0xe180000 0x40000>;
88 interrupt-parent = <&icu0>; 88 interrupt-parent = <&icu0>;
89 interrupts = <73 78>; 89 interrupts = <73 78>;
90 phy-mode = "rmii"; 90 phy-mode = "rmii";
91 mac-address = [ 00 11 22 33 44 55 ]; 91 mac-address = [ 00 11 22 33 44 55 ];
92 }; 92 };
93 93
94 stp0: stp@E100BB0 { 94 stp0: stp@e100bb0 {
95 #gpio-cells = <2>; 95 #gpio-cells = <2>;
96 compatible = "lantiq,gpio-stp-xway"; 96 compatible = "lantiq,gpio-stp-xway";
97 gpio-controller; 97 gpio-controller;
98 reg = <0xE100BB0 0x40>; 98 reg = <0xe100bb0 0x40>;
99 99
100 lantiq,shadow = <0xfff>; 100 lantiq,shadow = <0xfff>;
101 lantiq,groups = <0x3>; 101 lantiq,groups = <0x3>;
102 }; 102 };
103 103
104 pci@E105400 { 104 pci@e105400 {
105 lantiq,bus-clock = <33333333>; 105 lantiq,bus-clock = <33333333>;
106 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 106 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
107 interrupt-map = < 107 interrupt-map = <
diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile
index 9a9bb7ea0503..ec6f5b2bf093 100644
--- a/arch/mips/boot/dts/mscc/Makefile
+++ b/arch/mips/boot/dts/mscc/Makefile
@@ -1,3 +1,3 @@
1dtb-$(CONFIG_MSCC_OCELOT) += ocelot_pcb123.dtb 1dtb-$(CONFIG_MSCC_OCELOT) += ocelot_pcb123.dtb ocelot_pcb120.dtb
2 2
3obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) 3obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
index 8ce317c5b9ed..90c60d42f571 100644
--- a/arch/mips/boot/dts/mscc/ocelot.dtsi
+++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
@@ -78,6 +78,19 @@
78 status = "disabled"; 78 status = "disabled";
79 }; 79 };
80 80
81 i2c: i2c@100400 {
82 compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
83 pinctrl-0 = <&i2c_pins>;
84 pinctrl-names = "default";
85 reg = <0x100400 0x100>, <0x198 0x8>;
86 #address-cells = <1>;
87 #size-cells = <0>;
88 interrupts = <8>;
89 clocks = <&ahb_clk>;
90
91 status = "disabled";
92 };
93
81 uart2: serial@100800 { 94 uart2: serial@100800 {
82 pinctrl-0 = <&uart2_pins>; 95 pinctrl-0 = <&uart2_pins>;
83 pinctrl-names = "default"; 96 pinctrl-names = "default";
@@ -182,6 +195,11 @@
182 interrupts = <13>; 195 interrupts = <13>;
183 #interrupt-cells = <2>; 196 #interrupt-cells = <2>;
184 197
198 i2c_pins: i2c-pins {
199 pins = "GPIO_16", "GPIO_17";
200 function = "twi";
201 };
202
185 uart_pins: uart-pins { 203 uart_pins: uart-pins {
186 pins = "GPIO_6", "GPIO_7"; 204 pins = "GPIO_6", "GPIO_7";
187 function = "uart"; 205 function = "uart";
@@ -196,6 +214,7 @@
196 pins = "GPIO_14", "GPIO_15"; 214 pins = "GPIO_14", "GPIO_15";
197 function = "miim1"; 215 function = "miim1";
198 }; 216 };
217
199 }; 218 };
200 219
201 mdio0: mdio@107009c { 220 mdio0: mdio@107009c {
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
new file mode 100644
index 000000000000..33991fd209f5
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
@@ -0,0 +1,107 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2017 Microsemi Corporation */
3
4/dts-v1/;
5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/phy/phy-ocelot-serdes.h>
8#include "ocelot.dtsi"
9
10/ {
11 compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
12
13 chosen {
14 stdout-path = "serial0:115200n8";
15 };
16
17 memory@0 {
18 device_type = "memory";
19 reg = <0x0 0x0e000000>;
20 };
21};
22
23&gpio {
24 phy_int_pins: phy_int_pins {
25 pins = "GPIO_4";
26 function = "gpio";
27 };
28};
29
30&mdio0 {
31 status = "okay";
32};
33
34&mdio1 {
35 status = "okay";
36 pinctrl-names = "default";
37 pinctrl-0 = <&miim1>, <&phy_int_pins>;
38
39 phy7: ethernet-phy@0 {
40 reg = <0>;
41 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
42 interrupt-parent = <&gpio>;
43 };
44 phy6: ethernet-phy@1 {
45 reg = <1>;
46 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
47 interrupt-parent = <&gpio>;
48 };
49 phy5: ethernet-phy@2 {
50 reg = <2>;
51 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
52 interrupt-parent = <&gpio>;
53 };
54 phy4: ethernet-phy@3 {
55 reg = <3>;
56 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
57 interrupt-parent = <&gpio>;
58 };
59};
60
61&port0 {
62 phy-handle = <&phy0>;
63};
64
65&port1 {
66 phy-handle = <&phy1>;
67};
68
69&port2 {
70 phy-handle = <&phy2>;
71};
72
73&port3 {
74 phy-handle = <&phy3>;
75};
76
77&port4 {
78 phy-handle = <&phy7>;
79 phy-mode = "sgmii";
80 phys = <&serdes 4 SERDES1G(2)>;
81};
82
83&port5 {
84 phy-handle = <&phy4>;
85 phy-mode = "sgmii";
86 phys = <&serdes 5 SERDES1G(5)>;
87};
88
89&port6 {
90 phy-handle = <&phy6>;
91 phy-mode = "sgmii";
92 phys = <&serdes 6 SERDES1G(3)>;
93};
94
95&port9 {
96 phy-handle = <&phy5>;
97 phy-mode = "sgmii";
98 phys = <&serdes 9 SERDES1G(4)>;
99};
100
101&uart0 {
102 status = "okay";
103};
104
105&uart2 {
106 status = "okay";
107};
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
index 2266027759f9..ef852f382da8 100644
--- a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
@@ -36,6 +36,12 @@
36 }; 36 };
37}; 37};
38 38
39&i2c {
40 clock-frequency = <100000>;
41 i2c-sda-hold-time-ns = <300>;
42 status = "okay";
43};
44
39&mdio0 { 45&mdio0 {
40 status = "okay"; 46 status = "okay";
41}; 47};
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index 8272d8c648ca..cc1d8525e651 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -1180,8 +1180,8 @@ static int octeon_irq_gpio_xlat(struct irq_domain *d,
1180 type = IRQ_TYPE_LEVEL_LOW; 1180 type = IRQ_TYPE_LEVEL_LOW;
1181 break; 1181 break;
1182 default: 1182 default:
1183 pr_err("Error: (%s) Invalid irq trigger specification: %x\n", 1183 pr_err("Error: (%pOFn) Invalid irq trigger specification: %x\n",
1184 node->name, 1184 node,
1185 trigger); 1185 trigger);
1186 type = IRQ_TYPE_LEVEL_LOW; 1186 type = IRQ_TYPE_LEVEL_LOW;
1187 break; 1187 break;
@@ -2271,8 +2271,8 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
2271 2271
2272 parent_irq = irq_of_parse_and_map(ciu_node, 0); 2272 parent_irq = irq_of_parse_and_map(ciu_node, 0);
2273 if (!parent_irq) { 2273 if (!parent_irq) {
2274 pr_err("ERROR: Couldn't acquire parent_irq for %s\n", 2274 pr_err("ERROR: Couldn't acquire parent_irq for %pOFn\n",
2275 ciu_node->name); 2275 ciu_node);
2276 return -EINVAL; 2276 return -EINVAL;
2277 } 2277 }
2278 2278
@@ -2283,7 +2283,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
2283 2283
2284 addr = of_get_address(ciu_node, 0, NULL, NULL); 2284 addr = of_get_address(ciu_node, 0, NULL, NULL);
2285 if (!addr) { 2285 if (!addr) {
2286 pr_err("ERROR: Couldn't acquire reg(0) %s\n", ciu_node->name); 2286 pr_err("ERROR: Couldn't acquire reg(0) %pOFn\n", ciu_node);
2287 return -EINVAL; 2287 return -EINVAL;
2288 } 2288 }
2289 host_data->raw_reg = (u64)phys_to_virt( 2289 host_data->raw_reg = (u64)phys_to_virt(
@@ -2291,7 +2291,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
2291 2291
2292 addr = of_get_address(ciu_node, 1, NULL, NULL); 2292 addr = of_get_address(ciu_node, 1, NULL, NULL);
2293 if (!addr) { 2293 if (!addr) {
2294 pr_err("ERROR: Couldn't acquire reg(1) %s\n", ciu_node->name); 2294 pr_err("ERROR: Couldn't acquire reg(1) %pOFn\n", ciu_node);
2295 return -EINVAL; 2295 return -EINVAL;
2296 } 2296 }
2297 host_data->en_reg = (u64)phys_to_virt( 2297 host_data->en_reg = (u64)phys_to_virt(
@@ -2299,8 +2299,8 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
2299 2299
2300 r = of_property_read_u32(ciu_node, "cavium,max-bits", &val); 2300 r = of_property_read_u32(ciu_node, "cavium,max-bits", &val);
2301 if (r) { 2301 if (r) {
2302 pr_err("ERROR: Couldn't read cavium,max-bits from %s\n", 2302 pr_err("ERROR: Couldn't read cavium,max-bits from %pOFn\n",
2303 ciu_node->name); 2303 ciu_node);
2304 return r; 2304 return r;
2305 } 2305 }
2306 host_data->max_bits = val; 2306 host_data->max_bits = val;
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index c2426232db06..dfb95cffef3e 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -1161,15 +1161,12 @@ void __init device_tree_init(void)
1161 bool do_prune; 1161 bool do_prune;
1162 bool fill_mac; 1162 bool fill_mac;
1163 1163
1164#ifdef CONFIG_MIPS_ELF_APPENDED_DTB 1164 if (fw_passed_dtb) {
1165 if (!fdt_check_header(&__appended_dtb)) { 1165 fdt = (void *)fw_passed_dtb;
1166 fdt = &__appended_dtb;
1167 do_prune = false; 1166 do_prune = false;
1168 fill_mac = true; 1167 fill_mac = true;
1169 pr_info("Using appended Device Tree.\n"); 1168 pr_info("Using appended Device Tree.\n");
1170 } else 1169 } else if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) {
1171#endif
1172 if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) {
1173 fdt = phys_to_virt(octeon_bootinfo->fdt_addr); 1170 fdt = phys_to_virt(octeon_bootinfo->fdt_addr);
1174 if (fdt_check_header(fdt)) 1171 if (fdt_check_header(fdt))
1175 panic("Corrupt Device Tree passed to kernel."); 1172 panic("Corrupt Device Tree passed to kernel.");
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index 75e7c8625659..39f2a2ec1286 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -15,6 +15,7 @@
15#include <linux/sched/task_stack.h> 15#include <linux/sched/task_stack.h>
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/export.h> 17#include <linux/export.h>
18#include <linux/kexec.h>
18 19
19#include <asm/mmu_context.h> 20#include <asm/mmu_context.h>
20#include <asm/time.h> 21#include <asm/time.h>
@@ -424,6 +425,9 @@ const struct plat_smp_ops octeon_smp_ops = {
424 .cpu_disable = octeon_cpu_disable, 425 .cpu_disable = octeon_cpu_disable,
425 .cpu_die = octeon_cpu_die, 426 .cpu_die = octeon_cpu_die,
426#endif 427#endif
428#ifdef CONFIG_KEXEC
429 .kexec_nonboot_cpu = kexec_nonboot_cpu_jump,
430#endif
427}; 431};
428 432
429static irqreturn_t octeon_78xx_reched_interrupt(int irq, void *dev_id) 433static irqreturn_t octeon_78xx_reched_interrupt(int irq, void *dev_id)
@@ -501,6 +505,9 @@ static const struct plat_smp_ops octeon_78xx_smp_ops = {
501 .cpu_disable = octeon_cpu_disable, 505 .cpu_disable = octeon_cpu_disable,
502 .cpu_die = octeon_cpu_die, 506 .cpu_die = octeon_cpu_die,
503#endif 507#endif
508#ifdef CONFIG_KEXEC
509 .kexec_nonboot_cpu = kexec_nonboot_cpu_jump,
510#endif
504}; 511};
505 512
506void __init octeon_setup_smp(void) 513void __init octeon_setup_smp(void)
diff --git a/arch/mips/configs/generic/board-ocelot.config b/arch/mips/configs/generic/board-ocelot.config
index aa815761d85e..f607888d2483 100644
--- a/arch/mips/configs/generic/board-ocelot.config
+++ b/arch/mips/configs/generic/board-ocelot.config
@@ -18,17 +18,25 @@ CONFIG_SERIAL_8250=y
18CONFIG_SERIAL_8250_CONSOLE=y 18CONFIG_SERIAL_8250_CONSOLE=y
19CONFIG_SERIAL_OF_PLATFORM=y 19CONFIG_SERIAL_OF_PLATFORM=y
20 20
21CONFIG_GPIO_SYSFS=y 21CONFIG_NETDEVICES=y
22CONFIG_MSCC_OCELOT_SWITCH=y
23CONFIG_MSCC_OCELOT_SWITCH_OCELOT=y
24CONFIG_MDIO_MSCC_MIIM=y
25CONFIG_MICROSEMI_PHY=y
22 26
23CONFIG_I2C=y 27CONFIG_I2C=y
24CONFIG_I2C_CHARDEV=y 28CONFIG_I2C_CHARDEV=y
25CONFIG_I2C_MUX=y 29CONFIG_I2C_MUX=y
30CONFIG_I2C_DESIGNWARE_PLATFORM=y
26 31
27CONFIG_SPI=y 32CONFIG_SPI=y
28CONFIG_SPI_BITBANG=y 33CONFIG_SPI_BITBANG=y
29CONFIG_SPI_DESIGNWARE=y 34CONFIG_SPI_DESIGNWARE=y
35CONFIG_SPI_DW_MMIO=y
30CONFIG_SPI_SPIDEV=y 36CONFIG_SPI_SPIDEV=y
31 37
38CONFIG_GPIO_SYSFS=y
39
32CONFIG_POWER_RESET=y 40CONFIG_POWER_RESET=y
33CONFIG_POWER_RESET_OCELOT_RESET=y 41CONFIG_POWER_RESET_OCELOT_RESET=y
34 42
diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
index 08e33c6b2539..fd6019802657 100644
--- a/arch/mips/generic/Kconfig
+++ b/arch/mips/generic/Kconfig
@@ -65,11 +65,11 @@ config FIT_IMAGE_FDT_XILFPGA
65 Enable this to include the FDT for the MIPSfpga platform 65 Enable this to include the FDT for the MIPSfpga platform
66 from Imagination Technologies in the FIT kernel image. 66 from Imagination Technologies in the FIT kernel image.
67 67
68config FIT_IMAGE_FDT_OCELOT_PCB123 68config FIT_IMAGE_FDT_OCELOT
69 bool "Include FDT for Microsemi Ocelot PCB123" 69 bool "Include FDT for Microsemi Ocelot development platforms"
70 select MSCC_OCELOT 70 select MSCC_OCELOT
71 help 71 help
72 Enable this to include the FDT for the Ocelot PCB123 platform 72 Enable this to include the FDT for the Ocelot development platforms
73 from Microsemi in the FIT kernel image. 73 from Microsemi in the FIT kernel image.
74 This requires u-boot on the platform. 74 This requires u-boot on the platform.
75 75
diff --git a/arch/mips/generic/Makefile b/arch/mips/generic/Makefile
index d03a36f869a4..181aa1335419 100644
--- a/arch/mips/generic/Makefile
+++ b/arch/mips/generic/Makefile
@@ -15,5 +15,4 @@ obj-y += proc.o
15obj-$(CONFIG_YAMON_DT_SHIM) += yamon-dt.o 15obj-$(CONFIG_YAMON_DT_SHIM) += yamon-dt.o
16obj-$(CONFIG_LEGACY_BOARD_SEAD3) += board-sead3.o 16obj-$(CONFIG_LEGACY_BOARD_SEAD3) += board-sead3.o
17obj-$(CONFIG_LEGACY_BOARD_OCELOT) += board-ocelot.o 17obj-$(CONFIG_LEGACY_BOARD_OCELOT) += board-ocelot.o
18obj-$(CONFIG_KEXEC) += kexec.o
19obj-$(CONFIG_VIRT_BOARD_RANCHU) += board-ranchu.o 18obj-$(CONFIG_VIRT_BOARD_RANCHU) += board-ranchu.o
diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform
index 879cb80396c8..eaa19d189324 100644
--- a/arch/mips/generic/Platform
+++ b/arch/mips/generic/Platform
@@ -16,5 +16,5 @@ all-$(CONFIG_MIPS_GENERIC) := vmlinux.gz.itb
16its-y := vmlinux.its.S 16its-y := vmlinux.its.S
17its-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += board-boston.its.S 17its-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += board-boston.its.S
18its-$(CONFIG_FIT_IMAGE_FDT_NI169445) += board-ni169445.its.S 18its-$(CONFIG_FIT_IMAGE_FDT_NI169445) += board-ni169445.its.S
19its-$(CONFIG_FIT_IMAGE_FDT_OCELOT_PCB123) += board-ocelot_pcb123.its.S 19its-$(CONFIG_FIT_IMAGE_FDT_OCELOT) += board-ocelot.its.S
20its-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += board-xilfpga.its.S 20its-$(CONFIG_FIT_IMAGE_FDT_XILFPGA) += board-xilfpga.its.S
diff --git a/arch/mips/generic/board-ocelot_pcb123.its.S b/arch/mips/generic/board-ocelot.its.S
index 5a7d5e1c878a..3da23988149a 100644
--- a/arch/mips/generic/board-ocelot_pcb123.its.S
+++ b/arch/mips/generic/board-ocelot.its.S
@@ -11,6 +11,17 @@
11 algo = "sha1"; 11 algo = "sha1";
12 }; 12 };
13 }; 13 };
14
15 fdt@ocelot_pcb120 {
16 description = "MSCC Ocelot PCB120 Device Tree";
17 data = /incbin/("boot/dts/mscc/ocelot_pcb120.dtb");
18 type = "flat_dt";
19 arch = "mips";
20 compression = "none";
21 hash@0 {
22 algo = "sha1";
23 };
24 };
14 }; 25 };
15 26
16 configurations { 27 configurations {
@@ -19,5 +30,11 @@
19 kernel = "kernel@0"; 30 kernel = "kernel@0";
20 fdt = "fdt@ocelot_pcb123"; 31 fdt = "fdt@ocelot_pcb123";
21 }; 32 };
33
34 conf@ocelot_pcb120 {
35 description = "Ocelot Linux kernel";
36 kernel = "kernel@0";
37 fdt = "fdt@ocelot_pcb120";
38 };
22 }; 39 };
23}; 40};
diff --git a/arch/mips/generic/kexec.c b/arch/mips/generic/kexec.c
deleted file mode 100644
index 1ca409f58929..000000000000
--- a/arch/mips/generic/kexec.c
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * Copyright (C) 2016 Imagination Technologies
3 * Author: Marcin Nowakowski <marcin.nowakowski@mips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#include <linux/kexec.h>
12#include <linux/libfdt.h>
13#include <linux/uaccess.h>
14
15static int generic_kexec_prepare(struct kimage *image)
16{
17 int i;
18
19 for (i = 0; i < image->nr_segments; i++) {
20 struct fdt_header fdt;
21
22 if (image->segment[i].memsz <= sizeof(fdt))
23 continue;
24
25 if (copy_from_user(&fdt, image->segment[i].buf, sizeof(fdt)))
26 continue;
27
28 if (fdt_check_header(&fdt))
29 continue;
30
31 kexec_args[0] = -2;
32 kexec_args[1] = (unsigned long)
33 phys_to_virt((unsigned long)image->segment[i].mem);
34 break;
35 }
36 return 0;
37}
38
39static int __init register_generic_kexec(void)
40{
41 _machine_kexec_prepare = generic_kexec_prepare;
42 return 0;
43}
44arch_initcall(register_generic_kexec);
diff --git a/arch/mips/include/asm/asm-eva.h b/arch/mips/include/asm/asm-eva.h
index 1e38f0e1ea3e..d80be38c4144 100644
--- a/arch/mips/include/asm/asm-eva.h
+++ b/arch/mips/include/asm/asm-eva.h
@@ -15,6 +15,7 @@
15/* Kernel variants */ 15/* Kernel variants */
16 16
17#define kernel_cache(op, base) "cache " op ", " base "\n" 17#define kernel_cache(op, base) "cache " op ", " base "\n"
18#define kernel_pref(hint, base) "pref " hint ", " base "\n"
18#define kernel_ll(reg, addr) "ll " reg ", " addr "\n" 19#define kernel_ll(reg, addr) "ll " reg ", " addr "\n"
19#define kernel_sc(reg, addr) "sc " reg ", " addr "\n" 20#define kernel_sc(reg, addr) "sc " reg ", " addr "\n"
20#define kernel_lw(reg, addr) "lw " reg ", " addr "\n" 21#define kernel_lw(reg, addr) "lw " reg ", " addr "\n"
@@ -51,6 +52,7 @@
51 " .set pop\n" 52 " .set pop\n"
52 53
53#define user_cache(op, base) __BUILD_EVA_INSN("cachee", op, base) 54#define user_cache(op, base) __BUILD_EVA_INSN("cachee", op, base)
55#define user_pref(hint, base) __BUILD_EVA_INSN("prefe", hint, base)
54#define user_ll(reg, addr) __BUILD_EVA_INSN("lle", reg, addr) 56#define user_ll(reg, addr) __BUILD_EVA_INSN("lle", reg, addr)
55#define user_sc(reg, addr) __BUILD_EVA_INSN("sce", reg, addr) 57#define user_sc(reg, addr) __BUILD_EVA_INSN("sce", reg, addr)
56#define user_lw(reg, addr) __BUILD_EVA_INSN("lwe", reg, addr) 58#define user_lw(reg, addr) __BUILD_EVA_INSN("lwe", reg, addr)
@@ -72,6 +74,7 @@
72#else 74#else
73 75
74#define user_cache(op, base) kernel_cache(op, base) 76#define user_cache(op, base) kernel_cache(op, base)
77#define user_pref(hint, base) kernel_pref(hint, base)
75#define user_ll(reg, addr) kernel_ll(reg, addr) 78#define user_ll(reg, addr) kernel_ll(reg, addr)
76#define user_sc(reg, addr) kernel_sc(reg, addr) 79#define user_sc(reg, addr) kernel_sc(reg, addr)
77#define user_lw(reg, addr) kernel_lw(reg, addr) 80#define user_lw(reg, addr) kernel_lw(reg, addr)
@@ -99,6 +102,7 @@
99#else /* __ASSEMBLY__ */ 102#else /* __ASSEMBLY__ */
100 103
101#define kernel_cache(op, base) cache op, base 104#define kernel_cache(op, base) cache op, base
105#define kernel_pref(hint, base) pref hint, base
102#define kernel_ll(reg, addr) ll reg, addr 106#define kernel_ll(reg, addr) ll reg, addr
103#define kernel_sc(reg, addr) sc reg, addr 107#define kernel_sc(reg, addr) sc reg, addr
104#define kernel_lw(reg, addr) lw reg, addr 108#define kernel_lw(reg, addr) lw reg, addr
@@ -135,6 +139,7 @@
135 .set pop; 139 .set pop;
136 140
137#define user_cache(op, base) __BUILD_EVA_INSN(cachee, op, base) 141#define user_cache(op, base) __BUILD_EVA_INSN(cachee, op, base)
142#define user_pref(hint, base) __BUILD_EVA_INSN(prefe, hint, base)
138#define user_ll(reg, addr) __BUILD_EVA_INSN(lle, reg, addr) 143#define user_ll(reg, addr) __BUILD_EVA_INSN(lle, reg, addr)
139#define user_sc(reg, addr) __BUILD_EVA_INSN(sce, reg, addr) 144#define user_sc(reg, addr) __BUILD_EVA_INSN(sce, reg, addr)
140#define user_lw(reg, addr) __BUILD_EVA_INSN(lwe, reg, addr) 145#define user_lw(reg, addr) __BUILD_EVA_INSN(lwe, reg, addr)
@@ -155,6 +160,7 @@
155#else 160#else
156 161
157#define user_cache(op, base) kernel_cache(op, base) 162#define user_cache(op, base) kernel_cache(op, base)
163#define user_pref(hint, base) kernel_pref(hint, base)
158#define user_ll(reg, addr) kernel_ll(reg, addr) 164#define user_ll(reg, addr) kernel_ll(reg, addr)
159#define user_sc(reg, addr) kernel_sc(reg, addr) 165#define user_sc(reg, addr) kernel_sc(reg, addr)
160#define user_lw(reg, addr) kernel_lw(reg, addr) 166#define user_lw(reg, addr) kernel_lw(reg, addr)
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index 81fae23ce7cd..c23527ba65d0 100644
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -20,32 +20,6 @@
20#include <asm/sgidefs.h> 20#include <asm/sgidefs.h>
21#include <asm/asm-eva.h> 21#include <asm/asm-eva.h>
22 22
23#ifndef CAT
24#ifdef __STDC__
25#define __CAT(str1, str2) str1##str2
26#else
27#define __CAT(str1, str2) str1/**/str2
28#endif
29#define CAT(str1, str2) __CAT(str1, str2)
30#endif
31
32/*
33 * PIC specific declarations
34 * Not used for the kernel but here seems to be the right place.
35 */
36#ifdef __PIC__
37#define CPRESTORE(register) \
38 .cprestore register
39#define CPADD(register) \
40 .cpadd register
41#define CPLOAD(register) \
42 .cpload register
43#else
44#define CPRESTORE(register)
45#define CPADD(register)
46#define CPLOAD(register)
47#endif
48
49/* 23/*
50 * LEAF - declare leaf routine 24 * LEAF - declare leaf routine
51 */ 25 */
@@ -130,96 +104,6 @@ symbol = value
130 .popsection; 104 .popsection;
131 105
132/* 106/*
133 * Build text tables
134 */
135#define TTABLE(string) \
136 .pushsection .text; \
137 .word 1f; \
138 .popsection \
139 .pushsection .data; \
1401: .asciiz string; \
141 .popsection
142
143/*
144 * MIPS IV pref instruction.
145 * Use with .set noreorder only!
146 *
147 * MIPS IV implementations are free to treat this as a nop. The R5000
148 * is one of them. So we should have an option not to use this instruction.
149 */
150#ifdef CONFIG_CPU_HAS_PREFETCH
151
152#define PREF(hint,addr) \
153 .set push; \
154 .set arch=r5000; \
155 pref hint, addr; \
156 .set pop
157
158#define PREFE(hint, addr) \
159 .set push; \
160 .set mips0; \
161 .set eva; \
162 prefe hint, addr; \
163 .set pop
164
165#define PREFX(hint,addr) \
166 .set push; \
167 .set arch=r5000; \
168 prefx hint, addr; \
169 .set pop
170
171#else /* !CONFIG_CPU_HAS_PREFETCH */
172
173#define PREF(hint, addr)
174#define PREFE(hint, addr)
175#define PREFX(hint, addr)
176
177#endif /* !CONFIG_CPU_HAS_PREFETCH */
178
179/*
180 * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
181 */
182#if (_MIPS_ISA == _MIPS_ISA_MIPS1)
183#define MOVN(rd, rs, rt) \
184 .set push; \
185 .set reorder; \
186 beqz rt, 9f; \
187 move rd, rs; \
188 .set pop; \
1899:
190#define MOVZ(rd, rs, rt) \
191 .set push; \
192 .set reorder; \
193 bnez rt, 9f; \
194 move rd, rs; \
195 .set pop; \
1969:
197#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
198#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
199#define MOVN(rd, rs, rt) \
200 .set push; \
201 .set noreorder; \
202 bnezl rt, 9f; \
203 move rd, rs; \
204 .set pop; \
2059:
206#define MOVZ(rd, rs, rt) \
207 .set push; \
208 .set noreorder; \
209 beqzl rt, 9f; \
210 move rd, rs; \
211 .set pop; \
2129:
213#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
214#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
215 (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
216#define MOVN(rd, rs, rt) \
217 movn rd, rs, rt
218#define MOVZ(rd, rs, rt) \
219 movz rd, rs, rt
220#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
221
222/*
223 * Stack alignment 107 * Stack alignment
224 */ 108 */
225#if (_MIPS_SIM == _MIPS_SIM_ABI32) 109#if (_MIPS_SIM == _MIPS_SIM_ABI32)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 54c730aed327..266257d56fb6 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -20,6 +20,7 @@
20#include <linux/irqflags.h> 20#include <linux/irqflags.h>
21 21
22#include <asm/addrspace.h> 22#include <asm/addrspace.h>
23#include <asm/barrier.h>
23#include <asm/bug.h> 24#include <asm/bug.h>
24#include <asm/byteorder.h> 25#include <asm/byteorder.h>
25#include <asm/cpu.h> 26#include <asm/cpu.h>
@@ -34,11 +35,6 @@
34#include <mangle-port.h> 35#include <mangle-port.h>
35 36
36/* 37/*
37 * Slowdown I/O port space accesses for antique hardware.
38 */
39#undef CONF_SLOWDOWN_IO
40
41/*
42 * Raw operations are never swapped in software. OTOH values that raw 38 * Raw operations are never swapped in software. OTOH values that raw
43 * operations are working on may or may not have been swapped by the bus 39 * operations are working on may or may not have been swapped by the bus
44 * hardware. An example use would be for flash memory that's used for 40 * hardware. An example use would be for flash memory that's used for
@@ -50,6 +46,11 @@
50# define __raw_ioswabq(a, x) (x) 46# define __raw_ioswabq(a, x) (x)
51# define ____raw_ioswabq(a, x) (x) 47# define ____raw_ioswabq(a, x) (x)
52 48
49# define __relaxed_ioswabb ioswabb
50# define __relaxed_ioswabw ioswabw
51# define __relaxed_ioswabl ioswabl
52# define __relaxed_ioswabq ioswabq
53
53/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ 54/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
54 55
55#define IO_SPACE_LIMIT 0xffff 56#define IO_SPACE_LIMIT 0xffff
@@ -80,31 +81,29 @@ static inline void set_io_port_base(unsigned long base)
80} 81}
81 82
82/* 83/*
83 * Thanks to James van Artsdalen for a better timing-fix than 84 * Provide the necessary definitions for generic iomap. We make use of
84 * the two short jumps: using outb's to a nonexistent port seems 85 * mips_io_port_base for iomap(), but we don't reserve any low addresses for
85 * to guarantee better timings even on fast machines. 86 * use with I/O ports.
86 *
87 * On the other hand, I'd like to be sure of a non-existent port:
88 * I feel a bit unsafe about using 0x80 (should be safe, though)
89 *
90 * Linus
91 *
92 */ 87 */
93 88
94#define __SLOW_DOWN_IO \ 89#define HAVE_ARCH_PIO_SIZE
95 __asm__ __volatile__( \ 90#define PIO_OFFSET mips_io_port_base
96 "sb\t$0,0x80(%0)" \ 91#define PIO_MASK IO_SPACE_LIMIT
97 : : "r" (mips_io_port_base)); 92#define PIO_RESERVED 0x0UL
98 93
99#ifdef CONF_SLOWDOWN_IO 94/*
100#ifdef REALLY_SLOW_IO 95 * Enforce in-order execution of data I/O. In the MIPS architecture
101#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; } 96 * these are equivalent to corresponding platform-specific memory
102#else 97 * barriers defined in <asm/barrier.h>. API pinched from PowerPC,
103#define SLOW_DOWN_IO __SLOW_DOWN_IO 98 * with sync additionally defined.
104#endif 99 */
105#else 100#define iobarrier_rw() mb()
106#define SLOW_DOWN_IO 101#define iobarrier_r() rmb()
107#endif 102#define iobarrier_w() wmb()
103#define iobarrier_sync() iob()
104
105/* Some callers use this older API instead. */
106#define mmiowb() iobarrier_w()
108 107
109/* 108/*
110 * virt_to_phys - map virtual addresses to physical 109 * virt_to_phys - map virtual addresses to physical
@@ -172,11 +171,6 @@ static inline void *isa_bus_to_virt(unsigned long address)
172extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags); 171extern void __iomem * __ioremap(phys_addr_t offset, phys_addr_t size, unsigned long flags);
173extern void __iounmap(const volatile void __iomem *addr); 172extern void __iounmap(const volatile void __iomem *addr);
174 173
175#ifndef CONFIG_PCI
176struct pci_dev;
177static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
178#endif
179
180static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size, 174static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long size,
181 unsigned long flags) 175 unsigned long flags)
182{ 176{
@@ -316,13 +310,13 @@ static inline void iounmap(const volatile void __iomem *addr)
316#undef __IS_KSEG1 310#undef __IS_KSEG1
317} 311}
318 312
319#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_LOONGSON3_ENHANCEMENT) 313#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON3)
320#define war_io_reorder_wmb() wmb() 314#define war_io_reorder_wmb() wmb()
321#else 315#else
322#define war_io_reorder_wmb() barrier() 316#define war_io_reorder_wmb() barrier()
323#endif 317#endif
324 318
325#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \ 319#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq) \
326 \ 320 \
327static inline void pfx##write##bwlq(type val, \ 321static inline void pfx##write##bwlq(type val, \
328 volatile void __iomem *mem) \ 322 volatile void __iomem *mem) \
@@ -330,7 +324,10 @@ static inline void pfx##write##bwlq(type val, \
330 volatile type *__mem; \ 324 volatile type *__mem; \
331 type __val; \ 325 type __val; \
332 \ 326 \
333 war_io_reorder_wmb(); \ 327 if (barrier) \
328 iobarrier_rw(); \
329 else \
330 war_io_reorder_wmb(); \
334 \ 331 \
335 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ 332 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
336 \ 333 \
@@ -367,6 +364,9 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
367 \ 364 \
368 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ 365 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
369 \ 366 \
367 if (barrier) \
368 iobarrier_rw(); \
369 \
370 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ 370 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
371 __val = *__mem; \ 371 __val = *__mem; \
372 else if (cpu_has_64bits) { \ 372 else if (cpu_has_64bits) { \
@@ -390,18 +390,22 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
390 } \ 390 } \
391 \ 391 \
392 /* prevent prefetching of coherent DMA data prematurely */ \ 392 /* prevent prefetching of coherent DMA data prematurely */ \
393 rmb(); \ 393 if (!relax) \
394 rmb(); \
394 return pfx##ioswab##bwlq(__mem, __val); \ 395 return pfx##ioswab##bwlq(__mem, __val); \
395} 396}
396 397
397#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \ 398#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax, p) \
398 \ 399 \
399static inline void pfx##out##bwlq##p(type val, unsigned long port) \ 400static inline void pfx##out##bwlq##p(type val, unsigned long port) \
400{ \ 401{ \
401 volatile type *__addr; \ 402 volatile type *__addr; \
402 type __val; \ 403 type __val; \
403 \ 404 \
404 war_io_reorder_wmb(); \ 405 if (barrier) \
406 iobarrier_rw(); \
407 else \
408 war_io_reorder_wmb(); \
405 \ 409 \
406 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ 410 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
407 \ 411 \
@@ -411,7 +415,6 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \
411 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ 415 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
412 \ 416 \
413 *__addr = __val; \ 417 *__addr = __val; \
414 slow; \
415} \ 418} \
416 \ 419 \
417static inline type pfx##in##bwlq##p(unsigned long port) \ 420static inline type pfx##in##bwlq##p(unsigned long port) \
@@ -423,23 +426,27 @@ static inline type pfx##in##bwlq##p(unsigned long port) \
423 \ 426 \
424 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ 427 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
425 \ 428 \
429 if (barrier) \
430 iobarrier_rw(); \
431 \
426 __val = *__addr; \ 432 __val = *__addr; \
427 slow; \
428 \ 433 \
429 /* prevent prefetching of coherent DMA data prematurely */ \ 434 /* prevent prefetching of coherent DMA data prematurely */ \
430 rmb(); \ 435 if (!relax) \
436 rmb(); \
431 return pfx##ioswab##bwlq(__addr, __val); \ 437 return pfx##ioswab##bwlq(__addr, __val); \
432} 438}
433 439
434#define __BUILD_MEMORY_PFX(bus, bwlq, type) \ 440#define __BUILD_MEMORY_PFX(bus, bwlq, type, relax) \
435 \ 441 \
436__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1) 442__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1, relax, 1)
437 443
438#define BUILDIO_MEM(bwlq, type) \ 444#define BUILDIO_MEM(bwlq, type) \
439 \ 445 \
440__BUILD_MEMORY_PFX(__raw_, bwlq, type) \ 446__BUILD_MEMORY_PFX(__raw_, bwlq, type, 0) \
441__BUILD_MEMORY_PFX(, bwlq, type) \ 447__BUILD_MEMORY_PFX(__relaxed_, bwlq, type, 1) \
442__BUILD_MEMORY_PFX(__mem_, bwlq, type) \ 448__BUILD_MEMORY_PFX(__mem_, bwlq, type, 0) \
449__BUILD_MEMORY_PFX(, bwlq, type, 0)
443 450
444BUILDIO_MEM(b, u8) 451BUILDIO_MEM(b, u8)
445BUILDIO_MEM(w, u16) 452BUILDIO_MEM(w, u16)
@@ -447,8 +454,8 @@ BUILDIO_MEM(l, u32)
447BUILDIO_MEM(q, u64) 454BUILDIO_MEM(q, u64)
448 455
449#define __BUILD_IOPORT_PFX(bus, bwlq, type) \ 456#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
450 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \ 457 __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,) \
451 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO) 458 __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0, _p)
452 459
453#define BUILDIO_IOPORT(bwlq, type) \ 460#define BUILDIO_IOPORT(bwlq, type) \
454 __BUILD_IOPORT_PFX(, bwlq, type) \ 461 __BUILD_IOPORT_PFX(, bwlq, type) \
@@ -463,19 +470,19 @@ BUILDIO_IOPORT(q, u64)
463 470
464#define __BUILDIO(bwlq, type) \ 471#define __BUILDIO(bwlq, type) \
465 \ 472 \
466__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0) 473__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 1, 0, 0)
467 474
468__BUILDIO(q, u64) 475__BUILDIO(q, u64)
469 476
470#define readb_relaxed readb 477#define readb_relaxed __relaxed_readb
471#define readw_relaxed readw 478#define readw_relaxed __relaxed_readw
472#define readl_relaxed readl 479#define readl_relaxed __relaxed_readl
473#define readq_relaxed readq 480#define readq_relaxed __relaxed_readq
474 481
475#define writeb_relaxed writeb 482#define writeb_relaxed __relaxed_writeb
476#define writew_relaxed writew 483#define writew_relaxed __relaxed_writew
477#define writel_relaxed writel 484#define writel_relaxed __relaxed_writel
478#define writeq_relaxed writeq 485#define writeq_relaxed __relaxed_writeq
479 486
480#define readb_be(addr) \ 487#define readb_be(addr) \
481 __raw_readb((__force unsigned *)(addr)) 488 __raw_readb((__force unsigned *)(addr))
@@ -561,14 +568,6 @@ BUILDSTRING(l, u32)
561BUILDSTRING(q, u64) 568BUILDSTRING(q, u64)
562#endif 569#endif
563 570
564
565#ifdef CONFIG_CPU_CAVIUM_OCTEON
566#define mmiowb() wmb()
567#else
568/* Depends on MIPS II instruction set */
569#define mmiowb() asm volatile ("sync" ::: "memory")
570#endif
571
572static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) 571static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
573{ 572{
574 memset((void __force *) addr, val, count); 573 memset((void __force *) addr, val, count);
diff --git a/arch/mips/include/asm/kexec.h b/arch/mips/include/asm/kexec.h
index 493a3cc7c39a..40795ca89961 100644
--- a/arch/mips/include/asm/kexec.h
+++ b/arch/mips/include/asm/kexec.h
@@ -12,11 +12,11 @@
12#include <asm/stacktrace.h> 12#include <asm/stacktrace.h>
13 13
14/* Maximum physical address we can use pages from */ 14/* Maximum physical address we can use pages from */
15#define KEXEC_SOURCE_MEMORY_LIMIT (0x20000000) 15#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
16/* Maximum address we can reach in physical address mode */ 16/* Maximum address we can reach in physical address mode */
17#define KEXEC_DESTINATION_MEMORY_LIMIT (0x20000000) 17#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
18 /* Maximum address we can use for the control code buffer */ 18 /* Maximum address we can use for the control code buffer */
19#define KEXEC_CONTROL_MEMORY_LIMIT (0x20000000) 19#define KEXEC_CONTROL_MEMORY_LIMIT (-1UL)
20/* Reserve 3*4096 bytes for board-specific info */ 20/* Reserve 3*4096 bytes for board-specific info */
21#define KEXEC_CONTROL_PAGE_SIZE (4096 + 3*4096) 21#define KEXEC_CONTROL_PAGE_SIZE (4096 + 3*4096)
22 22
@@ -39,11 +39,12 @@ extern unsigned long kexec_args[4];
39extern int (*_machine_kexec_prepare)(struct kimage *); 39extern int (*_machine_kexec_prepare)(struct kimage *);
40extern void (*_machine_kexec_shutdown)(void); 40extern void (*_machine_kexec_shutdown)(void);
41extern void (*_machine_crash_shutdown)(struct pt_regs *regs); 41extern void (*_machine_crash_shutdown)(struct pt_regs *regs);
42extern void default_machine_crash_shutdown(struct pt_regs *regs); 42void default_machine_crash_shutdown(struct pt_regs *regs);
43void kexec_nonboot_cpu_jump(void);
44void kexec_reboot(void);
43#ifdef CONFIG_SMP 45#ifdef CONFIG_SMP
44extern const unsigned char kexec_smp_wait[]; 46extern const unsigned char kexec_smp_wait[];
45extern unsigned long secondary_kexec_args[4]; 47extern unsigned long secondary_kexec_args[4];
46extern void (*relocated_kexec_smp_wait) (void *);
47extern atomic_t kexec_ready_to_reboot; 48extern atomic_t kexec_ready_to_reboot;
48extern void (*_crash_smp_send_stop)(void); 49extern void (*_crash_smp_send_stop)(void);
49#endif 50#endif
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h
index 3644b68c0ccc..be9f727a9328 100644
--- a/arch/mips/include/asm/mach-loongson64/irq.h
+++ b/arch/mips/include/asm/mach-loongson64/irq.h
@@ -10,7 +10,7 @@
10#define MIPS_CPU_IRQ_BASE 56 10#define MIPS_CPU_IRQ_BASE 56
11 11
12#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* UART */ 12#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* UART */
13#define LOONGSON_HT1_IRQ (MIPS_CPU_IRQ_BASE + 3) /* HT1 */ 13#define LOONGSON_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 3) /* CASCADE */
14#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */ 14#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */
15 15
16#define LOONGSON_HT1_CFG_BASE loongson_sysconf.ht_control_base 16#define LOONGSON_HT1_CFG_BASE loongson_sysconf.ht_control_base
diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
index 312739117bb0..cbac603ced19 100644
--- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
@@ -11,6 +11,8 @@
11#ifndef __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H 11#ifndef __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H
12#define __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H 12#define __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H
13 13
14#include <asm/cpu.h>
15
14/* 16/*
15 * Override macros used in arch/mips/kernel/head.S. 17 * Override macros used in arch/mips/kernel/head.S.
16 */ 18 */
@@ -26,12 +28,15 @@
26 mfc0 t0, CP0_PAGEGRAIN 28 mfc0 t0, CP0_PAGEGRAIN
27 or t0, (0x1 << 29) 29 or t0, (0x1 << 29)
28 mtc0 t0, CP0_PAGEGRAIN 30 mtc0 t0, CP0_PAGEGRAIN
29#ifdef CONFIG_LOONGSON3_ENHANCEMENT
30 /* Enable STFill Buffer */ 31 /* Enable STFill Buffer */
32 mfc0 t0, CP0_PRID
33 andi t0, (PRID_IMP_MASK | PRID_REV_MASK)
34 slti t0, (PRID_IMP_LOONGSON_64 | PRID_REV_LOONGSON3A_R2)
35 bnez t0, 1f
31 mfc0 t0, CP0_CONFIG6 36 mfc0 t0, CP0_CONFIG6
32 or t0, 0x100 37 or t0, 0x100
33 mtc0 t0, CP0_CONFIG6 38 mtc0 t0, CP0_CONFIG6
34#endif 391:
35 _ehb 40 _ehb
36 .set pop 41 .set pop
37#endif 42#endif
@@ -52,12 +57,15 @@
52 mfc0 t0, CP0_PAGEGRAIN 57 mfc0 t0, CP0_PAGEGRAIN
53 or t0, (0x1 << 29) 58 or t0, (0x1 << 29)
54 mtc0 t0, CP0_PAGEGRAIN 59 mtc0 t0, CP0_PAGEGRAIN
55#ifdef CONFIG_LOONGSON3_ENHANCEMENT
56 /* Enable STFill Buffer */ 60 /* Enable STFill Buffer */
61 mfc0 t0, CP0_PRID
62 andi t0, (PRID_IMP_MASK | PRID_REV_MASK)
63 slti t0, (PRID_IMP_LOONGSON_64 | PRID_REV_LOONGSON3A_R2)
64 bnez t0, 1f
57 mfc0 t0, CP0_CONFIG6 65 mfc0 t0, CP0_CONFIG6
58 or t0, 0x100 66 or t0, 0x100
59 mtc0 t0, CP0_CONFIG6 67 mtc0 t0, CP0_CONFIG6
60#endif 681:
61 _ehb 69 _ehb
62 .set pop 70 .set pop
63#endif 71#endif
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 01df9ad62fb8..341a02c92985 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -2287,13 +2287,14 @@ do { \
2287 _write_32bit_cp1_register(dest, val, ) 2287 _write_32bit_cp1_register(dest, val, )
2288#endif 2288#endif
2289 2289
2290#ifdef HAVE_AS_DSP 2290#ifdef TOOLCHAIN_SUPPORTS_DSP
2291#define rddsp(mask) \ 2291#define rddsp(mask) \
2292({ \ 2292({ \
2293 unsigned int __dspctl; \ 2293 unsigned int __dspctl; \
2294 \ 2294 \
2295 __asm__ __volatile__( \ 2295 __asm__ __volatile__( \
2296 " .set push \n" \ 2296 " .set push \n" \
2297 " .set " MIPS_ISA_LEVEL " \n" \
2297 " .set dsp \n" \ 2298 " .set dsp \n" \
2298 " rddsp %0, %x1 \n" \ 2299 " rddsp %0, %x1 \n" \
2299 " .set pop \n" \ 2300 " .set pop \n" \
@@ -2306,6 +2307,7 @@ do { \
2306do { \ 2307do { \
2307 __asm__ __volatile__( \ 2308 __asm__ __volatile__( \
2308 " .set push \n" \ 2309 " .set push \n" \
2310 " .set " MIPS_ISA_LEVEL " \n" \
2309 " .set dsp \n" \ 2311 " .set dsp \n" \
2310 " wrdsp %0, %x1 \n" \ 2312 " wrdsp %0, %x1 \n" \
2311 " .set pop \n" \ 2313 " .set pop \n" \
@@ -2318,6 +2320,7 @@ do { \
2318 long mflo0; \ 2320 long mflo0; \
2319 __asm__( \ 2321 __asm__( \
2320 " .set push \n" \ 2322 " .set push \n" \
2323 " .set " MIPS_ISA_LEVEL " \n" \
2321 " .set dsp \n" \ 2324 " .set dsp \n" \
2322 " mflo %0, $ac0 \n" \ 2325 " mflo %0, $ac0 \n" \
2323 " .set pop \n" \ 2326 " .set pop \n" \
@@ -2330,6 +2333,7 @@ do { \
2330 long mflo1; \ 2333 long mflo1; \
2331 __asm__( \ 2334 __asm__( \
2332 " .set push \n" \ 2335 " .set push \n" \
2336 " .set " MIPS_ISA_LEVEL " \n" \
2333 " .set dsp \n" \ 2337 " .set dsp \n" \
2334 " mflo %0, $ac1 \n" \ 2338 " mflo %0, $ac1 \n" \
2335 " .set pop \n" \ 2339 " .set pop \n" \
@@ -2342,6 +2346,7 @@ do { \
2342 long mflo2; \ 2346 long mflo2; \
2343 __asm__( \ 2347 __asm__( \
2344 " .set push \n" \ 2348 " .set push \n" \
2349 " .set " MIPS_ISA_LEVEL " \n" \
2345 " .set dsp \n" \ 2350 " .set dsp \n" \
2346 " mflo %0, $ac2 \n" \ 2351 " mflo %0, $ac2 \n" \
2347 " .set pop \n" \ 2352 " .set pop \n" \
@@ -2354,6 +2359,7 @@ do { \
2354 long mflo3; \ 2359 long mflo3; \
2355 __asm__( \ 2360 __asm__( \
2356 " .set push \n" \ 2361 " .set push \n" \
2362 " .set " MIPS_ISA_LEVEL " \n" \
2357 " .set dsp \n" \ 2363 " .set dsp \n" \
2358 " mflo %0, $ac3 \n" \ 2364 " mflo %0, $ac3 \n" \
2359 " .set pop \n" \ 2365 " .set pop \n" \
@@ -2366,6 +2372,7 @@ do { \
2366 long mfhi0; \ 2372 long mfhi0; \
2367 __asm__( \ 2373 __asm__( \
2368 " .set push \n" \ 2374 " .set push \n" \
2375 " .set " MIPS_ISA_LEVEL " \n" \
2369 " .set dsp \n" \ 2376 " .set dsp \n" \
2370 " mfhi %0, $ac0 \n" \ 2377 " mfhi %0, $ac0 \n" \
2371 " .set pop \n" \ 2378 " .set pop \n" \
@@ -2378,6 +2385,7 @@ do { \
2378 long mfhi1; \ 2385 long mfhi1; \
2379 __asm__( \ 2386 __asm__( \
2380 " .set push \n" \ 2387 " .set push \n" \
2388 " .set " MIPS_ISA_LEVEL " \n" \
2381 " .set dsp \n" \ 2389 " .set dsp \n" \
2382 " mfhi %0, $ac1 \n" \ 2390 " mfhi %0, $ac1 \n" \
2383 " .set pop \n" \ 2391 " .set pop \n" \
@@ -2390,6 +2398,7 @@ do { \
2390 long mfhi2; \ 2398 long mfhi2; \
2391 __asm__( \ 2399 __asm__( \
2392 " .set push \n" \ 2400 " .set push \n" \
2401 " .set " MIPS_ISA_LEVEL " \n" \
2393 " .set dsp \n" \ 2402 " .set dsp \n" \
2394 " mfhi %0, $ac2 \n" \ 2403 " mfhi %0, $ac2 \n" \
2395 " .set pop \n" \ 2404 " .set pop \n" \
@@ -2402,6 +2411,7 @@ do { \
2402 long mfhi3; \ 2411 long mfhi3; \
2403 __asm__( \ 2412 __asm__( \
2404 " .set push \n" \ 2413 " .set push \n" \
2414 " .set " MIPS_ISA_LEVEL " \n" \
2405 " .set dsp \n" \ 2415 " .set dsp \n" \
2406 " mfhi %0, $ac3 \n" \ 2416 " mfhi %0, $ac3 \n" \
2407 " .set pop \n" \ 2417 " .set pop \n" \
@@ -2414,6 +2424,7 @@ do { \
2414({ \ 2424({ \
2415 __asm__( \ 2425 __asm__( \
2416 " .set push \n" \ 2426 " .set push \n" \
2427 " .set " MIPS_ISA_LEVEL " \n" \
2417 " .set dsp \n" \ 2428 " .set dsp \n" \
2418 " mtlo %0, $ac0 \n" \ 2429 " mtlo %0, $ac0 \n" \
2419 " .set pop \n" \ 2430 " .set pop \n" \
@@ -2425,6 +2436,7 @@ do { \
2425({ \ 2436({ \
2426 __asm__( \ 2437 __asm__( \
2427 " .set push \n" \ 2438 " .set push \n" \
2439 " .set " MIPS_ISA_LEVEL " \n" \
2428 " .set dsp \n" \ 2440 " .set dsp \n" \
2429 " mtlo %0, $ac1 \n" \ 2441 " mtlo %0, $ac1 \n" \
2430 " .set pop \n" \ 2442 " .set pop \n" \
@@ -2436,6 +2448,7 @@ do { \
2436({ \ 2448({ \
2437 __asm__( \ 2449 __asm__( \
2438 " .set push \n" \ 2450 " .set push \n" \
2451 " .set " MIPS_ISA_LEVEL " \n" \
2439 " .set dsp \n" \ 2452 " .set dsp \n" \
2440 " mtlo %0, $ac2 \n" \ 2453 " mtlo %0, $ac2 \n" \
2441 " .set pop \n" \ 2454 " .set pop \n" \
@@ -2447,6 +2460,7 @@ do { \
2447({ \ 2460({ \
2448 __asm__( \ 2461 __asm__( \
2449 " .set push \n" \ 2462 " .set push \n" \
2463 " .set " MIPS_ISA_LEVEL " \n" \
2450 " .set dsp \n" \ 2464 " .set dsp \n" \
2451 " mtlo %0, $ac3 \n" \ 2465 " mtlo %0, $ac3 \n" \
2452 " .set pop \n" \ 2466 " .set pop \n" \
@@ -2458,6 +2472,7 @@ do { \
2458({ \ 2472({ \
2459 __asm__( \ 2473 __asm__( \
2460 " .set push \n" \ 2474 " .set push \n" \
2475 " .set " MIPS_ISA_LEVEL " \n" \
2461 " .set dsp \n" \ 2476 " .set dsp \n" \
2462 " mthi %0, $ac0 \n" \ 2477 " mthi %0, $ac0 \n" \
2463 " .set pop \n" \ 2478 " .set pop \n" \
@@ -2469,6 +2484,7 @@ do { \
2469({ \ 2484({ \
2470 __asm__( \ 2485 __asm__( \
2471 " .set push \n" \ 2486 " .set push \n" \
2487 " .set " MIPS_ISA_LEVEL " \n" \
2472 " .set dsp \n" \ 2488 " .set dsp \n" \
2473 " mthi %0, $ac1 \n" \ 2489 " mthi %0, $ac1 \n" \
2474 " .set pop \n" \ 2490 " .set pop \n" \
@@ -2480,6 +2496,7 @@ do { \
2480({ \ 2496({ \
2481 __asm__( \ 2497 __asm__( \
2482 " .set push \n" \ 2498 " .set push \n" \
2499 " .set " MIPS_ISA_LEVEL " \n" \
2483 " .set dsp \n" \ 2500 " .set dsp \n" \
2484 " mthi %0, $ac2 \n" \ 2501 " mthi %0, $ac2 \n" \
2485 " .set pop \n" \ 2502 " .set pop \n" \
@@ -2491,6 +2508,7 @@ do { \
2491({ \ 2508({ \
2492 __asm__( \ 2509 __asm__( \
2493 " .set push \n" \ 2510 " .set push \n" \
2511 " .set " MIPS_ISA_LEVEL " \n" \
2494 " .set dsp \n" \ 2512 " .set dsp \n" \
2495 " mthi %0, $ac3 \n" \ 2513 " mthi %0, $ac3 \n" \
2496 " .set pop \n" \ 2514 " .set pop \n" \
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 7f12d7e27c94..d19b2d65336b 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -48,58 +48,14 @@ extern void (*r4k_blast_icache)(void);
48 : \ 48 : \
49 : "i" (op), "R" (*(unsigned char *)(addr))) 49 : "i" (op), "R" (*(unsigned char *)(addr)))
50 50
51#ifdef CONFIG_MIPS_MT
52
53#define __iflush_prologue \
54 unsigned long redundance; \
55 extern int mt_n_iflushes; \
56 for (redundance = 0; redundance < mt_n_iflushes; redundance++) {
57
58#define __iflush_epilogue \
59 }
60
61#define __dflush_prologue \
62 unsigned long redundance; \
63 extern int mt_n_dflushes; \
64 for (redundance = 0; redundance < mt_n_dflushes; redundance++) {
65
66#define __dflush_epilogue \
67 }
68
69#define __inv_dflush_prologue __dflush_prologue
70#define __inv_dflush_epilogue __dflush_epilogue
71#define __sflush_prologue {
72#define __sflush_epilogue }
73#define __inv_sflush_prologue __sflush_prologue
74#define __inv_sflush_epilogue __sflush_epilogue
75
76#else /* CONFIG_MIPS_MT */
77
78#define __iflush_prologue {
79#define __iflush_epilogue }
80#define __dflush_prologue {
81#define __dflush_epilogue }
82#define __inv_dflush_prologue {
83#define __inv_dflush_epilogue }
84#define __sflush_prologue {
85#define __sflush_epilogue }
86#define __inv_sflush_prologue {
87#define __inv_sflush_epilogue }
88
89#endif /* CONFIG_MIPS_MT */
90
91static inline void flush_icache_line_indexed(unsigned long addr) 51static inline void flush_icache_line_indexed(unsigned long addr)
92{ 52{
93 __iflush_prologue
94 cache_op(Index_Invalidate_I, addr); 53 cache_op(Index_Invalidate_I, addr);
95 __iflush_epilogue
96} 54}
97 55
98static inline void flush_dcache_line_indexed(unsigned long addr) 56static inline void flush_dcache_line_indexed(unsigned long addr)
99{ 57{
100 __dflush_prologue
101 cache_op(Index_Writeback_Inv_D, addr); 58 cache_op(Index_Writeback_Inv_D, addr);
102 __dflush_epilogue
103} 59}
104 60
105static inline void flush_scache_line_indexed(unsigned long addr) 61static inline void flush_scache_line_indexed(unsigned long addr)
@@ -109,7 +65,6 @@ static inline void flush_scache_line_indexed(unsigned long addr)
109 65
110static inline void flush_icache_line(unsigned long addr) 66static inline void flush_icache_line(unsigned long addr)
111{ 67{
112 __iflush_prologue
113 switch (boot_cpu_type()) { 68 switch (boot_cpu_type()) {
114 case CPU_LOONGSON2: 69 case CPU_LOONGSON2:
115 cache_op(Hit_Invalidate_I_Loongson2, addr); 70 cache_op(Hit_Invalidate_I_Loongson2, addr);
@@ -119,21 +74,16 @@ static inline void flush_icache_line(unsigned long addr)
119 cache_op(Hit_Invalidate_I, addr); 74 cache_op(Hit_Invalidate_I, addr);
120 break; 75 break;
121 } 76 }
122 __iflush_epilogue
123} 77}
124 78
125static inline void flush_dcache_line(unsigned long addr) 79static inline void flush_dcache_line(unsigned long addr)
126{ 80{
127 __dflush_prologue
128 cache_op(Hit_Writeback_Inv_D, addr); 81 cache_op(Hit_Writeback_Inv_D, addr);
129 __dflush_epilogue
130} 82}
131 83
132static inline void invalidate_dcache_line(unsigned long addr) 84static inline void invalidate_dcache_line(unsigned long addr)
133{ 85{
134 __dflush_prologue
135 cache_op(Hit_Invalidate_D, addr); 86 cache_op(Hit_Invalidate_D, addr);
136 __dflush_epilogue
137} 87}
138 88
139static inline void invalidate_scache_line(unsigned long addr) 89static inline void invalidate_scache_line(unsigned long addr)
@@ -586,13 +536,9 @@ static inline void extra##blast_##pfx##cache##lsize(void) \
586 current_cpu_data.desc.waybit; \ 536 current_cpu_data.desc.waybit; \
587 unsigned long ws, addr; \ 537 unsigned long ws, addr; \
588 \ 538 \
589 __##pfx##flush_prologue \
590 \
591 for (ws = 0; ws < ws_end; ws += ws_inc) \ 539 for (ws = 0; ws < ws_end; ws += ws_inc) \
592 for (addr = start; addr < end; addr += lsize * 32) \ 540 for (addr = start; addr < end; addr += lsize * 32) \
593 cache##lsize##_unroll32(addr|ws, indexop); \ 541 cache##lsize##_unroll32(addr|ws, indexop); \
594 \
595 __##pfx##flush_epilogue \
596} \ 542} \
597 \ 543 \
598static inline void extra##blast_##pfx##cache##lsize##_page(unsigned long page) \ 544static inline void extra##blast_##pfx##cache##lsize##_page(unsigned long page) \
@@ -600,14 +546,10 @@ static inline void extra##blast_##pfx##cache##lsize##_page(unsigned long page) \
600 unsigned long start = page; \ 546 unsigned long start = page; \
601 unsigned long end = page + PAGE_SIZE; \ 547 unsigned long end = page + PAGE_SIZE; \
602 \ 548 \
603 __##pfx##flush_prologue \
604 \
605 do { \ 549 do { \
606 cache##lsize##_unroll32(start, hitop); \ 550 cache##lsize##_unroll32(start, hitop); \
607 start += lsize * 32; \ 551 start += lsize * 32; \
608 } while (start < end); \ 552 } while (start < end); \
609 \
610 __##pfx##flush_epilogue \
611} \ 553} \
612 \ 554 \
613static inline void extra##blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \ 555static inline void extra##blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
@@ -620,13 +562,9 @@ static inline void extra##blast_##pfx##cache##lsize##_page_indexed(unsigned long
620 current_cpu_data.desc.waybit; \ 562 current_cpu_data.desc.waybit; \
621 unsigned long ws, addr; \ 563 unsigned long ws, addr; \
622 \ 564 \
623 __##pfx##flush_prologue \
624 \
625 for (ws = 0; ws < ws_end; ws += ws_inc) \ 565 for (ws = 0; ws < ws_end; ws += ws_inc) \
626 for (addr = start; addr < end; addr += lsize * 32) \ 566 for (addr = start; addr < end; addr += lsize * 32) \
627 cache##lsize##_unroll32(addr|ws, indexop); \ 567 cache##lsize##_unroll32(addr|ws, indexop); \
628 \
629 __##pfx##flush_epilogue \
630} 568}
631 569
632__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, ) 570__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
@@ -656,14 +594,10 @@ static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
656 unsigned long start = page; \ 594 unsigned long start = page; \
657 unsigned long end = page + PAGE_SIZE; \ 595 unsigned long end = page + PAGE_SIZE; \
658 \ 596 \
659 __##pfx##flush_prologue \
660 \
661 do { \ 597 do { \
662 cache##lsize##_unroll32_user(start, hitop); \ 598 cache##lsize##_unroll32_user(start, hitop); \
663 start += lsize * 32; \ 599 start += lsize * 32; \
664 } while (start < end); \ 600 } while (start < end); \
665 \
666 __##pfx##flush_epilogue \
667} 601}
668 602
669__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 603__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
@@ -685,16 +619,12 @@ static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start,
685 unsigned long addr = start & ~(lsize - 1); \ 619 unsigned long addr = start & ~(lsize - 1); \
686 unsigned long aend = (end - 1) & ~(lsize - 1); \ 620 unsigned long aend = (end - 1) & ~(lsize - 1); \
687 \ 621 \
688 __##pfx##flush_prologue \
689 \
690 while (1) { \ 622 while (1) { \
691 prot##cache_op(hitop, addr); \ 623 prot##cache_op(hitop, addr); \
692 if (addr == aend) \ 624 if (addr == aend) \
693 break; \ 625 break; \
694 addr += lsize; \ 626 addr += lsize; \
695 } \ 627 } \
696 \
697 __##pfx##flush_epilogue \
698} 628}
699 629
700#ifndef CONFIG_EVA 630#ifndef CONFIG_EVA
@@ -712,8 +642,6 @@ static inline void protected_blast_##pfx##cache##_range(unsigned long start,\
712 unsigned long addr = start & ~(lsize - 1); \ 642 unsigned long addr = start & ~(lsize - 1); \
713 unsigned long aend = (end - 1) & ~(lsize - 1); \ 643 unsigned long aend = (end - 1) & ~(lsize - 1); \
714 \ 644 \
715 __##pfx##flush_prologue \
716 \
717 if (!uaccess_kernel()) { \ 645 if (!uaccess_kernel()) { \
718 while (1) { \ 646 while (1) { \
719 protected_cachee_op(hitop, addr); \ 647 protected_cachee_op(hitop, addr); \
@@ -730,7 +658,6 @@ static inline void protected_blast_##pfx##cache##_range(unsigned long start,\
730 } \ 658 } \
731 \ 659 \
732 } \ 660 } \
733 __##pfx##flush_epilogue \
734} 661}
735 662
736__BUILD_PROT_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D) 663__BUILD_PROT_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D)
diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h
index 53b2cb8e5966..b7123f9c0785 100644
--- a/arch/mips/include/asm/smp-ops.h
+++ b/arch/mips/include/asm/smp-ops.h
@@ -33,6 +33,9 @@ struct plat_smp_ops {
33 int (*cpu_disable)(void); 33 int (*cpu_disable)(void);
34 void (*cpu_die)(unsigned int cpu); 34 void (*cpu_die)(unsigned int cpu);
35#endif 35#endif
36#ifdef CONFIG_KEXEC
37 void (*kexec_nonboot_cpu)(void);
38#endif
36}; 39};
37 40
38extern void register_smp_ops(const struct plat_smp_ops *ops); 41extern void register_smp_ops(const struct plat_smp_ops *ops);
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index 056a6bf13491..7990c1c70471 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -91,6 +91,22 @@ static inline void __cpu_die(unsigned int cpu)
91extern void play_dead(void); 91extern void play_dead(void);
92#endif 92#endif
93 93
94#ifdef CONFIG_KEXEC
95static inline void kexec_nonboot_cpu(void)
96{
97 extern const struct plat_smp_ops *mp_ops; /* private */
98
99 return mp_ops->kexec_nonboot_cpu();
100}
101
102static inline void *kexec_nonboot_cpu_func(void)
103{
104 extern const struct plat_smp_ops *mp_ops; /* private */
105
106 return mp_ops->kexec_nonboot_cpu;
107}
108#endif
109
94/* 110/*
95 * This function will set up the necessary IPIs for Linux to communicate 111 * This function will set up the necessary IPIs for Linux to communicate
96 * with the CPUs in mask. 112 * with the CPUs in mask.
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index f10e1e15e1c6..210c2802cf4d 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -113,22 +113,4 @@ obj-$(CONFIG_MIPS_CPC) += mips-cpc.o
113obj-$(CONFIG_CPU_PM) += pm.o 113obj-$(CONFIG_CPU_PM) += pm.o
114obj-$(CONFIG_MIPS_CPS_PM) += pm-cps.o 114obj-$(CONFIG_MIPS_CPS_PM) += pm-cps.o
115 115
116#
117# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is not
118# safe to unconditionnaly use the assembler -mdsp / -mdspr2 switches
119# here because the compiler may use DSP ASE instructions (such as lwx) in
120# code paths where we cannot check that the CPU we are running on supports it.
121# Proper abstraction using HAVE_AS_DSP and macros is done in
122# arch/mips/include/asm/mipsregs.h.
123#
124ifeq ($(CONFIG_CPU_MIPSR2), y)
125CFLAGS_DSP = -DHAVE_AS_DSP
126
127CFLAGS_signal.o = $(CFLAGS_DSP)
128CFLAGS_signal32.o = $(CFLAGS_DSP)
129CFLAGS_process.o = $(CFLAGS_DSP)
130CFLAGS_branch.o = $(CFLAGS_DSP)
131CFLAGS_ptrace.o = $(CFLAGS_DSP)
132endif
133
134CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS) 116CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS)
diff --git a/arch/mips/kernel/crash.c b/arch/mips/kernel/crash.c
index d455363d51c3..2c7288041a99 100644
--- a/arch/mips/kernel/crash.c
+++ b/arch/mips/kernel/crash.c
@@ -36,6 +36,9 @@ static void crash_shutdown_secondary(void *passed_regs)
36 if (!cpu_online(cpu)) 36 if (!cpu_online(cpu))
37 return; 37 return;
38 38
39 /* We won't be sent IPIs any more. */
40 set_cpu_online(cpu, false);
41
39 local_irq_disable(); 42 local_irq_disable();
40 if (!cpumask_test_cpu(cpu, &cpus_in_crash)) 43 if (!cpumask_test_cpu(cpu, &cpus_in_crash))
41 crash_save_cpu(regs, cpu); 44 crash_save_cpu(regs, cpu);
@@ -43,7 +46,9 @@ static void crash_shutdown_secondary(void *passed_regs)
43 46
44 while (!atomic_read(&kexec_ready_to_reboot)) 47 while (!atomic_read(&kexec_ready_to_reboot))
45 cpu_relax(); 48 cpu_relax();
46 relocated_kexec_smp_wait(NULL); 49
50 kexec_reboot();
51
47 /* NOTREACHED */ 52 /* NOTREACHED */
48} 53}
49 54
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index d1bb506adc10..351d40fe0859 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -77,7 +77,7 @@ EXPORT(_stext)
77 */ 77 */
78FEXPORT(__kernel_entry) 78FEXPORT(__kernel_entry)
79 j kernel_entry 79 j kernel_entry
80#endif 80#endif /* CONFIG_BOOT_RAW */
81 81
82 __REF 82 __REF
83 83
@@ -94,24 +94,26 @@ NESTED(kernel_entry, 16, sp) # kernel entry point
940: 940:
95 95
96#ifdef CONFIG_USE_OF 96#ifdef CONFIG_USE_OF
97#ifdef CONFIG_MIPS_RAW_APPENDED_DTB 97#if defined(CONFIG_MIPS_RAW_APPENDED_DTB) || \
98 defined(CONFIG_MIPS_ELF_APPENDED_DTB)
99
98 PTR_LA t2, __appended_dtb 100 PTR_LA t2, __appended_dtb
99 101
100#ifdef CONFIG_CPU_BIG_ENDIAN 102#ifdef CONFIG_CPU_BIG_ENDIAN
101 li t1, 0xd00dfeed 103 li t1, 0xd00dfeed
102#else 104#else /* !CONFIG_CPU_BIG_ENDIAN */
103 li t1, 0xedfe0dd0 105 li t1, 0xedfe0dd0
104#endif 106#endif /* !CONFIG_CPU_BIG_ENDIAN */
105 lw t0, (t2) 107 lw t0, (t2)
106 beq t0, t1, dtb_found 108 beq t0, t1, dtb_found
107#endif 109#endif /* CONFIG_MIPS_RAW_APPENDED_DTB || CONFIG_MIPS_ELF_APPENDED_DTB */
108 li t1, -2 110 li t1, -2
109 move t2, a1 111 move t2, a1
110 beq a0, t1, dtb_found 112 beq a0, t1, dtb_found
111 113
112 li t2, 0 114 li t2, 0
113dtb_found: 115dtb_found:
114#endif 116#endif /* CONFIG_USE_OF */
115 PTR_LA t0, __bss_start # clear .bss 117 PTR_LA t0, __bss_start # clear .bss
116 LONG_S zero, (t0) 118 LONG_S zero, (t0)
117 PTR_LA t1, __bss_stop - LONGSIZE 119 PTR_LA t1, __bss_stop - LONGSIZE
@@ -156,9 +158,9 @@ dtb_found:
156 * newly sync'd icache. 158 * newly sync'd icache.
157 */ 159 */
158 jr.hb v0 160 jr.hb v0
159#else 161#else /* !CONFIG_RELOCATABLE */
160 j start_kernel 162 j start_kernel
161#endif 163#endif /* !CONFIG_RELOCATABLE */
162 END(kernel_entry) 164 END(kernel_entry)
163 165
164#ifdef CONFIG_SMP 166#ifdef CONFIG_SMP
diff --git a/arch/mips/kernel/machine_kexec.c b/arch/mips/kernel/machine_kexec.c
index 8b574bcd39ba..93936dce04d6 100644
--- a/arch/mips/kernel/machine_kexec.c
+++ b/arch/mips/kernel/machine_kexec.c
@@ -9,6 +9,7 @@
9#include <linux/kexec.h> 9#include <linux/kexec.h>
10#include <linux/mm.h> 10#include <linux/mm.h>
11#include <linux/delay.h> 11#include <linux/delay.h>
12#include <linux/libfdt.h>
12 13
13#include <asm/cacheflush.h> 14#include <asm/cacheflush.h>
14#include <asm/page.h> 15#include <asm/page.h>
@@ -19,15 +20,18 @@ extern const size_t relocate_new_kernel_size;
19extern unsigned long kexec_start_address; 20extern unsigned long kexec_start_address;
20extern unsigned long kexec_indirection_page; 21extern unsigned long kexec_indirection_page;
21 22
22int (*_machine_kexec_prepare)(struct kimage *) = NULL; 23static unsigned long reboot_code_buffer;
23void (*_machine_kexec_shutdown)(void) = NULL; 24
24void (*_machine_crash_shutdown)(struct pt_regs *regs) = NULL;
25#ifdef CONFIG_SMP 25#ifdef CONFIG_SMP
26void (*relocated_kexec_smp_wait) (void *); 26static void (*relocated_kexec_smp_wait)(void *);
27
27atomic_t kexec_ready_to_reboot = ATOMIC_INIT(0); 28atomic_t kexec_ready_to_reboot = ATOMIC_INIT(0);
28void (*_crash_smp_send_stop)(void) = NULL; 29void (*_crash_smp_send_stop)(void) = NULL;
29#endif 30#endif
30 31
32void (*_machine_kexec_shutdown)(void) = NULL;
33void (*_machine_crash_shutdown)(struct pt_regs *regs) = NULL;
34
31static void kexec_image_info(const struct kimage *kimage) 35static void kexec_image_info(const struct kimage *kimage)
32{ 36{
33 unsigned long i; 37 unsigned long i;
@@ -48,13 +52,59 @@ static void kexec_image_info(const struct kimage *kimage)
48 } 52 }
49} 53}
50 54
55#ifdef CONFIG_UHI_BOOT
56
57static int uhi_machine_kexec_prepare(struct kimage *kimage)
58{
59 int i;
60
61 /*
62 * In case DTB file is not passed to the new kernel, a flat device
63 * tree will be created by kexec tool. It holds modified command
64 * line for the new kernel.
65 */
66 for (i = 0; i < kimage->nr_segments; i++) {
67 struct fdt_header fdt;
68
69 if (kimage->segment[i].memsz <= sizeof(fdt))
70 continue;
71
72 if (copy_from_user(&fdt, kimage->segment[i].buf, sizeof(fdt)))
73 continue;
74
75 if (fdt_check_header(&fdt))
76 continue;
77
78 kexec_args[0] = -2;
79 kexec_args[1] = (unsigned long)
80 phys_to_virt((unsigned long)kimage->segment[i].mem);
81 break;
82 }
83
84 return 0;
85}
86
87int (*_machine_kexec_prepare)(struct kimage *) = uhi_machine_kexec_prepare;
88
89#else
90
91int (*_machine_kexec_prepare)(struct kimage *) = NULL;
92
93#endif /* CONFIG_UHI_BOOT */
94
51int 95int
52machine_kexec_prepare(struct kimage *kimage) 96machine_kexec_prepare(struct kimage *kimage)
53{ 97{
98#ifdef CONFIG_SMP
99 if (!kexec_nonboot_cpu_func())
100 return -EINVAL;
101#endif
102
54 kexec_image_info(kimage); 103 kexec_image_info(kimage);
55 104
56 if (_machine_kexec_prepare) 105 if (_machine_kexec_prepare)
57 return _machine_kexec_prepare(kimage); 106 return _machine_kexec_prepare(kimage);
107
58 return 0; 108 return 0;
59} 109}
60 110
@@ -63,11 +113,41 @@ machine_kexec_cleanup(struct kimage *kimage)
63{ 113{
64} 114}
65 115
116#ifdef CONFIG_SMP
117static void kexec_shutdown_secondary(void *param)
118{
119 int cpu = smp_processor_id();
120
121 if (!cpu_online(cpu))
122 return;
123
124 /* We won't be sent IPIs any more. */
125 set_cpu_online(cpu, false);
126
127 local_irq_disable();
128 while (!atomic_read(&kexec_ready_to_reboot))
129 cpu_relax();
130
131 kexec_reboot();
132
133 /* NOTREACHED */
134}
135#endif
136
66void 137void
67machine_shutdown(void) 138machine_shutdown(void)
68{ 139{
69 if (_machine_kexec_shutdown) 140 if (_machine_kexec_shutdown)
70 _machine_kexec_shutdown(); 141 _machine_kexec_shutdown();
142
143#ifdef CONFIG_SMP
144 smp_call_function(kexec_shutdown_secondary, NULL, 0);
145
146 while (num_online_cpus() > 1) {
147 cpu_relax();
148 mdelay(1);
149 }
150#endif
71} 151}
72 152
73void 153void
@@ -79,12 +159,57 @@ machine_crash_shutdown(struct pt_regs *regs)
79 default_machine_crash_shutdown(regs); 159 default_machine_crash_shutdown(regs);
80} 160}
81 161
82typedef void (*noretfun_t)(void) __noreturn; 162#ifdef CONFIG_SMP
163void kexec_nonboot_cpu_jump(void)
164{
165 local_flush_icache_range((unsigned long)relocated_kexec_smp_wait,
166 reboot_code_buffer + relocate_new_kernel_size);
167
168 relocated_kexec_smp_wait(NULL);
169}
170#endif
171
172void kexec_reboot(void)
173{
174 void (*do_kexec)(void) __noreturn;
175
176 /*
177 * We know we were online, and there will be no incoming IPIs at
178 * this point. Mark online again before rebooting so that the crash
179 * analysis tool will see us correctly.
180 */
181 set_cpu_online(smp_processor_id(), true);
182
183 /* Ensure remote CPUs observe that we're online before rebooting. */
184 smp_mb__after_atomic();
185
186#ifdef CONFIG_SMP
187 if (smp_processor_id() > 0) {
188 /*
189 * Instead of cpu_relax() or wait, this is needed for kexec
190 * smp reboot. Kdump usually doesn't require an smp new
191 * kernel, but kexec may do.
192 */
193 kexec_nonboot_cpu();
194
195 /* NOTREACHED */
196 }
197#endif
198
199 /*
200 * Make sure we get correct instructions written by the
201 * machine_kexec() CPU.
202 */
203 local_flush_icache_range(reboot_code_buffer,
204 reboot_code_buffer + relocate_new_kernel_size);
205
206 do_kexec = (void *)reboot_code_buffer;
207 do_kexec();
208}
83 209
84void 210void
85machine_kexec(struct kimage *image) 211machine_kexec(struct kimage *image)
86{ 212{
87 unsigned long reboot_code_buffer;
88 unsigned long entry; 213 unsigned long entry;
89 unsigned long *ptr; 214 unsigned long *ptr;
90 215
@@ -118,6 +243,9 @@ machine_kexec(struct kimage *image)
118 *ptr = (unsigned long) phys_to_virt(*ptr); 243 *ptr = (unsigned long) phys_to_virt(*ptr);
119 } 244 }
120 245
246 /* Mark offline BEFORE disabling local irq. */
247 set_cpu_online(smp_processor_id(), false);
248
121 /* 249 /*
122 * we do not want to be bothered. 250 * we do not want to be bothered.
123 */ 251 */
@@ -125,6 +253,7 @@ machine_kexec(struct kimage *image)
125 253
126 printk("Will call new kernel at %08lx\n", image->start); 254 printk("Will call new kernel at %08lx\n", image->start);
127 printk("Bye ...\n"); 255 printk("Bye ...\n");
256 /* Make reboot code buffer available to the boot CPU. */
128 __flush_cache_all(); 257 __flush_cache_all();
129#ifdef CONFIG_SMP 258#ifdef CONFIG_SMP
130 /* All secondary cpus now may jump to kexec_wait cycle */ 259 /* All secondary cpus now may jump to kexec_wait cycle */
@@ -133,5 +262,5 @@ machine_kexec(struct kimage *image)
133 smp_wmb(); 262 smp_wmb();
134 atomic_set(&kexec_ready_to_reboot, 1); 263 atomic_set(&kexec_ready_to_reboot, 1);
135#endif 264#endif
136 ((noretfun_t) reboot_code_buffer)(); 265 kexec_reboot();
137} 266}
diff --git a/arch/mips/kernel/mips-mt.c b/arch/mips/kernel/mips-mt.c
index efaa2527657d..9f85b98d24ac 100644
--- a/arch/mips/kernel/mips-mt.c
+++ b/arch/mips/kernel/mips-mt.c
@@ -154,40 +154,6 @@ static int __init config7_set(char *str)
154} 154}
155__setup("config7=", config7_set); 155__setup("config7=", config7_set);
156 156
157/* Experimental cache flush control parameters that should go away some day */
158int mt_protiflush;
159int mt_protdflush;
160int mt_n_iflushes = 1;
161int mt_n_dflushes = 1;
162
163static int __init set_protiflush(char *s)
164{
165 mt_protiflush = 1;
166 return 1;
167}
168__setup("protiflush", set_protiflush);
169
170static int __init set_protdflush(char *s)
171{
172 mt_protdflush = 1;
173 return 1;
174}
175__setup("protdflush", set_protdflush);
176
177static int __init niflush(char *s)
178{
179 get_option(&s, &mt_n_iflushes);
180 return 1;
181}
182__setup("niflush=", niflush);
183
184static int __init ndflush(char *s)
185{
186 get_option(&s, &mt_n_dflushes);
187 return 1;
188}
189__setup("ndflush=", ndflush);
190
191static unsigned int itc_base; 157static unsigned int itc_base;
192 158
193static int __init set_itc_base(char *str) 159static int __init set_itc_base(char *str)
@@ -232,16 +198,6 @@ void mips_mt_set_cpuoptions(void)
232 printk("Config7: 0x%08x\n", read_c0_config7()); 198 printk("Config7: 0x%08x\n", read_c0_config7());
233 } 199 }
234 200
235 /* Report Cache management debug options */
236 if (mt_protiflush)
237 printk("I-cache flushes single-threaded\n");
238 if (mt_protdflush)
239 printk("D-cache flushes single-threaded\n");
240 if (mt_n_iflushes != 1)
241 printk("I-Cache Flushes Repeated %d times\n", mt_n_iflushes);
242 if (mt_n_dflushes != 1)
243 printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes);
244
245 if (itc_base != 0) { 201 if (itc_base != 0) {
246 /* 202 /*
247 * Configure ITC mapping. This code is very 203 * Configure ITC mapping. This code is very
@@ -283,21 +239,6 @@ void mips_mt_set_cpuoptions(void)
283 } 239 }
284} 240}
285 241
286/*
287 * Function to protect cache flushes from concurrent execution
288 * depends on MP software model chosen.
289 */
290
291void mt_cflush_lockdown(void)
292{
293 /* FILL IN VSMP and AP/SP VERSIONS HERE */
294}
295
296void mt_cflush_release(void)
297{
298 /* FILL IN VSMP and AP/SP VERSIONS HERE */
299}
300
301struct class *mt_class; 242struct class *mt_class;
302 243
303static int __init mt_init(void) 244static int __init mt_init(void)
diff --git a/arch/mips/kernel/relocate.c b/arch/mips/kernel/relocate.c
index cbf4cc0b0b6c..3d80a51256de 100644
--- a/arch/mips/kernel/relocate.c
+++ b/arch/mips/kernel/relocate.c
@@ -146,7 +146,7 @@ int __init do_relocations(void *kbase_old, void *kbase_new, long offset)
146 break; 146 break;
147 147
148 type = (*r >> 24) & 0xff; 148 type = (*r >> 24) & 0xff;
149 loc_orig = (void *)(kbase_old + ((*r & 0x00ffffff) << 2)); 149 loc_orig = kbase_old + ((*r & 0x00ffffff) << 2);
150 loc_new = RELOCATED(loc_orig); 150 loc_new = RELOCATED(loc_orig);
151 151
152 if (reloc_handlers_rel[type] == NULL) { 152 if (reloc_handlers_rel[type] == NULL) {
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index e64b9e8bb002..01a5ff4c41ff 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -333,7 +333,7 @@ static void __init finalize_initrd(void)
333 333
334 maybe_bswap_initrd(); 334 maybe_bswap_initrd();
335 335
336 reserve_bootmem(__pa(initrd_start), size, BOOTMEM_DEFAULT); 336 memblock_reserve(__pa(initrd_start), size);
337 initrd_below_start_ok = 1; 337 initrd_below_start_ok = 1;
338 338
339 pr_info("Initial ramdisk at: 0x%lx (%lu bytes)\n", 339 pr_info("Initial ramdisk at: 0x%lx (%lu bytes)\n",
@@ -370,20 +370,10 @@ static void __init bootmem_init(void)
370 370
371#else /* !CONFIG_SGI_IP27 */ 371#else /* !CONFIG_SGI_IP27 */
372 372
373static unsigned long __init bootmap_bytes(unsigned long pages)
374{
375 unsigned long bytes = DIV_ROUND_UP(pages, 8);
376
377 return ALIGN(bytes, sizeof(long));
378}
379
380static void __init bootmem_init(void) 373static void __init bootmem_init(void)
381{ 374{
382 unsigned long reserved_end; 375 unsigned long reserved_end;
383 unsigned long mapstart = ~0UL;
384 unsigned long bootmap_size;
385 phys_addr_t ramstart = PHYS_ADDR_MAX; 376 phys_addr_t ramstart = PHYS_ADDR_MAX;
386 bool bootmap_valid = false;
387 int i; 377 int i;
388 378
389 /* 379 /*
@@ -395,6 +385,8 @@ static void __init bootmem_init(void)
395 init_initrd(); 385 init_initrd();
396 reserved_end = (unsigned long) PFN_UP(__pa_symbol(&_end)); 386 reserved_end = (unsigned long) PFN_UP(__pa_symbol(&_end));
397 387
388 memblock_reserve(PHYS_OFFSET, reserved_end << PAGE_SHIFT);
389
398 /* 390 /*
399 * max_low_pfn is not a number of pages. The number of pages 391 * max_low_pfn is not a number of pages. The number of pages
400 * of the system is given by 'max_low_pfn - min_low_pfn'. 392 * of the system is given by 'max_low_pfn - min_low_pfn'.
@@ -442,9 +434,6 @@ static void __init bootmem_init(void)
442 if (initrd_end && end <= (unsigned long)PFN_UP(__pa(initrd_end))) 434 if (initrd_end && end <= (unsigned long)PFN_UP(__pa(initrd_end)))
443 continue; 435 continue;
444#endif 436#endif
445 if (start >= mapstart)
446 continue;
447 mapstart = max(reserved_end, start);
448 } 437 }
449 438
450 if (min_low_pfn >= max_low_pfn) 439 if (min_low_pfn >= max_low_pfn)
@@ -456,9 +445,11 @@ static void __init bootmem_init(void)
456 /* 445 /*
457 * Reserve any memory between the start of RAM and PHYS_OFFSET 446 * Reserve any memory between the start of RAM and PHYS_OFFSET
458 */ 447 */
459 if (ramstart > PHYS_OFFSET) 448 if (ramstart > PHYS_OFFSET) {
460 add_memory_region(PHYS_OFFSET, ramstart - PHYS_OFFSET, 449 add_memory_region(PHYS_OFFSET, ramstart - PHYS_OFFSET,
461 BOOT_MEM_RESERVED); 450 BOOT_MEM_RESERVED);
451 memblock_reserve(PHYS_OFFSET, ramstart - PHYS_OFFSET);
452 }
462 453
463 if (min_low_pfn > ARCH_PFN_OFFSET) { 454 if (min_low_pfn > ARCH_PFN_OFFSET) {
464 pr_info("Wasting %lu bytes for tracking %lu unused pages\n", 455 pr_info("Wasting %lu bytes for tracking %lu unused pages\n",
@@ -483,52 +474,6 @@ static void __init bootmem_init(void)
483 max_low_pfn = PFN_DOWN(HIGHMEM_START); 474 max_low_pfn = PFN_DOWN(HIGHMEM_START);
484 } 475 }
485 476
486#ifdef CONFIG_BLK_DEV_INITRD
487 /*
488 * mapstart should be after initrd_end
489 */
490 if (initrd_end)
491 mapstart = max(mapstart, (unsigned long)PFN_UP(__pa(initrd_end)));
492#endif
493
494 /*
495 * check that mapstart doesn't overlap with any of
496 * memory regions that have been reserved through eg. DTB
497 */
498 bootmap_size = bootmap_bytes(max_low_pfn - min_low_pfn);
499
500 bootmap_valid = memory_region_available(PFN_PHYS(mapstart),
501 bootmap_size);
502 for (i = 0; i < boot_mem_map.nr_map && !bootmap_valid; i++) {
503 unsigned long mapstart_addr;
504
505 switch (boot_mem_map.map[i].type) {
506 case BOOT_MEM_RESERVED:
507 mapstart_addr = PFN_ALIGN(boot_mem_map.map[i].addr +
508 boot_mem_map.map[i].size);
509 if (PHYS_PFN(mapstart_addr) < mapstart)
510 break;
511
512 bootmap_valid = memory_region_available(mapstart_addr,
513 bootmap_size);
514 if (bootmap_valid)
515 mapstart = PHYS_PFN(mapstart_addr);
516 break;
517 default:
518 break;
519 }
520 }
521
522 if (!bootmap_valid)
523 panic("No memory area to place a bootmap bitmap");
524
525 /*
526 * Initialize the boot-time allocator with low memory only.
527 */
528 if (bootmap_size != init_bootmem_node(NODE_DATA(0), mapstart,
529 min_low_pfn, max_low_pfn))
530 panic("Unexpected memory size required for bootmap");
531
532 for (i = 0; i < boot_mem_map.nr_map; i++) { 477 for (i = 0; i < boot_mem_map.nr_map; i++) {
533 unsigned long start, end; 478 unsigned long start, end;
534 479
@@ -577,9 +522,9 @@ static void __init bootmem_init(void)
577 default: 522 default:
578 /* Not usable memory */ 523 /* Not usable memory */
579 if (start > min_low_pfn && end < max_low_pfn) 524 if (start > min_low_pfn && end < max_low_pfn)
580 reserve_bootmem(boot_mem_map.map[i].addr, 525 memblock_reserve(boot_mem_map.map[i].addr,
581 boot_mem_map.map[i].size, 526 boot_mem_map.map[i].size);
582 BOOTMEM_DEFAULT); 527
583 continue; 528 continue;
584 } 529 }
585 530
@@ -602,15 +547,9 @@ static void __init bootmem_init(void)
602 size = end - start; 547 size = end - start;
603 548
604 /* Register lowmem ranges */ 549 /* Register lowmem ranges */
605 free_bootmem(PFN_PHYS(start), size << PAGE_SHIFT);
606 memory_present(0, start, end); 550 memory_present(0, start, end);
607 } 551 }
608 552
609 /*
610 * Reserve the bootmap memory.
611 */
612 reserve_bootmem(PFN_PHYS(mapstart), bootmap_size, BOOTMEM_DEFAULT);
613
614#ifdef CONFIG_RELOCATABLE 553#ifdef CONFIG_RELOCATABLE
615 /* 554 /*
616 * The kernel reserves all memory below its _end symbol as bootmem, 555 * The kernel reserves all memory below its _end symbol as bootmem,
@@ -642,29 +581,6 @@ static void __init bootmem_init(void)
642 581
643#endif /* CONFIG_SGI_IP27 */ 582#endif /* CONFIG_SGI_IP27 */
644 583
645/*
646 * arch_mem_init - initialize memory management subsystem
647 *
648 * o plat_mem_setup() detects the memory configuration and will record detected
649 * memory areas using add_memory_region.
650 *
651 * At this stage the memory configuration of the system is known to the
652 * kernel but generic memory management system is still entirely uninitialized.
653 *
654 * o bootmem_init()
655 * o sparse_init()
656 * o paging_init()
657 * o dma_contiguous_reserve()
658 *
659 * At this stage the bootmem allocator is ready to use.
660 *
661 * NOTE: historically plat_mem_setup did the entire platform initialization.
662 * This was rather impractical because it meant plat_mem_setup had to
663 * get away without any kind of memory allocator. To keep old code from
664 * breaking plat_setup was just renamed to plat_mem_setup and a second platform
665 * initialization hook for anything else was introduced.
666 */
667
668static int usermem __initdata; 584static int usermem __initdata;
669 585
670static int __init early_parse_mem(char *p) 586static int __init early_parse_mem(char *p)
@@ -841,6 +757,28 @@ static void __init request_crashkernel(struct resource *res)
841#define BUILTIN_EXTEND_WITH_PROM \ 757#define BUILTIN_EXTEND_WITH_PROM \
842 IS_ENABLED(CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND) 758 IS_ENABLED(CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND)
843 759
760/*
761 * arch_mem_init - initialize memory management subsystem
762 *
763 * o plat_mem_setup() detects the memory configuration and will record detected
764 * memory areas using add_memory_region.
765 *
766 * At this stage the memory configuration of the system is known to the
767 * kernel but generic memory management system is still entirely uninitialized.
768 *
769 * o bootmem_init()
770 * o sparse_init()
771 * o paging_init()
772 * o dma_contiguous_reserve()
773 *
774 * At this stage the bootmem allocator is ready to use.
775 *
776 * NOTE: historically plat_mem_setup did the entire platform initialization.
777 * This was rather impractical because it meant plat_mem_setup had to
778 * get away without any kind of memory allocator. To keep old code from
779 * breaking plat_setup was just renamed to plat_mem_setup and a second platform
780 * initialization hook for anything else was introduced.
781 */
844static void __init arch_mem_init(char **cmdline_p) 782static void __init arch_mem_init(char **cmdline_p)
845{ 783{
846 struct memblock_region *reg; 784 struct memblock_region *reg;
@@ -916,21 +854,29 @@ static void __init arch_mem_init(char **cmdline_p)
916 early_init_fdt_scan_reserved_mem(); 854 early_init_fdt_scan_reserved_mem();
917 855
918 bootmem_init(); 856 bootmem_init();
857
858 /*
859 * Prevent memblock from allocating high memory.
860 * This cannot be done before max_low_pfn is detected, so up
861 * to this point is possible to only reserve physical memory
862 * with memblock_reserve; memblock_virt_alloc* can be used
863 * only after this point
864 */
865 memblock_set_current_limit(PFN_PHYS(max_low_pfn));
866
919#ifdef CONFIG_PROC_VMCORE 867#ifdef CONFIG_PROC_VMCORE
920 if (setup_elfcorehdr && setup_elfcorehdr_size) { 868 if (setup_elfcorehdr && setup_elfcorehdr_size) {
921 printk(KERN_INFO "kdump reserved memory at %lx-%lx\n", 869 printk(KERN_INFO "kdump reserved memory at %lx-%lx\n",
922 setup_elfcorehdr, setup_elfcorehdr_size); 870 setup_elfcorehdr, setup_elfcorehdr_size);
923 reserve_bootmem(setup_elfcorehdr, setup_elfcorehdr_size, 871 memblock_reserve(setup_elfcorehdr, setup_elfcorehdr_size);
924 BOOTMEM_DEFAULT);
925 } 872 }
926#endif 873#endif
927 874
928 mips_parse_crashkernel(); 875 mips_parse_crashkernel();
929#ifdef CONFIG_KEXEC 876#ifdef CONFIG_KEXEC
930 if (crashk_res.start != crashk_res.end) 877 if (crashk_res.start != crashk_res.end)
931 reserve_bootmem(crashk_res.start, 878 memblock_reserve(crashk_res.start,
932 crashk_res.end - crashk_res.start + 1, 879 crashk_res.end - crashk_res.start + 1);
933 BOOTMEM_DEFAULT);
934#endif 880#endif
935 device_tree_init(); 881 device_tree_init();
936 sparse_init(); 882 sparse_init();
@@ -940,7 +886,7 @@ static void __init arch_mem_init(char **cmdline_p)
940 /* Tell bootmem about cma reserved memblock section */ 886 /* Tell bootmem about cma reserved memblock section */
941 for_each_memblock(reserved, reg) 887 for_each_memblock(reserved, reg)
942 if (reg->size != 0) 888 if (reg->size != 0)
943 reserve_bootmem(reg->base, reg->size, BOOTMEM_DEFAULT); 889 memblock_reserve(reg->base, reg->size);
944 890
945 reserve_bootmem_region(__pa_symbol(&__nosave_begin), 891 reserve_bootmem_region(__pa_symbol(&__nosave_begin),
946 __pa_symbol(&__nosave_end)); /* Reserve for hibernation */ 892 __pa_symbol(&__nosave_end)); /* Reserve for hibernation */
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 159e83add4bb..76fae9b79f13 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -25,6 +25,7 @@
25#include <linux/linkage.h> 25#include <linux/linkage.h>
26#include <linux/bug.h> 26#include <linux/bug.h>
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/kexec.h>
28 29
29#include <asm/time.h> 30#include <asm/time.h>
30#include <asm/pgtable.h> 31#include <asm/pgtable.h>
@@ -423,6 +424,9 @@ const struct plat_smp_ops bmips43xx_smp_ops = {
423 .cpu_disable = bmips_cpu_disable, 424 .cpu_disable = bmips_cpu_disable,
424 .cpu_die = bmips_cpu_die, 425 .cpu_die = bmips_cpu_die,
425#endif 426#endif
427#ifdef CONFIG_KEXEC
428 .kexec_nonboot_cpu = kexec_nonboot_cpu_jump,
429#endif
426}; 430};
427 431
428const struct plat_smp_ops bmips5000_smp_ops = { 432const struct plat_smp_ops bmips5000_smp_ops = {
@@ -437,6 +441,9 @@ const struct plat_smp_ops bmips5000_smp_ops = {
437 .cpu_disable = bmips_cpu_disable, 441 .cpu_disable = bmips_cpu_disable,
438 .cpu_die = bmips_cpu_die, 442 .cpu_die = bmips_cpu_die,
439#endif 443#endif
444#ifdef CONFIG_KEXEC
445 .kexec_nonboot_cpu = kexec_nonboot_cpu_jump,
446#endif
440}; 447};
441 448
442#endif /* CONFIG_SMP */ 449#endif /* CONFIG_SMP */
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index 03f1026ad148..faccfa4b280b 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -398,6 +398,55 @@ static void cps_smp_finish(void)
398 local_irq_enable(); 398 local_irq_enable();
399} 399}
400 400
401#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC)
402
403enum cpu_death {
404 CPU_DEATH_HALT,
405 CPU_DEATH_POWER,
406};
407
408static void cps_shutdown_this_cpu(enum cpu_death death)
409{
410 unsigned int cpu, core, vpe_id;
411
412 cpu = smp_processor_id();
413 core = cpu_core(&cpu_data[cpu]);
414
415 if (death == CPU_DEATH_HALT) {
416 vpe_id = cpu_vpe_id(&cpu_data[cpu]);
417
418 pr_debug("Halting core %d VP%d\n", core, vpe_id);
419 if (cpu_has_mipsmt) {
420 /* Halt this TC */
421 write_c0_tchalt(TCHALT_H);
422 instruction_hazard();
423 } else if (cpu_has_vp) {
424 write_cpc_cl_vp_stop(1 << vpe_id);
425
426 /* Ensure that the VP_STOP register is written */
427 wmb();
428 }
429 } else {
430 pr_debug("Gating power to core %d\n", core);
431 /* Power down the core */
432 cps_pm_enter_state(CPS_PM_POWER_GATED);
433 }
434}
435
436#ifdef CONFIG_KEXEC
437
438static void cps_kexec_nonboot_cpu(void)
439{
440 if (cpu_has_mipsmt || cpu_has_vp)
441 cps_shutdown_this_cpu(CPU_DEATH_HALT);
442 else
443 cps_shutdown_this_cpu(CPU_DEATH_POWER);
444}
445
446#endif /* CONFIG_KEXEC */
447
448#endif /* CONFIG_HOTPLUG_CPU || CONFIG_KEXEC */
449
401#ifdef CONFIG_HOTPLUG_CPU 450#ifdef CONFIG_HOTPLUG_CPU
402 451
403static int cps_cpu_disable(void) 452static int cps_cpu_disable(void)
@@ -421,19 +470,15 @@ static int cps_cpu_disable(void)
421} 470}
422 471
423static unsigned cpu_death_sibling; 472static unsigned cpu_death_sibling;
424static enum { 473static enum cpu_death cpu_death;
425 CPU_DEATH_HALT,
426 CPU_DEATH_POWER,
427} cpu_death;
428 474
429void play_dead(void) 475void play_dead(void)
430{ 476{
431 unsigned int cpu, core, vpe_id; 477 unsigned int cpu;
432 478
433 local_irq_disable(); 479 local_irq_disable();
434 idle_task_exit(); 480 idle_task_exit();
435 cpu = smp_processor_id(); 481 cpu = smp_processor_id();
436 core = cpu_core(&cpu_data[cpu]);
437 cpu_death = CPU_DEATH_POWER; 482 cpu_death = CPU_DEATH_POWER;
438 483
439 pr_debug("CPU%d going offline\n", cpu); 484 pr_debug("CPU%d going offline\n", cpu);
@@ -456,25 +501,7 @@ void play_dead(void)
456 /* This CPU has chosen its way out */ 501 /* This CPU has chosen its way out */
457 (void)cpu_report_death(); 502 (void)cpu_report_death();
458 503
459 if (cpu_death == CPU_DEATH_HALT) { 504 cps_shutdown_this_cpu(cpu_death);
460 vpe_id = cpu_vpe_id(&cpu_data[cpu]);
461
462 pr_debug("Halting core %d VP%d\n", core, vpe_id);
463 if (cpu_has_mipsmt) {
464 /* Halt this TC */
465 write_c0_tchalt(TCHALT_H);
466 instruction_hazard();
467 } else if (cpu_has_vp) {
468 write_cpc_cl_vp_stop(1 << vpe_id);
469
470 /* Ensure that the VP_STOP register is written */
471 wmb();
472 }
473 } else {
474 pr_debug("Gating power to core %d\n", core);
475 /* Power down the core */
476 cps_pm_enter_state(CPS_PM_POWER_GATED);
477 }
478 505
479 /* This should never be reached */ 506 /* This should never be reached */
480 panic("Failed to offline CPU %u", cpu); 507 panic("Failed to offline CPU %u", cpu);
@@ -593,6 +620,9 @@ static const struct plat_smp_ops cps_smp_ops = {
593 .cpu_disable = cps_cpu_disable, 620 .cpu_disable = cps_cpu_disable,
594 .cpu_die = cps_cpu_die, 621 .cpu_die = cps_cpu_die,
595#endif 622#endif
623#ifdef CONFIG_KEXEC
624 .kexec_nonboot_cpu = cps_kexec_nonboot_cpu,
625#endif
596}; 626};
597 627
598bool mips_cps_smp_in_use(void) 628bool mips_cps_smp_in_use(void)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 9dab0ed1b227..5feef28deac8 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -29,6 +29,7 @@
29#include <linux/spinlock.h> 29#include <linux/spinlock.h>
30#include <linux/kallsyms.h> 30#include <linux/kallsyms.h>
31#include <linux/bootmem.h> 31#include <linux/bootmem.h>
32#include <linux/memblock.h>
32#include <linux/interrupt.h> 33#include <linux/interrupt.h>
33#include <linux/ptrace.h> 34#include <linux/ptrace.h>
34#include <linux/kgdb.h> 35#include <linux/kgdb.h>
@@ -348,7 +349,7 @@ static void __show_regs(const struct pt_regs *regs)
348 */ 349 */
349void show_regs(struct pt_regs *regs) 350void show_regs(struct pt_regs *regs)
350{ 351{
351 __show_regs((struct pt_regs *)regs); 352 __show_regs(regs);
352 dump_stack(); 353 dump_stack();
353} 354}
354 355
@@ -2260,8 +2261,10 @@ void __init trap_init(void)
2260 unsigned long size = 0x200 + VECTORSPACING*64; 2261 unsigned long size = 0x200 + VECTORSPACING*64;
2261 phys_addr_t ebase_pa; 2262 phys_addr_t ebase_pa;
2262 2263
2264 memblock_set_bottom_up(true);
2263 ebase = (unsigned long) 2265 ebase = (unsigned long)
2264 __alloc_bootmem(size, 1 << fls(size), 0); 2266 __alloc_bootmem(size, 1 << fls(size), 0);
2267 memblock_set_bottom_up(false);
2265 2268
2266 /* 2269 /*
2267 * Try to ensure ebase resides in KSeg0 if possible. 2270 * Try to ensure ebase resides in KSeg0 if possible.
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 2d0b912f9e3e..ce446eed62d2 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -130,7 +130,7 @@ do { \
130 : "r" (addr), "i" (-EFAULT)); \ 130 : "r" (addr), "i" (-EFAULT)); \
131} while(0) 131} while(0)
132 132
133#ifndef CONFIG_CPU_MIPSR6 133#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
134#define _LoadW(addr, value, res, type) \ 134#define _LoadW(addr, value, res, type) \
135do { \ 135do { \
136 __asm__ __volatile__ ( \ 136 __asm__ __volatile__ ( \
@@ -151,8 +151,8 @@ do { \
151 : "r" (addr), "i" (-EFAULT)); \ 151 : "r" (addr), "i" (-EFAULT)); \
152} while(0) 152} while(0)
153 153
154#else 154#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
155/* MIPSR6 has no lwl instruction */ 155/* For CPUs without lwl instruction */
156#define _LoadW(addr, value, res, type) \ 156#define _LoadW(addr, value, res, type) \
157do { \ 157do { \
158 __asm__ __volatile__ ( \ 158 __asm__ __volatile__ ( \
@@ -186,7 +186,7 @@ do { \
186 : "r" (addr), "i" (-EFAULT)); \ 186 : "r" (addr), "i" (-EFAULT)); \
187} while(0) 187} while(0)
188 188
189#endif /* CONFIG_CPU_MIPSR6 */ 189#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
190 190
191#define _LoadHWU(addr, value, res, type) \ 191#define _LoadHWU(addr, value, res, type) \
192do { \ 192do { \
@@ -212,7 +212,7 @@ do { \
212 : "r" (addr), "i" (-EFAULT)); \ 212 : "r" (addr), "i" (-EFAULT)); \
213} while(0) 213} while(0)
214 214
215#ifndef CONFIG_CPU_MIPSR6 215#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
216#define _LoadWU(addr, value, res, type) \ 216#define _LoadWU(addr, value, res, type) \
217do { \ 217do { \
218 __asm__ __volatile__ ( \ 218 __asm__ __volatile__ ( \
@@ -255,8 +255,8 @@ do { \
255 : "r" (addr), "i" (-EFAULT)); \ 255 : "r" (addr), "i" (-EFAULT)); \
256} while(0) 256} while(0)
257 257
258#else 258#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
259/* MIPSR6 has not lwl and ldl instructions */ 259/* For CPUs without lwl and ldl instructions */
260#define _LoadWU(addr, value, res, type) \ 260#define _LoadWU(addr, value, res, type) \
261do { \ 261do { \
262 __asm__ __volatile__ ( \ 262 __asm__ __volatile__ ( \
@@ -339,7 +339,7 @@ do { \
339 : "r" (addr), "i" (-EFAULT)); \ 339 : "r" (addr), "i" (-EFAULT)); \
340} while(0) 340} while(0)
341 341
342#endif /* CONFIG_CPU_MIPSR6 */ 342#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
343 343
344 344
345#define _StoreHW(addr, value, res, type) \ 345#define _StoreHW(addr, value, res, type) \
@@ -365,7 +365,7 @@ do { \
365 : "r" (value), "r" (addr), "i" (-EFAULT));\ 365 : "r" (value), "r" (addr), "i" (-EFAULT));\
366} while(0) 366} while(0)
367 367
368#ifndef CONFIG_CPU_MIPSR6 368#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
369#define _StoreW(addr, value, res, type) \ 369#define _StoreW(addr, value, res, type) \
370do { \ 370do { \
371 __asm__ __volatile__ ( \ 371 __asm__ __volatile__ ( \
@@ -406,8 +406,7 @@ do { \
406 : "r" (value), "r" (addr), "i" (-EFAULT)); \ 406 : "r" (value), "r" (addr), "i" (-EFAULT)); \
407} while(0) 407} while(0)
408 408
409#else 409#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
410/* MIPSR6 has no swl and sdl instructions */
411#define _StoreW(addr, value, res, type) \ 410#define _StoreW(addr, value, res, type) \
412do { \ 411do { \
413 __asm__ __volatile__ ( \ 412 __asm__ __volatile__ ( \
@@ -483,7 +482,7 @@ do { \
483 : "memory"); \ 482 : "memory"); \
484} while(0) 483} while(0)
485 484
486#endif /* CONFIG_CPU_MIPSR6 */ 485#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
487 486
488#else /* __BIG_ENDIAN */ 487#else /* __BIG_ENDIAN */
489 488
@@ -509,7 +508,7 @@ do { \
509 : "r" (addr), "i" (-EFAULT)); \ 508 : "r" (addr), "i" (-EFAULT)); \
510} while(0) 509} while(0)
511 510
512#ifndef CONFIG_CPU_MIPSR6 511#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
513#define _LoadW(addr, value, res, type) \ 512#define _LoadW(addr, value, res, type) \
514do { \ 513do { \
515 __asm__ __volatile__ ( \ 514 __asm__ __volatile__ ( \
@@ -530,8 +529,8 @@ do { \
530 : "r" (addr), "i" (-EFAULT)); \ 529 : "r" (addr), "i" (-EFAULT)); \
531} while(0) 530} while(0)
532 531
533#else 532#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
534/* MIPSR6 has no lwl instruction */ 533/* For CPUs without lwl instruction */
535#define _LoadW(addr, value, res, type) \ 534#define _LoadW(addr, value, res, type) \
536do { \ 535do { \
537 __asm__ __volatile__ ( \ 536 __asm__ __volatile__ ( \
@@ -565,7 +564,7 @@ do { \
565 : "r" (addr), "i" (-EFAULT)); \ 564 : "r" (addr), "i" (-EFAULT)); \
566} while(0) 565} while(0)
567 566
568#endif /* CONFIG_CPU_MIPSR6 */ 567#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
569 568
570 569
571#define _LoadHWU(addr, value, res, type) \ 570#define _LoadHWU(addr, value, res, type) \
@@ -592,7 +591,7 @@ do { \
592 : "r" (addr), "i" (-EFAULT)); \ 591 : "r" (addr), "i" (-EFAULT)); \
593} while(0) 592} while(0)
594 593
595#ifndef CONFIG_CPU_MIPSR6 594#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
596#define _LoadWU(addr, value, res, type) \ 595#define _LoadWU(addr, value, res, type) \
597do { \ 596do { \
598 __asm__ __volatile__ ( \ 597 __asm__ __volatile__ ( \
@@ -635,8 +634,8 @@ do { \
635 : "r" (addr), "i" (-EFAULT)); \ 634 : "r" (addr), "i" (-EFAULT)); \
636} while(0) 635} while(0)
637 636
638#else 637#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
639/* MIPSR6 has not lwl and ldl instructions */ 638/* For CPUs without lwl and ldl instructions */
640#define _LoadWU(addr, value, res, type) \ 639#define _LoadWU(addr, value, res, type) \
641do { \ 640do { \
642 __asm__ __volatile__ ( \ 641 __asm__ __volatile__ ( \
@@ -718,7 +717,7 @@ do { \
718 : "=&r" (value), "=r" (res) \ 717 : "=&r" (value), "=r" (res) \
719 : "r" (addr), "i" (-EFAULT)); \ 718 : "r" (addr), "i" (-EFAULT)); \
720} while(0) 719} while(0)
721#endif /* CONFIG_CPU_MIPSR6 */ 720#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
722 721
723#define _StoreHW(addr, value, res, type) \ 722#define _StoreHW(addr, value, res, type) \
724do { \ 723do { \
@@ -743,7 +742,7 @@ do { \
743 : "r" (value), "r" (addr), "i" (-EFAULT));\ 742 : "r" (value), "r" (addr), "i" (-EFAULT));\
744} while(0) 743} while(0)
745 744
746#ifndef CONFIG_CPU_MIPSR6 745#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
747#define _StoreW(addr, value, res, type) \ 746#define _StoreW(addr, value, res, type) \
748do { \ 747do { \
749 __asm__ __volatile__ ( \ 748 __asm__ __volatile__ ( \
@@ -784,8 +783,8 @@ do { \
784 : "r" (value), "r" (addr), "i" (-EFAULT)); \ 783 : "r" (value), "r" (addr), "i" (-EFAULT)); \
785} while(0) 784} while(0)
786 785
787#else 786#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
788/* MIPSR6 has no swl and sdl instructions */ 787/* For CPUs without swl and sdl instructions */
789#define _StoreW(addr, value, res, type) \ 788#define _StoreW(addr, value, res, type) \
790do { \ 789do { \
791 __asm__ __volatile__ ( \ 790 __asm__ __volatile__ ( \
@@ -861,7 +860,7 @@ do { \
861 : "memory"); \ 860 : "memory"); \
862} while(0) 861} while(0)
863 862
864#endif /* CONFIG_CPU_MIPSR6 */ 863#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
865#endif 864#endif
866 865
867#define LoadHWU(addr, value, res) _LoadHWU(addr, value, res, kernel) 866#define LoadHWU(addr, value, res) _LoadHWU(addr, value, res, kernel)
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 6537e022ef62..479f50559c83 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -7,7 +7,7 @@ lib-y += bitops.o csum_partial.o delay.o memcpy.o memset.o \
7 mips-atomic.o strncpy_user.o \ 7 mips-atomic.o strncpy_user.o \
8 strnlen_user.o uncached.o 8 strnlen_user.o uncached.o
9 9
10obj-y += iomap.o iomap_copy.o 10obj-y += iomap_copy.o
11obj-$(CONFIG_PCI) += iomap-pci.o 11obj-$(CONFIG_PCI) += iomap-pci.o
12lib-$(CONFIG_GENERIC_CSUM) := $(filter-out csum_partial.o, $(lib-y)) 12lib-$(CONFIG_GENERIC_CSUM) := $(filter-out csum_partial.o, $(lib-y))
13 13
diff --git a/arch/mips/lib/iomap-pci.c b/arch/mips/lib/iomap-pci.c
index 4850509c5534..210f5a95ecb1 100644
--- a/arch/mips/lib/iomap-pci.c
+++ b/arch/mips/lib/iomap-pci.c
@@ -44,10 +44,3 @@ void __iomem *__pci_ioport_map(struct pci_dev *dev,
44} 44}
45 45
46#endif /* CONFIG_PCI_DRIVERS_LEGACY */ 46#endif /* CONFIG_PCI_DRIVERS_LEGACY */
47
48void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
49{
50 iounmap(addr);
51}
52
53EXPORT_SYMBOL(pci_iounmap);
diff --git a/arch/mips/lib/iomap.c b/arch/mips/lib/iomap.c
deleted file mode 100644
index 9b31653f318c..000000000000
--- a/arch/mips/lib/iomap.c
+++ /dev/null
@@ -1,227 +0,0 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Implement the default iomap interfaces
4 *
5 * (C) Copyright 2004 Linus Torvalds
6 * (C) Copyright 2006 Ralf Baechle <ralf@linux-mips.org>
7 * (C) Copyright 2007 MIPS Technologies, Inc.
8 * written by Ralf Baechle <ralf@linux-mips.org>
9 */
10#include <linux/export.h>
11#include <asm/io.h>
12
13/*
14 * Read/write from/to an (offsettable) iomem cookie. It might be a PIO
15 * access or a MMIO access, these functions don't care. The info is
16 * encoded in the hardware mapping set up by the mapping functions
17 * (or the cookie itself, depending on implementation and hw).
18 *
19 * The generic routines don't assume any hardware mappings, and just
20 * encode the PIO/MMIO as part of the cookie. They coldly assume that
21 * the MMIO IO mappings are not in the low address range.
22 *
23 * Architectures for which this is not true can't use this generic
24 * implementation and should do their own copy.
25 */
26
27#define PIO_MASK 0x0ffffUL
28
29unsigned int ioread8(void __iomem *addr)
30{
31 return readb(addr);
32}
33
34EXPORT_SYMBOL(ioread8);
35
36unsigned int ioread16(void __iomem *addr)
37{
38 return readw(addr);
39}
40
41EXPORT_SYMBOL(ioread16);
42
43unsigned int ioread16be(void __iomem *addr)
44{
45 return be16_to_cpu(__raw_readw(addr));
46}
47
48EXPORT_SYMBOL(ioread16be);
49
50unsigned int ioread32(void __iomem *addr)
51{
52 return readl(addr);
53}
54
55EXPORT_SYMBOL(ioread32);
56
57unsigned int ioread32be(void __iomem *addr)
58{
59 return be32_to_cpu(__raw_readl(addr));
60}
61
62EXPORT_SYMBOL(ioread32be);
63
64void iowrite8(u8 val, void __iomem *addr)
65{
66 writeb(val, addr);
67}
68
69EXPORT_SYMBOL(iowrite8);
70
71void iowrite16(u16 val, void __iomem *addr)
72{
73 writew(val, addr);
74}
75
76EXPORT_SYMBOL(iowrite16);
77
78void iowrite16be(u16 val, void __iomem *addr)
79{
80 __raw_writew(cpu_to_be16(val), addr);
81}
82
83EXPORT_SYMBOL(iowrite16be);
84
85void iowrite32(u32 val, void __iomem *addr)
86{
87 writel(val, addr);
88}
89
90EXPORT_SYMBOL(iowrite32);
91
92void iowrite32be(u32 val, void __iomem *addr)
93{
94 __raw_writel(cpu_to_be32(val), addr);
95}
96
97EXPORT_SYMBOL(iowrite32be);
98
99/*
100 * These are the "repeat MMIO read/write" functions.
101 * Note the "__mem" accesses, since we want to convert
102 * to CPU byte order if the host bus happens to not match the
103 * endianness of PCI/ISA (see mach-generic/mangle-port.h).
104 */
105static inline void mmio_insb(void __iomem *addr, u8 *dst, int count)
106{
107 while (--count >= 0) {
108 u8 data = __mem_readb(addr);
109 *dst = data;
110 dst++;
111 }
112}
113
114static inline void mmio_insw(void __iomem *addr, u16 *dst, int count)
115{
116 while (--count >= 0) {
117 u16 data = __mem_readw(addr);
118 *dst = data;
119 dst++;
120 }
121}
122
123static inline void mmio_insl(void __iomem *addr, u32 *dst, int count)
124{
125 while (--count >= 0) {
126 u32 data = __mem_readl(addr);
127 *dst = data;
128 dst++;
129 }
130}
131
132static inline void mmio_outsb(void __iomem *addr, const u8 *src, int count)
133{
134 while (--count >= 0) {
135 __mem_writeb(*src, addr);
136 src++;
137 }
138}
139
140static inline void mmio_outsw(void __iomem *addr, const u16 *src, int count)
141{
142 while (--count >= 0) {
143 __mem_writew(*src, addr);
144 src++;
145 }
146}
147
148static inline void mmio_outsl(void __iomem *addr, const u32 *src, int count)
149{
150 while (--count >= 0) {
151 __mem_writel(*src, addr);
152 src++;
153 }
154}
155
156void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
157{
158 mmio_insb(addr, dst, count);
159}
160
161EXPORT_SYMBOL(ioread8_rep);
162
163void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
164{
165 mmio_insw(addr, dst, count);
166}
167
168EXPORT_SYMBOL(ioread16_rep);
169
170void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
171{
172 mmio_insl(addr, dst, count);
173}
174
175EXPORT_SYMBOL(ioread32_rep);
176
177void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
178{
179 mmio_outsb(addr, src, count);
180}
181
182EXPORT_SYMBOL(iowrite8_rep);
183
184void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
185{
186 mmio_outsw(addr, src, count);
187}
188
189EXPORT_SYMBOL(iowrite16_rep);
190
191void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
192{
193 mmio_outsl(addr, src, count);
194}
195
196EXPORT_SYMBOL(iowrite32_rep);
197
198/*
199 * Create a virtual mapping cookie for an IO port range
200 *
201 * This uses the same mapping are as the in/out family which has to be setup
202 * by the platform initialization code.
203 *
204 * Just to make matters somewhat more interesting on MIPS systems with
205 * multiple host bridge each will have it's own ioport address space.
206 */
207static void __iomem *ioport_map_legacy(unsigned long port, unsigned int nr)
208{
209 return (void __iomem *) (mips_io_port_base + port);
210}
211
212void __iomem *ioport_map(unsigned long port, unsigned int nr)
213{
214 if (port > PIO_MASK)
215 return NULL;
216
217 return ioport_map_legacy(port, nr);
218}
219
220EXPORT_SYMBOL(ioport_map);
221
222void ioport_unmap(void __iomem *addr)
223{
224 /* Nothing to do */
225}
226
227EXPORT_SYMBOL(ioport_unmap);
diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S
index 03e3304d6ae5..cdd19d8561e8 100644
--- a/arch/mips/lib/memcpy.S
+++ b/arch/mips/lib/memcpy.S
@@ -204,9 +204,10 @@
204#define LOADB(reg, addr, handler) EXC(lb, LD_INSN, reg, addr, handler) 204#define LOADB(reg, addr, handler) EXC(lb, LD_INSN, reg, addr, handler)
205#define STOREB(reg, addr, handler) EXC(sb, ST_INSN, reg, addr, handler) 205#define STOREB(reg, addr, handler) EXC(sb, ST_INSN, reg, addr, handler)
206 206
207#define _PREF(hint, addr, type) \ 207#ifdef CONFIG_CPU_HAS_PREFETCH
208# define _PREF(hint, addr, type) \
208 .if \mode == LEGACY_MODE; \ 209 .if \mode == LEGACY_MODE; \
209 PREF(hint, addr); \ 210 kernel_pref(hint, addr); \
210 .else; \ 211 .else; \
211 .if ((\from == USEROP) && (type == SRC_PREFETCH)) || \ 212 .if ((\from == USEROP) && (type == SRC_PREFETCH)) || \
212 ((\to == USEROP) && (type == DST_PREFETCH)); \ 213 ((\to == USEROP) && (type == DST_PREFETCH)); \
@@ -218,12 +219,15 @@
218 * used later on. Therefore use $v1. \ 219 * used later on. Therefore use $v1. \
219 */ \ 220 */ \
220 .set at=v1; \ 221 .set at=v1; \
221 PREFE(hint, addr); \ 222 user_pref(hint, addr); \
222 .set noat; \ 223 .set noat; \
223 .else; \ 224 .else; \
224 PREF(hint, addr); \ 225 kernel_pref(hint, addr); \
225 .endif; \ 226 .endif; \
226 .endif 227 .endif
228#else
229# define _PREF(hint, addr, type)
230#endif
227 231
228#define PREFS(hint, addr) _PREF(hint, addr, SRC_PREFETCH) 232#define PREFS(hint, addr) _PREF(hint, addr, SRC_PREFETCH)
229#define PREFD(hint, addr) _PREF(hint, addr, DST_PREFETCH) 233#define PREFD(hint, addr) _PREF(hint, addr, DST_PREFETCH)
@@ -297,7 +301,7 @@
297 and t0, src, ADDRMASK 301 and t0, src, ADDRMASK
298 PREFS( 0, 2*32(src) ) 302 PREFS( 0, 2*32(src) )
299 PREFD( 1, 2*32(dst) ) 303 PREFD( 1, 2*32(dst) )
300#ifndef CONFIG_CPU_MIPSR6 304#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
301 bnez t1, .Ldst_unaligned\@ 305 bnez t1, .Ldst_unaligned\@
302 nop 306 nop
303 bnez t0, .Lsrc_unaligned_dst_aligned\@ 307 bnez t0, .Lsrc_unaligned_dst_aligned\@
@@ -385,7 +389,7 @@
385 bne rem, len, 1b 389 bne rem, len, 1b
386 .set noreorder 390 .set noreorder
387 391
388#ifndef CONFIG_CPU_MIPSR6 392#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
389 /* 393 /*
390 * src and dst are aligned, need to copy rem bytes (rem < NBYTES) 394 * src and dst are aligned, need to copy rem bytes (rem < NBYTES)
391 * A loop would do only a byte at a time with possible branch 395 * A loop would do only a byte at a time with possible branch
@@ -487,7 +491,7 @@
487 bne len, rem, 1b 491 bne len, rem, 1b
488 .set noreorder 492 .set noreorder
489 493
490#endif /* !CONFIG_CPU_MIPSR6 */ 494#endif /* CONFIG_CPU_HAS_LOAD_STORE_LR */
491.Lcopy_bytes_checklen\@: 495.Lcopy_bytes_checklen\@:
492 beqz len, .Ldone\@ 496 beqz len, .Ldone\@
493 nop 497 nop
@@ -516,7 +520,7 @@
516 jr ra 520 jr ra
517 nop 521 nop
518 522
519#ifdef CONFIG_CPU_MIPSR6 523#ifndef CONFIG_CPU_HAS_LOAD_STORE_LR
520.Lcopy_unaligned_bytes\@: 524.Lcopy_unaligned_bytes\@:
5211: 5251:
522 COPY_BYTE(0) 526 COPY_BYTE(0)
@@ -530,7 +534,7 @@
530 ADD src, src, 8 534 ADD src, src, 8
531 b 1b 535 b 1b
532 ADD dst, dst, 8 536 ADD dst, dst, 8
533#endif /* CONFIG_CPU_MIPSR6 */ 537#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
534 .if __memcpy == 1 538 .if __memcpy == 1
535 END(memcpy) 539 END(memcpy)
536 .set __memcpy, 0 540 .set __memcpy, 0
diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S
index 069acec3df9f..418611ef13cf 100644
--- a/arch/mips/lib/memset.S
+++ b/arch/mips/lib/memset.S
@@ -78,7 +78,6 @@
78#endif 78#endif
79 .endm 79 .endm
80 80
81 .set noreorder
82 .align 5 81 .align 5
83 82
84 /* 83 /*
@@ -94,13 +93,16 @@
94 .endif 93 .endif
95 94
96 sltiu t0, a2, STORSIZE /* very small region? */ 95 sltiu t0, a2, STORSIZE /* very small region? */
96 .set noreorder
97 bnez t0, .Lsmall_memset\@ 97 bnez t0, .Lsmall_memset\@
98 andi t0, a0, STORMASK /* aligned? */ 98 andi t0, a0, STORMASK /* aligned? */
99 .set reorder
99 100
100#ifdef CONFIG_CPU_MICROMIPS 101#ifdef CONFIG_CPU_MICROMIPS
101 move t8, a1 /* used by 'swp' instruction */ 102 move t8, a1 /* used by 'swp' instruction */
102 move t9, a1 103 move t9, a1
103#endif 104#endif
105 .set noreorder
104#ifndef CONFIG_CPU_DADDI_WORKAROUNDS 106#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
105 beqz t0, 1f 107 beqz t0, 1f
106 PTR_SUBU t0, STORSIZE /* alignment in bytes */ 108 PTR_SUBU t0, STORSIZE /* alignment in bytes */
@@ -111,8 +113,9 @@
111 PTR_SUBU t0, AT /* alignment in bytes */ 113 PTR_SUBU t0, AT /* alignment in bytes */
112 .set at 114 .set at
113#endif 115#endif
116 .set reorder
114 117
115#ifndef CONFIG_CPU_MIPSR6 118#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
116 R10KCBARRIER(0(ra)) 119 R10KCBARRIER(0(ra))
117#ifdef __MIPSEB__ 120#ifdef __MIPSEB__
118 EX(LONG_S_L, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */ 121 EX(LONG_S_L, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */
@@ -122,11 +125,13 @@
122 PTR_SUBU a0, t0 /* long align ptr */ 125 PTR_SUBU a0, t0 /* long align ptr */
123 PTR_ADDU a2, t0 /* correct size */ 126 PTR_ADDU a2, t0 /* correct size */
124 127
125#else /* CONFIG_CPU_MIPSR6 */ 128#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
126#define STORE_BYTE(N) \ 129#define STORE_BYTE(N) \
127 EX(sb, a1, N(a0), .Lbyte_fixup\@); \ 130 EX(sb, a1, N(a0), .Lbyte_fixup\@); \
131 .set noreorder; \
128 beqz t0, 0f; \ 132 beqz t0, 0f; \
129 PTR_ADDU t0, 1; 133 PTR_ADDU t0, 1; \
134 .set reorder;
130 135
131 PTR_ADDU a2, t0 /* correct size */ 136 PTR_ADDU a2, t0 /* correct size */
132 PTR_ADDU t0, 1 137 PTR_ADDU t0, 1
@@ -145,19 +150,17 @@
145 ori a0, STORMASK 150 ori a0, STORMASK
146 xori a0, STORMASK 151 xori a0, STORMASK
147 PTR_ADDIU a0, STORSIZE 152 PTR_ADDIU a0, STORSIZE
148#endif /* CONFIG_CPU_MIPSR6 */ 153#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
1491: ori t1, a2, 0x3f /* # of full blocks */ 1541: ori t1, a2, 0x3f /* # of full blocks */
150 xori t1, 0x3f 155 xori t1, 0x3f
156 andi t0, a2, 0x40-STORSIZE
151 beqz t1, .Lmemset_partial\@ /* no block to fill */ 157 beqz t1, .Lmemset_partial\@ /* no block to fill */
152 andi t0, a2, 0x40-STORSIZE
153 158
154 PTR_ADDU t1, a0 /* end address */ 159 PTR_ADDU t1, a0 /* end address */
155 .set reorder
1561: PTR_ADDIU a0, 64 1601: PTR_ADDIU a0, 64
157 R10KCBARRIER(0(ra)) 161 R10KCBARRIER(0(ra))
158 f_fill64 a0, -64, FILL64RG, .Lfwd_fixup\@, \mode 162 f_fill64 a0, -64, FILL64RG, .Lfwd_fixup\@, \mode
159 bne t1, a0, 1b 163 bne t1, a0, 1b
160 .set noreorder
161 164
162.Lmemset_partial\@: 165.Lmemset_partial\@:
163 R10KCBARRIER(0(ra)) 166 R10KCBARRIER(0(ra))
@@ -173,20 +176,18 @@
173 PTR_SUBU t1, AT 176 PTR_SUBU t1, AT
174 .set at 177 .set at
175#endif 178#endif
179 PTR_ADDU a0, t0 /* dest ptr */
176 jr t1 180 jr t1
177 PTR_ADDU a0, t0 /* dest ptr */
178 181
179 .set push
180 .set noreorder
181 .set nomacro
182 /* ... but first do longs ... */ 182 /* ... but first do longs ... */
183 f_fill64 a0, -64, FILL64RG, .Lpartial_fixup\@, \mode 183 f_fill64 a0, -64, FILL64RG, .Lpartial_fixup\@, \mode
1842: .set pop 1842: andi a2, STORMASK /* At most one long to go */
185 andi a2, STORMASK /* At most one long to go */
186 185
186 .set noreorder
187 beqz a2, 1f 187 beqz a2, 1f
188#ifndef CONFIG_CPU_MIPSR6 188#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
189 PTR_ADDU a0, a2 /* What's left */ 189 PTR_ADDU a0, a2 /* What's left */
190 .set reorder
190 R10KCBARRIER(0(ra)) 191 R10KCBARRIER(0(ra))
191#ifdef __MIPSEB__ 192#ifdef __MIPSEB__
192 EX(LONG_S_R, a1, -1(a0), .Llast_fixup\@) 193 EX(LONG_S_R, a1, -1(a0), .Llast_fixup\@)
@@ -195,6 +196,7 @@
195#endif 196#endif
196#else 197#else
197 PTR_SUBU t0, $0, a2 198 PTR_SUBU t0, $0, a2
199 .set reorder
198 move a2, zero /* No remaining longs */ 200 move a2, zero /* No remaining longs */
199 PTR_ADDIU t0, 1 201 PTR_ADDIU t0, 1
200 STORE_BYTE(0) 202 STORE_BYTE(0)
@@ -210,41 +212,42 @@
210#endif 212#endif
2110: 2130:
212#endif 214#endif
2131: jr ra 2151: move a2, zero
214 move a2, zero 216 jr ra
215 217
216.Lsmall_memset\@: 218.Lsmall_memset\@:
219 PTR_ADDU t1, a0, a2
217 beqz a2, 2f 220 beqz a2, 2f
218 PTR_ADDU t1, a0, a2
219 221
2201: PTR_ADDIU a0, 1 /* fill bytewise */ 2221: PTR_ADDIU a0, 1 /* fill bytewise */
221 R10KCBARRIER(0(ra)) 223 R10KCBARRIER(0(ra))
224 .set noreorder
222 bne t1, a0, 1b 225 bne t1, a0, 1b
223 EX(sb, a1, -1(a0), .Lsmall_fixup\@) 226 EX(sb, a1, -1(a0), .Lsmall_fixup\@)
227 .set reorder
224 228
2252: jr ra /* done */ 2292: move a2, zero
226 move a2, zero 230 jr ra /* done */
227 .if __memset == 1 231 .if __memset == 1
228 END(memset) 232 END(memset)
229 .set __memset, 0 233 .set __memset, 0
230 .hidden __memset 234 .hidden __memset
231 .endif 235 .endif
232 236
233#ifdef CONFIG_CPU_MIPSR6 237#ifndef CONFIG_CPU_HAS_LOAD_STORE_LR
234.Lbyte_fixup\@: 238.Lbyte_fixup\@:
235 /* 239 /*
236 * unset_bytes = (#bytes - (#unaligned bytes)) - (-#unaligned bytes remaining + 1) + 1 240 * unset_bytes = (#bytes - (#unaligned bytes)) - (-#unaligned bytes remaining + 1) + 1
237 * a2 = a2 - t0 + 1 241 * a2 = a2 - t0 + 1
238 */ 242 */
239 PTR_SUBU a2, t0 243 PTR_SUBU a2, t0
244 PTR_ADDIU a2, 1
240 jr ra 245 jr ra
241 PTR_ADDIU a2, 1 246#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
242#endif /* CONFIG_CPU_MIPSR6 */
243 247
244.Lfirst_fixup\@: 248.Lfirst_fixup\@:
245 /* unset_bytes already in a2 */ 249 /* unset_bytes already in a2 */
246 jr ra 250 jr ra
247 nop
248 251
249.Lfwd_fixup\@: 252.Lfwd_fixup\@:
250 /* 253 /*
@@ -255,8 +258,8 @@
255 andi a2, 0x3f 258 andi a2, 0x3f
256 LONG_L t0, THREAD_BUADDR(t0) 259 LONG_L t0, THREAD_BUADDR(t0)
257 LONG_ADDU a2, t1 260 LONG_ADDU a2, t1
261 LONG_SUBU a2, t0
258 jr ra 262 jr ra
259 LONG_SUBU a2, t0
260 263
261.Lpartial_fixup\@: 264.Lpartial_fixup\@:
262 /* 265 /*
@@ -267,24 +270,21 @@
267 andi a2, STORMASK 270 andi a2, STORMASK
268 LONG_L t0, THREAD_BUADDR(t0) 271 LONG_L t0, THREAD_BUADDR(t0)
269 LONG_ADDU a2, a0 272 LONG_ADDU a2, a0
273 LONG_SUBU a2, t0
270 jr ra 274 jr ra
271 LONG_SUBU a2, t0
272 275
273.Llast_fixup\@: 276.Llast_fixup\@:
274 /* unset_bytes already in a2 */ 277 /* unset_bytes already in a2 */
275 jr ra 278 jr ra
276 nop
277 279
278.Lsmall_fixup\@: 280.Lsmall_fixup\@:
279 /* 281 /*
280 * unset_bytes = end_addr - current_addr + 1 282 * unset_bytes = end_addr - current_addr + 1
281 * a2 = t1 - a0 + 1 283 * a2 = t1 - a0 + 1
282 */ 284 */
283 .set reorder
284 PTR_SUBU a2, t1, a0 285 PTR_SUBU a2, t1, a0
285 PTR_ADDIU a2, 1 286 PTR_ADDIU a2, 1
286 jr ra 287 jr ra
287 .set noreorder
288 288
289 .endm 289 .endm
290 290
@@ -298,8 +298,8 @@
298 298
299LEAF(memset) 299LEAF(memset)
300EXPORT_SYMBOL(memset) 300EXPORT_SYMBOL(memset)
301 move v0, a0 /* result */
301 beqz a1, 1f 302 beqz a1, 1f
302 move v0, a0 /* result */
303 303
304 andi a1, 0xff /* spread fillword */ 304 andi a1, 0xff /* spread fillword */
305 LONG_SLL t1, a1, 8 305 LONG_SLL t1, a1, 8
diff --git a/arch/mips/loongson64/common/Makefile b/arch/mips/loongson64/common/Makefile
index 57ee03022941..684624f61f5a 100644
--- a/arch/mips/loongson64/common/Makefile
+++ b/arch/mips/loongson64/common/Makefile
@@ -6,7 +6,6 @@
6obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \ 6obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \
7 bonito-irq.o mem.o machtype.o platform.o serial.o 7 bonito-irq.o mem.o machtype.o platform.o serial.o
8obj-$(CONFIG_PCI) += pci.o 8obj-$(CONFIG_PCI) += pci.o
9obj-$(CONFIG_CPU_LOONGSON2) += dma.o
10 9
11# 10#
12# Serial port support 11# Serial port support
diff --git a/arch/mips/loongson64/fuloong-2e/Makefile b/arch/mips/loongson64/fuloong-2e/Makefile
index b7622720c1ad..0a9a472bec0a 100644
--- a/arch/mips/loongson64/fuloong-2e/Makefile
+++ b/arch/mips/loongson64/fuloong-2e/Makefile
@@ -2,4 +2,4 @@
2# Makefile for Lemote Fuloong2e mini-PC board. 2# Makefile for Lemote Fuloong2e mini-PC board.
3# 3#
4 4
5obj-y += irq.o reset.o 5obj-y += irq.o reset.o dma.o
diff --git a/arch/mips/loongson64/fuloong-2e/dma.c b/arch/mips/loongson64/fuloong-2e/dma.c
new file mode 100644
index 000000000000..e122292bf666
--- /dev/null
+++ b/arch/mips/loongson64/fuloong-2e/dma.c
@@ -0,0 +1,12 @@
1// SPDX-License-Identifier: GPL-2.0
2#include <linux/dma-direct.h>
3
4dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
5{
6 return paddr | 0x80000000;
7}
8
9phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr)
10{
11 return dma_addr & 0x7fffffff;
12}
diff --git a/arch/mips/loongson64/lemote-2f/Makefile b/arch/mips/loongson64/lemote-2f/Makefile
index 08b8abcbfef5..b5792c334cd5 100644
--- a/arch/mips/loongson64/lemote-2f/Makefile
+++ b/arch/mips/loongson64/lemote-2f/Makefile
@@ -2,7 +2,7 @@
2# Makefile for lemote loongson2f family machines 2# Makefile for lemote loongson2f family machines
3# 3#
4 4
5obj-y += clock.o machtype.o irq.o reset.o ec_kb3310b.o 5obj-y += clock.o machtype.o irq.o reset.o dma.o ec_kb3310b.o
6 6
7# 7#
8# Suspend Support 8# Suspend Support
diff --git a/arch/mips/loongson64/common/dma.c b/arch/mips/loongson64/lemote-2f/dma.c
index 48f04126bde2..abf0e39d7e46 100644
--- a/arch/mips/loongson64/common/dma.c
+++ b/arch/mips/loongson64/lemote-2f/dma.c
@@ -8,11 +8,7 @@ dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
8 8
9phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr) 9phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr)
10{ 10{
11#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT)
12 if (dma_addr > 0x8fffffff) 11 if (dma_addr > 0x8fffffff)
13 return dma_addr; 12 return dma_addr;
14 return dma_addr & 0x0fffffff; 13 return dma_addr & 0x0fffffff;
15#else
16 return dma_addr & 0x7fffffff;
17#endif
18} 14}
diff --git a/arch/mips/loongson64/loongson-3/irq.c b/arch/mips/loongson64/loongson-3/irq.c
index cbeb20f9fc95..5605061f5f98 100644
--- a/arch/mips/loongson64/loongson-3/irq.c
+++ b/arch/mips/loongson64/loongson-3/irq.c
@@ -96,51 +96,8 @@ void mach_irq_dispatch(unsigned int pending)
96 } 96 }
97} 97}
98 98
99static struct irqaction cascade_irqaction = { 99static inline void mask_loongson_irq(struct irq_data *d) { }
100 .handler = no_action, 100static inline void unmask_loongson_irq(struct irq_data *d) { }
101 .flags = IRQF_NO_SUSPEND,
102 .name = "cascade",
103};
104
105static inline void mask_loongson_irq(struct irq_data *d)
106{
107 clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
108 irq_disable_hazard();
109
110 /* Workaround: UART IRQ may deliver to any core */
111 if (d->irq == LOONGSON_UART_IRQ) {
112 int cpu = smp_processor_id();
113 int node_id = cpu_logical_map(cpu) / loongson_sysconf.cores_per_node;
114 int core_id = cpu_logical_map(cpu) % loongson_sysconf.cores_per_node;
115 u64 intenclr_addr = smp_group[node_id] |
116 (u64)(&LOONGSON_INT_ROUTER_INTENCLR);
117 u64 introuter_lpc_addr = smp_group[node_id] |
118 (u64)(&LOONGSON_INT_ROUTER_LPC);
119
120 *(volatile u32 *)intenclr_addr = 1 << 10;
121 *(volatile u8 *)introuter_lpc_addr = 0x10 + (1<<core_id);
122 }
123}
124
125static inline void unmask_loongson_irq(struct irq_data *d)
126{
127 /* Workaround: UART IRQ may deliver to any core */
128 if (d->irq == LOONGSON_UART_IRQ) {
129 int cpu = smp_processor_id();
130 int node_id = cpu_logical_map(cpu) / loongson_sysconf.cores_per_node;
131 int core_id = cpu_logical_map(cpu) % loongson_sysconf.cores_per_node;
132 u64 intenset_addr = smp_group[node_id] |
133 (u64)(&LOONGSON_INT_ROUTER_INTENSET);
134 u64 introuter_lpc_addr = smp_group[node_id] |
135 (u64)(&LOONGSON_INT_ROUTER_LPC);
136
137 *(volatile u32 *)intenset_addr = 1 << 10;
138 *(volatile u8 *)introuter_lpc_addr = 0x10 + (1<<core_id);
139 }
140
141 set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
142 irq_enable_hazard();
143}
144 101
145 /* For MIPS IRQs which shared by all cores */ 102 /* For MIPS IRQs which shared by all cores */
146static struct irq_chip loongson_irq_chip = { 103static struct irq_chip loongson_irq_chip = {
@@ -183,12 +140,11 @@ void __init mach_init_irq(void)
183 chip->irq_set_affinity = plat_set_irq_affinity; 140 chip->irq_set_affinity = plat_set_irq_affinity;
184 141
185 irq_set_chip_and_handler(LOONGSON_UART_IRQ, 142 irq_set_chip_and_handler(LOONGSON_UART_IRQ,
186 &loongson_irq_chip, handle_level_irq); 143 &loongson_irq_chip, handle_percpu_irq);
187 144 irq_set_chip_and_handler(LOONGSON_BRIDGE_IRQ,
188 /* setup HT1 irq */ 145 &loongson_irq_chip, handle_percpu_irq);
189 setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction);
190 146
191 set_c0_status(STATUSF_IP2 | STATUSF_IP6); 147 set_c0_status(STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP6);
192} 148}
193 149
194#ifdef CONFIG_HOTPLUG_CPU 150#ifdef CONFIG_HOTPLUG_CPU
diff --git a/arch/mips/loongson64/loongson-3/numa.c b/arch/mips/loongson64/loongson-3/numa.c
index 9717106de4a5..c1e6ec52c614 100644
--- a/arch/mips/loongson64/loongson-3/numa.c
+++ b/arch/mips/loongson64/loongson-3/numa.c
@@ -180,43 +180,39 @@ static void __init szmem(unsigned int node)
180 180
181static void __init node_mem_init(unsigned int node) 181static void __init node_mem_init(unsigned int node)
182{ 182{
183 unsigned long bootmap_size;
184 unsigned long node_addrspace_offset; 183 unsigned long node_addrspace_offset;
185 unsigned long start_pfn, end_pfn, freepfn; 184 unsigned long start_pfn, end_pfn;
186 185
187 node_addrspace_offset = nid_to_addroffset(node); 186 node_addrspace_offset = nid_to_addroffset(node);
188 pr_info("Node%d's addrspace_offset is 0x%lx\n", 187 pr_info("Node%d's addrspace_offset is 0x%lx\n",
189 node, node_addrspace_offset); 188 node, node_addrspace_offset);
190 189
191 get_pfn_range_for_nid(node, &start_pfn, &end_pfn); 190 get_pfn_range_for_nid(node, &start_pfn, &end_pfn);
192 freepfn = start_pfn; 191 pr_info("Node%d: start_pfn=0x%lx, end_pfn=0x%lx\n",
193 if (node == 0) 192 node, start_pfn, end_pfn);
194 freepfn = PFN_UP(__pa_symbol(&_end)); /* kernel end address */
195 pr_info("Node%d: start_pfn=0x%lx, end_pfn=0x%lx, freepfn=0x%lx\n",
196 node, start_pfn, end_pfn, freepfn);
197 193
198 __node_data[node] = prealloc__node_data + node; 194 __node_data[node] = prealloc__node_data + node;
199 195
200 NODE_DATA(node)->bdata = &bootmem_node_data[node];
201 NODE_DATA(node)->node_start_pfn = start_pfn; 196 NODE_DATA(node)->node_start_pfn = start_pfn;
202 NODE_DATA(node)->node_spanned_pages = end_pfn - start_pfn; 197 NODE_DATA(node)->node_spanned_pages = end_pfn - start_pfn;
203 198
204 bootmap_size = init_bootmem_node(NODE_DATA(node), freepfn,
205 start_pfn, end_pfn);
206 free_bootmem_with_active_regions(node, end_pfn); 199 free_bootmem_with_active_regions(node, end_pfn);
207 if (node == 0) /* used by finalize_initrd() */ 200
201 if (node == 0) {
202 /* kernel end address */
203 unsigned long kernel_end_pfn = PFN_UP(__pa_symbol(&_end));
204
205 /* used by finalize_initrd() */
208 max_low_pfn = end_pfn; 206 max_low_pfn = end_pfn;
209 207
210 /* This is reserved for the kernel and bdata->node_bootmem_map */ 208 /* Reserve the kernel text/data/bss */
211 reserve_bootmem_node(NODE_DATA(node), start_pfn << PAGE_SHIFT, 209 memblock_reserve(start_pfn << PAGE_SHIFT,
212 ((freepfn - start_pfn) << PAGE_SHIFT) + bootmap_size, 210 ((kernel_end_pfn - start_pfn) << PAGE_SHIFT));
213 BOOTMEM_DEFAULT);
214 211
215 if (node == 0 && node_end_pfn(0) >= (0xffffffff >> PAGE_SHIFT)) {
216 /* Reserve 0xfe000000~0xffffffff for RS780E integrated GPU */ 212 /* Reserve 0xfe000000~0xffffffff for RS780E integrated GPU */
217 reserve_bootmem_node(NODE_DATA(node), 213 if (node_end_pfn(0) >= (0xffffffff >> PAGE_SHIFT))
218 (node_addrspace_offset | 0xfe000000), 214 memblock_reserve((node_addrspace_offset | 0xfe000000),
219 32 << 20, BOOTMEM_DEFAULT); 215 32 << 20);
220 } 216 }
221 217
222 sparse_memory_present_with_active_regions(node); 218 sparse_memory_present_with_active_regions(node);
diff --git a/arch/mips/loongson64/loongson-3/smp.c b/arch/mips/loongson64/loongson-3/smp.c
index fea95d003269..b5c1e0aa955e 100644
--- a/arch/mips/loongson64/loongson-3/smp.c
+++ b/arch/mips/loongson64/loongson-3/smp.c
@@ -21,6 +21,7 @@
21#include <linux/sched/task_stack.h> 21#include <linux/sched/task_stack.h>
22#include <linux/smp.h> 22#include <linux/smp.h>
23#include <linux/cpufreq.h> 23#include <linux/cpufreq.h>
24#include <linux/kexec.h>
24#include <asm/processor.h> 25#include <asm/processor.h>
25#include <asm/time.h> 26#include <asm/time.h>
26#include <asm/clock.h> 27#include <asm/clock.h>
@@ -349,7 +350,7 @@ static void loongson3_smp_finish(void)
349 write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ); 350 write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
350 local_irq_enable(); 351 local_irq_enable();
351 loongson3_ipi_write64(0, 352 loongson3_ipi_write64(0,
352 (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x0)); 353 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0);
353 pr_info("CPU#%d finished, CP0_ST=%x\n", 354 pr_info("CPU#%d finished, CP0_ST=%x\n",
354 smp_processor_id(), read_c0_status()); 355 smp_processor_id(), read_c0_status());
355} 356}
@@ -416,13 +417,13 @@ static int loongson3_boot_secondary(int cpu, struct task_struct *idle)
416 cpu, startargs[0], startargs[1], startargs[2]); 417 cpu, startargs[0], startargs[1], startargs[2]);
417 418
418 loongson3_ipi_write64(startargs[3], 419 loongson3_ipi_write64(startargs[3],
419 (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x18)); 420 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x18);
420 loongson3_ipi_write64(startargs[2], 421 loongson3_ipi_write64(startargs[2],
421 (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x10)); 422 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x10);
422 loongson3_ipi_write64(startargs[1], 423 loongson3_ipi_write64(startargs[1],
423 (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x8)); 424 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x8);
424 loongson3_ipi_write64(startargs[0], 425 loongson3_ipi_write64(startargs[0],
425 (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x0)); 426 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0);
426 return 0; 427 return 0;
427} 428}
428 429
@@ -749,4 +750,7 @@ const struct plat_smp_ops loongson3_smp_ops = {
749 .cpu_disable = loongson3_cpu_disable, 750 .cpu_disable = loongson3_cpu_disable,
750 .cpu_die = loongson3_cpu_die, 751 .cpu_die = loongson3_cpu_die,
751#endif 752#endif
753#ifdef CONFIG_KEXEC
754 .kexec_nonboot_cpu = kexec_nonboot_cpu_jump,
755#endif
752}; 756};
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 400676ce03f4..15cae0f11880 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -32,7 +32,6 @@
32#include <linux/kcore.h> 32#include <linux/kcore.h>
33#include <linux/initrd.h> 33#include <linux/initrd.h>
34 34
35#include <asm/asm-offsets.h>
36#include <asm/bootinfo.h> 35#include <asm/bootinfo.h>
37#include <asm/cachectl.h> 36#include <asm/cachectl.h>
38#include <asm/cpu.h> 37#include <asm/cpu.h>
@@ -521,17 +520,13 @@ unsigned long pgd_current[NR_CPUS];
521#endif 520#endif
522 521
523/* 522/*
524 * gcc 3.3 and older have trouble determining that PTRS_PER_PGD and PGD_ORDER
525 * are constants. So we use the variants from asm-offset.h until that gcc
526 * will officially be retired.
527 *
528 * Align swapper_pg_dir in to 64K, allows its address to be loaded 523 * Align swapper_pg_dir in to 64K, allows its address to be loaded
529 * with a single LUI instruction in the TLB handlers. If we used 524 * with a single LUI instruction in the TLB handlers. If we used
530 * __aligned(64K), its size would get rounded up to the alignment 525 * __aligned(64K), its size would get rounded up to the alignment
531 * size, and waste space. So we place it in its own section and align 526 * size, and waste space. So we place it in its own section and align
532 * it in the linker script. 527 * it in the linker script.
533 */ 528 */
534pgd_t swapper_pg_dir[_PTRS_PER_PGD] __section(.bss..swapper_pg_dir); 529pgd_t swapper_pg_dir[PTRS_PER_PGD] __section(.bss..swapper_pg_dir);
535#ifndef __PAGETABLE_PUD_FOLDED 530#ifndef __PAGETABLE_PUD_FOLDED
536pud_t invalid_pud_table[PTRS_PER_PUD] __page_aligned_bss; 531pud_t invalid_pud_table[PTRS_PER_PUD] __page_aligned_bss;
537#endif 532#endif
diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c
index f4961bc9a61d..cf33dd8a487e 100644
--- a/arch/mips/netlogic/common/irq.c
+++ b/arch/mips/netlogic/common/irq.c
@@ -291,7 +291,7 @@ static int __init xlp_of_pic_init(struct device_node *node,
291 /* we need a hack to get the PIC's SoC chip id */ 291 /* we need a hack to get the PIC's SoC chip id */
292 ret = of_address_to_resource(node, 0, &res); 292 ret = of_address_to_resource(node, 0, &res);
293 if (ret < 0) { 293 if (ret < 0) {
294 pr_err("PIC %s: reg property not found!\n", node->name); 294 pr_err("PIC %pOFn: reg property not found!\n", node);
295 return -EINVAL; 295 return -EINVAL;
296 } 296 }
297 297
@@ -304,21 +304,21 @@ static int __init xlp_of_pic_init(struct device_node *node,
304 break; 304 break;
305 } 305 }
306 if (socid == NLM_NR_NODES) { 306 if (socid == NLM_NR_NODES) {
307 pr_err("PIC %s: Node mapping for bus %d not found!\n", 307 pr_err("PIC %pOFn: Node mapping for bus %d not found!\n",
308 node->name, bus); 308 node, bus);
309 return -EINVAL; 309 return -EINVAL;
310 } 310 }
311 } else { 311 } else {
312 socid = (res.start >> 18) & 0x3; 312 socid = (res.start >> 18) & 0x3;
313 if (!nlm_node_present(socid)) { 313 if (!nlm_node_present(socid)) {
314 pr_err("PIC %s: node %d does not exist!\n", 314 pr_err("PIC %pOFn: node %d does not exist!\n",
315 node->name, socid); 315 node, socid);
316 return -EINVAL; 316 return -EINVAL;
317 } 317 }
318 } 318 }
319 319
320 if (!nlm_node_present(socid)) { 320 if (!nlm_node_present(socid)) {
321 pr_err("PIC %s: node %d does not exist!\n", node->name, socid); 321 pr_err("PIC %pOFn: node %d does not exist!\n", node, socid);
322 return -EINVAL; 322 return -EINVAL;
323 } 323 }
324 324
@@ -326,7 +326,7 @@ static int __init xlp_of_pic_init(struct device_node *node,
326 nlm_irq_to_xirq(socid, PIC_IRQ_BASE), PIC_IRQ_BASE, 326 nlm_irq_to_xirq(socid, PIC_IRQ_BASE), PIC_IRQ_BASE,
327 &xlp_pic_irq_domain_ops, NULL); 327 &xlp_pic_irq_domain_ops, NULL);
328 if (xlp_pic_domain == NULL) { 328 if (xlp_pic_domain == NULL) {
329 pr_err("PIC %s: Creating legacy domain failed!\n", node->name); 329 pr_err("PIC %pOFn: Creating legacy domain failed!\n", node);
330 return -EINVAL; 330 return -EINVAL;
331 } 331 }
332 pr_info("Node %d: IRQ domain created for PIC@%pR\n", socid, &res); 332 pr_info("Node %d: IRQ domain created for PIC@%pR\n", socid, &res);
diff --git a/arch/mips/pci/ops-loongson3.c b/arch/mips/pci/ops-loongson3.c
index 9e118431e226..2f6ad36bdea6 100644
--- a/arch/mips/pci/ops-loongson3.c
+++ b/arch/mips/pci/ops-loongson3.c
@@ -18,22 +18,36 @@ static int loongson3_pci_config_access(unsigned char access_type,
18 int where, u32 *data) 18 int where, u32 *data)
19{ 19{
20 unsigned char busnum = bus->number; 20 unsigned char busnum = bus->number;
21 u_int64_t addr, type;
22 void *addrp;
23 int device = PCI_SLOT(devfn);
24 int function = PCI_FUNC(devfn); 21 int function = PCI_FUNC(devfn);
22 int device = PCI_SLOT(devfn);
25 int reg = where & ~3; 23 int reg = where & ~3;
24 void *addrp;
25 u64 addr;
26
27 if (where < PCI_CFG_SPACE_SIZE) { /* standard config */
28 addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
29 if (busnum == 0) {
30 if (device > 31)
31 return PCIBIOS_DEVICE_NOT_FOUND;
32 addrp = (void *)TO_UNCAC(HT1LO_PCICFG_BASE | addr);
33 } else {
34 addrp = (void *)TO_UNCAC(HT1LO_PCICFG_BASE_TP1 | addr);
35 }
36 } else if (where < PCI_CFG_SPACE_EXP_SIZE) { /* extended config */
37 struct pci_dev *rootdev;
38
39 rootdev = pci_get_domain_bus_and_slot(0, 0, 0);
40 if (!rootdev)
41 return PCIBIOS_DEVICE_NOT_FOUND;
26 42
27 addr = (busnum << 16) | (device << 11) | (function << 8) | reg; 43 addr = pci_resource_start(rootdev, 3);
28 if (busnum == 0) { 44 if (!addr)
29 if (device > 31)
30 return PCIBIOS_DEVICE_NOT_FOUND; 45 return PCIBIOS_DEVICE_NOT_FOUND;
31 addrp = (void *)(TO_UNCAC(HT1LO_PCICFG_BASE) | (addr & 0xffff));
32 type = 0;
33 46
47 addr |= busnum << 20 | device << 15 | function << 12 | reg;
48 addrp = (void *)TO_UNCAC(addr);
34 } else { 49 } else {
35 addrp = (void *)(TO_UNCAC(HT1LO_PCICFG_BASE_TP1) | (addr)); 50 return PCIBIOS_DEVICE_NOT_FOUND;
36 type = 0x10000;
37 } 51 }
38 52
39 if (access_type == PCI_ACCESS_WRITE) 53 if (access_type == PCI_ACCESS_WRITE)
diff --git a/arch/mips/pci/pci-legacy.c b/arch/mips/pci/pci-legacy.c
index f1e92bf743c2..3c3b1e6abb53 100644
--- a/arch/mips/pci/pci-legacy.c
+++ b/arch/mips/pci/pci-legacy.c
@@ -127,8 +127,12 @@ static void pcibios_scanbus(struct pci_controller *hose)
127 if (pci_has_flag(PCI_PROBE_ONLY)) { 127 if (pci_has_flag(PCI_PROBE_ONLY)) {
128 pci_bus_claim_resources(bus); 128 pci_bus_claim_resources(bus);
129 } else { 129 } else {
130 struct pci_bus *child;
131
130 pci_bus_size_bridges(bus); 132 pci_bus_size_bridges(bus);
131 pci_bus_assign_resources(bus); 133 pci_bus_assign_resources(bus);
134 list_for_each_entry(child, &bus->children, node)
135 pcie_bus_configure_settings(child);
132 } 136 }
133 pci_bus_add_devices(bus); 137 pci_bus_add_devices(bus);
134} 138}
diff --git a/arch/mips/pci/pci-rt2880.c b/arch/mips/pci/pci-rt2880.c
index 711cdccdf65b..f376a1df326a 100644
--- a/arch/mips/pci/pci-rt2880.c
+++ b/arch/mips/pci/pci-rt2880.c
@@ -246,6 +246,8 @@ static int rt288x_pci_probe(struct platform_device *pdev)
246 rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000); 246 rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
247 (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0); 247 (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
248 248
249 rt2880_pci_controller.of_node = pdev->dev.of_node;
250
249 register_pci_controller(&rt2880_pci_controller); 251 register_pci_controller(&rt2880_pci_controller);
250 return 0; 252 return 0;
251} 253}
diff --git a/arch/mips/pmcs-msp71xx/msp_usb.c b/arch/mips/pmcs-msp71xx/msp_usb.c
index c87c5f810cd1..d38ac70b5a2e 100644
--- a/arch/mips/pmcs-msp71xx/msp_usb.c
+++ b/arch/mips/pmcs-msp71xx/msp_usb.c
@@ -133,13 +133,13 @@ static int __init msp_usb_setup(void)
133 * "D" for device-mode. If it works for Ethernet, why not USB... 133 * "D" for device-mode. If it works for Ethernet, why not USB...
134 * -- hammtrev, 2007/03/22 134 * -- hammtrev, 2007/03/22
135 */ 135 */
136 snprintf((char *)&envstr[0], sizeof(envstr), "usbmode"); 136 snprintf(&envstr[0], sizeof(envstr), "usbmode");
137 137
138 /* set default host mode */ 138 /* set default host mode */
139 val = 1; 139 val = 1;
140 140
141 /* get environment string */ 141 /* get environment string */
142 strp = prom_getenv((char *)&envstr[0]); 142 strp = prom_getenv(&envstr[0]);
143 if (strp) { 143 if (strp) {
144 /* compare string */ 144 /* compare string */
145 if (!strcmp(strp, "device")) 145 if (!strcmp(strp, "device"))
diff --git a/arch/mips/ralink/cevt-rt3352.c b/arch/mips/ralink/cevt-rt3352.c
index 92f284d2b802..61a08943eb2f 100644
--- a/arch/mips/ralink/cevt-rt3352.c
+++ b/arch/mips/ralink/cevt-rt3352.c
@@ -134,7 +134,7 @@ static int __init ralink_systick_init(struct device_node *np)
134 systick.dev.min_delta_ticks = 0x3; 134 systick.dev.min_delta_ticks = 0x3;
135 systick.dev.irq = irq_of_parse_and_map(np, 0); 135 systick.dev.irq = irq_of_parse_and_map(np, 0);
136 if (!systick.dev.irq) { 136 if (!systick.dev.irq) {
137 pr_err("%s: request_irq failed", np->name); 137 pr_err("%pOFn: request_irq failed", np);
138 return -EINVAL; 138 return -EINVAL;
139 } 139 }
140 140
@@ -146,8 +146,8 @@ static int __init ralink_systick_init(struct device_node *np)
146 146
147 clockevents_register_device(&systick.dev); 147 clockevents_register_device(&systick.dev);
148 148
149 pr_info("%s: running - mult: %d, shift: %d\n", 149 pr_info("%pOFn: running - mult: %d, shift: %d\n",
150 np->name, systick.dev.mult, systick.dev.shift); 150 np, systick.dev.mult, systick.dev.shift);
151 151
152 return 0; 152 return 0;
153} 153}
diff --git a/arch/mips/ralink/ill_acc.c b/arch/mips/ralink/ill_acc.c
index 765d5ba98fa2..fc056f2acfeb 100644
--- a/arch/mips/ralink/ill_acc.c
+++ b/arch/mips/ralink/ill_acc.c
@@ -62,7 +62,7 @@ static int __init ill_acc_of_setup(void)
62 62
63 pdev = of_find_device_by_node(np); 63 pdev = of_find_device_by_node(np);
64 if (!pdev) { 64 if (!pdev) {
65 pr_err("%s: failed to lookup pdev\n", np->name); 65 pr_err("%pOFn: failed to lookup pdev\n", np);
66 return -EINVAL; 66 return -EINVAL;
67 } 67 }
68 68
diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
index 93d472c60ce4..0f2264e0cf76 100644
--- a/arch/mips/ralink/rt305x.c
+++ b/arch/mips/ralink/rt305x.c
@@ -49,6 +49,10 @@ static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
49static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) }; 49static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
50static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) }; 50static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
51static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) }; 51static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
52static struct rt2880_pmx_func rt3352_cs1_func[] = {
53 FUNC("spi_cs1", 0, 45, 1),
54 FUNC("wdg_cs1", 1, 45, 1),
55};
52 56
53static struct rt2880_pmx_group rt3050_pinmux_data[] = { 57static struct rt2880_pmx_group rt3050_pinmux_data[] = {
54 GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), 58 GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
@@ -75,6 +79,7 @@ static struct rt2880_pmx_group rt3352_pinmux_data[] = {
75 GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA), 79 GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
76 GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA), 80 GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
77 GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED), 81 GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
82 GRP("spi_cs1", rt3352_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1),
78 { 0 } 83 { 0 }
79}; 84};
80 85
diff --git a/arch/mips/sgi-ip22/ip28-berr.c b/arch/mips/sgi-ip22/ip28-berr.c
index 2ed8e4990b7a..082541d33161 100644
--- a/arch/mips/sgi-ip22/ip28-berr.c
+++ b/arch/mips/sgi-ip22/ip28-berr.c
@@ -464,7 +464,7 @@ void ip22_be_interrupt(int irq)
464 die_if_kernel("Oops", regs); 464 die_if_kernel("Oops", regs);
465 force_sig(SIGBUS, current); 465 force_sig(SIGBUS, current);
466 } else if (debug_be_interrupt) 466 } else if (debug_be_interrupt)
467 show_regs((struct pt_regs *)regs); 467 show_regs(regs);
468} 468}
469 469
470static int ip28_be_handler(struct pt_regs *regs, int is_fixup) 470static int ip28_be_handler(struct pt_regs *regs, int is_fixup)
diff --git a/arch/mips/sgi-ip27/ip27-memory.c b/arch/mips/sgi-ip27/ip27-memory.c
index 59133d0abc83..6f7bef052b7f 100644
--- a/arch/mips/sgi-ip27/ip27-memory.c
+++ b/arch/mips/sgi-ip27/ip27-memory.c
@@ -389,7 +389,6 @@ static void __init node_mem_init(cnodeid_t node)
389{ 389{
390 unsigned long slot_firstpfn = slot_getbasepfn(node, 0); 390 unsigned long slot_firstpfn = slot_getbasepfn(node, 0);
391 unsigned long slot_freepfn = node_getfirstfree(node); 391 unsigned long slot_freepfn = node_getfirstfree(node);
392 unsigned long bootmap_size;
393 unsigned long start_pfn, end_pfn; 392 unsigned long start_pfn, end_pfn;
394 393
395 get_pfn_range_for_nid(node, &start_pfn, &end_pfn); 394 get_pfn_range_for_nid(node, &start_pfn, &end_pfn);
@@ -400,7 +399,6 @@ static void __init node_mem_init(cnodeid_t node)
400 __node_data[node] = __va(slot_freepfn << PAGE_SHIFT); 399 __node_data[node] = __va(slot_freepfn << PAGE_SHIFT);
401 memset(__node_data[node], 0, PAGE_SIZE); 400 memset(__node_data[node], 0, PAGE_SIZE);
402 401
403 NODE_DATA(node)->bdata = &bootmem_node_data[node];
404 NODE_DATA(node)->node_start_pfn = start_pfn; 402 NODE_DATA(node)->node_start_pfn = start_pfn;
405 NODE_DATA(node)->node_spanned_pages = end_pfn - start_pfn; 403 NODE_DATA(node)->node_spanned_pages = end_pfn - start_pfn;
406 404
@@ -409,12 +407,11 @@ static void __init node_mem_init(cnodeid_t node)
409 slot_freepfn += PFN_UP(sizeof(struct pglist_data) + 407 slot_freepfn += PFN_UP(sizeof(struct pglist_data) +
410 sizeof(struct hub_data)); 408 sizeof(struct hub_data));
411 409
412 bootmap_size = init_bootmem_node(NODE_DATA(node), slot_freepfn,
413 start_pfn, end_pfn);
414 free_bootmem_with_active_regions(node, end_pfn); 410 free_bootmem_with_active_regions(node, end_pfn);
415 reserve_bootmem_node(NODE_DATA(node), slot_firstpfn << PAGE_SHIFT, 411
416 ((slot_freepfn - slot_firstpfn) << PAGE_SHIFT) + bootmap_size, 412 memblock_reserve(slot_firstpfn << PAGE_SHIFT,
417 BOOTMEM_DEFAULT); 413 ((slot_freepfn - slot_firstpfn) << PAGE_SHIFT));
414
418 sparse_memory_present_with_active_regions(node); 415 sparse_memory_present_with_active_regions(node);
419} 416}
420 417
diff --git a/arch/mips/tools/.gitignore b/arch/mips/tools/.gitignore
new file mode 100644
index 000000000000..56d34ccccce4
--- /dev/null
+++ b/arch/mips/tools/.gitignore
@@ -0,0 +1 @@
elf-entry
diff --git a/arch/mips/tools/Makefile b/arch/mips/tools/Makefile
new file mode 100644
index 000000000000..3baee4bc6775
--- /dev/null
+++ b/arch/mips/tools/Makefile
@@ -0,0 +1,5 @@
1# SPDX-License-Identifier: GPL-2.0
2hostprogs-y := elf-entry
3PHONY += elf-entry
4elf-entry: $(obj)/elf-entry
5 @:
diff --git a/arch/mips/tools/elf-entry.c b/arch/mips/tools/elf-entry.c
new file mode 100644
index 000000000000..adde79ce7fc0
--- /dev/null
+++ b/arch/mips/tools/elf-entry.c
@@ -0,0 +1,96 @@
1// SPDX-License-Identifier: GPL-2.0
2#include <byteswap.h>
3#include <elf.h>
4#include <endian.h>
5#include <inttypes.h>
6#include <stdint.h>
7#include <stdio.h>
8#include <stdlib.h>
9#include <string.h>
10
11#ifdef be32toh
12/* If libc provides [bl]e{32,64}toh() then we'll use them */
13#elif BYTE_ORDER == LITTLE_ENDIAN
14# define be32toh(x) bswap_32(x)
15# define le32toh(x) (x)
16# define be64toh(x) bswap_64(x)
17# define le64toh(x) (x)
18#elif BYTE_ORDER == BIG_ENDIAN
19# define be32toh(x) (x)
20# define le32toh(x) bswap_32(x)
21# define be64toh(x) (x)
22# define le64toh(x) bswap_64(x)
23#endif
24
25__attribute__((noreturn))
26static void die(const char *msg)
27{
28 fputs(msg, stderr);
29 exit(EXIT_FAILURE);
30}
31
32int main(int argc, const char *argv[])
33{
34 uint64_t entry;
35 size_t nread;
36 FILE *file;
37 union {
38 Elf32_Ehdr ehdr32;
39 Elf64_Ehdr ehdr64;
40 } hdr;
41
42 if (argc != 2)
43 die("Usage: elf-entry <elf-file>\n");
44
45 file = fopen(argv[1], "r");
46 if (!file) {
47 perror("Unable to open input file");
48 return EXIT_FAILURE;
49 }
50
51 nread = fread(&hdr, 1, sizeof(hdr), file);
52 if (nread != sizeof(hdr)) {
53 perror("Unable to read input file");
54 return EXIT_FAILURE;
55 }
56
57 if (memcmp(hdr.ehdr32.e_ident, ELFMAG, SELFMAG))
58 die("Input is not an ELF\n");
59
60 switch (hdr.ehdr32.e_ident[EI_CLASS]) {
61 case ELFCLASS32:
62 switch (hdr.ehdr32.e_ident[EI_DATA]) {
63 case ELFDATA2LSB:
64 entry = le32toh(hdr.ehdr32.e_entry);
65 break;
66 case ELFDATA2MSB:
67 entry = be32toh(hdr.ehdr32.e_entry);
68 break;
69 default:
70 die("Invalid ELF encoding\n");
71 }
72
73 /* Sign extend to form a canonical address */
74 entry = (int64_t)(int32_t)entry;
75 break;
76
77 case ELFCLASS64:
78 switch (hdr.ehdr32.e_ident[EI_DATA]) {
79 case ELFDATA2LSB:
80 entry = le64toh(hdr.ehdr64.e_entry);
81 break;
82 case ELFDATA2MSB:
83 entry = be64toh(hdr.ehdr64.e_entry);
84 break;
85 default:
86 die("Invalid ELF encoding\n");
87 }
88 break;
89
90 default:
91 die("Invalid ELF class\n");
92 }
93
94 printf("0x%016" PRIx64 "\n", entry);
95 return EXIT_SUCCESS;
96}
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index f6d9182ef82a..70a1ab66d252 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -960,12 +960,11 @@ void __init txx9_sramc_init(struct resource *r)
960 goto exit_put; 960 goto exit_put;
961 err = sysfs_create_bin_file(&dev->dev.kobj, &dev->bindata_attr); 961 err = sysfs_create_bin_file(&dev->dev.kobj, &dev->bindata_attr);
962 if (err) { 962 if (err) {
963 device_unregister(&dev->dev);
964 iounmap(dev->base); 963 iounmap(dev->base);
965 kfree(dev); 964 device_unregister(&dev->dev);
966 } 965 }
967 return; 966 return;
968exit_put: 967exit_put:
968 iounmap(dev->base);
969 put_device(&dev->dev); 969 put_device(&dev->dev);
970 return;
971} 970}
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-03 09:13:36 -0400