5 files changed, 92 insertions, 40 deletions

diff --git a/drivers/gpu/drm/arm/malidp_drv.c b/drivers/gpu/drm/arm/malidp_drv.c
index d53b625b14fe..ebf90c794eab 100644
--- a/drivers/gpu/drm/arm/malidp_drv.c
+++ b/drivers/gpu/drm/arm/malidp_drv.c
@@ -42,6 +42,7 @@ static int malidp_set_and_wait_config_valid(struct drm_device *drm)
         struct malidp_hw_device *hwdev = malidp->dev;
         int ret;
 
+        atomic_set(&malidp->config_valid, 0);
         hwdev->set_config_valid(hwdev);
         /* don't wait for config_valid flag if we are in config mode */
         if (hwdev->in_config_mode(hwdev))
@@ -91,8 +92,7 @@ static void malidp_atomic_commit_tail(struct drm_atomic_state *state)
 
         drm_atomic_helper_commit_modeset_disables(drm, state);
         drm_atomic_helper_commit_modeset_enables(drm, state);
-        drm_atomic_helper_commit_planes(drm, state,
-                                        DRM_PLANE_COMMIT_ACTIVE_ONLY);
+        drm_atomic_helper_commit_planes(drm, state, 0);
 
         malidp_atomic_commit_hw_done(state);
 
@@ -155,6 +155,12 @@ static int malidp_init(struct drm_device *drm)
         return 0;
 }
 
+static void malidp_fini(struct drm_device *drm)
+{
+        malidp_de_planes_destroy(drm);
+        drm_mode_config_cleanup(drm);
+}
+
 static int malidp_irq_init(struct platform_device *pdev)
 {
         int irq_de, irq_se, ret = 0;
@@ -375,6 +381,8 @@ static int malidp_bind(struct device *dev)
         if (ret < 0)
                 goto irq_init_fail;
 
+        drm->irq_enabled = true;
+
         ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
         if (ret < 0) {
                 DRM_ERROR("failed to initialise vblank\n");
@@ -400,6 +408,7 @@ fbdev_fail:
 vblank_fail:
         malidp_se_irq_fini(drm);
         malidp_de_irq_fini(drm);
+        drm->irq_enabled = false;
 irq_init_fail:
         component_unbind_all(dev, drm);
 bind_fail:
@@ -408,8 +417,7 @@ bind_fail:
 port_fail:
         drm_dev_unregister(drm);
 register_fail:
-        malidp_de_planes_destroy(drm);
-        drm_mode_config_cleanup(drm);
+        malidp_fini(drm);
 init_fail:
         drm->dev_private = NULL;
         dev_set_drvdata(dev, NULL);
@@ -442,8 +450,7 @@ static void malidp_unbind(struct device *dev)
         of_node_put(malidp->crtc.port);
         malidp->crtc.port = NULL;
         drm_dev_unregister(drm);
-        malidp_de_planes_destroy(drm);
-        drm_mode_config_cleanup(drm);
+        malidp_fini(drm);
         drm->dev_private = NULL;
         dev_set_drvdata(dev, NULL);
         clk_disable_unprepare(hwdev->mclk);
diff --git a/drivers/gpu/drm/arm/malidp_drv.h b/drivers/gpu/drm/arm/malidp_drv.h
index 271d2fb9711c..9fc8a2e405e4 100644
--- a/drivers/gpu/drm/arm/malidp_drv.h
+++ b/drivers/gpu/drm/arm/malidp_drv.h
@@ -39,6 +39,9 @@ struct malidp_plane_state {
 
         /* size of the required rotation memory if plane is rotated */
         u32 rotmem_size;
+        /* internal format ID */
+        u8 format;
+        u8 n_planes;
 };
 
 #define to_malidp_plane(x) container_of(x, struct malidp_plane, base)
diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c
index be815d0cc772..4bdf531f7844 100644
--- a/drivers/gpu/drm/arm/malidp_hw.c
+++ b/drivers/gpu/drm/arm/malidp_hw.c
@@ -125,6 +125,7 @@ static void malidp500_leave_config_mode(struct malidp_hw_device *hwdev)
 {
         u32 status, count = 100;
 
+        malidp_hw_clearbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID);
         malidp_hw_clearbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL);
         while (count) {
                 status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
@@ -266,6 +267,7 @@ static void malidp550_leave_config_mode(struct malidp_hw_device *hwdev)
 {
         u32 status, count = 100;
 
+        malidp_hw_clearbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID);
         malidp_hw_clearbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL);
         while (count) {
                 status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);
@@ -436,6 +438,7 @@ const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES] = {
                         },
                         .input_formats = malidp500_de_formats,
                         .n_input_formats = ARRAY_SIZE(malidp500_de_formats),
+                        .bus_align_bytes = 8,
                 },
                 .query_hw = malidp500_query_hw,
                 .enter_config_mode = malidp500_enter_config_mode,
@@ -468,6 +471,7 @@ const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES] = {
                         },
                         .input_formats = malidp550_de_formats,
                         .n_input_formats = ARRAY_SIZE(malidp550_de_formats),
+                        .bus_align_bytes = 8,
                 },
                 .query_hw = malidp550_query_hw,
                 .enter_config_mode = malidp550_enter_config_mode,
@@ -501,6 +505,7 @@ const struct malidp_hw_device malidp_device[MALIDP_MAX_DEVICES] = {
                         },
                         .input_formats = malidp550_de_formats,
                         .n_input_formats = ARRAY_SIZE(malidp550_de_formats),
+                        .bus_align_bytes = 16,
                 },
                 .query_hw = malidp650_query_hw,
                 .enter_config_mode = malidp550_enter_config_mode,
diff --git a/drivers/gpu/drm/arm/malidp_hw.h b/drivers/gpu/drm/arm/malidp_hw.h
index 141743e9f3a6..087e1202db3d 100644
--- a/drivers/gpu/drm/arm/malidp_hw.h
+++ b/drivers/gpu/drm/arm/malidp_hw.h
@@ -88,6 +88,9 @@ struct malidp_hw_regmap {
         /* list of supported input formats for each layer */
         const struct malidp_input_format *input_formats;
         const u8 n_input_formats;
+
+        /* pitch alignment requirement in bytes */
+        const u8 bus_align_bytes;
 };
 
 struct malidp_hw_device {
@@ -229,6 +232,12 @@ void malidp_se_irq_fini(struct drm_device *drm);
 u8 malidp_hw_get_format_id(const struct malidp_hw_regmap *map,
                            u8 layer_id, u32 format);
 
+static inline bool malidp_hw_pitch_valid(struct malidp_hw_device *hwdev,
+                                         unsigned int pitch)
+{
+        return !(pitch & (hwdev->map.bus_align_bytes - 1));
+}
+
 /*
  * background color components are defined as 12bits values,
  * they will be shifted right when stored on hardware that
diff --git a/drivers/gpu/drm/arm/malidp_planes.c b/drivers/gpu/drm/arm/malidp_planes.c
index abaca03b9d36..63eec8f37cfc 100644
--- a/drivers/gpu/drm/arm/malidp_planes.c
+++ b/drivers/gpu/drm/arm/malidp_planes.c
@@ -27,6 +27,10 @@
 #define   LAYER_H_FLIP                  (1 << 10)
 #define   LAYER_V_FLIP                  (1 << 11)
 #define   LAYER_ROT_MASK                (0xf << 8)
+#define   LAYER_COMP_MASK               (0x3 << 12)
+#define   LAYER_COMP_PIXEL              (0x3 << 12)
+#define   LAYER_COMP_PLANE              (0x2 << 12)
+#define MALIDP_LAYER_COMPOSE            0x008
 #define MALIDP_LAYER_SIZE               0x00c
 #define   LAYER_H_VAL(x)                (((x) & 0x1fff) << 0)
 #define   LAYER_V_VAL(x)                (((x) & 0x1fff) << 16)
@@ -34,6 +38,14 @@
 #define MALIDP_LAYER_OFFSET             0x014
 #define MALIDP_LAYER_STRIDE             0x018
 
+/*
+ * This 4-entry look-up-table is used to determine the full 8-bit alpha value
+ * for formats with 1- or 2-bit alpha channels.
+ * We set it to give 100%/0% opacity for 1-bit formats and 100%/66%/33%/0%
+ * opacity for 2-bit formats.
+ */
+#define MALIDP_ALPHA_LUT 0xffaa5500
+
 static void malidp_de_plane_destroy(struct drm_plane *plane)
 {
         struct malidp_plane *mp = to_malidp_plane(plane);
@@ -46,7 +58,8 @@ static void malidp_de_plane_destroy(struct drm_plane *plane)
         devm_kfree(plane->dev->dev, mp);
 }
 
-struct drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane)
+static struct
+drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane)
 {
         struct malidp_plane_state *state, *m_state;
 
@@ -58,13 +71,15 @@ struct drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane)
                 m_state = to_malidp_plane_state(plane->state);
                 __drm_atomic_helper_plane_duplicate_state(plane, &state->base);
                 state->rotmem_size = m_state->rotmem_size;
+                state->format = m_state->format;
+                state->n_planes = m_state->n_planes;
         }
 
         return &state->base;
 }
 
-void malidp_destroy_plane_state(struct drm_plane *plane,
-                                struct drm_plane_state *state)
+static void malidp_destroy_plane_state(struct drm_plane *plane,
+                                       struct drm_plane_state *state)
 {
         struct malidp_plane_state *m_state = to_malidp_plane_state(state);
 
@@ -75,6 +90,7 @@ void malidp_destroy_plane_state(struct drm_plane *plane,
 static const struct drm_plane_funcs malidp_de_plane_funcs = {
         .update_plane = drm_atomic_helper_update_plane,
         .disable_plane = drm_atomic_helper_disable_plane,
+        .set_property = drm_atomic_helper_plane_set_property,
         .destroy = malidp_de_plane_destroy,
         .reset = drm_atomic_helper_plane_reset,
         .atomic_duplicate_state = malidp_duplicate_plane_state,
@@ -86,17 +102,29 @@ static int malidp_de_plane_check(struct drm_plane *plane,
 {
         struct malidp_plane *mp = to_malidp_plane(plane);
         struct malidp_plane_state *ms = to_malidp_plane_state(state);
-        u8 format_id;
+        struct drm_framebuffer *fb;
+        int i;
         u32 src_w, src_h;
 
         if (!state->crtc || !state->fb)
                 return 0;
 
-        format_id = malidp_hw_get_format_id(&mp->hwdev->map, mp->layer->id,
-                                            state->fb->pixel_format);
-        if (format_id == MALIDP_INVALID_FORMAT_ID)
+        fb = state->fb;
+
+        ms->format = malidp_hw_get_format_id(&mp->hwdev->map, mp->layer->id,
+                                            fb->pixel_format);
+        if (ms->format == MALIDP_INVALID_FORMAT_ID)
                 return -EINVAL;
 
+        ms->n_planes = drm_format_num_planes(fb->pixel_format);
+        for (i = 0; i < ms->n_planes; i++) {
+                if (!malidp_hw_pitch_valid(mp->hwdev, fb->pitches[i])) {
+                        DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n",
+                                      fb->pitches[i], i);
+                        return -EINVAL;
+                }
+        }
+
         src_w = state->src_w >> 16;
         src_h = state->src_h >> 16;
 
@@ -135,17 +163,13 @@ static void malidp_de_plane_update(struct drm_plane *plane,
         struct drm_gem_cma_object *obj;
         struct malidp_plane *mp;
         const struct malidp_hw_regmap *map;
-        u8 format_id;
+        struct malidp_plane_state *ms = to_malidp_plane_state(plane->state);
         u16 ptr;
-        u32 format, src_w, src_h, dest_w, dest_h, val = 0;
-        int num_planes, i;
+        u32 src_w, src_h, dest_w, dest_h, val;
+        int i;
 
         mp = to_malidp_plane(plane);
-
         map = &mp->hwdev->map;
-        format = plane->state->fb->pixel_format;
-        format_id = malidp_hw_get_format_id(map, mp->layer->id, format);
-        num_planes = drm_format_num_planes(format);
 
         /* convert src values from Q16 fixed point to integer */
         src_w = plane->state->src_w >> 16;
@@ -158,9 +182,9 @@ static void malidp_de_plane_update(struct drm_plane *plane,
                 dest_h = plane->state->crtc_h;
         }
 
-        malidp_hw_write(mp->hwdev, format_id, mp->layer->base);
+        malidp_hw_write(mp->hwdev, ms->format, mp->layer->base);
 
-        for (i = 0; i < num_planes; i++) {
+        for (i = 0; i < ms->n_planes; i++) {
                 /* calculate the offset for the layer's plane registers */
                 ptr = mp->layer->ptr + (i << 4);
 
@@ -181,9 +205,9 @@ static void malidp_de_plane_update(struct drm_plane *plane,
                         LAYER_V_VAL(plane->state->crtc_y),
                         mp->layer->base + MALIDP_LAYER_OFFSET);
 
-        /* first clear the rotation bits in the register */
-        malidp_hw_clearbits(mp->hwdev, LAYER_ROT_MASK,
-                            mp->layer->base + MALIDP_LAYER_CONTROL);
+        /* first clear the rotation bits */
+        val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL);
+        val &= ~LAYER_ROT_MASK;
 
         /* setup the rotation and axis flip bits */
         if (plane->state->rotation & DRM_ROTATE_MASK)
@@ -193,11 +217,18 @@ static void malidp_de_plane_update(struct drm_plane *plane,
         if (plane->state->rotation & DRM_REFLECT_Y)
                 val |= LAYER_H_FLIP;
 
+        /*
+         * always enable pixel alpha blending until we have a way to change
+         * blend modes
+         */
+        val &= ~LAYER_COMP_MASK;
+        val |= LAYER_COMP_PIXEL;
+
         /* set the 'enable layer' bit */
         val |= LAYER_ENABLE;
 
-        malidp_hw_setbits(mp->hwdev, val,
-                          mp->layer->base + MALIDP_LAYER_CONTROL);
+        malidp_hw_write(mp->hwdev, val,
+                        mp->layer->base + MALIDP_LAYER_CONTROL);
 }
 
 static void malidp_de_plane_disable(struct drm_plane *plane,
@@ -222,6 +253,8 @@ int malidp_de_planes_init(struct drm_device *drm)
         struct malidp_plane *plane = NULL;
         enum drm_plane_type plane_type;
         unsigned long crtcs = 1 << drm->mode_config.num_crtc;
+        unsigned long flags = DRM_ROTATE_0 | DRM_ROTATE_90 | DRM_ROTATE_180 |
+                              DRM_ROTATE_270 | DRM_REFLECT_X | DRM_REFLECT_Y;
         u32 *formats;
         int ret, i, j, n;
 
@@ -254,23 +287,18 @@ int malidp_de_planes_init(struct drm_device *drm)
                 if (ret < 0)
                         goto cleanup;
 
-                /* SMART layer can't be rotated */
-                if (id != DE_SMART) {
-                        unsigned long flags = DRM_ROTATE_0 |
-                                              DRM_ROTATE_90 |
-                                              DRM_ROTATE_180 |
-                                              DRM_ROTATE_270 |
-                                              DRM_REFLECT_X |
-                                              DRM_REFLECT_Y;
-                        drm_plane_create_rotation_property(&plane->base,
-                                                           DRM_ROTATE_0,
-                                                           flags);
-                }
-
                 drm_plane_helper_add(&plane->base,
                                      &malidp_de_plane_helper_funcs);
                 plane->hwdev = malidp->dev;
                 plane->layer = &map->layers[i];
+
+                /* Skip the features which the SMART layer doesn't have */
+                if (id == DE_SMART)
+                        continue;
+
+                drm_plane_create_rotation_property(&plane->base, DRM_ROTATE_0, flags);
+                malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT,
+                                plane->layer->base + MALIDP_LAYER_COMPOSE);
         }
 
         kfree(formats);