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-rw-r--r--arch/arm/mach-omap2/pm34xx.c71
-rw-r--r--arch/arm/mach-omap2/prm3xxx.c90
-rw-r--r--arch/arm/mach-omap2/prm3xxx.h1
3 files changed, 92 insertions, 70 deletions
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index acb895deb3cc..3ea04ac10d16 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -376,79 +376,10 @@ static void __init omap3_d2d_idle(void)
376 376
377static void __init prcm_setup_regs(void) 377static void __init prcm_setup_regs(void)
378{ 378{
379 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
380 OMAP3630_EN_UART4_MASK : 0;
381 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
382 OMAP3630_GRPSEL_UART4_MASK : 0;
383
384 /* XXX This should be handled by hwmod code or SCM init code */ 379 /* XXX This should be handled by hwmod code or SCM init code */
385 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 380 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
386 381
387 /* 382 omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva());
388 * Enable control of expternal oscillator through
389 * sys_clkreq. In the long run clock framework should
390 * take care of this.
391 */
392 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
393 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
394 OMAP3430_GR_MOD,
395 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
396
397 /* setup wakup source */
398 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
399 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
400 WKUP_MOD, PM_WKEN);
401 /* No need to write EN_IO, that is always enabled */
402 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
403 OMAP3430_GRPSEL_GPT1_MASK |
404 OMAP3430_GRPSEL_GPT12_MASK,
405 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
406
407 /* Enable PM_WKEN to support DSS LPR */
408 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
409 OMAP3430_DSS_MOD, PM_WKEN);
410
411 /* Enable wakeups in PER */
412 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
413 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
414 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
415 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
416 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
417 OMAP3430_EN_MCBSP4_MASK,
418 OMAP3430_PER_MOD, PM_WKEN);
419 /* and allow them to wake up MPU */
420 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
421 OMAP3430_GRPSEL_GPIO2_MASK |
422 OMAP3430_GRPSEL_GPIO3_MASK |
423 OMAP3430_GRPSEL_GPIO4_MASK |
424 OMAP3430_GRPSEL_GPIO5_MASK |
425 OMAP3430_GRPSEL_GPIO6_MASK |
426 OMAP3430_GRPSEL_UART3_MASK |
427 OMAP3430_GRPSEL_MCBSP2_MASK |
428 OMAP3430_GRPSEL_MCBSP3_MASK |
429 OMAP3430_GRPSEL_MCBSP4_MASK,
430 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
431
432 /* Don't attach IVA interrupts */
433 if (omap3_has_iva()) {
434 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
435 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
436 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
437 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
438 OMAP3430_PM_IVAGRPSEL);
439 }
440
441 /* Clear any pending 'reset' flags */
442 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
443 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
444 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
445 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
446 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
447 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
448 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
449
450 /* Clear any pending PRCM interrupts */
451 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
452 383
453 /* 384 /*
454 * We need to idle iva2_pwrdm even on am3703 with no iva2. 385 * We need to idle iva2_pwrdm even on am3703 with no iva2.
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 4d93b844bcc4..48218a450cb0 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -275,6 +275,96 @@ void __init omap3_prm_reset_modem(void)
275} 275}
276 276
277/** 277/**
278 * omap3_prm_init_pm - initialize PM related registers for PRM
279 * @has_uart4: SoC has UART4
280 * @has_iva: SoC has IVA
281 *
282 * Initializes PRM registers for PM use. Called from PM init.
283 */
284void __init omap3_prm_init_pm(bool has_uart4, bool has_iva)
285{
286 u32 en_uart4_mask;
287 u32 grpsel_uart4_mask;
288
289 /*
290 * Enable control of expternal oscillator through
291 * sys_clkreq. In the long run clock framework should
292 * take care of this.
293 */
294 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
295 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
296 OMAP3430_GR_MOD,
297 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
298
299 /* setup wakup source */
300 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
301 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
302 WKUP_MOD, PM_WKEN);
303 /* No need to write EN_IO, that is always enabled */
304 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
305 OMAP3430_GRPSEL_GPT1_MASK |
306 OMAP3430_GRPSEL_GPT12_MASK,
307 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
308
309 /* Enable PM_WKEN to support DSS LPR */
310 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
311 OMAP3430_DSS_MOD, PM_WKEN);
312
313 if (has_uart4) {
314 en_uart4_mask = OMAP3630_EN_UART4_MASK;
315 grpsel_uart4_mask = OMAP3630_GRPSEL_UART4_MASK;
316 }
317
318 /* Enable wakeups in PER */
319 omap2_prm_write_mod_reg(en_uart4_mask |
320 OMAP3430_EN_GPIO2_MASK |
321 OMAP3430_EN_GPIO3_MASK |
322 OMAP3430_EN_GPIO4_MASK |
323 OMAP3430_EN_GPIO5_MASK |
324 OMAP3430_EN_GPIO6_MASK |
325 OMAP3430_EN_UART3_MASK |
326 OMAP3430_EN_MCBSP2_MASK |
327 OMAP3430_EN_MCBSP3_MASK |
328 OMAP3430_EN_MCBSP4_MASK,
329 OMAP3430_PER_MOD, PM_WKEN);
330
331 /* and allow them to wake up MPU */
332 omap2_prm_write_mod_reg(grpsel_uart4_mask |
333 OMAP3430_GRPSEL_GPIO2_MASK |
334 OMAP3430_GRPSEL_GPIO3_MASK |
335 OMAP3430_GRPSEL_GPIO4_MASK |
336 OMAP3430_GRPSEL_GPIO5_MASK |
337 OMAP3430_GRPSEL_GPIO6_MASK |
338 OMAP3430_GRPSEL_UART3_MASK |
339 OMAP3430_GRPSEL_MCBSP2_MASK |
340 OMAP3430_GRPSEL_MCBSP3_MASK |
341 OMAP3430_GRPSEL_MCBSP4_MASK,
342 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
343
344 /* Don't attach IVA interrupts */
345 if (has_iva) {
346 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
347 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
348 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
349 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
350 OMAP3430_PM_IVAGRPSEL);
351 }
352
353 /* Clear any pending 'reset' flags */
354 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
355 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
356 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
357 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
358 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
359 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
360 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD,
361 OMAP2_RM_RSTST);
362
363 /* Clear any pending PRCM interrupts */
364 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
365}
366
367/**
278 * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain 368 * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
279 * 369 *
280 * Clear any previously-latched I/O wakeup events and ensure that the 370 * Clear any previously-latched I/O wakeup events and ensure that the
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index c5f9cbabb5bb..bc37d42a8704 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -167,6 +167,7 @@ void omap3xxx_prm_iva_idle(void);
167void omap3_prm_reset_modem(void); 167void omap3_prm_reset_modem(void);
168int omap3xxx_prm_clear_global_cold_reset(void); 168int omap3xxx_prm_clear_global_cold_reset(void);
169void omap3_prm_save_scratchpad_contents(u32 *ptr); 169void omap3_prm_save_scratchpad_contents(u32 *ptr);
170void omap3_prm_init_pm(bool has_uart4, bool has_iva);
170 171
171#endif /* __ASSEMBLER */ 172#endif /* __ASSEMBLER */
172 173
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-21 06:42:31 -0500