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-rw-r--r--drivers/pinctrl/meson/pinctrl-meson.c2
-rw-r--r--drivers/pinctrl/pinctrl-amd.c19
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos.c91
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos.h31
4 files changed, 90 insertions, 53 deletions
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index a579126832af..620c231a2889 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -212,7 +212,7 @@ static int meson_pmx_request_gpio(struct pinctrl_dev *pcdev,
212{ 212{
213 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 213 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
214 214
215 meson_pmx_disable_other_groups(pc, range->pin_base + offset, -1); 215 meson_pmx_disable_other_groups(pc, offset, -1);
216 216
217 return 0; 217 return 0;
218} 218}
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index aea310a91821..c9a146948192 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -382,26 +382,21 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
382{ 382{
383 int ret = 0; 383 int ret = 0;
384 u32 pin_reg; 384 u32 pin_reg;
385 unsigned long flags; 385 unsigned long flags, irq_flags;
386 bool level_trig;
387 u32 active_level;
388 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 386 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
389 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 387 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
390 388
391 spin_lock_irqsave(&gpio_dev->lock, flags); 389 spin_lock_irqsave(&gpio_dev->lock, flags);
392 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 390 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
393 391
394 /* 392 /* Ignore the settings coming from the client and
395 * When level_trig is set EDGE and active_level is set HIGH in BIOS 393 * read the values from the ACPI tables
396 * default settings, ignore incoming settings from client and use 394 * while setting the trigger type
397 * BIOS settings to configure GPIO register.
398 */ 395 */
399 level_trig = !(pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF));
400 active_level = pin_reg & (ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
401 396
402 if(level_trig && 397 irq_flags = irq_get_trigger_type(d->irq);
403 ((active_level >> ACTIVE_LEVEL_OFF) == ACTIVE_HIGH)) 398 if (irq_flags != IRQ_TYPE_NONE)
404 type = IRQ_TYPE_EDGE_FALLING; 399 type = irq_flags;
405 400
406 switch (type & IRQ_TYPE_SENSE_MASK) { 401 switch (type & IRQ_TYPE_SENSE_MASK) {
407 case IRQ_TYPE_EDGE_RISING: 402 case IRQ_TYPE_EDGE_RISING:
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 12f7d1eb65bc..07409fde02b2 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -56,6 +56,17 @@ static const struct samsung_pin_bank_type bank_type_alive = {
56 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 56 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
57}; 57};
58 58
59/* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */
60static const struct samsung_pin_bank_type exynos5433_bank_type_off = {
61 .fld_width = { 4, 1, 2, 4, 2, 2, },
62 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
63};
64
65static const struct samsung_pin_bank_type exynos5433_bank_type_alive = {
66 .fld_width = { 4, 1, 2, 4, },
67 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
68};
69
59static void exynos_irq_mask(struct irq_data *irqd) 70static void exynos_irq_mask(struct irq_data *irqd)
60{ 71{
61 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 72 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
@@ -1335,82 +1346,82 @@ const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
1335 1346
1336/* pin banks of exynos5433 pin-controller - ALIVE */ 1347/* pin banks of exynos5433 pin-controller - ALIVE */
1337static const struct samsung_pin_bank_data exynos5433_pin_banks0[] = { 1348static const struct samsung_pin_bank_data exynos5433_pin_banks0[] = {
1338 EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 1349 EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
1339 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 1350 EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
1340 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 1351 EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
1341 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), 1352 EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
1342 EXYNOS_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1), 1353 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1),
1343 EXYNOS_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1), 1354 EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1),
1344 EXYNOS_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1), 1355 EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1),
1345 EXYNOS_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1), 1356 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1),
1346 EXYNOS_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1), 1357 EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1),
1347}; 1358};
1348 1359
1349/* pin banks of exynos5433 pin-controller - AUD */ 1360/* pin banks of exynos5433 pin-controller - AUD */
1350static const struct samsung_pin_bank_data exynos5433_pin_banks1[] = { 1361static const struct samsung_pin_bank_data exynos5433_pin_banks1[] = {
1351 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 1362 EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1352 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 1363 EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1353}; 1364};
1354 1365
1355/* pin banks of exynos5433 pin-controller - CPIF */ 1366/* pin banks of exynos5433 pin-controller - CPIF */
1356static const struct samsung_pin_bank_data exynos5433_pin_banks2[] = { 1367static const struct samsung_pin_bank_data exynos5433_pin_banks2[] = {
1357 EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00), 1368 EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),
1358}; 1369};
1359 1370
1360/* pin banks of exynos5433 pin-controller - eSE */ 1371/* pin banks of exynos5433 pin-controller - eSE */
1361static const struct samsung_pin_bank_data exynos5433_pin_banks3[] = { 1372static const struct samsung_pin_bank_data exynos5433_pin_banks3[] = {
1362 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00), 1373 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),
1363}; 1374};
1364 1375
1365/* pin banks of exynos5433 pin-controller - FINGER */ 1376/* pin banks of exynos5433 pin-controller - FINGER */
1366static const struct samsung_pin_bank_data exynos5433_pin_banks4[] = { 1377static const struct samsung_pin_bank_data exynos5433_pin_banks4[] = {
1367 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00), 1378 EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),
1368}; 1379};
1369 1380
1370/* pin banks of exynos5433 pin-controller - FSYS */ 1381/* pin banks of exynos5433 pin-controller - FSYS */
1371static const struct samsung_pin_bank_data exynos5433_pin_banks5[] = { 1382static const struct samsung_pin_bank_data exynos5433_pin_banks5[] = {
1372 EXYNOS_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00), 1383 EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),
1373 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04), 1384 EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),
1374 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08), 1385 EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),
1375 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c), 1386 EXYNOS5433_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c),
1376 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10), 1387 EXYNOS5433_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10),
1377 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14), 1388 EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14),
1378}; 1389};
1379 1390
1380/* pin banks of exynos5433 pin-controller - IMEM */ 1391/* pin banks of exynos5433 pin-controller - IMEM */
1381static const struct samsung_pin_bank_data exynos5433_pin_banks6[] = { 1392static const struct samsung_pin_bank_data exynos5433_pin_banks6[] = {
1382 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00), 1393 EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),
1383}; 1394};
1384 1395
1385/* pin banks of exynos5433 pin-controller - NFC */ 1396/* pin banks of exynos5433 pin-controller - NFC */
1386static const struct samsung_pin_bank_data exynos5433_pin_banks7[] = { 1397static const struct samsung_pin_bank_data exynos5433_pin_banks7[] = {
1387 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), 1398 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
1388}; 1399};
1389 1400
1390/* pin banks of exynos5433 pin-controller - PERIC */ 1401/* pin banks of exynos5433 pin-controller - PERIC */
1391static const struct samsung_pin_bank_data exynos5433_pin_banks8[] = { 1402static const struct samsung_pin_bank_data exynos5433_pin_banks8[] = {
1392 EXYNOS_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00), 1403 EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),
1393 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04), 1404 EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),
1394 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08), 1405 EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),
1395 EXYNOS_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c), 1406 EXYNOS5433_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c),
1396 EXYNOS_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10), 1407 EXYNOS5433_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10),
1397 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14), 1408 EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14),
1398 EXYNOS_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18), 1409 EXYNOS5433_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18),
1399 EXYNOS_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c), 1410 EXYNOS5433_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c),
1400 EXYNOS_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20), 1411 EXYNOS5433_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20),
1401 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24), 1412 EXYNOS5433_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24),
1402 EXYNOS_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28), 1413 EXYNOS5433_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28),
1403 EXYNOS_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c), 1414 EXYNOS5433_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c),
1404 EXYNOS_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30), 1415 EXYNOS5433_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30),
1405 EXYNOS_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34), 1416 EXYNOS5433_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34),
1406 EXYNOS_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38), 1417 EXYNOS5433_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38),
1407 EXYNOS_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c), 1418 EXYNOS5433_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c),
1408 EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), 1419 EXYNOS5433_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
1409}; 1420};
1410 1421
1411/* pin banks of exynos5433 pin-controller - TOUCH */ 1422/* pin banks of exynos5433 pin-controller - TOUCH */
1412static const struct samsung_pin_bank_data exynos5433_pin_banks9[] = { 1423static const struct samsung_pin_bank_data exynos5433_pin_banks9[] = {
1413 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), 1424 EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
1414}; 1425};
1415 1426
1416/* 1427/*
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index 5821525a2c84..a473092fb8d2 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -90,6 +90,37 @@
90 .pctl_res_idx = pctl_idx, \ 90 .pctl_res_idx = pctl_idx, \
91 } \ 91 } \
92 92
93#define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \
94 { \
95 .type = &exynos5433_bank_type_off, \
96 .pctl_offset = reg, \
97 .nr_pins = pins, \
98 .eint_type = EINT_TYPE_GPIO, \
99 .eint_offset = offs, \
100 .name = id \
101 }
102
103#define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs) \
104 { \
105 .type = &exynos5433_bank_type_alive, \
106 .pctl_offset = reg, \
107 .nr_pins = pins, \
108 .eint_type = EINT_TYPE_WKUP, \
109 .eint_offset = offs, \
110 .name = id \
111 }
112
113#define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \
114 { \
115 .type = &exynos5433_bank_type_alive, \
116 .pctl_offset = reg, \
117 .nr_pins = pins, \
118 .eint_type = EINT_TYPE_WKUP, \
119 .eint_offset = offs, \
120 .name = id, \
121 .pctl_res_idx = pctl_idx, \
122 } \
123
93/** 124/**
94 * struct exynos_weint_data: irq specific data for all the wakeup interrupts 125 * struct exynos_weint_data: irq specific data for all the wakeup interrupts
95 * generated by the external wakeup interrupt controller. 126 * generated by the external wakeup interrupt controller.
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-26 10:34:50 -0500