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-rw-r--r--arch/arm/mach-mvebu/include/mach/bridge-regs.h85
-rw-r--r--arch/arm/mach-mvebu/include/mach/kirkwood.h142
-rw-r--r--arch/arm/mach-mvebu/kirkwood-pm.c2
-rw-r--r--arch/arm/mach-mvebu/kirkwood.c9
-rw-r--r--arch/arm/mach-mvebu/kirkwood.h22
5 files changed, 26 insertions, 234 deletions
diff --git a/arch/arm/mach-mvebu/include/mach/bridge-regs.h b/arch/arm/mach-mvebu/include/mach/bridge-regs.h
deleted file mode 100644
index 6eb8fea1f76f..000000000000
--- a/arch/arm/mach-mvebu/include/mach/bridge-regs.h
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * arch/arm/mach-mvebu/include/mach/bridge-regs.h
3 *
4 * Mbus-L to Mbus Bridge Registers
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_BRIDGE_REGS_H
12#define __ASM_ARCH_BRIDGE_REGS_H
13
14#include <mach/kirkwood.h>
15
16#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0100)
17#define CPU_CONFIG_PHYS (BRIDGE_PHYS_BASE + 0x0100)
18#define CPU_CONFIG_ERROR_PROP 0x00000004
19
20#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
21#define CPU_CONTROL_PHYS (BRIDGE_PHYS_BASE + 0x0104)
22#define CPU_RESET 0x00000002
23
24#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
25#define SOFT_RESET_OUT_EN 0x00000004
26
27#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
28#define SOFT_RESET 0x00000001
29
30#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110)
31
32#define BRIDGE_INT_TIMER1_CLR (~0x0004)
33
34#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
35#define IRQ_CAUSE_LOW_OFF 0x0000
36#define IRQ_MASK_LOW_OFF 0x0004
37#define IRQ_CAUSE_HIGH_OFF 0x0010
38#define IRQ_MASK_HIGH_OFF 0x0014
39
40#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
41#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
42
43#define L2_CONFIG_REG (BRIDGE_VIRT_BASE + 0x0128)
44#define L2_WRITETHROUGH 0x00000010
45
46#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE + 0x11c)
47#define CGC_BIT_GE0 (0)
48#define CGC_BIT_PEX0 (2)
49#define CGC_BIT_USB0 (3)
50#define CGC_BIT_SDIO (4)
51#define CGC_BIT_TSU (5)
52#define CGC_BIT_DUNIT (6)
53#define CGC_BIT_RUNIT (7)
54#define CGC_BIT_XOR0 (8)
55#define CGC_BIT_AUDIO (9)
56#define CGC_BIT_SATA0 (14)
57#define CGC_BIT_SATA1 (15)
58#define CGC_BIT_XOR1 (16)
59#define CGC_BIT_CRYPTO (17)
60#define CGC_BIT_PEX1 (18)
61#define CGC_BIT_GE1 (19)
62#define CGC_BIT_TDM (20)
63#define CGC_GE0 (1 << 0)
64#define CGC_PEX0 (1 << 2)
65#define CGC_USB0 (1 << 3)
66#define CGC_SDIO (1 << 4)
67#define CGC_TSU (1 << 5)
68#define CGC_DUNIT (1 << 6)
69#define CGC_RUNIT (1 << 7)
70#define CGC_XOR0 (1 << 8)
71#define CGC_AUDIO (1 << 9)
72#define CGC_POWERSAVE (1 << 11)
73#define CGC_SATA0 (1 << 14)
74#define CGC_SATA1 (1 << 15)
75#define CGC_XOR1 (1 << 16)
76#define CGC_CRYPTO (1 << 17)
77#define CGC_PEX1 (1 << 18)
78#define CGC_GE1 (1 << 19)
79#define CGC_TDM (1 << 20)
80#define CGC_RESERVED (0x6 << 21)
81
82#define MEMORY_PM_CTRL (BRIDGE_VIRT_BASE + 0x118)
83#define MEMORY_PM_CTRL_PHYS (BRIDGE_PHYS_BASE + 0x118)
84
85#endif
diff --git a/arch/arm/mach-mvebu/include/mach/kirkwood.h b/arch/arm/mach-mvebu/include/mach/kirkwood.h
deleted file mode 100644
index 9d966dc78d67..000000000000
--- a/arch/arm/mach-mvebu/include/mach/kirkwood.h
+++ /dev/null
@@ -1,142 +0,0 @@
1/*
2 * arch/arm/mach-mvebu/include/mach/kirkwood.h
3 *
4 * Generic definitions for Marvell Kirkwood SoC flavors:
5 * 88F6180, 88F6192 and 88F6281.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#ifndef __ASM_ARCH_KIRKWOOD_H
13#define __ASM_ARCH_KIRKWOOD_H
14
15/*
16 * Marvell Kirkwood address maps.
17 *
18 * phys
19 * e0000000 PCIe #0 Memory space
20 * e8000000 PCIe #1 Memory space
21 * f1000000 on-chip peripheral registers
22 * f2000000 PCIe #0 I/O space
23 * f3000000 PCIe #1 I/O space
24 * f4000000 NAND controller address window
25 * f5000000 Security Accelerator SRAM
26 *
27 * virt phys size
28 * fed00000 f1000000 1M on-chip peripheral registers
29 * fee00000 f2000000 1M PCIe #0 I/O space
30 * fef00000 f3000000 1M PCIe #1 I/O space
31 */
32
33#define KIRKWOOD_SRAM_PHYS_BASE 0xf5000000
34#define KIRKWOOD_SRAM_SIZE SZ_2K
35
36#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf4000000
37#define KIRKWOOD_NAND_MEM_SIZE SZ_1K
38
39#define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000
40#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00010000
41#define KIRKWOOD_PCIE1_IO_SIZE SZ_64K
42
43#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000
44#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000
45#define KIRKWOOD_PCIE_IO_SIZE SZ_64K
46
47#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
48#define KIRKWOOD_REGS_VIRT_BASE IOMEM(0xfed00000)
49#define KIRKWOOD_REGS_SIZE SZ_1M
50
51#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000
52#define KIRKWOOD_PCIE_MEM_BUS_BASE 0xe0000000
53#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M
54
55#define KIRKWOOD_PCIE1_MEM_PHYS_BASE 0xe8000000
56#define KIRKWOOD_PCIE1_MEM_BUS_BASE 0xe8000000
57#define KIRKWOOD_PCIE1_MEM_SIZE SZ_128M
58
59/*
60 * Register Map
61 */
62#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x00000)
63#define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000)
64#define DDR_WINDOW_CPU_BASE (DDR_PHYS_BASE + 0x1500)
65#define DDR_WINDOW_CPU_SZ (0x20)
66#define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418)
67
68#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x10000)
69#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x10000)
70#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE + 0x0030)
71#define DEVICE_ID (DEV_BUS_VIRT_BASE + 0x0034)
72#define GPIO_LOW_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100)
73#define GPIO_HIGH_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0140)
74#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0300)
75#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0600)
76#define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000)
77#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000)
78#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000)
79#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100)
80#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100)
81
82#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x20000)
83#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
84#define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE)
85#define BRIDGE_WINS_SZ (0x80)
86
87#define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x30000)
88
89#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x40000)
90#define PCIE_LINK_CTRL (PCIE_VIRT_BASE + 0x70)
91#define PCIE_STATUS (PCIE_VIRT_BASE + 0x1a04)
92#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x44000)
93#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE + 0x70)
94#define PCIE1_STATUS (PCIE1_VIRT_BASE + 0x1a04)
95
96#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x50000)
97
98#define XOR0_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60800)
99#define XOR0_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60800)
100#define XOR1_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60900)
101#define XOR1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60900)
102#define XOR0_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60A00)
103#define XOR0_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60A00)
104#define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60B00)
105#define XOR1_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60B00)
106
107#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x70000)
108#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x74000)
109
110#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x80000)
111#define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x80000)
112#define SATA0_IF_CTRL (SATA_VIRT_BASE + 0x2050)
113#define SATA0_PHY_MODE_2 (SATA_VIRT_BASE + 0x2330)
114#define SATA1_IF_CTRL (SATA_VIRT_BASE + 0x4050)
115#define SATA1_PHY_MODE_2 (SATA_VIRT_BASE + 0x4330)
116
117#define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x90000)
118
119#define AUDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0xA0000)
120#define AUDIO_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0xA0000)
121
122/*
123 * Supported devices and revisions.
124 */
125#define MV88F6281_DEV_ID 0x6281
126#define MV88F6281_REV_Z0 0
127#define MV88F6281_REV_A0 2
128#define MV88F6281_REV_A1 3
129
130#define MV88F6192_DEV_ID 0x6192
131#define MV88F6192_REV_Z0 0
132#define MV88F6192_REV_A0 2
133#define MV88F6192_REV_A1 3
134
135#define MV88F6180_DEV_ID 0x6180
136#define MV88F6180_REV_A0 2
137#define MV88F6180_REV_A1 3
138
139#define MV88F6282_DEV_ID 0x6282
140#define MV88F6282_REV_A0 0
141#define MV88F6282_REV_A1 1
142#endif
diff --git a/arch/arm/mach-mvebu/kirkwood-pm.c b/arch/arm/mach-mvebu/kirkwood-pm.c
index b8c8365b84d8..cbb816f2120c 100644
--- a/arch/arm/mach-mvebu/kirkwood-pm.c
+++ b/arch/arm/mach-mvebu/kirkwood-pm.c
@@ -17,7 +17,7 @@
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/suspend.h> 18#include <linux/suspend.h>
19#include <linux/io.h> 19#include <linux/io.h>
20#include <mach/bridge-regs.h> 20#include "kirkwood.h"
21 21
22static void __iomem *ddr_operation_base; 22static void __iomem *ddr_operation_base;
23static void __iomem *memory_pm_ctrl; 23static void __iomem *memory_pm_ctrl;
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
index 4c7bbec11b1a..8a38b10532e5 100644
--- a/arch/arm/mach-mvebu/kirkwood.c
+++ b/arch/arm/mach-mvebu/kirkwood.c
@@ -13,19 +13,16 @@
13#include <linux/clk.h> 13#include <linux/clk.h>
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/mbus.h>
16#include <linux/of.h> 17#include <linux/of.h>
17#include <linux/of_address.h> 18#include <linux/of_address.h>
18#include <linux/of_net.h> 19#include <linux/of_net.h>
19#include <linux/of_platform.h> 20#include <linux/of_platform.h>
20#include <linux/dma-mapping.h> 21#include <linux/slab.h>
21#include <linux/irqchip.h>
22#include <linux/kexec.h>
23#include <asm/hardware/cache-feroceon-l2.h> 22#include <asm/hardware/cache-feroceon-l2.h>
24#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
25#include <asm/mach/map.h> 24#include <asm/mach/map.h>
26#include <mach/bridge-regs.h> 25#include "kirkwood.h"
27#include <plat/common.h>
28#include <plat/pcie.h>
29#include "kirkwood-pm.h" 26#include "kirkwood-pm.h"
30#include "common.h" 27#include "common.h"
31 28
diff --git a/arch/arm/mach-mvebu/kirkwood.h b/arch/arm/mach-mvebu/kirkwood.h
new file mode 100644
index 000000000000..89f3d1f51643
--- /dev/null
+++ b/arch/arm/mach-mvebu/kirkwood.h
@@ -0,0 +1,22 @@
1/*
2 * arch/arm/mach-mvebu/kirkwood.h
3 *
4 * Generic definitions for Marvell Kirkwood SoC flavors:
5 * 88F6180, 88F6192 and 88F6281.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
13#define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000)
14#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
15
16#define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418)
17
18#define CPU_CONFIG_PHYS (BRIDGE_PHYS_BASE + 0x0100)
19#define CPU_CONFIG_ERROR_PROP 0x00000004
20
21#define CPU_CONTROL_PHYS (BRIDGE_PHYS_BASE + 0x0104)
22#define MEMORY_PM_CTRL_PHYS (BRIDGE_PHYS_BASE + 0x0118)
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 21:55:40 -0500