1 files changed, 10 insertions, 1 deletions

diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 03b4cc0ec3a7..66ca906aa790 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -836,6 +836,16 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
         }
 
         /*
+         * If SSBD is controlled by the SPEC_CTRL MSR, then set the proper
+         * bit in the mask to allow guests to use the mitigation even in the
+         * case where the host does not enable it.
+         */
+        if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
+            static_cpu_has(X86_FEATURE_AMD_SSBD)) {
+                x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
+        }
+
+        /*
          * We have three CPU feature flags that are in play here:
          *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
          *  - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
@@ -852,7 +862,6 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void)
                         x86_amd_ssb_disable();
                 } else {
                         x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
-                        x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
                         wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
                 }
         }