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-rw-r--r--Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt3
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos.c376
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos.h3
-rw-r--r--drivers/pinctrl/samsung/pinctrl-s3c24xx.c30
-rw-r--r--drivers/pinctrl/samsung/pinctrl-s3c64xx.c31
-rw-r--r--drivers/pinctrl/samsung/pinctrl-samsung.c131
-rw-r--r--drivers/pinctrl/samsung/pinctrl-samsung.h82
7 files changed, 435 insertions, 221 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index e82aaf492517..8425838a6dff 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -18,6 +18,7 @@ Required Properties:
18 - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. 18 - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
19 - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller. 19 - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
20 - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. 20 - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
21 - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
21 22
22- reg: Base address of the pin controller hardware module and length of 23- reg: Base address of the pin controller hardware module and length of
23 the address space it occupies. 24 the address space it occupies.
@@ -136,6 +137,8 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
136 found on Samsung S3C64xx SoCs, 137 found on Samsung S3C64xx SoCs,
137 - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller 138 - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
138 found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs. 139 found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs.
140 - samsung,exynos7-wakeup-eint: represents wakeup interrupt controller
141 found on Samsung Exynos7 SoC.
139 - interrupt-parent: phandle of the interrupt parent to which the external 142 - interrupt-parent: phandle of the interrupt parent to which the external
140 wakeup interrupts are forwarded to. 143 wakeup interrupts are forwarded to.
141 - interrupts: interrupt used by multiplexed wakeup interrupts. 144 - interrupts: interrupt used by multiplexed wakeup interrupts.
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index d7154ed0b0eb..d5d4cfc55873 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -46,22 +46,16 @@ static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip)
46 return container_of(chip, struct exynos_irq_chip, chip); 46 return container_of(chip, struct exynos_irq_chip, chip);
47} 47}
48 48
49static struct samsung_pin_bank_type bank_type_off = { 49static const struct samsung_pin_bank_type bank_type_off = {
50 .fld_width = { 4, 1, 2, 2, 2, 2, }, 50 .fld_width = { 4, 1, 2, 2, 2, 2, },
51 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 51 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
52}; 52};
53 53
54static struct samsung_pin_bank_type bank_type_alive = { 54static const struct samsung_pin_bank_type bank_type_alive = {
55 .fld_width = { 4, 1, 2, 2, }, 55 .fld_width = { 4, 1, 2, 2, },
56 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 56 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
57}; 57};
58 58
59/* list of external wakeup controllers supported */
60static const struct of_device_id exynos_wkup_irq_ids[] = {
61 { .compatible = "samsung,exynos4210-wakeup-eint", },
62 { }
63};
64
65static void exynos_irq_mask(struct irq_data *irqd) 59static void exynos_irq_mask(struct irq_data *irqd)
66{ 60{
67 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 61 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
@@ -171,7 +165,7 @@ static int exynos_irq_request_resources(struct irq_data *irqd)
171 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 165 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
172 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 166 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
173 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 167 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
174 struct samsung_pin_bank_type *bank_type = bank->type; 168 const struct samsung_pin_bank_type *bank_type = bank->type;
175 struct samsung_pinctrl_drv_data *d = bank->drvdata; 169 struct samsung_pinctrl_drv_data *d = bank->drvdata;
176 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; 170 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
177 unsigned long reg_con = our_chip->eint_con + bank->eint_offset; 171 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
@@ -210,7 +204,7 @@ static void exynos_irq_release_resources(struct irq_data *irqd)
210 struct irq_chip *chip = irq_data_get_irq_chip(irqd); 204 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
211 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); 205 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
212 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 206 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
213 struct samsung_pin_bank_type *bank_type = bank->type; 207 const struct samsung_pin_bank_type *bank_type = bank->type;
214 struct samsung_pinctrl_drv_data *d = bank->drvdata; 208 struct samsung_pinctrl_drv_data *d = bank->drvdata;
215 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; 209 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
216 unsigned long reg_con = our_chip->eint_con + bank->eint_offset; 210 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
@@ -254,31 +248,30 @@ static struct exynos_irq_chip exynos_gpio_irq_chip = {
254 .eint_pend = EXYNOS_GPIO_EPEND_OFFSET, 248 .eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
255}; 249};
256 250
257static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq, 251static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq,
258 irq_hw_number_t hw) 252 irq_hw_number_t hw)
259{ 253{
260 struct samsung_pin_bank *b = h->host_data; 254 struct samsung_pin_bank *b = h->host_data;
261 255
262 irq_set_chip_data(virq, b); 256 irq_set_chip_data(virq, b);
263 irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip.chip, 257 irq_set_chip_and_handler(virq, &b->irq_chip->chip,
264 handle_level_irq); 258 handle_level_irq);
265 set_irq_flags(virq, IRQF_VALID); 259 set_irq_flags(virq, IRQF_VALID);
266 return 0; 260 return 0;
267} 261}
268 262
269/* 263/*
270 * irq domain callbacks for external gpio interrupt controller. 264 * irq domain callbacks for external gpio and wakeup interrupt controllers.
271 */ 265 */
272static const struct irq_domain_ops exynos_gpio_irqd_ops = { 266static const struct irq_domain_ops exynos_eint_irqd_ops = {
273 .map = exynos_gpio_irq_map, 267 .map = exynos_eint_irq_map,
274 .xlate = irq_domain_xlate_twocell, 268 .xlate = irq_domain_xlate_twocell,
275}; 269};
276 270
277static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) 271static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
278{ 272{
279 struct samsung_pinctrl_drv_data *d = data; 273 struct samsung_pinctrl_drv_data *d = data;
280 struct samsung_pin_ctrl *ctrl = d->ctrl; 274 struct samsung_pin_bank *bank = d->pin_banks;
281 struct samsung_pin_bank *bank = ctrl->pin_banks;
282 unsigned int svc, group, pin, virq; 275 unsigned int svc, group, pin, virq;
283 276
284 svc = readl(d->virt_base + EXYNOS_SVC_OFFSET); 277 svc = readl(d->virt_base + EXYNOS_SVC_OFFSET);
@@ -325,12 +318,12 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
325 return -ENXIO; 318 return -ENXIO;
326 } 319 }
327 320
328 bank = d->ctrl->pin_banks; 321 bank = d->pin_banks;
329 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { 322 for (i = 0; i < d->nr_banks; ++i, ++bank) {
330 if (bank->eint_type != EINT_TYPE_GPIO) 323 if (bank->eint_type != EINT_TYPE_GPIO)
331 continue; 324 continue;
332 bank->irq_domain = irq_domain_add_linear(bank->of_node, 325 bank->irq_domain = irq_domain_add_linear(bank->of_node,
333 bank->nr_pins, &exynos_gpio_irqd_ops, bank); 326 bank->nr_pins, &exynos_eint_irqd_ops, bank);
334 if (!bank->irq_domain) { 327 if (!bank->irq_domain) {
335 dev_err(dev, "gpio irq domain add failed\n"); 328 dev_err(dev, "gpio irq domain add failed\n");
336 ret = -ENXIO; 329 ret = -ENXIO;
@@ -344,6 +337,8 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
344 ret = -ENOMEM; 337 ret = -ENOMEM;
345 goto err_domains; 338 goto err_domains;
346 } 339 }
340
341 bank->irq_chip = &exynos_gpio_irq_chip;
347 } 342 }
348 343
349 return 0; 344 return 0;
@@ -383,9 +378,9 @@ static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
383/* 378/*
384 * irq_chip for wakeup interrupts 379 * irq_chip for wakeup interrupts
385 */ 380 */
386static struct exynos_irq_chip exynos_wkup_irq_chip = { 381static struct exynos_irq_chip exynos4210_wkup_irq_chip __initdata = {
387 .chip = { 382 .chip = {
388 .name = "exynos_wkup_irq_chip", 383 .name = "exynos4210_wkup_irq_chip",
389 .irq_unmask = exynos_irq_unmask, 384 .irq_unmask = exynos_irq_unmask,
390 .irq_mask = exynos_irq_mask, 385 .irq_mask = exynos_irq_mask,
391 .irq_ack = exynos_irq_ack, 386 .irq_ack = exynos_irq_ack,
@@ -399,6 +394,31 @@ static struct exynos_irq_chip exynos_wkup_irq_chip = {
399 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, 394 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
400}; 395};
401 396
397static struct exynos_irq_chip exynos7_wkup_irq_chip __initdata = {
398 .chip = {
399 .name = "exynos7_wkup_irq_chip",
400 .irq_unmask = exynos_irq_unmask,
401 .irq_mask = exynos_irq_mask,
402 .irq_ack = exynos_irq_ack,
403 .irq_set_type = exynos_irq_set_type,
404 .irq_set_wake = exynos_wkup_irq_set_wake,
405 .irq_request_resources = exynos_irq_request_resources,
406 .irq_release_resources = exynos_irq_release_resources,
407 },
408 .eint_con = EXYNOS7_WKUP_ECON_OFFSET,
409 .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
410 .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
411};
412
413/* list of external wakeup controllers supported */
414static const struct of_device_id exynos_wkup_irq_ids[] = {
415 { .compatible = "samsung,exynos4210-wakeup-eint",
416 .data = &exynos4210_wkup_irq_chip },
417 { .compatible = "samsung,exynos7-wakeup-eint",
418 .data = &exynos7_wkup_irq_chip },
419 { }
420};
421
402/* interrupt handler for wakeup interrupts 0..15 */ 422/* interrupt handler for wakeup interrupts 0..15 */
403static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc) 423static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
404{ 424{
@@ -445,9 +465,9 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
445 465
446 for (i = 0; i < eintd->nr_banks; ++i) { 466 for (i = 0; i < eintd->nr_banks; ++i) {
447 struct samsung_pin_bank *b = eintd->banks[i]; 467 struct samsung_pin_bank *b = eintd->banks[i];
448 pend = readl(d->virt_base + EXYNOS_WKUP_EPEND_OFFSET 468 pend = readl(d->virt_base + b->irq_chip->eint_pend
449 + b->eint_offset); 469 + b->eint_offset);
450 mask = readl(d->virt_base + EXYNOS_WKUP_EMASK_OFFSET 470 mask = readl(d->virt_base + b->irq_chip->eint_mask
451 + b->eint_offset); 471 + b->eint_offset);
452 exynos_irq_demux_eint(pend & ~mask, b->irq_domain); 472 exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
453 } 473 }
@@ -455,24 +475,6 @@ static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
455 chained_irq_exit(chip, desc); 475 chained_irq_exit(chip, desc);
456} 476}
457 477
458static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
459 irq_hw_number_t hw)
460{
461 irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip.chip,
462 handle_level_irq);
463 irq_set_chip_data(virq, h->host_data);
464 set_irq_flags(virq, IRQF_VALID);
465 return 0;
466}
467
468/*
469 * irq domain callbacks for external wakeup interrupt controller.
470 */
471static const struct irq_domain_ops exynos_wkup_irqd_ops = {
472 .map = exynos_wkup_irq_map,
473 .xlate = irq_domain_xlate_twocell,
474};
475
476/* 478/*
477 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts. 479 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
478 * @d: driver data of samsung pinctrl driver. 480 * @d: driver data of samsung pinctrl driver.
@@ -485,12 +487,18 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
485 struct samsung_pin_bank *bank; 487 struct samsung_pin_bank *bank;
486 struct exynos_weint_data *weint_data; 488 struct exynos_weint_data *weint_data;
487 struct exynos_muxed_weint_data *muxed_data; 489 struct exynos_muxed_weint_data *muxed_data;
490 struct exynos_irq_chip *irq_chip;
488 unsigned int muxed_banks = 0; 491 unsigned int muxed_banks = 0;
489 unsigned int i; 492 unsigned int i;
490 int idx, irq; 493 int idx, irq;
491 494
492 for_each_child_of_node(dev->of_node, np) { 495 for_each_child_of_node(dev->of_node, np) {
493 if (of_match_node(exynos_wkup_irq_ids, np)) { 496 const struct of_device_id *match;
497
498 match = of_match_node(exynos_wkup_irq_ids, np);
499 if (match) {
500 irq_chip = kmemdup(match->data,
501 sizeof(*irq_chip), GFP_KERNEL);
494 wkup_np = np; 502 wkup_np = np;
495 break; 503 break;
496 } 504 }
@@ -498,18 +506,20 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
498 if (!wkup_np) 506 if (!wkup_np)
499 return -ENODEV; 507 return -ENODEV;
500 508
501 bank = d->ctrl->pin_banks; 509 bank = d->pin_banks;
502 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { 510 for (i = 0; i < d->nr_banks; ++i, ++bank) {
503 if (bank->eint_type != EINT_TYPE_WKUP) 511 if (bank->eint_type != EINT_TYPE_WKUP)
504 continue; 512 continue;
505 513
506 bank->irq_domain = irq_domain_add_linear(bank->of_node, 514 bank->irq_domain = irq_domain_add_linear(bank->of_node,
507 bank->nr_pins, &exynos_wkup_irqd_ops, bank); 515 bank->nr_pins, &exynos_eint_irqd_ops, bank);
508 if (!bank->irq_domain) { 516 if (!bank->irq_domain) {
509 dev_err(dev, "wkup irq domain add failed\n"); 517 dev_err(dev, "wkup irq domain add failed\n");
510 return -ENXIO; 518 return -ENXIO;
511 } 519 }
512 520
521 bank->irq_chip = irq_chip;
522
513 if (!of_find_property(bank->of_node, "interrupts", NULL)) { 523 if (!of_find_property(bank->of_node, "interrupts", NULL)) {
514 bank->eint_type = EINT_TYPE_WKUP_MUX; 524 bank->eint_type = EINT_TYPE_WKUP_MUX;
515 ++muxed_banks; 525 ++muxed_banks;
@@ -556,9 +566,9 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
556 irq_set_chained_handler(irq, exynos_irq_demux_eint16_31); 566 irq_set_chained_handler(irq, exynos_irq_demux_eint16_31);
557 irq_set_handler_data(irq, muxed_data); 567 irq_set_handler_data(irq, muxed_data);
558 568
559 bank = d->ctrl->pin_banks; 569 bank = d->pin_banks;
560 idx = 0; 570 idx = 0;
561 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { 571 for (i = 0; i < d->nr_banks; ++i, ++bank) {
562 if (bank->eint_type != EINT_TYPE_WKUP_MUX) 572 if (bank->eint_type != EINT_TYPE_WKUP_MUX)
563 continue; 573 continue;
564 574
@@ -590,11 +600,10 @@ static void exynos_pinctrl_suspend_bank(
590 600
591static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) 601static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
592{ 602{
593 struct samsung_pin_ctrl *ctrl = drvdata->ctrl; 603 struct samsung_pin_bank *bank = drvdata->pin_banks;
594 struct samsung_pin_bank *bank = ctrl->pin_banks;
595 int i; 604 int i;
596 605
597 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) 606 for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
598 if (bank->eint_type == EINT_TYPE_GPIO) 607 if (bank->eint_type == EINT_TYPE_GPIO)
599 exynos_pinctrl_suspend_bank(drvdata, bank); 608 exynos_pinctrl_suspend_bank(drvdata, bank);
600} 609}
@@ -626,17 +635,16 @@ static void exynos_pinctrl_resume_bank(
626 635
627static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) 636static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
628{ 637{
629 struct samsung_pin_ctrl *ctrl = drvdata->ctrl; 638 struct samsung_pin_bank *bank = drvdata->pin_banks;
630 struct samsung_pin_bank *bank = ctrl->pin_banks;
631 int i; 639 int i;
632 640
633 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) 641 for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
634 if (bank->eint_type == EINT_TYPE_GPIO) 642 if (bank->eint_type == EINT_TYPE_GPIO)
635 exynos_pinctrl_resume_bank(drvdata, bank); 643 exynos_pinctrl_resume_bank(drvdata, bank);
636} 644}
637 645
638/* pin banks of s5pv210 pin-controller */ 646/* pin banks of s5pv210 pin-controller */
639static struct samsung_pin_bank s5pv210_pin_bank[] = { 647static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
640 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 648 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
641 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04), 649 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
642 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 650 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
@@ -673,7 +681,7 @@ static struct samsung_pin_bank s5pv210_pin_bank[] = {
673 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c), 681 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
674}; 682};
675 683
676struct samsung_pin_ctrl s5pv210_pin_ctrl[] = { 684const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
677 { 685 {
678 /* pin-controller instance 0 data */ 686 /* pin-controller instance 0 data */
679 .pin_banks = s5pv210_pin_bank, 687 .pin_banks = s5pv210_pin_bank,
@@ -682,12 +690,11 @@ struct samsung_pin_ctrl s5pv210_pin_ctrl[] = {
682 .eint_wkup_init = exynos_eint_wkup_init, 690 .eint_wkup_init = exynos_eint_wkup_init,
683 .suspend = exynos_pinctrl_suspend, 691 .suspend = exynos_pinctrl_suspend,
684 .resume = exynos_pinctrl_resume, 692 .resume = exynos_pinctrl_resume,
685 .label = "s5pv210-gpio-ctrl0",
686 }, 693 },
687}; 694};
688 695
689/* pin banks of exynos3250 pin-controller 0 */ 696/* pin banks of exynos3250 pin-controller 0 */
690static struct samsung_pin_bank exynos3250_pin_banks0[] = { 697static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = {
691 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 698 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
692 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 699 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
693 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 700 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
@@ -698,7 +705,7 @@ static struct samsung_pin_bank exynos3250_pin_banks0[] = {
698}; 705};
699 706
700/* pin banks of exynos3250 pin-controller 1 */ 707/* pin banks of exynos3250 pin-controller 1 */
701static struct samsung_pin_bank exynos3250_pin_banks1[] = { 708static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = {
702 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"), 709 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
703 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"), 710 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
704 EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"), 711 EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
@@ -721,7 +728,7 @@ static struct samsung_pin_bank exynos3250_pin_banks1[] = {
721 * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes 728 * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
722 * two gpio/pin-mux/pinconfig controllers. 729 * two gpio/pin-mux/pinconfig controllers.
723 */ 730 */
724struct samsung_pin_ctrl exynos3250_pin_ctrl[] = { 731const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
725 { 732 {
726 /* pin-controller instance 0 data */ 733 /* pin-controller instance 0 data */
727 .pin_banks = exynos3250_pin_banks0, 734 .pin_banks = exynos3250_pin_banks0,
@@ -729,7 +736,6 @@ struct samsung_pin_ctrl exynos3250_pin_ctrl[] = {
729 .eint_gpio_init = exynos_eint_gpio_init, 736 .eint_gpio_init = exynos_eint_gpio_init,
730 .suspend = exynos_pinctrl_suspend, 737 .suspend = exynos_pinctrl_suspend,
731 .resume = exynos_pinctrl_resume, 738 .resume = exynos_pinctrl_resume,
732 .label = "exynos3250-gpio-ctrl0",
733 }, { 739 }, {
734 /* pin-controller instance 1 data */ 740 /* pin-controller instance 1 data */
735 .pin_banks = exynos3250_pin_banks1, 741 .pin_banks = exynos3250_pin_banks1,
@@ -738,12 +744,11 @@ struct samsung_pin_ctrl exynos3250_pin_ctrl[] = {
738 .eint_wkup_init = exynos_eint_wkup_init, 744 .eint_wkup_init = exynos_eint_wkup_init,
739 .suspend = exynos_pinctrl_suspend, 745 .suspend = exynos_pinctrl_suspend,
740 .resume = exynos_pinctrl_resume, 746 .resume = exynos_pinctrl_resume,
741 .label = "exynos3250-gpio-ctrl1",
742 }, 747 },
743}; 748};
744 749
745/* pin banks of exynos4210 pin-controller 0 */ 750/* pin banks of exynos4210 pin-controller 0 */
746static struct samsung_pin_bank exynos4210_pin_banks0[] = { 751static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = {
747 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 752 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
748 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 753 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
749 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 754 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
@@ -763,7 +768,7 @@ static struct samsung_pin_bank exynos4210_pin_banks0[] = {
763}; 768};
764 769
765/* pin banks of exynos4210 pin-controller 1 */ 770/* pin banks of exynos4210 pin-controller 1 */
766static struct samsung_pin_bank exynos4210_pin_banks1[] = { 771static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = {
767 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00), 772 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
768 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04), 773 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
769 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), 774 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
@@ -787,7 +792,7 @@ static struct samsung_pin_bank exynos4210_pin_banks1[] = {
787}; 792};
788 793
789/* pin banks of exynos4210 pin-controller 2 */ 794/* pin banks of exynos4210 pin-controller 2 */
790static struct samsung_pin_bank exynos4210_pin_banks2[] = { 795static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = {
791 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"), 796 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
792}; 797};
793 798
@@ -795,7 +800,7 @@ static struct samsung_pin_bank exynos4210_pin_banks2[] = {
795 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes 800 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
796 * three gpio/pin-mux/pinconfig controllers. 801 * three gpio/pin-mux/pinconfig controllers.
797 */ 802 */
798struct samsung_pin_ctrl exynos4210_pin_ctrl[] = { 803const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {
799 { 804 {
800 /* pin-controller instance 0 data */ 805 /* pin-controller instance 0 data */
801 .pin_banks = exynos4210_pin_banks0, 806 .pin_banks = exynos4210_pin_banks0,
@@ -803,7 +808,6 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
803 .eint_gpio_init = exynos_eint_gpio_init, 808 .eint_gpio_init = exynos_eint_gpio_init,
804 .suspend = exynos_pinctrl_suspend, 809 .suspend = exynos_pinctrl_suspend,
805 .resume = exynos_pinctrl_resume, 810 .resume = exynos_pinctrl_resume,
806 .label = "exynos4210-gpio-ctrl0",
807 }, { 811 }, {
808 /* pin-controller instance 1 data */ 812 /* pin-controller instance 1 data */
809 .pin_banks = exynos4210_pin_banks1, 813 .pin_banks = exynos4210_pin_banks1,
@@ -812,17 +816,15 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
812 .eint_wkup_init = exynos_eint_wkup_init, 816 .eint_wkup_init = exynos_eint_wkup_init,
813 .suspend = exynos_pinctrl_suspend, 817 .suspend = exynos_pinctrl_suspend,
814 .resume = exynos_pinctrl_resume, 818 .resume = exynos_pinctrl_resume,
815 .label = "exynos4210-gpio-ctrl1",
816 }, { 819 }, {
817 /* pin-controller instance 2 data */ 820 /* pin-controller instance 2 data */
818 .pin_banks = exynos4210_pin_banks2, 821 .pin_banks = exynos4210_pin_banks2,
819 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2), 822 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),
820 .label = "exynos4210-gpio-ctrl2",
821 }, 823 },
822}; 824};
823 825
824/* pin banks of exynos4x12 pin-controller 0 */ 826/* pin banks of exynos4x12 pin-controller 0 */
825static struct samsung_pin_bank exynos4x12_pin_banks0[] = { 827static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = {
826 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 828 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
827 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 829 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
828 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 830 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
@@ -839,7 +841,7 @@ static struct samsung_pin_bank exynos4x12_pin_banks0[] = {
839}; 841};
840 842
841/* pin banks of exynos4x12 pin-controller 1 */ 843/* pin banks of exynos4x12 pin-controller 1 */
842static struct samsung_pin_bank exynos4x12_pin_banks1[] = { 844static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = {
843 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), 845 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
844 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), 846 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
845 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), 847 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
@@ -866,12 +868,12 @@ static struct samsung_pin_bank exynos4x12_pin_banks1[] = {
866}; 868};
867 869
868/* pin banks of exynos4x12 pin-controller 2 */ 870/* pin banks of exynos4x12 pin-controller 2 */
869static struct samsung_pin_bank exynos4x12_pin_banks2[] = { 871static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = {
870 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 872 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
871}; 873};
872 874
873/* pin banks of exynos4x12 pin-controller 3 */ 875/* pin banks of exynos4x12 pin-controller 3 */
874static struct samsung_pin_bank exynos4x12_pin_banks3[] = { 876static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = {
875 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), 877 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
876 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), 878 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
877 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08), 879 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
@@ -883,7 +885,7 @@ static struct samsung_pin_bank exynos4x12_pin_banks3[] = {
883 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes 885 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
884 * four gpio/pin-mux/pinconfig controllers. 886 * four gpio/pin-mux/pinconfig controllers.
885 */ 887 */
886struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = { 888const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {
887 { 889 {
888 /* pin-controller instance 0 data */ 890 /* pin-controller instance 0 data */
889 .pin_banks = exynos4x12_pin_banks0, 891 .pin_banks = exynos4x12_pin_banks0,
@@ -891,7 +893,6 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
891 .eint_gpio_init = exynos_eint_gpio_init, 893 .eint_gpio_init = exynos_eint_gpio_init,
892 .suspend = exynos_pinctrl_suspend, 894 .suspend = exynos_pinctrl_suspend,
893 .resume = exynos_pinctrl_resume, 895 .resume = exynos_pinctrl_resume,
894 .label = "exynos4x12-gpio-ctrl0",
895 }, { 896 }, {
896 /* pin-controller instance 1 data */ 897 /* pin-controller instance 1 data */
897 .pin_banks = exynos4x12_pin_banks1, 898 .pin_banks = exynos4x12_pin_banks1,
@@ -900,7 +901,6 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
900 .eint_wkup_init = exynos_eint_wkup_init, 901 .eint_wkup_init = exynos_eint_wkup_init,
901 .suspend = exynos_pinctrl_suspend, 902 .suspend = exynos_pinctrl_suspend,
902 .resume = exynos_pinctrl_resume, 903 .resume = exynos_pinctrl_resume,
903 .label = "exynos4x12-gpio-ctrl1",
904 }, { 904 }, {
905 /* pin-controller instance 2 data */ 905 /* pin-controller instance 2 data */
906 .pin_banks = exynos4x12_pin_banks2, 906 .pin_banks = exynos4x12_pin_banks2,
@@ -908,7 +908,6 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
908 .eint_gpio_init = exynos_eint_gpio_init, 908 .eint_gpio_init = exynos_eint_gpio_init,
909 .suspend = exynos_pinctrl_suspend, 909 .suspend = exynos_pinctrl_suspend,
910 .resume = exynos_pinctrl_resume, 910 .resume = exynos_pinctrl_resume,
911 .label = "exynos4x12-gpio-ctrl2",
912 }, { 911 }, {
913 /* pin-controller instance 3 data */ 912 /* pin-controller instance 3 data */
914 .pin_banks = exynos4x12_pin_banks3, 913 .pin_banks = exynos4x12_pin_banks3,
@@ -916,12 +915,86 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
916 .eint_gpio_init = exynos_eint_gpio_init, 915 .eint_gpio_init = exynos_eint_gpio_init,
917 .suspend = exynos_pinctrl_suspend, 916 .suspend = exynos_pinctrl_suspend,
918 .resume = exynos_pinctrl_resume, 917 .resume = exynos_pinctrl_resume,
919 .label = "exynos4x12-gpio-ctrl3", 918 },
919};
920
921/* pin banks of exynos4415 pin-controller 0 */
922static const struct samsung_pin_bank_data exynos4415_pin_banks0[] = {
923 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
924 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
925 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
926 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
927 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
928 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
929 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
930 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
931 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
932 EXYNOS_PIN_BANK_EINTG(1, 0x1C0, "gpf2", 0x38),
933};
934
935/* pin banks of exynos4415 pin-controller 1 */
936static const struct samsung_pin_bank_data exynos4415_pin_banks1[] = {
937 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
938 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
939 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
940 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
941 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpl0", 0x18),
942 EXYNOS_PIN_BANK_EINTN(6, 0x120, "mp00"),
943 EXYNOS_PIN_BANK_EINTN(4, 0x140, "mp01"),
944 EXYNOS_PIN_BANK_EINTN(6, 0x160, "mp02"),
945 EXYNOS_PIN_BANK_EINTN(8, 0x180, "mp03"),
946 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "mp04"),
947 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "mp05"),
948 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "mp06"),
949 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
950 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
951 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
952 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
953 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
954 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
955 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
956 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
957 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
958};
959
960/* pin banks of exynos4415 pin-controller 2 */
961static const struct samsung_pin_bank_data exynos4415_pin_banks2[] = {
962 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
963 EXYNOS_PIN_BANK_EINTN(2, 0x000, "etc1"),
964};
965
966/*
967 * Samsung pinctrl driver data for Exynos4415 SoC. Exynos4415 SoC includes
968 * three gpio/pin-mux/pinconfig controllers.
969 */
970const struct samsung_pin_ctrl exynos4415_pin_ctrl[] = {
971 {
972 /* pin-controller instance 0 data */
973 .pin_banks = exynos4415_pin_banks0,
974 .nr_banks = ARRAY_SIZE(exynos4415_pin_banks0),
975 .eint_gpio_init = exynos_eint_gpio_init,
976 .suspend = exynos_pinctrl_suspend,
977 .resume = exynos_pinctrl_resume,
978 }, {
979 /* pin-controller instance 1 data */
980 .pin_banks = exynos4415_pin_banks1,
981 .nr_banks = ARRAY_SIZE(exynos4415_pin_banks1),
982 .eint_gpio_init = exynos_eint_gpio_init,
983 .eint_wkup_init = exynos_eint_wkup_init,
984 .suspend = exynos_pinctrl_suspend,
985 .resume = exynos_pinctrl_resume,
986 }, {
987 /* pin-controller instance 2 data */
988 .pin_banks = exynos4415_pin_banks2,
989 .nr_banks = ARRAY_SIZE(exynos4415_pin_banks2),
990 .eint_gpio_init = exynos_eint_gpio_init,
991 .suspend = exynos_pinctrl_suspend,
992 .resume = exynos_pinctrl_resume,
920 }, 993 },
921}; 994};
922 995
923/* pin banks of exynos5250 pin-controller 0 */ 996/* pin banks of exynos5250 pin-controller 0 */
924static struct samsung_pin_bank exynos5250_pin_banks0[] = { 997static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = {
925 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 998 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
926 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 999 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
927 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 1000 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
@@ -950,7 +1023,7 @@ static struct samsung_pin_bank exynos5250_pin_banks0[] = {
950}; 1023};
951 1024
952/* pin banks of exynos5250 pin-controller 1 */ 1025/* pin banks of exynos5250 pin-controller 1 */
953static struct samsung_pin_bank exynos5250_pin_banks1[] = { 1026static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = {
954 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), 1027 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
955 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), 1028 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
956 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08), 1029 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
@@ -963,7 +1036,7 @@ static struct samsung_pin_bank exynos5250_pin_banks1[] = {
963}; 1036};
964 1037
965/* pin banks of exynos5250 pin-controller 2 */ 1038/* pin banks of exynos5250 pin-controller 2 */
966static struct samsung_pin_bank exynos5250_pin_banks2[] = { 1039static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = {
967 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), 1040 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
968 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), 1041 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
969 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), 1042 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
@@ -972,7 +1045,7 @@ static struct samsung_pin_bank exynos5250_pin_banks2[] = {
972}; 1045};
973 1046
974/* pin banks of exynos5250 pin-controller 3 */ 1047/* pin banks of exynos5250 pin-controller 3 */
975static struct samsung_pin_bank exynos5250_pin_banks3[] = { 1048static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = {
976 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 1049 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
977}; 1050};
978 1051
@@ -980,7 +1053,7 @@ static struct samsung_pin_bank exynos5250_pin_banks3[] = {
980 * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes 1053 * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
981 * four gpio/pin-mux/pinconfig controllers. 1054 * four gpio/pin-mux/pinconfig controllers.
982 */ 1055 */
983struct samsung_pin_ctrl exynos5250_pin_ctrl[] = { 1056const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {
984 { 1057 {
985 /* pin-controller instance 0 data */ 1058 /* pin-controller instance 0 data */
986 .pin_banks = exynos5250_pin_banks0, 1059 .pin_banks = exynos5250_pin_banks0,
@@ -989,7 +1062,6 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
989 .eint_wkup_init = exynos_eint_wkup_init, 1062 .eint_wkup_init = exynos_eint_wkup_init,
990 .suspend = exynos_pinctrl_suspend, 1063 .suspend = exynos_pinctrl_suspend,
991 .resume = exynos_pinctrl_resume, 1064 .resume = exynos_pinctrl_resume,
992 .label = "exynos5250-gpio-ctrl0",
993 }, { 1065 }, {
994 /* pin-controller instance 1 data */ 1066 /* pin-controller instance 1 data */
995 .pin_banks = exynos5250_pin_banks1, 1067 .pin_banks = exynos5250_pin_banks1,
@@ -997,7 +1069,6 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
997 .eint_gpio_init = exynos_eint_gpio_init, 1069 .eint_gpio_init = exynos_eint_gpio_init,
998 .suspend = exynos_pinctrl_suspend, 1070 .suspend = exynos_pinctrl_suspend,
999 .resume = exynos_pinctrl_resume, 1071 .resume = exynos_pinctrl_resume,
1000 .label = "exynos5250-gpio-ctrl1",
1001 }, { 1072 }, {
1002 /* pin-controller instance 2 data */ 1073 /* pin-controller instance 2 data */
1003 .pin_banks = exynos5250_pin_banks2, 1074 .pin_banks = exynos5250_pin_banks2,
@@ -1005,7 +1076,6 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
1005 .eint_gpio_init = exynos_eint_gpio_init, 1076 .eint_gpio_init = exynos_eint_gpio_init,
1006 .suspend = exynos_pinctrl_suspend, 1077 .suspend = exynos_pinctrl_suspend,
1007 .resume = exynos_pinctrl_resume, 1078 .resume = exynos_pinctrl_resume,
1008 .label = "exynos5250-gpio-ctrl2",
1009 }, { 1079 }, {
1010 /* pin-controller instance 3 data */ 1080 /* pin-controller instance 3 data */
1011 .pin_banks = exynos5250_pin_banks3, 1081 .pin_banks = exynos5250_pin_banks3,
@@ -1013,12 +1083,11 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
1013 .eint_gpio_init = exynos_eint_gpio_init, 1083 .eint_gpio_init = exynos_eint_gpio_init,
1014 .suspend = exynos_pinctrl_suspend, 1084 .suspend = exynos_pinctrl_suspend,
1015 .resume = exynos_pinctrl_resume, 1085 .resume = exynos_pinctrl_resume,
1016 .label = "exynos5250-gpio-ctrl3",
1017 }, 1086 },
1018}; 1087};
1019 1088
1020/* pin banks of exynos5260 pin-controller 0 */ 1089/* pin banks of exynos5260 pin-controller 0 */
1021static struct samsung_pin_bank exynos5260_pin_banks0[] = { 1090static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = {
1022 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), 1091 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
1023 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), 1092 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
1024 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 1093 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
@@ -1043,7 +1112,7 @@ static struct samsung_pin_bank exynos5260_pin_banks0[] = {
1043}; 1112};
1044 1113
1045/* pin banks of exynos5260 pin-controller 1 */ 1114/* pin banks of exynos5260 pin-controller 1 */
1046static struct samsung_pin_bank exynos5260_pin_banks1[] = { 1115static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = {
1047 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), 1116 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
1048 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), 1117 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
1049 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), 1118 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
@@ -1052,7 +1121,7 @@ static struct samsung_pin_bank exynos5260_pin_banks1[] = {
1052}; 1121};
1053 1122
1054/* pin banks of exynos5260 pin-controller 2 */ 1123/* pin banks of exynos5260 pin-controller 2 */
1055static struct samsung_pin_bank exynos5260_pin_banks2[] = { 1124static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = {
1056 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), 1125 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1057 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), 1126 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1058}; 1127};
@@ -1061,31 +1130,28 @@ static struct samsung_pin_bank exynos5260_pin_banks2[] = {
1061 * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes 1130 * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
1062 * three gpio/pin-mux/pinconfig controllers. 1131 * three gpio/pin-mux/pinconfig controllers.
1063 */ 1132 */
1064struct samsung_pin_ctrl exynos5260_pin_ctrl[] = { 1133const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
1065 { 1134 {
1066 /* pin-controller instance 0 data */ 1135 /* pin-controller instance 0 data */
1067 .pin_banks = exynos5260_pin_banks0, 1136 .pin_banks = exynos5260_pin_banks0,
1068 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0), 1137 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
1069 .eint_gpio_init = exynos_eint_gpio_init, 1138 .eint_gpio_init = exynos_eint_gpio_init,
1070 .eint_wkup_init = exynos_eint_wkup_init, 1139 .eint_wkup_init = exynos_eint_wkup_init,
1071 .label = "exynos5260-gpio-ctrl0",
1072 }, { 1140 }, {
1073 /* pin-controller instance 1 data */ 1141 /* pin-controller instance 1 data */
1074 .pin_banks = exynos5260_pin_banks1, 1142 .pin_banks = exynos5260_pin_banks1,
1075 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1), 1143 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
1076 .eint_gpio_init = exynos_eint_gpio_init, 1144 .eint_gpio_init = exynos_eint_gpio_init,
1077 .label = "exynos5260-gpio-ctrl1",
1078 }, { 1145 }, {
1079 /* pin-controller instance 2 data */ 1146 /* pin-controller instance 2 data */
1080 .pin_banks = exynos5260_pin_banks2, 1147 .pin_banks = exynos5260_pin_banks2,
1081 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2), 1148 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2),
1082 .eint_gpio_init = exynos_eint_gpio_init, 1149 .eint_gpio_init = exynos_eint_gpio_init,
1083 .label = "exynos5260-gpio-ctrl2",
1084 }, 1150 },
1085}; 1151};
1086 1152
1087/* pin banks of exynos5420 pin-controller 0 */ 1153/* pin banks of exynos5420 pin-controller 0 */
1088static struct samsung_pin_bank exynos5420_pin_banks0[] = { 1154static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = {
1089 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), 1155 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
1090 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), 1156 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
1091 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), 1157 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
@@ -1094,7 +1160,7 @@ static struct samsung_pin_bank exynos5420_pin_banks0[] = {
1094}; 1160};
1095 1161
1096/* pin banks of exynos5420 pin-controller 1 */ 1162/* pin banks of exynos5420 pin-controller 1 */
1097static struct samsung_pin_bank exynos5420_pin_banks1[] = { 1163static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = {
1098 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00), 1164 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
1099 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04), 1165 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
1100 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), 1166 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
@@ -1111,7 +1177,7 @@ static struct samsung_pin_bank exynos5420_pin_banks1[] = {
1111}; 1177};
1112 1178
1113/* pin banks of exynos5420 pin-controller 2 */ 1179/* pin banks of exynos5420 pin-controller 2 */
1114static struct samsung_pin_bank exynos5420_pin_banks2[] = { 1180static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = {
1115 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), 1181 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
1116 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), 1182 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
1117 EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08), 1183 EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
@@ -1123,7 +1189,7 @@ static struct samsung_pin_bank exynos5420_pin_banks2[] = {
1123}; 1189};
1124 1190
1125/* pin banks of exynos5420 pin-controller 3 */ 1191/* pin banks of exynos5420 pin-controller 3 */
1126static struct samsung_pin_bank exynos5420_pin_banks3[] = { 1192static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = {
1127 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 1193 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
1128 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), 1194 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
1129 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), 1195 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
@@ -1136,7 +1202,7 @@ static struct samsung_pin_bank exynos5420_pin_banks3[] = {
1136}; 1202};
1137 1203
1138/* pin banks of exynos5420 pin-controller 4 */ 1204/* pin banks of exynos5420 pin-controller 4 */
1139static struct samsung_pin_bank exynos5420_pin_banks4[] = { 1205static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = {
1140 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), 1206 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
1141}; 1207};
1142 1208
@@ -1144,37 +1210,137 @@ static struct samsung_pin_bank exynos5420_pin_banks4[] = {
1144 * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes 1210 * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
1145 * four gpio/pin-mux/pinconfig controllers. 1211 * four gpio/pin-mux/pinconfig controllers.
1146 */ 1212 */
1147struct samsung_pin_ctrl exynos5420_pin_ctrl[] = { 1213const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
1148 { 1214 {
1149 /* pin-controller instance 0 data */ 1215 /* pin-controller instance 0 data */
1150 .pin_banks = exynos5420_pin_banks0, 1216 .pin_banks = exynos5420_pin_banks0,
1151 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0), 1217 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
1152 .eint_gpio_init = exynos_eint_gpio_init, 1218 .eint_gpio_init = exynos_eint_gpio_init,
1153 .eint_wkup_init = exynos_eint_wkup_init, 1219 .eint_wkup_init = exynos_eint_wkup_init,
1154 .label = "exynos5420-gpio-ctrl0",
1155 }, { 1220 }, {
1156 /* pin-controller instance 1 data */ 1221 /* pin-controller instance 1 data */
1157 .pin_banks = exynos5420_pin_banks1, 1222 .pin_banks = exynos5420_pin_banks1,
1158 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1), 1223 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),
1159 .eint_gpio_init = exynos_eint_gpio_init, 1224 .eint_gpio_init = exynos_eint_gpio_init,
1160 .label = "exynos5420-gpio-ctrl1",
1161 }, { 1225 }, {
1162 /* pin-controller instance 2 data */ 1226 /* pin-controller instance 2 data */
1163 .pin_banks = exynos5420_pin_banks2, 1227 .pin_banks = exynos5420_pin_banks2,
1164 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2), 1228 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2),
1165 .eint_gpio_init = exynos_eint_gpio_init, 1229 .eint_gpio_init = exynos_eint_gpio_init,
1166 .label = "exynos5420-gpio-ctrl2",
1167 }, { 1230 }, {
1168 /* pin-controller instance 3 data */ 1231 /* pin-controller instance 3 data */
1169 .pin_banks = exynos5420_pin_banks3, 1232 .pin_banks = exynos5420_pin_banks3,
1170 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3), 1233 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3),
1171 .eint_gpio_init = exynos_eint_gpio_init, 1234 .eint_gpio_init = exynos_eint_gpio_init,
1172 .label = "exynos5420-gpio-ctrl3",
1173 }, { 1235 }, {
1174 /* pin-controller instance 4 data */ 1236 /* pin-controller instance 4 data */
1175 .pin_banks = exynos5420_pin_banks4, 1237 .pin_banks = exynos5420_pin_banks4,
1176 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4), 1238 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4),
1177 .eint_gpio_init = exynos_eint_gpio_init, 1239 .eint_gpio_init = exynos_eint_gpio_init,
1178 .label = "exynos5420-gpio-ctrl4", 1240 },
1241};
1242
1243/* pin banks of exynos7 pin-controller - ALIVE */
1244static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = {
1245 EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
1246 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
1247 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
1248 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
1249};
1250
1251/* pin banks of exynos7 pin-controller - BUS0 */
1252static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = {
1253 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
1254 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04),
1255 EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08),
1256 EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c),
1257 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),
1258 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
1259 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
1260 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c),
1261 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20),
1262 EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24),
1263 EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28),
1264 EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c),
1265 EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30),
1266 EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),
1267 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38),
1268};
1269
1270/* pin banks of exynos7 pin-controller - NFC */
1271static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = {
1272 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
1273};
1274
1275/* pin banks of exynos7 pin-controller - TOUCH */
1276static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = {
1277 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
1278};
1279
1280/* pin banks of exynos7 pin-controller - FF */
1281static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = {
1282 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00),
1283};
1284
1285/* pin banks of exynos7 pin-controller - ESE */
1286static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = {
1287 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00),
1288};
1289
1290/* pin banks of exynos7 pin-controller - FSYS0 */
1291static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = {
1292 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00),
1293};
1294
1295/* pin banks of exynos7 pin-controller - FSYS1 */
1296static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
1297 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00),
1298 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
1299 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08),
1300 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
1301};
1302
1303const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
1304 {
1305 /* pin-controller instance 0 Alive data */
1306 .pin_banks = exynos7_pin_banks0,
1307 .nr_banks = ARRAY_SIZE(exynos7_pin_banks0),
1308 .eint_gpio_init = exynos_eint_gpio_init,
1309 .eint_wkup_init = exynos_eint_wkup_init,
1310 }, {
1311 /* pin-controller instance 1 BUS0 data */
1312 .pin_banks = exynos7_pin_banks1,
1313 .nr_banks = ARRAY_SIZE(exynos7_pin_banks1),
1314 .eint_gpio_init = exynos_eint_gpio_init,
1315 }, {
1316 /* pin-controller instance 2 NFC data */
1317 .pin_banks = exynos7_pin_banks2,
1318 .nr_banks = ARRAY_SIZE(exynos7_pin_banks2),
1319 .eint_gpio_init = exynos_eint_gpio_init,
1320 }, {
1321 /* pin-controller instance 3 TOUCH data */
1322 .pin_banks = exynos7_pin_banks3,
1323 .nr_banks = ARRAY_SIZE(exynos7_pin_banks3),
1324 .eint_gpio_init = exynos_eint_gpio_init,
1325 }, {
1326 /* pin-controller instance 4 FF data */
1327 .pin_banks = exynos7_pin_banks4,
1328 .nr_banks = ARRAY_SIZE(exynos7_pin_banks4),
1329 .eint_gpio_init = exynos_eint_gpio_init,
1330 }, {
1331 /* pin-controller instance 5 ESE data */
1332 .pin_banks = exynos7_pin_banks5,
1333 .nr_banks = ARRAY_SIZE(exynos7_pin_banks5),
1334 .eint_gpio_init = exynos_eint_gpio_init,
1335 }, {
1336 /* pin-controller instance 6 FSYS0 data */
1337 .pin_banks = exynos7_pin_banks6,
1338 .nr_banks = ARRAY_SIZE(exynos7_pin_banks6),
1339 .eint_gpio_init = exynos_eint_gpio_init,
1340 }, {
1341 /* pin-controller instance 7 FSYS1 data */
1342 .pin_banks = exynos7_pin_banks7,
1343 .nr_banks = ARRAY_SIZE(exynos7_pin_banks7),
1344 .eint_gpio_init = exynos_eint_gpio_init,
1179 }, 1345 },
1180}; 1346};
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index 3c91c357792f..0f0f7cedb2dc 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -25,6 +25,9 @@
25#define EXYNOS_WKUP_ECON_OFFSET 0xE00 25#define EXYNOS_WKUP_ECON_OFFSET 0xE00
26#define EXYNOS_WKUP_EMASK_OFFSET 0xF00 26#define EXYNOS_WKUP_EMASK_OFFSET 0xF00
27#define EXYNOS_WKUP_EPEND_OFFSET 0xF40 27#define EXYNOS_WKUP_EPEND_OFFSET 0xF40
28#define EXYNOS7_WKUP_ECON_OFFSET 0x700
29#define EXYNOS7_WKUP_EMASK_OFFSET 0x900
30#define EXYNOS7_WKUP_EPEND_OFFSET 0xA00
28#define EXYNOS_SVC_OFFSET 0xB08 31#define EXYNOS_SVC_OFFSET 0xB08
29#define EXYNOS_EINT_FUNC 0xF 32#define EXYNOS_EINT_FUNC 0xF
30 33
diff --git a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
index ad3eaad17001..f1993f42114c 100644
--- a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
+++ b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
@@ -44,12 +44,12 @@
44#define EINT_EDGE_BOTH 6 44#define EINT_EDGE_BOTH 6
45#define EINT_MASK 0xf 45#define EINT_MASK 0xf
46 46
47static struct samsung_pin_bank_type bank_type_1bit = { 47static const struct samsung_pin_bank_type bank_type_1bit = {
48 .fld_width = { 1, 1, }, 48 .fld_width = { 1, 1, },
49 .reg_offset = { 0x00, 0x04, }, 49 .reg_offset = { 0x00, 0x04, },
50}; 50};
51 51
52static struct samsung_pin_bank_type bank_type_2bit = { 52static const struct samsung_pin_bank_type bank_type_2bit = {
53 .fld_width = { 2, 1, 2, }, 53 .fld_width = { 2, 1, 2, },
54 .reg_offset = { 0x00, 0x04, 0x08, }, 54 .reg_offset = { 0x00, 0x04, 0x08, },
55}; 55};
@@ -143,7 +143,7 @@ static void s3c24xx_eint_set_handler(unsigned int irq, unsigned int type)
143static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d, 143static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d,
144 struct samsung_pin_bank *bank, int pin) 144 struct samsung_pin_bank *bank, int pin)
145{ 145{
146 struct samsung_pin_bank_type *bank_type = bank->type; 146 const struct samsung_pin_bank_type *bank_type = bank->type;
147 unsigned long flags; 147 unsigned long flags;
148 void __iomem *reg; 148 void __iomem *reg;
149 u8 shift; 149 u8 shift;
@@ -518,8 +518,8 @@ static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d)
518 irq_set_handler_data(irq, eint_data); 518 irq_set_handler_data(irq, eint_data);
519 } 519 }
520 520
521 bank = d->ctrl->pin_banks; 521 bank = d->pin_banks;
522 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { 522 for (i = 0; i < d->nr_banks; ++i, ++bank) {
523 struct s3c24xx_eint_domain_data *ddata; 523 struct s3c24xx_eint_domain_data *ddata;
524 unsigned int mask; 524 unsigned int mask;
525 unsigned int irq; 525 unsigned int irq;
@@ -561,7 +561,7 @@ static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d)
561 return 0; 561 return 0;
562} 562}
563 563
564static struct samsung_pin_bank s3c2412_pin_banks[] = { 564static const struct samsung_pin_bank_data s3c2412_pin_banks[] __initconst = {
565 PIN_BANK_A(23, 0x000, "gpa"), 565 PIN_BANK_A(23, 0x000, "gpa"),
566 PIN_BANK_2BIT(11, 0x010, "gpb"), 566 PIN_BANK_2BIT(11, 0x010, "gpb"),
567 PIN_BANK_2BIT(16, 0x020, "gpc"), 567 PIN_BANK_2BIT(16, 0x020, "gpc"),
@@ -573,16 +573,15 @@ static struct samsung_pin_bank s3c2412_pin_banks[] = {
573 PIN_BANK_2BIT(13, 0x080, "gpj"), 573 PIN_BANK_2BIT(13, 0x080, "gpj"),
574}; 574};
575 575
576struct samsung_pin_ctrl s3c2412_pin_ctrl[] = { 576const struct samsung_pin_ctrl s3c2412_pin_ctrl[] __initconst = {
577 { 577 {
578 .pin_banks = s3c2412_pin_banks, 578 .pin_banks = s3c2412_pin_banks,
579 .nr_banks = ARRAY_SIZE(s3c2412_pin_banks), 579 .nr_banks = ARRAY_SIZE(s3c2412_pin_banks),
580 .eint_wkup_init = s3c24xx_eint_init, 580 .eint_wkup_init = s3c24xx_eint_init,
581 .label = "S3C2412-GPIO",
582 }, 581 },
583}; 582};
584 583
585static struct samsung_pin_bank s3c2416_pin_banks[] = { 584static const struct samsung_pin_bank_data s3c2416_pin_banks[] __initconst = {
586 PIN_BANK_A(27, 0x000, "gpa"), 585 PIN_BANK_A(27, 0x000, "gpa"),
587 PIN_BANK_2BIT(11, 0x010, "gpb"), 586 PIN_BANK_2BIT(11, 0x010, "gpb"),
588 PIN_BANK_2BIT(16, 0x020, "gpc"), 587 PIN_BANK_2BIT(16, 0x020, "gpc"),
@@ -596,16 +595,15 @@ static struct samsung_pin_bank s3c2416_pin_banks[] = {
596 PIN_BANK_2BIT(2, 0x100, "gpm"), 595 PIN_BANK_2BIT(2, 0x100, "gpm"),
597}; 596};
598 597
599struct samsung_pin_ctrl s3c2416_pin_ctrl[] = { 598const struct samsung_pin_ctrl s3c2416_pin_ctrl[] __initconst = {
600 { 599 {
601 .pin_banks = s3c2416_pin_banks, 600 .pin_banks = s3c2416_pin_banks,
602 .nr_banks = ARRAY_SIZE(s3c2416_pin_banks), 601 .nr_banks = ARRAY_SIZE(s3c2416_pin_banks),
603 .eint_wkup_init = s3c24xx_eint_init, 602 .eint_wkup_init = s3c24xx_eint_init,
604 .label = "S3C2416-GPIO",
605 }, 603 },
606}; 604};
607 605
608static struct samsung_pin_bank s3c2440_pin_banks[] = { 606static const struct samsung_pin_bank_data s3c2440_pin_banks[] __initconst = {
609 PIN_BANK_A(25, 0x000, "gpa"), 607 PIN_BANK_A(25, 0x000, "gpa"),
610 PIN_BANK_2BIT(11, 0x010, "gpb"), 608 PIN_BANK_2BIT(11, 0x010, "gpb"),
611 PIN_BANK_2BIT(16, 0x020, "gpc"), 609 PIN_BANK_2BIT(16, 0x020, "gpc"),
@@ -617,16 +615,15 @@ static struct samsung_pin_bank s3c2440_pin_banks[] = {
617 PIN_BANK_2BIT(13, 0x0d0, "gpj"), 615 PIN_BANK_2BIT(13, 0x0d0, "gpj"),
618}; 616};
619 617
620struct samsung_pin_ctrl s3c2440_pin_ctrl[] = { 618const struct samsung_pin_ctrl s3c2440_pin_ctrl[] __initconst = {
621 { 619 {
622 .pin_banks = s3c2440_pin_banks, 620 .pin_banks = s3c2440_pin_banks,
623 .nr_banks = ARRAY_SIZE(s3c2440_pin_banks), 621 .nr_banks = ARRAY_SIZE(s3c2440_pin_banks),
624 .eint_wkup_init = s3c24xx_eint_init, 622 .eint_wkup_init = s3c24xx_eint_init,
625 .label = "S3C2440-GPIO",
626 }, 623 },
627}; 624};
628 625
629static struct samsung_pin_bank s3c2450_pin_banks[] = { 626static const struct samsung_pin_bank_data s3c2450_pin_banks[] __initconst = {
630 PIN_BANK_A(28, 0x000, "gpa"), 627 PIN_BANK_A(28, 0x000, "gpa"),
631 PIN_BANK_2BIT(11, 0x010, "gpb"), 628 PIN_BANK_2BIT(11, 0x010, "gpb"),
632 PIN_BANK_2BIT(16, 0x020, "gpc"), 629 PIN_BANK_2BIT(16, 0x020, "gpc"),
@@ -641,11 +638,10 @@ static struct samsung_pin_bank s3c2450_pin_banks[] = {
641 PIN_BANK_2BIT(2, 0x100, "gpm"), 638 PIN_BANK_2BIT(2, 0x100, "gpm"),
642}; 639};
643 640
644struct samsung_pin_ctrl s3c2450_pin_ctrl[] = { 641const struct samsung_pin_ctrl s3c2450_pin_ctrl[] __initconst = {
645 { 642 {
646 .pin_banks = s3c2450_pin_banks, 643 .pin_banks = s3c2450_pin_banks,
647 .nr_banks = ARRAY_SIZE(s3c2450_pin_banks), 644 .nr_banks = ARRAY_SIZE(s3c2450_pin_banks),
648 .eint_wkup_init = s3c24xx_eint_init, 645 .eint_wkup_init = s3c24xx_eint_init,
649 .label = "S3C2450-GPIO",
650 }, 646 },
651}; 647};
diff --git a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
index 89143c903000..7756c1e9e763 100644
--- a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
+++ b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
@@ -68,32 +68,32 @@
68#define EINT_CON_MASK 0xF 68#define EINT_CON_MASK 0xF
69#define EINT_CON_LEN 4 69#define EINT_CON_LEN 4
70 70
71static struct samsung_pin_bank_type bank_type_4bit_off = { 71static const struct samsung_pin_bank_type bank_type_4bit_off = {
72 .fld_width = { 4, 1, 2, 0, 2, 2, }, 72 .fld_width = { 4, 1, 2, 0, 2, 2, },
73 .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, }, 73 .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
74}; 74};
75 75
76static struct samsung_pin_bank_type bank_type_4bit_alive = { 76static const struct samsung_pin_bank_type bank_type_4bit_alive = {
77 .fld_width = { 4, 1, 2, }, 77 .fld_width = { 4, 1, 2, },
78 .reg_offset = { 0x00, 0x04, 0x08, }, 78 .reg_offset = { 0x00, 0x04, 0x08, },
79}; 79};
80 80
81static struct samsung_pin_bank_type bank_type_4bit2_off = { 81static const struct samsung_pin_bank_type bank_type_4bit2_off = {
82 .fld_width = { 4, 1, 2, 0, 2, 2, }, 82 .fld_width = { 4, 1, 2, 0, 2, 2, },
83 .reg_offset = { 0x00, 0x08, 0x0c, 0, 0x10, 0x14, }, 83 .reg_offset = { 0x00, 0x08, 0x0c, 0, 0x10, 0x14, },
84}; 84};
85 85
86static struct samsung_pin_bank_type bank_type_4bit2_alive = { 86static const struct samsung_pin_bank_type bank_type_4bit2_alive = {
87 .fld_width = { 4, 1, 2, }, 87 .fld_width = { 4, 1, 2, },
88 .reg_offset = { 0x00, 0x08, 0x0c, }, 88 .reg_offset = { 0x00, 0x08, 0x0c, },
89}; 89};
90 90
91static struct samsung_pin_bank_type bank_type_2bit_off = { 91static const struct samsung_pin_bank_type bank_type_2bit_off = {
92 .fld_width = { 2, 1, 2, 0, 2, 2, }, 92 .fld_width = { 2, 1, 2, 0, 2, 2, },
93 .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, }, 93 .reg_offset = { 0x00, 0x04, 0x08, 0, 0x0c, 0x10, },
94}; 94};
95 95
96static struct samsung_pin_bank_type bank_type_2bit_alive = { 96static const struct samsung_pin_bank_type bank_type_2bit_alive = {
97 .fld_width = { 2, 1, 2, }, 97 .fld_width = { 2, 1, 2, },
98 .reg_offset = { 0x00, 0x04, 0x08, }, 98 .reg_offset = { 0x00, 0x04, 0x08, },
99}; 99};
@@ -272,7 +272,7 @@ static void s3c64xx_irq_set_handler(unsigned int irq, unsigned int type)
272static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d, 272static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d,
273 struct samsung_pin_bank *bank, int pin) 273 struct samsung_pin_bank *bank, int pin)
274{ 274{
275 struct samsung_pin_bank_type *bank_type = bank->type; 275 const struct samsung_pin_bank_type *bank_type = bank->type;
276 unsigned long flags; 276 unsigned long flags;
277 void __iomem *reg; 277 void __iomem *reg;
278 u8 shift; 278 u8 shift;
@@ -468,8 +468,8 @@ static int s3c64xx_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
468 } 468 }
469 469
470 nr_domains = 0; 470 nr_domains = 0;
471 bank = d->ctrl->pin_banks; 471 bank = d->pin_banks;
472 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { 472 for (i = 0; i < d->nr_banks; ++i, ++bank) {
473 unsigned int nr_eints; 473 unsigned int nr_eints;
474 unsigned int mask; 474 unsigned int mask;
475 475
@@ -497,9 +497,9 @@ static int s3c64xx_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
497 } 497 }
498 data->drvdata = d; 498 data->drvdata = d;
499 499
500 bank = d->ctrl->pin_banks; 500 bank = d->pin_banks;
501 nr_domains = 0; 501 nr_domains = 0;
502 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { 502 for (i = 0; i < d->nr_banks; ++i, ++bank) {
503 if (bank->eint_type != EINT_TYPE_GPIO) 503 if (bank->eint_type != EINT_TYPE_GPIO)
504 continue; 504 continue;
505 505
@@ -735,8 +735,8 @@ static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d)
735 irq_set_handler_data(irq, data); 735 irq_set_handler_data(irq, data);
736 } 736 }
737 737
738 bank = d->ctrl->pin_banks; 738 bank = d->pin_banks;
739 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) { 739 for (i = 0; i < d->nr_banks; ++i, ++bank) {
740 struct s3c64xx_eint0_domain_data *ddata; 740 struct s3c64xx_eint0_domain_data *ddata;
741 unsigned int nr_eints; 741 unsigned int nr_eints;
742 unsigned int mask; 742 unsigned int mask;
@@ -780,7 +780,7 @@ static int s3c64xx_eint_eint0_init(struct samsung_pinctrl_drv_data *d)
780} 780}
781 781
782/* pin banks of s3c64xx pin-controller 0 */ 782/* pin banks of s3c64xx pin-controller 0 */
783static struct samsung_pin_bank s3c64xx_pin_banks0[] = { 783static const struct samsung_pin_bank_data s3c64xx_pin_banks0[] __initconst = {
784 PIN_BANK_4BIT_EINTG(8, 0x000, "gpa", 0), 784 PIN_BANK_4BIT_EINTG(8, 0x000, "gpa", 0),
785 PIN_BANK_4BIT_EINTG(7, 0x020, "gpb", 8), 785 PIN_BANK_4BIT_EINTG(7, 0x020, "gpb", 8),
786 PIN_BANK_4BIT_EINTG(8, 0x040, "gpc", 16), 786 PIN_BANK_4BIT_EINTG(8, 0x040, "gpc", 16),
@@ -804,13 +804,12 @@ static struct samsung_pin_bank s3c64xx_pin_banks0[] = {
804 * Samsung pinctrl driver data for S3C64xx SoC. S3C64xx SoC includes 804 * Samsung pinctrl driver data for S3C64xx SoC. S3C64xx SoC includes
805 * one gpio/pin-mux/pinconfig controller. 805 * one gpio/pin-mux/pinconfig controller.
806 */ 806 */
807struct samsung_pin_ctrl s3c64xx_pin_ctrl[] = { 807const struct samsung_pin_ctrl s3c64xx_pin_ctrl[] __initconst = {
808 { 808 {
809 /* pin-controller instance 1 data */ 809 /* pin-controller instance 1 data */
810 .pin_banks = s3c64xx_pin_banks0, 810 .pin_banks = s3c64xx_pin_banks0,
811 .nr_banks = ARRAY_SIZE(s3c64xx_pin_banks0), 811 .nr_banks = ARRAY_SIZE(s3c64xx_pin_banks0),
812 .eint_gpio_init = s3c64xx_eint_gpio_init, 812 .eint_gpio_init = s3c64xx_eint_gpio_init,
813 .eint_wkup_init = s3c64xx_eint_eint0_init, 813 .eint_wkup_init = s3c64xx_eint_eint0_init,
814 .label = "S3C64xx-GPIO",
815 }, 814 },
816}; 815};
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index 2d37c8f49f3c..32940a01a84f 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -349,7 +349,7 @@ static void pin_to_reg_bank(struct samsung_pinctrl_drv_data *drvdata,
349{ 349{
350 struct samsung_pin_bank *b; 350 struct samsung_pin_bank *b;
351 351
352 b = drvdata->ctrl->pin_banks; 352 b = drvdata->pin_banks;
353 353
354 while ((pin >= b->pin_base) && 354 while ((pin >= b->pin_base) &&
355 ((b->pin_base + b->nr_pins - 1) < pin)) 355 ((b->pin_base + b->nr_pins - 1) < pin))
@@ -366,7 +366,7 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
366 unsigned group, bool enable) 366 unsigned group, bool enable)
367{ 367{
368 struct samsung_pinctrl_drv_data *drvdata; 368 struct samsung_pinctrl_drv_data *drvdata;
369 struct samsung_pin_bank_type *type; 369 const struct samsung_pin_bank_type *type;
370 struct samsung_pin_bank *bank; 370 struct samsung_pin_bank *bank;
371 void __iomem *reg; 371 void __iomem *reg;
372 u32 mask, shift, data, pin_offset; 372 u32 mask, shift, data, pin_offset;
@@ -378,7 +378,7 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
378 func = &drvdata->pmx_functions[selector]; 378 func = &drvdata->pmx_functions[selector];
379 grp = &drvdata->pin_groups[group]; 379 grp = &drvdata->pin_groups[group];
380 380
381 pin_to_reg_bank(drvdata, grp->pins[0] - drvdata->ctrl->base, 381 pin_to_reg_bank(drvdata, grp->pins[0] - drvdata->pin_base,
382 &reg, &pin_offset, &bank); 382 &reg, &pin_offset, &bank);
383 type = bank->type; 383 type = bank->type;
384 mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1; 384 mask = (1 << type->fld_width[PINCFG_TYPE_FUNC]) - 1;
@@ -422,7 +422,7 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
422 unsigned long *config, bool set) 422 unsigned long *config, bool set)
423{ 423{
424 struct samsung_pinctrl_drv_data *drvdata; 424 struct samsung_pinctrl_drv_data *drvdata;
425 struct samsung_pin_bank_type *type; 425 const struct samsung_pin_bank_type *type;
426 struct samsung_pin_bank *bank; 426 struct samsung_pin_bank *bank;
427 void __iomem *reg_base; 427 void __iomem *reg_base;
428 enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config); 428 enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config);
@@ -431,7 +431,7 @@ static int samsung_pinconf_rw(struct pinctrl_dev *pctldev, unsigned int pin,
431 unsigned long flags; 431 unsigned long flags;
432 432
433 drvdata = pinctrl_dev_get_drvdata(pctldev); 433 drvdata = pinctrl_dev_get_drvdata(pctldev);
434 pin_to_reg_bank(drvdata, pin - drvdata->ctrl->base, &reg_base, 434 pin_to_reg_bank(drvdata, pin - drvdata->pin_base, &reg_base,
435 &pin_offset, &bank); 435 &pin_offset, &bank);
436 type = bank->type; 436 type = bank->type;
437 437
@@ -528,7 +528,7 @@ static const struct pinconf_ops samsung_pinconf_ops = {
528static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 528static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
529{ 529{
530 struct samsung_pin_bank *bank = gc_to_pin_bank(gc); 530 struct samsung_pin_bank *bank = gc_to_pin_bank(gc);
531 struct samsung_pin_bank_type *type = bank->type; 531 const struct samsung_pin_bank_type *type = bank->type;
532 unsigned long flags; 532 unsigned long flags;
533 void __iomem *reg; 533 void __iomem *reg;
534 u32 data; 534 u32 data;
@@ -552,7 +552,7 @@ static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset)
552 void __iomem *reg; 552 void __iomem *reg;
553 u32 data; 553 u32 data;
554 struct samsung_pin_bank *bank = gc_to_pin_bank(gc); 554 struct samsung_pin_bank *bank = gc_to_pin_bank(gc);
555 struct samsung_pin_bank_type *type = bank->type; 555 const struct samsung_pin_bank_type *type = bank->type;
556 556
557 reg = bank->drvdata->virt_base + bank->pctl_offset; 557 reg = bank->drvdata->virt_base + bank->pctl_offset;
558 558
@@ -569,7 +569,7 @@ static int samsung_gpio_get(struct gpio_chip *gc, unsigned offset)
569static int samsung_gpio_set_direction(struct gpio_chip *gc, 569static int samsung_gpio_set_direction(struct gpio_chip *gc,
570 unsigned offset, bool input) 570 unsigned offset, bool input)
571{ 571{
572 struct samsung_pin_bank_type *type; 572 const struct samsung_pin_bank_type *type;
573 struct samsung_pin_bank *bank; 573 struct samsung_pin_bank *bank;
574 struct samsung_pinctrl_drv_data *drvdata; 574 struct samsung_pinctrl_drv_data *drvdata;
575 void __iomem *reg; 575 void __iomem *reg;
@@ -834,32 +834,32 @@ static int samsung_pinctrl_register(struct platform_device *pdev,
834 ctrldesc->confops = &samsung_pinconf_ops; 834 ctrldesc->confops = &samsung_pinconf_ops;
835 835
836 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * 836 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
837 drvdata->ctrl->nr_pins, GFP_KERNEL); 837 drvdata->nr_pins, GFP_KERNEL);
838 if (!pindesc) { 838 if (!pindesc) {
839 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); 839 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
840 return -ENOMEM; 840 return -ENOMEM;
841 } 841 }
842 ctrldesc->pins = pindesc; 842 ctrldesc->pins = pindesc;
843 ctrldesc->npins = drvdata->ctrl->nr_pins; 843 ctrldesc->npins = drvdata->nr_pins;
844 844
845 /* dynamically populate the pin number and pin name for pindesc */ 845 /* dynamically populate the pin number and pin name for pindesc */
846 for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++) 846 for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++)
847 pdesc->number = pin + drvdata->ctrl->base; 847 pdesc->number = pin + drvdata->pin_base;
848 848
849 /* 849 /*
850 * allocate space for storing the dynamically generated names for all 850 * allocate space for storing the dynamically generated names for all
851 * the pins which belong to this pin-controller. 851 * the pins which belong to this pin-controller.
852 */ 852 */
853 pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH * 853 pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH *
854 drvdata->ctrl->nr_pins, GFP_KERNEL); 854 drvdata->nr_pins, GFP_KERNEL);
855 if (!pin_names) { 855 if (!pin_names) {
856 dev_err(&pdev->dev, "mem alloc for pin names failed\n"); 856 dev_err(&pdev->dev, "mem alloc for pin names failed\n");
857 return -ENOMEM; 857 return -ENOMEM;
858 } 858 }
859 859
860 /* for each pin, the name of the pin is pin-bank name + pin number */ 860 /* for each pin, the name of the pin is pin-bank name + pin number */
861 for (bank = 0; bank < drvdata->ctrl->nr_banks; bank++) { 861 for (bank = 0; bank < drvdata->nr_banks; bank++) {
862 pin_bank = &drvdata->ctrl->pin_banks[bank]; 862 pin_bank = &drvdata->pin_banks[bank];
863 for (pin = 0; pin < pin_bank->nr_pins; pin++) { 863 for (pin = 0; pin < pin_bank->nr_pins; pin++) {
864 sprintf(pin_names, "%s-%d", pin_bank->name, pin); 864 sprintf(pin_names, "%s-%d", pin_bank->name, pin);
865 pdesc = pindesc + pin_bank->pin_base + pin; 865 pdesc = pindesc + pin_bank->pin_base + pin;
@@ -878,11 +878,11 @@ static int samsung_pinctrl_register(struct platform_device *pdev,
878 return -EINVAL; 878 return -EINVAL;
879 } 879 }
880 880
881 for (bank = 0; bank < drvdata->ctrl->nr_banks; ++bank) { 881 for (bank = 0; bank < drvdata->nr_banks; ++bank) {
882 pin_bank = &drvdata->ctrl->pin_banks[bank]; 882 pin_bank = &drvdata->pin_banks[bank];
883 pin_bank->grange.name = pin_bank->name; 883 pin_bank->grange.name = pin_bank->name;
884 pin_bank->grange.id = bank; 884 pin_bank->grange.id = bank;
885 pin_bank->grange.pin_base = drvdata->ctrl->base 885 pin_bank->grange.pin_base = drvdata->pin_base
886 + pin_bank->pin_base; 886 + pin_bank->pin_base;
887 pin_bank->grange.base = pin_bank->gpio_chip.base; 887 pin_bank->grange.base = pin_bank->gpio_chip.base;
888 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; 888 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
@@ -918,17 +918,16 @@ static const struct gpio_chip samsung_gpiolib_chip = {
918static int samsung_gpiolib_register(struct platform_device *pdev, 918static int samsung_gpiolib_register(struct platform_device *pdev,
919 struct samsung_pinctrl_drv_data *drvdata) 919 struct samsung_pinctrl_drv_data *drvdata)
920{ 920{
921 struct samsung_pin_ctrl *ctrl = drvdata->ctrl; 921 struct samsung_pin_bank *bank = drvdata->pin_banks;
922 struct samsung_pin_bank *bank = ctrl->pin_banks;
923 struct gpio_chip *gc; 922 struct gpio_chip *gc;
924 int ret; 923 int ret;
925 int i; 924 int i;
926 925
927 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 926 for (i = 0; i < drvdata->nr_banks; ++i, ++bank) {
928 bank->gpio_chip = samsung_gpiolib_chip; 927 bank->gpio_chip = samsung_gpiolib_chip;
929 928
930 gc = &bank->gpio_chip; 929 gc = &bank->gpio_chip;
931 gc->base = ctrl->base + bank->pin_base; 930 gc->base = drvdata->pin_base + bank->pin_base;
932 gc->ngpio = bank->nr_pins; 931 gc->ngpio = bank->nr_pins;
933 gc->dev = &pdev->dev; 932 gc->dev = &pdev->dev;
934 gc->of_node = bank->of_node; 933 gc->of_node = bank->of_node;
@@ -954,51 +953,70 @@ fail:
954static int samsung_gpiolib_unregister(struct platform_device *pdev, 953static int samsung_gpiolib_unregister(struct platform_device *pdev,
955 struct samsung_pinctrl_drv_data *drvdata) 954 struct samsung_pinctrl_drv_data *drvdata)
956{ 955{
957 struct samsung_pin_ctrl *ctrl = drvdata->ctrl; 956 struct samsung_pin_bank *bank = drvdata->pin_banks;
958 struct samsung_pin_bank *bank = ctrl->pin_banks;
959 int i; 957 int i;
960 958
961 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) 959 for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
962 gpiochip_remove(&bank->gpio_chip); 960 gpiochip_remove(&bank->gpio_chip);
961
963 return 0; 962 return 0;
964} 963}
965 964
966static const struct of_device_id samsung_pinctrl_dt_match[]; 965static const struct of_device_id samsung_pinctrl_dt_match[];
967 966
968/* retrieve the soc specific data */ 967/* retrieve the soc specific data */
969static struct samsung_pin_ctrl *samsung_pinctrl_get_soc_data( 968static const struct samsung_pin_ctrl *
970 struct samsung_pinctrl_drv_data *d, 969samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
971 struct platform_device *pdev) 970 struct platform_device *pdev)
972{ 971{
973 int id; 972 int id;
974 const struct of_device_id *match; 973 const struct of_device_id *match;
975 struct device_node *node = pdev->dev.of_node; 974 struct device_node *node = pdev->dev.of_node;
976 struct device_node *np; 975 struct device_node *np;
977 struct samsung_pin_ctrl *ctrl; 976 const struct samsung_pin_bank_data *bdata;
977 const struct samsung_pin_ctrl *ctrl;
978 struct samsung_pin_bank *bank; 978 struct samsung_pin_bank *bank;
979 int i; 979 int i;
980 980
981 id = of_alias_get_id(node, "pinctrl"); 981 id = of_alias_get_id(node, "pinctrl");
982 if (id < 0) { 982 if (id < 0) {
983 dev_err(&pdev->dev, "failed to get alias id\n"); 983 dev_err(&pdev->dev, "failed to get alias id\n");
984 return NULL; 984 return ERR_PTR(-ENOENT);
985 } 985 }
986 match = of_match_node(samsung_pinctrl_dt_match, node); 986 match = of_match_node(samsung_pinctrl_dt_match, node);
987 ctrl = (struct samsung_pin_ctrl *)match->data + id; 987 ctrl = (struct samsung_pin_ctrl *)match->data + id;
988 988
989 bank = ctrl->pin_banks; 989 d->suspend = ctrl->suspend;
990 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 990 d->resume = ctrl->resume;
991 d->nr_banks = ctrl->nr_banks;
992 d->pin_banks = devm_kcalloc(&pdev->dev, d->nr_banks,
993 sizeof(*d->pin_banks), GFP_KERNEL);
994 if (!d->pin_banks)
995 return ERR_PTR(-ENOMEM);
996
997 bank = d->pin_banks;
998 bdata = ctrl->pin_banks;
999 for (i = 0; i < ctrl->nr_banks; ++i, ++bdata, ++bank) {
1000 bank->type = bdata->type;
1001 bank->pctl_offset = bdata->pctl_offset;
1002 bank->nr_pins = bdata->nr_pins;
1003 bank->eint_func = bdata->eint_func;
1004 bank->eint_type = bdata->eint_type;
1005 bank->eint_mask = bdata->eint_mask;
1006 bank->eint_offset = bdata->eint_offset;
1007 bank->name = bdata->name;
1008
991 spin_lock_init(&bank->slock); 1009 spin_lock_init(&bank->slock);
992 bank->drvdata = d; 1010 bank->drvdata = d;
993 bank->pin_base = ctrl->nr_pins; 1011 bank->pin_base = d->nr_pins;
994 ctrl->nr_pins += bank->nr_pins; 1012 d->nr_pins += bank->nr_pins;
995 } 1013 }
996 1014
997 for_each_child_of_node(node, np) { 1015 for_each_child_of_node(node, np) {
998 if (!of_find_property(np, "gpio-controller", NULL)) 1016 if (!of_find_property(np, "gpio-controller", NULL))
999 continue; 1017 continue;
1000 bank = ctrl->pin_banks; 1018 bank = d->pin_banks;
1001 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1019 for (i = 0; i < d->nr_banks; ++i, ++bank) {
1002 if (!strcmp(bank->name, np->name)) { 1020 if (!strcmp(bank->name, np->name)) {
1003 bank->of_node = np; 1021 bank->of_node = np;
1004 break; 1022 break;
@@ -1006,8 +1024,8 @@ static struct samsung_pin_ctrl *samsung_pinctrl_get_soc_data(
1006 } 1024 }
1007 } 1025 }
1008 1026
1009 ctrl->base = pin_base; 1027 d->pin_base = pin_base;
1010 pin_base += ctrl->nr_pins; 1028 pin_base += d->nr_pins;
1011 1029
1012 return ctrl; 1030 return ctrl;
1013} 1031}
@@ -1015,8 +1033,8 @@ static struct samsung_pin_ctrl *samsung_pinctrl_get_soc_data(
1015static int samsung_pinctrl_probe(struct platform_device *pdev) 1033static int samsung_pinctrl_probe(struct platform_device *pdev)
1016{ 1034{
1017 struct samsung_pinctrl_drv_data *drvdata; 1035 struct samsung_pinctrl_drv_data *drvdata;
1036 const struct samsung_pin_ctrl *ctrl;
1018 struct device *dev = &pdev->dev; 1037 struct device *dev = &pdev->dev;
1019 struct samsung_pin_ctrl *ctrl;
1020 struct resource *res; 1038 struct resource *res;
1021 int ret; 1039 int ret;
1022 1040
@@ -1033,11 +1051,10 @@ static int samsung_pinctrl_probe(struct platform_device *pdev)
1033 } 1051 }
1034 1052
1035 ctrl = samsung_pinctrl_get_soc_data(drvdata, pdev); 1053 ctrl = samsung_pinctrl_get_soc_data(drvdata, pdev);
1036 if (!ctrl) { 1054 if (IS_ERR(ctrl)) {
1037 dev_err(&pdev->dev, "driver data not available\n"); 1055 dev_err(&pdev->dev, "driver data not available\n");
1038 return -EINVAL; 1056 return PTR_ERR(ctrl);
1039 } 1057 }
1040 drvdata->ctrl = ctrl;
1041 drvdata->dev = dev; 1058 drvdata->dev = dev;
1042 1059
1043 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1060 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1082,16 +1099,14 @@ static int samsung_pinctrl_probe(struct platform_device *pdev)
1082static void samsung_pinctrl_suspend_dev( 1099static void samsung_pinctrl_suspend_dev(
1083 struct samsung_pinctrl_drv_data *drvdata) 1100 struct samsung_pinctrl_drv_data *drvdata)
1084{ 1101{
1085 struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
1086 void __iomem *virt_base = drvdata->virt_base; 1102 void __iomem *virt_base = drvdata->virt_base;
1087 int i; 1103 int i;
1088 1104
1089 for (i = 0; i < ctrl->nr_banks; i++) { 1105 for (i = 0; i < drvdata->nr_banks; i++) {
1090 struct samsung_pin_bank *bank = &ctrl->pin_banks[i]; 1106 struct samsung_pin_bank *bank = &drvdata->pin_banks[i];
1091 void __iomem *reg = virt_base + bank->pctl_offset; 1107 void __iomem *reg = virt_base + bank->pctl_offset;
1092 1108 const u8 *offs = bank->type->reg_offset;
1093 u8 *offs = bank->type->reg_offset; 1109 const u8 *widths = bank->type->fld_width;
1094 u8 *widths = bank->type->fld_width;
1095 enum pincfg_type type; 1110 enum pincfg_type type;
1096 1111
1097 /* Registers without a powerdown config aren't lost */ 1112 /* Registers without a powerdown config aren't lost */
@@ -1116,8 +1131,8 @@ static void samsung_pinctrl_suspend_dev(
1116 } 1131 }
1117 } 1132 }
1118 1133
1119 if (ctrl->suspend) 1134 if (drvdata->suspend)
1120 ctrl->suspend(drvdata); 1135 drvdata->suspend(drvdata);
1121} 1136}
1122 1137
1123/** 1138/**
@@ -1130,19 +1145,17 @@ static void samsung_pinctrl_suspend_dev(
1130 */ 1145 */
1131static void samsung_pinctrl_resume_dev(struct samsung_pinctrl_drv_data *drvdata) 1146static void samsung_pinctrl_resume_dev(struct samsung_pinctrl_drv_data *drvdata)
1132{ 1147{
1133 struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
1134 void __iomem *virt_base = drvdata->virt_base; 1148 void __iomem *virt_base = drvdata->virt_base;
1135 int i; 1149 int i;
1136 1150
1137 if (ctrl->resume) 1151 if (drvdata->resume)
1138 ctrl->resume(drvdata); 1152 drvdata->resume(drvdata);
1139 1153
1140 for (i = 0; i < ctrl->nr_banks; i++) { 1154 for (i = 0; i < drvdata->nr_banks; i++) {
1141 struct samsung_pin_bank *bank = &ctrl->pin_banks[i]; 1155 struct samsung_pin_bank *bank = &drvdata->pin_banks[i];
1142 void __iomem *reg = virt_base + bank->pctl_offset; 1156 void __iomem *reg = virt_base + bank->pctl_offset;
1143 1157 const u8 *offs = bank->type->reg_offset;
1144 u8 *offs = bank->type->reg_offset; 1158 const u8 *widths = bank->type->fld_width;
1145 u8 *widths = bank->type->fld_width;
1146 enum pincfg_type type; 1159 enum pincfg_type type;
1147 1160
1148 /* Registers without a powerdown config aren't lost */ 1161 /* Registers without a powerdown config aren't lost */
@@ -1218,6 +1231,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
1218 .data = (void *)exynos4210_pin_ctrl }, 1231 .data = (void *)exynos4210_pin_ctrl },
1219 { .compatible = "samsung,exynos4x12-pinctrl", 1232 { .compatible = "samsung,exynos4x12-pinctrl",
1220 .data = (void *)exynos4x12_pin_ctrl }, 1233 .data = (void *)exynos4x12_pin_ctrl },
1234 { .compatible = "samsung,exynos4415-pinctrl",
1235 .data = (void *)exynos4415_pin_ctrl },
1221 { .compatible = "samsung,exynos5250-pinctrl", 1236 { .compatible = "samsung,exynos5250-pinctrl",
1222 .data = (void *)exynos5250_pin_ctrl }, 1237 .data = (void *)exynos5250_pin_ctrl },
1223 { .compatible = "samsung,exynos5260-pinctrl", 1238 { .compatible = "samsung,exynos5260-pinctrl",
@@ -1226,6 +1241,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
1226 .data = (void *)exynos5420_pin_ctrl }, 1241 .data = (void *)exynos5420_pin_ctrl },
1227 { .compatible = "samsung,s5pv210-pinctrl", 1242 { .compatible = "samsung,s5pv210-pinctrl",
1228 .data = (void *)s5pv210_pin_ctrl }, 1243 .data = (void *)s5pv210_pin_ctrl },
1244 { .compatible = "samsung,exynos7-pinctrl",
1245 .data = (void *)exynos7_pin_ctrl },
1229#endif 1246#endif
1230#ifdef CONFIG_PINCTRL_S3C64XX 1247#ifdef CONFIG_PINCTRL_S3C64XX
1231 { .compatible = "samsung,s3c64xx-pinctrl", 1248 { .compatible = "samsung,s3c64xx-pinctrl",
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 5cedc9d26390..1b8c0139d604 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -113,39 +113,66 @@ struct samsung_pin_bank_type {
113}; 113};
114 114
115/** 115/**
116 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
117 * @type: type of the bank (register offsets and bitfield widths)
118 * @pctl_offset: starting offset of the pin-bank registers.
119 * @nr_pins: number of pins included in this bank.
120 * @eint_func: function to set in CON register to configure pin as EINT.
121 * @eint_type: type of the external interrupt supported by the bank.
122 * @eint_mask: bit mask of pins which support EINT function.
123 * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
124 * @name: name to be prefixed for each pin in this pin bank.
125 */
126struct samsung_pin_bank_data {
127 const struct samsung_pin_bank_type *type;
128 u32 pctl_offset;
129 u8 nr_pins;
130 u8 eint_func;
131 enum eint_type eint_type;
132 u32 eint_mask;
133 u32 eint_offset;
134 const char *name;
135};
136
137/**
116 * struct samsung_pin_bank: represent a controller pin-bank. 138 * struct samsung_pin_bank: represent a controller pin-bank.
117 * @type: type of the bank (register offsets and bitfield widths) 139 * @type: type of the bank (register offsets and bitfield widths)
118 * @pctl_offset: starting offset of the pin-bank registers. 140 * @pctl_offset: starting offset of the pin-bank registers.
119 * @pin_base: starting pin number of the bank.
120 * @nr_pins: number of pins included in this bank. 141 * @nr_pins: number of pins included in this bank.
121 * @eint_func: function to set in CON register to configure pin as EINT. 142 * @eint_func: function to set in CON register to configure pin as EINT.
122 * @eint_type: type of the external interrupt supported by the bank. 143 * @eint_type: type of the external interrupt supported by the bank.
123 * @eint_mask: bit mask of pins which support EINT function. 144 * @eint_mask: bit mask of pins which support EINT function.
145 * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
124 * @name: name to be prefixed for each pin in this pin bank. 146 * @name: name to be prefixed for each pin in this pin bank.
147 * @pin_base: starting pin number of the bank.
148 * @soc_priv: per-bank private data for SoC-specific code.
125 * @of_node: OF node of the bank. 149 * @of_node: OF node of the bank.
126 * @drvdata: link to controller driver data 150 * @drvdata: link to controller driver data
127 * @irq_domain: IRQ domain of the bank. 151 * @irq_domain: IRQ domain of the bank.
128 * @gpio_chip: GPIO chip of the bank. 152 * @gpio_chip: GPIO chip of the bank.
129 * @grange: linux gpio pin range supported by this bank. 153 * @grange: linux gpio pin range supported by this bank.
154 * @irq_chip: link to irq chip for external gpio and wakeup interrupts.
130 * @slock: spinlock protecting bank registers 155 * @slock: spinlock protecting bank registers
131 * @pm_save: saved register values during suspend 156 * @pm_save: saved register values during suspend
132 */ 157 */
133struct samsung_pin_bank { 158struct samsung_pin_bank {
134 struct samsung_pin_bank_type *type; 159 const struct samsung_pin_bank_type *type;
135 u32 pctl_offset; 160 u32 pctl_offset;
136 u32 pin_base;
137 u8 nr_pins; 161 u8 nr_pins;
138 u8 eint_func; 162 u8 eint_func;
139 enum eint_type eint_type; 163 enum eint_type eint_type;
140 u32 eint_mask; 164 u32 eint_mask;
141 u32 eint_offset; 165 u32 eint_offset;
142 char *name; 166 const char *name;
167
168 u32 pin_base;
143 void *soc_priv; 169 void *soc_priv;
144 struct device_node *of_node; 170 struct device_node *of_node;
145 struct samsung_pinctrl_drv_data *drvdata; 171 struct samsung_pinctrl_drv_data *drvdata;
146 struct irq_domain *irq_domain; 172 struct irq_domain *irq_domain;
147 struct gpio_chip gpio_chip; 173 struct gpio_chip gpio_chip;
148 struct pinctrl_gpio_range grange; 174 struct pinctrl_gpio_range grange;
175 struct exynos_irq_chip *irq_chip;
149 spinlock_t slock; 176 spinlock_t slock;
150 177
151 u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/ 178 u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
@@ -155,27 +182,19 @@ struct samsung_pin_bank {
155 * struct samsung_pin_ctrl: represent a pin controller. 182 * struct samsung_pin_ctrl: represent a pin controller.
156 * @pin_banks: list of pin banks included in this controller. 183 * @pin_banks: list of pin banks included in this controller.
157 * @nr_banks: number of pin banks. 184 * @nr_banks: number of pin banks.
158 * @base: starting system wide pin number.
159 * @nr_pins: number of pins supported by the controller.
160 * @eint_gpio_init: platform specific callback to setup the external gpio 185 * @eint_gpio_init: platform specific callback to setup the external gpio
161 * interrupts for the controller. 186 * interrupts for the controller.
162 * @eint_wkup_init: platform specific callback to setup the external wakeup 187 * @eint_wkup_init: platform specific callback to setup the external wakeup
163 * interrupts for the controller. 188 * interrupts for the controller.
164 * @label: for debug information.
165 */ 189 */
166struct samsung_pin_ctrl { 190struct samsung_pin_ctrl {
167 struct samsung_pin_bank *pin_banks; 191 const struct samsung_pin_bank_data *pin_banks;
168 u32 nr_banks; 192 u32 nr_banks;
169 193
170 u32 base;
171 u32 nr_pins;
172
173 int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *); 194 int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
174 int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *); 195 int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
175 void (*suspend)(struct samsung_pinctrl_drv_data *); 196 void (*suspend)(struct samsung_pinctrl_drv_data *);
176 void (*resume)(struct samsung_pinctrl_drv_data *); 197 void (*resume)(struct samsung_pinctrl_drv_data *);
177
178 char *label;
179}; 198};
180 199
181/** 200/**
@@ -191,6 +210,8 @@ struct samsung_pin_ctrl {
191 * @nr_groups: number of such pin groups. 210 * @nr_groups: number of such pin groups.
192 * @pmx_functions: list of pin functions available to the driver. 211 * @pmx_functions: list of pin functions available to the driver.
193 * @nr_function: number of such pin functions. 212 * @nr_function: number of such pin functions.
213 * @pin_base: starting system wide pin number.
214 * @nr_pins: number of pins supported by the controller.
194 */ 215 */
195struct samsung_pinctrl_drv_data { 216struct samsung_pinctrl_drv_data {
196 struct list_head node; 217 struct list_head node;
@@ -198,7 +219,6 @@ struct samsung_pinctrl_drv_data {
198 struct device *dev; 219 struct device *dev;
199 int irq; 220 int irq;
200 221
201 struct samsung_pin_ctrl *ctrl;
202 struct pinctrl_desc pctl; 222 struct pinctrl_desc pctl;
203 struct pinctrl_dev *pctl_dev; 223 struct pinctrl_dev *pctl_dev;
204 224
@@ -206,6 +226,14 @@ struct samsung_pinctrl_drv_data {
206 unsigned int nr_groups; 226 unsigned int nr_groups;
207 const struct samsung_pmx_func *pmx_functions; 227 const struct samsung_pmx_func *pmx_functions;
208 unsigned int nr_functions; 228 unsigned int nr_functions;
229
230 struct samsung_pin_bank *pin_banks;
231 u32 nr_banks;
232 unsigned int pin_base;
233 unsigned int nr_pins;
234
235 void (*suspend)(struct samsung_pinctrl_drv_data *);
236 void (*resume)(struct samsung_pinctrl_drv_data *);
209}; 237};
210 238
211/** 239/**
@@ -236,17 +264,19 @@ struct samsung_pmx_func {
236}; 264};
237 265
238/* list of all exported SoC specific data */ 266/* list of all exported SoC specific data */
239extern struct samsung_pin_ctrl exynos3250_pin_ctrl[]; 267extern const struct samsung_pin_ctrl exynos3250_pin_ctrl[];
240extern struct samsung_pin_ctrl exynos4210_pin_ctrl[]; 268extern const struct samsung_pin_ctrl exynos4210_pin_ctrl[];
241extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; 269extern const struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
242extern struct samsung_pin_ctrl exynos5250_pin_ctrl[]; 270extern const struct samsung_pin_ctrl exynos4415_pin_ctrl[];
243extern struct samsung_pin_ctrl exynos5260_pin_ctrl[]; 271extern const struct samsung_pin_ctrl exynos5250_pin_ctrl[];
244extern struct samsung_pin_ctrl exynos5420_pin_ctrl[]; 272extern const struct samsung_pin_ctrl exynos5260_pin_ctrl[];
245extern struct samsung_pin_ctrl s3c64xx_pin_ctrl[]; 273extern const struct samsung_pin_ctrl exynos5420_pin_ctrl[];
246extern struct samsung_pin_ctrl s3c2412_pin_ctrl[]; 274extern const struct samsung_pin_ctrl exynos7_pin_ctrl[];
247extern struct samsung_pin_ctrl s3c2416_pin_ctrl[]; 275extern const struct samsung_pin_ctrl s3c64xx_pin_ctrl[];
248extern struct samsung_pin_ctrl s3c2440_pin_ctrl[]; 276extern const struct samsung_pin_ctrl s3c2412_pin_ctrl[];
249extern struct samsung_pin_ctrl s3c2450_pin_ctrl[]; 277extern const struct samsung_pin_ctrl s3c2416_pin_ctrl[];
250extern struct samsung_pin_ctrl s5pv210_pin_ctrl[]; 278extern const struct samsung_pin_ctrl s3c2440_pin_ctrl[];
279extern const struct samsung_pin_ctrl s3c2450_pin_ctrl[];
280extern const struct samsung_pin_ctrl s5pv210_pin_ctrl[];
251 281
252#endif /* __PINCTRL_SAMSUNG_H */ 282#endif /* __PINCTRL_SAMSUNG_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 19:42:54 -0400