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-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c12
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c16
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c290
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c3
-rw-r--r--drivers/gpu/drm/amd/display/modules/color/color_gamma.c8
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h14
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h18
-rw-r--r--drivers/gpu/drm/amd/include/atomfirmware.h88
-rw-r--r--drivers/gpu/drm/amd/powerplay/amd_powerplay.c9
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c42
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c102
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h115
-rw-r--r--drivers/gpu/drm/radeon/mkregtable.c2
-rw-r--r--drivers/gpu/drm/radeon/r100_track.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_dp_mst.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_tv.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_trace.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_trace_points.c2
-rw-r--r--drivers/gpu/drm/scheduler/sched_main.c59
-rw-r--r--include/drm/drm_pciids.h2
23 files changed, 567 insertions, 229 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index f5fb93795a69..dd9a4fb9ce39 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -826,21 +826,13 @@ int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
826{ 826{
827 struct drm_minor *minor = adev->ddev->primary; 827 struct drm_minor *minor = adev->ddev->primary;
828 struct dentry *ent, *root = minor->debugfs_root; 828 struct dentry *ent, *root = minor->debugfs_root;
829 unsigned i, j; 829 unsigned int i;
830 830
831 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) { 831 for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
832 ent = debugfs_create_file(debugfs_regs_names[i], 832 ent = debugfs_create_file(debugfs_regs_names[i],
833 S_IFREG | S_IRUGO, root, 833 S_IFREG | S_IRUGO, root,
834 adev, debugfs_regs[i]); 834 adev, debugfs_regs[i]);
835 if (IS_ERR(ent)) { 835 if (!i && !IS_ERR_OR_NULL(ent))
836 for (j = 0; j < i; j++) {
837 debugfs_remove(adev->debugfs_regs[i]);
838 adev->debugfs_regs[i] = NULL;
839 }
840 return PTR_ERR(ent);
841 }
842
843 if (!i)
844 i_size_write(ent->d_inode, adev->rmmio_size); 836 i_size_write(ent->d_inode, adev->rmmio_size);
845 adev->debugfs_regs[i] = ent; 837 adev->debugfs_regs[i] = ent;
846 } 838 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index 3a072a7a39f0..df9b173c3d0b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -574,7 +574,7 @@ void amdgpu_vmid_mgr_init(struct amdgpu_device *adev)
574 /* skip over VMID 0, since it is the system VM */ 574 /* skip over VMID 0, since it is the system VM */
575 for (j = 1; j < id_mgr->num_ids; ++j) { 575 for (j = 1; j < id_mgr->num_ids; ++j) {
576 amdgpu_vmid_reset(adev, i, j); 576 amdgpu_vmid_reset(adev, i, j);
577 amdgpu_sync_create(&id_mgr->ids[i].active); 577 amdgpu_sync_create(&id_mgr->ids[j].active);
578 list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru); 578 list_add_tail(&id_mgr->ids[j].list, &id_mgr->ids_lru);
579 } 579 }
580 } 580 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c
index b160b958e5fe..f212402570a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.c
@@ -1,4 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: MIT
2/* Copyright Red Hat Inc 2010. 2/* Copyright Red Hat Inc 2010.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index e61f6a3ca241..6d7baf59d6e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -97,6 +97,7 @@ MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
97static const struct soc15_reg_golden golden_settings_gc_9_0[] = 97static const struct soc15_reg_golden golden_settings_gc_9_0[] =
98{ 98{
99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000),
100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
@@ -4904,7 +4905,20 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4904static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) 4905static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4905{ 4906{
4906 /* init asci gds info */ 4907 /* init asci gds info */
4907 adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); 4908 switch (adev->asic_type) {
4909 case CHIP_VEGA10:
4910 case CHIP_VEGA12:
4911 case CHIP_VEGA20:
4912 adev->gds.mem.total_size = 0x10000;
4913 break;
4914 case CHIP_RAVEN:
4915 adev->gds.mem.total_size = 0x1000;
4916 break;
4917 default:
4918 adev->gds.mem.total_size = 0x10000;
4919 break;
4920 }
4921
4908 adev->gds.gws.total_size = 64; 4922 adev->gds.gws.total_size = 64;
4909 adev->gds.oa.total_size = 16; 4923 adev->gds.oa.total_size = 16;
4910 4924
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index c20d413f277c..04fa3d972636 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -148,6 +148,7 @@ static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
148 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 148 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
149 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 149 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
150 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 150 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
151 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xFE000000, 0x00000000),
151}; 152};
152 153
153static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = { 154static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
@@ -177,6 +178,7 @@ static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
177 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001), 178 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
178 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 179 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
179 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 180 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
181 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xFE000000, 0x00000000),
180}; 182};
181 183
182static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 184static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index e9282415c24f..eae90922fdbe 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -37,6 +37,11 @@
37 37
38#include "ivsrcid/vcn/irqsrcs_vcn_1_0.h" 38#include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
39 39
40#define mmUVD_RBC_XX_IB_REG_CHECK 0x05ab
41#define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 1
42#define mmUVD_REG_XX_MASK 0x05ac
43#define mmUVD_REG_XX_MASK_BASE_IDX 1
44
40static int vcn_v1_0_stop(struct amdgpu_device *adev); 45static int vcn_v1_0_stop(struct amdgpu_device *adev);
41static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); 46static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
42static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); 47static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
@@ -320,6 +325,24 @@ static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
320 adev->gfx.config.gb_addr_config); 325 adev->gfx.config.gb_addr_config);
321 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 326 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
322 adev->gfx.config.gb_addr_config); 327 adev->gfx.config.gb_addr_config);
328 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
329 adev->gfx.config.gb_addr_config);
330 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
331 adev->gfx.config.gb_addr_config);
332 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
333 adev->gfx.config.gb_addr_config);
334 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
335 adev->gfx.config.gb_addr_config);
336 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
337 adev->gfx.config.gb_addr_config);
338 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
339 adev->gfx.config.gb_addr_config);
340 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
341 adev->gfx.config.gb_addr_config);
342 WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,
343 adev->gfx.config.gb_addr_config);
344 WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,
345 adev->gfx.config.gb_addr_config);
323} 346}
324 347
325static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev) 348static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
@@ -371,16 +394,27 @@ static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
371 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, 394 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
372 0xFFFFFFFF, 0); 395 0xFFFFFFFF, 0);
373 396
397 /* VCN global tiling registers */
374 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 398 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
375 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 399 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
376 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 400 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
377 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 401 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
378 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 402 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
379 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 403 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
380 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, 404 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
381 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 405 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
382 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, 406 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
383 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 407 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
408 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
409 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
410 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
411 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
412 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
413 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
414 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
415 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
416 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
417 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
384} 418}
385 419
386/** 420/**
@@ -743,41 +777,24 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
743 lmi_swap_cntl = 0; 777 lmi_swap_cntl = 0;
744 778
745 vcn_1_0_disable_static_power_gating(adev); 779 vcn_1_0_disable_static_power_gating(adev);
780
781 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
782 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
783
746 /* disable clock gating */ 784 /* disable clock gating */
747 vcn_v1_0_disable_clock_gating(adev); 785 vcn_v1_0_disable_clock_gating(adev);
748 786
749 vcn_v1_0_mc_resume_spg_mode(adev);
750
751 /* disable interupt */ 787 /* disable interupt */
752 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 788 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
753 ~UVD_MASTINT_EN__VCPU_EN_MASK); 789 ~UVD_MASTINT_EN__VCPU_EN_MASK);
754 790
755 /* stall UMC and register bus before resetting VCPU */
756 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
757 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
758 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
759 mdelay(1);
760
761 /* put LMI, VCPU, RBC etc... into reset */
762 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
763 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
764 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
765 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
766 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
767 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
768 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
769 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
770 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
771 mdelay(5);
772
773 /* initialize VCN memory controller */ 791 /* initialize VCN memory controller */
774 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, 792 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
775 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 793 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
776 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 794 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
777 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 795 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
778 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 796 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
779 UVD_LMI_CTRL__REQ_MODE_MASK | 797 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
780 0x00100000L);
781 798
782#ifdef __BIG_ENDIAN 799#ifdef __BIG_ENDIAN
783 /* swap (8 in 32) RB and IB */ 800 /* swap (8 in 32) RB and IB */
@@ -785,29 +802,49 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
785#endif 802#endif
786 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 803 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
787 804
788 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040); 805 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
789 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0); 806 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
790 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040); 807 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
791 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0); 808 WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp);
792 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_ALU, 0); 809
793 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 0x88); 810 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
811 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
812 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
813 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
814 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
815
816 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
817 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
818 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
819 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
820 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
794 821
795 /* take all subblocks out of reset, except VCPU */ 822 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
796 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 823 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
797 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 824 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
798 mdelay(5); 825 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
826
827 vcn_v1_0_mc_resume_spg_mode(adev);
828
829 WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK, 0x10);
830 WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK,
831 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK) | 0x3);
799 832
800 /* enable VCPU clock */ 833 /* enable VCPU clock */
801 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 834 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
802 UVD_VCPU_CNTL__CLK_EN_MASK); 835
836 /* boot up the VCPU */
837 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
838 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
803 839
804 /* enable UMC */ 840 /* enable UMC */
805 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 841 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
806 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 842 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
807 843
808 /* boot up the VCPU */ 844 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);
809 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 0); 845 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
810 mdelay(10); 846 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
847 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp);
811 848
812 for (i = 0; i < 10; ++i) { 849 for (i = 0; i < 10; ++i) {
813 uint32_t status; 850 uint32_t status;
@@ -839,24 +876,22 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
839 } 876 }
840 /* enable master interrupt */ 877 /* enable master interrupt */
841 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 878 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
842 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 879 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK);
843 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
844 880
845 /* enable system interrupt for JRBC, TODO: move to set interrupt*/ 881 /* enable system interrupt for JRBC, TODO: move to set interrupt*/
846 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), 882 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
847 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 883 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,
848 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK); 884 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK);
849 885
850 /* clear the bit 4 of VCN_STATUS */ 886 /* clear the busy bit of UVD_STATUS */
851 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, 887 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;
852 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 888 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
853 889
854 /* force RBC into idle state */ 890 /* force RBC into idle state */
855 rb_bufsz = order_base_2(ring->ring_size); 891 rb_bufsz = order_base_2(ring->ring_size);
856 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 892 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
857 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 893 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
858 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 894 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
859 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
860 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 895 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
861 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 896 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
862 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 897 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
@@ -923,7 +958,7 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
923static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) 958static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
924{ 959{
925 struct amdgpu_ring *ring = &adev->vcn.ring_dec; 960 struct amdgpu_ring *ring = &adev->vcn.ring_dec;
926 uint32_t rb_bufsz, tmp, reg_data; 961 uint32_t rb_bufsz, tmp;
927 uint32_t lmi_swap_cntl; 962 uint32_t lmi_swap_cntl;
928 963
929 /* disable byte swapping */ 964 /* disable byte swapping */
@@ -932,47 +967,33 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
932 vcn_1_0_enable_static_power_gating(adev); 967 vcn_1_0_enable_static_power_gating(adev);
933 968
934 /* enable dynamic power gating mode */ 969 /* enable dynamic power gating mode */
935 reg_data = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 970 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
936 reg_data |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 971 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
937 reg_data |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 972 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
938 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data); 973 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
939 974
940 /* enable clock gating */ 975 /* enable clock gating */
941 vcn_v1_0_clock_gating_dpg_mode(adev, 0); 976 vcn_v1_0_clock_gating_dpg_mode(adev, 0);
942 977
943 /* enable VCPU clock */ 978 /* enable VCPU clock */
944 reg_data = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 979 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
945 reg_data |= UVD_VCPU_CNTL__CLK_EN_MASK; 980 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
946 reg_data |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 981 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
947 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, reg_data, 0xFFFFFFFF, 0); 982 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);
948 983
949 /* disable interupt */ 984 /* disable interupt */
950 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, 985 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
951 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 986 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
952 987
953 /* stall UMC and register bus before resetting VCPU */
954 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,
955 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
956
957 /* put LMI, VCPU, RBC etc... into reset */
958 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET,
959 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
960 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
961 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
962 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
963 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
964 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
965 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
966 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
967 0xFFFFFFFF, 0);
968
969 /* initialize VCN memory controller */ 988 /* initialize VCN memory controller */
970 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, 989 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
971 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 990 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
972 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 991 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
973 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 992 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
974 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 993 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
975 UVD_LMI_CTRL__REQ_MODE_MASK | 994 UVD_LMI_CTRL__REQ_MODE_MASK |
995 UVD_LMI_CTRL__CRC_RESET_MASK |
996 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
976 0x00100000L, 0xFFFFFFFF, 0); 997 0x00100000L, 0xFFFFFFFF, 0);
977 998
978#ifdef __BIG_ENDIAN 999#ifdef __BIG_ENDIAN
@@ -981,45 +1002,54 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
981#endif 1002#endif
982 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0); 1003 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0);
983 1004
984 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040, 0xFFFFFFFF, 0); 1005 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_CNTL,
985 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0, 0xFFFFFFFF, 0); 1006 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0);
986 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040, 0xFFFFFFFF, 0);
987 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0, 0xFFFFFFFF, 0);
988 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_ALU, 0, 0xFFFFFFFF, 0);
989 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX, 0x88, 0xFFFFFFFF, 0);
990 1007
991 vcn_v1_0_mc_resume_dpg_mode(adev); 1008 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0,
1009 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1010 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1011 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1012 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0);
992 1013
993 /* take all subblocks out of reset, except VCPU */ 1014 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0,
994 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 1015 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
995 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 0xFFFFFFFF, 0); 1016 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1017 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1018 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0);
996 1019
997 /* enable VCPU clock */ 1020 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX,
998 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, 1021 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
999 UVD_VCPU_CNTL__CLK_EN_MASK, 0xFFFFFFFF, 0); 1022 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1023 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0);
1000 1024
1001 /* enable UMC */ 1025 vcn_v1_0_mc_resume_dpg_mode(adev);
1002 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, 1026
1003 0, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); 1027 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);
1028 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);
1004 1029
1005 /* boot up the VCPU */ 1030 /* boot up the VCPU */
1006 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); 1031 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);
1007 1032
1033 /* enable UMC */
1034 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2,
1035 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,
1036 0xFFFFFFFF, 0);
1037
1008 /* enable master interrupt */ 1038 /* enable master interrupt */
1009 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, 1039 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN,
1010 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 1040 UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
1011 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 0);
1012 1041
1013 vcn_v1_0_clock_gating_dpg_mode(adev, 1); 1042 vcn_v1_0_clock_gating_dpg_mode(adev, 1);
1014 /* setup mmUVD_LMI_CTRL */ 1043 /* setup mmUVD_LMI_CTRL */
1015 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, 1044 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
1016 (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1045 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
1017 UVD_LMI_CTRL__CRC_RESET_MASK | 1046 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1018 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1047 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1019 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1048 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
1020 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1049 UVD_LMI_CTRL__REQ_MODE_MASK |
1021 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1050 UVD_LMI_CTRL__CRC_RESET_MASK |
1022 0x00100000L), 0xFFFFFFFF, 1); 1051 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1052 0x00100000L, 0xFFFFFFFF, 1);
1023 1053
1024 tmp = adev->gfx.config.gb_addr_config; 1054 tmp = adev->gfx.config.gb_addr_config;
1025 /* setup VCN global tiling registers */ 1055 /* setup VCN global tiling registers */
@@ -1035,7 +1065,6 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
1035 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1065 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1036 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1066 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1037 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1067 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1038 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
1039 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1068 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1040 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1069 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1041 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1070 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
@@ -1095,28 +1124,39 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
1095 */ 1124 */
1096static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev) 1125static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
1097{ 1126{
1098 /* force RBC into idle state */ 1127 int ret_code, tmp;
1099 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, 0x11010101);
1100 1128
1101 /* Stall UMC and register bus before resetting VCPU */ 1129 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code);
1102 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 1130
1103 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 1131 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1104 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1132 UVD_LMI_STATUS__READ_CLEAN_MASK |
1105 mdelay(1); 1133 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1134 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1135 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);
1106 1136
1107 /* put VCPU into reset */ 1137 /* put VCPU into reset */
1108 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 1138 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1109 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1139 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1110 mdelay(5); 1140 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1141
1142 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1143 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1144 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code);
1111 1145
1112 /* disable VCPU clock */ 1146 /* disable VCPU clock */
1113 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 0x0); 1147 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1148 ~UVD_VCPU_CNTL__CLK_EN_MASK);
1114 1149
1115 /* Unstall UMC and register bus */ 1150 /* reset LMI UMC/LMI */
1116 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 1151 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1117 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1152 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1153 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1154
1155 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1156 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1157 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1118 1158
1119 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0); 1159 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
1120 1160
1121 vcn_v1_0_enable_clock_gating(adev); 1161 vcn_v1_0_enable_clock_gating(adev);
1122 vcn_1_0_enable_static_power_gating(adev); 1162 vcn_1_0_enable_static_power_gating(adev);
@@ -1125,13 +1165,23 @@ static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
1125 1165
1126static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev) 1166static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
1127{ 1167{
1128 int ret_code; 1168 int ret_code = 0;
1129 1169
1130 /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */ 1170 /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
1131 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1171 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1132 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1172 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1133 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1173 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1134 1174
1175 if (!ret_code) {
1176 int tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1177 /* wait for read ptr to be equal to write ptr */
1178 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
1179
1180 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1181 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1182 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
1183 }
1184
1135 /* disable dynamic power gating mode */ 1185 /* disable dynamic power gating mode */
1136 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, 1186 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1137 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1187 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 0ef4a40d2247..9a7ac58eb18e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -705,7 +705,8 @@ int connector_debugfs_init(struct amdgpu_dm_connector *connector)
705 int i; 705 int i;
706 struct dentry *ent, *dir = connector->base.debugfs_entry; 706 struct dentry *ent, *dir = connector->base.debugfs_entry;
707 707
708 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 708 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
709 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
709 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) { 710 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {
710 ent = debugfs_create_file(dp_debugfs_entries[i].name, 711 ent = debugfs_create_file(dp_debugfs_entries[i].name,
711 0644, 712 0644,
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index 15427f4fc990..cdcefd087487 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -1069,10 +1069,14 @@ static void build_evenly_distributed_points(
1069 struct dividers dividers) 1069 struct dividers dividers)
1070{ 1070{
1071 struct gamma_pixel *p = points; 1071 struct gamma_pixel *p = points;
1072 struct gamma_pixel *p_last = p + numberof_points - 1; 1072 struct gamma_pixel *p_last;
1073 1073
1074 uint32_t i = 0; 1074 uint32_t i = 0;
1075 1075
1076 // This function should not gets called with 0 as a parameter
1077 ASSERT(numberof_points > 0);
1078 p_last = p + numberof_points - 1;
1079
1076 do { 1080 do {
1077 struct fixed31_32 value = dc_fixpt_from_fraction(i, 1081 struct fixed31_32 value = dc_fixpt_from_fraction(i,
1078 numberof_points - 1); 1082 numberof_points - 1);
@@ -1083,7 +1087,7 @@ static void build_evenly_distributed_points(
1083 1087
1084 ++p; 1088 ++p;
1085 ++i; 1089 ++i;
1086 } while (i != numberof_points); 1090 } while (i < numberof_points);
1087 1091
1088 p->r = dc_fixpt_div(p_last->r, dividers.divider1); 1092 p->r = dc_fixpt_div(p_last->r, dividers.divider1);
1089 p->g = dc_fixpt_div(p_last->g, dividers.divider1); 1093 p->g = dc_fixpt_div(p_last->g, dividers.divider1);
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
index 4b7da589e14a..442ca7c471a5 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
@@ -82,6 +82,18 @@
82#define mmUVD_LCM_CGC_CNTRL 0x0123 82#define mmUVD_LCM_CGC_CNTRL 0x0123
83#define mmUVD_LCM_CGC_CNTRL_BASE_IDX 1 83#define mmUVD_LCM_CGC_CNTRL_BASE_IDX 1
84 84
85#define mmUVD_MIF_CURR_UV_ADDR_CONFIG 0x0184
86#define mmUVD_MIF_CURR_UV_ADDR_CONFIG_BASE_IDX 1
87#define mmUVD_MIF_REF_UV_ADDR_CONFIG 0x0185
88#define mmUVD_MIF_REF_UV_ADDR_CONFIG_BASE_IDX 1
89#define mmUVD_MIF_RECON1_UV_ADDR_CONFIG 0x0186
90#define mmUVD_MIF_RECON1_UV_ADDR_CONFIG_BASE_IDX 1
91#define mmUVD_MIF_CURR_ADDR_CONFIG 0x0192
92#define mmUVD_MIF_CURR_ADDR_CONFIG_BASE_IDX 1
93#define mmUVD_MIF_REF_ADDR_CONFIG 0x0193
94#define mmUVD_MIF_REF_ADDR_CONFIG_BASE_IDX 1
95#define mmUVD_MIF_RECON1_ADDR_CONFIG 0x01c5
96#define mmUVD_MIF_RECON1_ADDR_CONFIG_BASE_IDX 1
85 97
86// addressBlock: uvd_uvdnpdec 98// addressBlock: uvd_uvdnpdec
87// base address: 0x20000 99// base address: 0x20000
@@ -327,6 +339,8 @@
327#define mmUVD_LMI_VM_CTRL_BASE_IDX 1 339#define mmUVD_LMI_VM_CTRL_BASE_IDX 1
328#define mmUVD_LMI_SWAP_CNTL 0x056d 340#define mmUVD_LMI_SWAP_CNTL 0x056d
329#define mmUVD_LMI_SWAP_CNTL_BASE_IDX 1 341#define mmUVD_LMI_SWAP_CNTL_BASE_IDX 1
342#define mmUVD_MPC_CNTL 0x0577
343#define mmUVD_MPC_CNTL_BASE_IDX 1
330#define mmUVD_MPC_SET_MUXA0 0x0579 344#define mmUVD_MPC_SET_MUXA0 0x0579
331#define mmUVD_MPC_SET_MUXA0_BASE_IDX 1 345#define mmUVD_MPC_SET_MUXA0_BASE_IDX 1
332#define mmUVD_MPC_SET_MUXA1 0x057a 346#define mmUVD_MPC_SET_MUXA1 0x057a
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
index 26382f5d5354..63457f9df4c5 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
@@ -985,6 +985,7 @@
985#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 985#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
986#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 986#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9
987#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 987#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb
988#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11
988#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L 989#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L
989#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L 990#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L
990#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L 991#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L
@@ -993,6 +994,7 @@
993#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L 994#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L
994#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L 995#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L
995#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L 996#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L
997#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L
996//UVD_MASTINT_EN 998//UVD_MASTINT_EN
997#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 999#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0
998#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 1000#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1
@@ -1045,6 +1047,19 @@
1045#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L 1047#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L
1046#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L 1048#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L
1047#define UVD_LMI_CTRL__RFU_MASK 0xF8000000L 1049#define UVD_LMI_CTRL__RFU_MASK 0xF8000000L
1050//UVD_LMI_STATUS
1051#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0
1052#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1
1053#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2
1054#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3
1055#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6
1056#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9
1057#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L
1058#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L
1059#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L
1060#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L
1061#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L
1062#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L
1048//UVD_LMI_SWAP_CNTL 1063//UVD_LMI_SWAP_CNTL
1049#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 1064#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
1050#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 1065#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
@@ -1078,6 +1093,9 @@
1078#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L 1093#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L
1079#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L 1094#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L
1080#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L 1095#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L
1096//UVD_MPC_CNTL
1097#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3
1098#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L
1081//UVD_MPC_SET_MUXA0 1099//UVD_MPC_SET_MUXA0
1082#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 1100#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0
1083#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 1101#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index 8ae7adb7329b..d2e7c0fa96c2 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -1532,6 +1532,94 @@ struct atom_smc_dpm_info_v4_3
1532 uint32_t boardreserved[10]; 1532 uint32_t boardreserved[10];
1533}; 1533};
1534 1534
1535struct smudpm_i2ccontrollerconfig_t {
1536 uint32_t enabled;
1537 uint32_t slaveaddress;
1538 uint32_t controllerport;
1539 uint32_t controllername;
1540 uint32_t thermalthrottler;
1541 uint32_t i2cprotocol;
1542 uint32_t i2cspeed;
1543};
1544
1545struct atom_smc_dpm_info_v4_4
1546{
1547 struct atom_common_table_header table_header;
1548 uint32_t i2c_padding[3];
1549
1550 uint16_t maxvoltagestepgfx;
1551 uint16_t maxvoltagestepsoc;
1552
1553 uint8_t vddgfxvrmapping;
1554 uint8_t vddsocvrmapping;
1555 uint8_t vddmem0vrmapping;
1556 uint8_t vddmem1vrmapping;
1557
1558 uint8_t gfxulvphasesheddingmask;
1559 uint8_t soculvphasesheddingmask;
1560 uint8_t externalsensorpresent;
1561 uint8_t padding8_v;
1562
1563 uint16_t gfxmaxcurrent;
1564 uint8_t gfxoffset;
1565 uint8_t padding_telemetrygfx;
1566
1567 uint16_t socmaxcurrent;
1568 uint8_t socoffset;
1569 uint8_t padding_telemetrysoc;
1570
1571 uint16_t mem0maxcurrent;
1572 uint8_t mem0offset;
1573 uint8_t padding_telemetrymem0;
1574
1575 uint16_t mem1maxcurrent;
1576 uint8_t mem1offset;
1577 uint8_t padding_telemetrymem1;
1578
1579
1580 uint8_t acdcgpio;
1581 uint8_t acdcpolarity;
1582 uint8_t vr0hotgpio;
1583 uint8_t vr0hotpolarity;
1584
1585 uint8_t vr1hotgpio;
1586 uint8_t vr1hotpolarity;
1587 uint8_t padding1;
1588 uint8_t padding2;
1589
1590
1591 uint8_t ledpin0;
1592 uint8_t ledpin1;
1593 uint8_t ledpin2;
1594 uint8_t padding8_4;
1595
1596
1597 uint8_t pllgfxclkspreadenabled;
1598 uint8_t pllgfxclkspreadpercent;
1599 uint16_t pllgfxclkspreadfreq;
1600
1601
1602 uint8_t uclkspreadenabled;
1603 uint8_t uclkspreadpercent;
1604 uint16_t uclkspreadfreq;
1605
1606
1607 uint8_t fclkspreadenabled;
1608 uint8_t fclkspreadpercent;
1609 uint16_t fclkspreadfreq;
1610
1611
1612 uint8_t fllgfxclkspreadenabled;
1613 uint8_t fllgfxclkspreadpercent;
1614 uint16_t fllgfxclkspreadfreq;
1615
1616
1617 struct smudpm_i2ccontrollerconfig_t i2ccontrollers[7];
1618
1619
1620 uint32_t boardreserved[10];
1621};
1622
1535/* 1623/*
1536 *************************************************************************** 1624 ***************************************************************************
1537 Data Table asic_profiling_info structure 1625 Data Table asic_profiling_info structure
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 75b56ae032ce..e8964cae6b93 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -894,9 +894,14 @@ static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
894 pr_info("%s was not implemented.\n", __func__); 894 pr_info("%s was not implemented.\n", __func__);
895 return ret; 895 return ret;
896 } 896 }
897
898 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
899 pr_info("power profile setting is for manual dpm mode only.\n");
900 return ret;
901 }
902
897 mutex_lock(&hwmgr->smu_lock); 903 mutex_lock(&hwmgr->smu_lock);
898 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) 904 ret = hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
899 ret = hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
900 mutex_unlock(&hwmgr->smu_lock); 905 mutex_unlock(&hwmgr->smu_lock);
901 return ret; 906 return ret;
902} 907}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 958af7b48827..b4dbbb7c334c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -3175,6 +3175,34 @@ static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
3175 return result; 3175 return result;
3176} 3176}
3177 3177
3178static int conv_power_profile_to_pplib_workload(int power_profile)
3179{
3180 int pplib_workload = 0;
3181
3182 switch (power_profile) {
3183 case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
3184 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
3185 break;
3186 case PP_SMC_POWER_PROFILE_POWERSAVING:
3187 pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
3188 break;
3189 case PP_SMC_POWER_PROFILE_VIDEO:
3190 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
3191 break;
3192 case PP_SMC_POWER_PROFILE_VR:
3193 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
3194 break;
3195 case PP_SMC_POWER_PROFILE_COMPUTE:
3196 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
3197 break;
3198 case PP_SMC_POWER_PROFILE_CUSTOM:
3199 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
3200 break;
3201 }
3202
3203 return pplib_workload;
3204}
3205
3178static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) 3206static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
3179{ 3207{
3180 DpmActivityMonitorCoeffInt_t activity_monitor; 3208 DpmActivityMonitorCoeffInt_t activity_monitor;
@@ -3210,7 +3238,7 @@ static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
3210 3238
3211 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 3239 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
3212 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 3240 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3213 workload_type = i + 1; 3241 workload_type = conv_power_profile_to_pplib_workload(i);
3214 result = vega20_get_activity_monitor_coeff(hwmgr, 3242 result = vega20_get_activity_monitor_coeff(hwmgr,
3215 (uint8_t *)(&activity_monitor), workload_type); 3243 (uint8_t *)(&activity_monitor), workload_type);
3216 PP_ASSERT_WITH_CODE(!result, 3244 PP_ASSERT_WITH_CODE(!result,
@@ -3283,10 +3311,15 @@ static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
3283static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) 3311static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
3284{ 3312{
3285 DpmActivityMonitorCoeffInt_t activity_monitor; 3313 DpmActivityMonitorCoeffInt_t activity_monitor;
3286 int result = 0; 3314 int workload_type, result = 0;
3287 3315
3288 hwmgr->power_profile_mode = input[size]; 3316 hwmgr->power_profile_mode = input[size];
3289 3317
3318 if (hwmgr->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
3319 pr_err("Invalid power profile mode %d\n", hwmgr->power_profile_mode);
3320 return -EINVAL;
3321 }
3322
3290 if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 3323 if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
3291 if (size < 10) 3324 if (size < 10)
3292 return -EINVAL; 3325 return -EINVAL;
@@ -3353,8 +3386,11 @@ static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, ui
3353 return result); 3386 return result);
3354 } 3387 }
3355 3388
3389 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
3390 workload_type =
3391 conv_power_profile_to_pplib_workload(hwmgr->power_profile_mode);
3356 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, 3392 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
3357 1 << hwmgr->power_profile_mode); 3393 1 << workload_type);
3358 3394
3359 return 0; 3395 return 0;
3360} 3396}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c
index 32fe38452094..e5f7f8230065 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c
@@ -100,9 +100,8 @@ static void dump_pptable(PPTable_t *pptable)
100 pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold); 100 pr_info("PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
101 101
102 pr_info("MemoryOnPackage = 0x%02x\n", pptable->MemoryOnPackage); 102 pr_info("MemoryOnPackage = 0x%02x\n", pptable->MemoryOnPackage);
103 pr_info("padding8_limits[0] = 0x%02x\n", pptable->padding8_limits[0]); 103 pr_info("padding8_limits = 0x%02x\n", pptable->padding8_limits);
104 pr_info("padding8_limits[1] = 0x%02x\n", pptable->padding8_limits[1]); 104 pr_info("Tvr_SocLimit = %d\n", pptable->Tvr_SocLimit);
105 pr_info("padding8_limits[2] = 0x%02x\n", pptable->padding8_limits[2]);
106 105
107 pr_info("UlvVoltageOffsetSoc = %d\n", pptable->UlvVoltageOffsetSoc); 106 pr_info("UlvVoltageOffsetSoc = %d\n", pptable->UlvVoltageOffsetSoc);
108 pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx); 107 pr_info("UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
@@ -417,8 +416,8 @@ static void dump_pptable(PPTable_t *pptable)
417 pr_info("FanGainEdge = %d\n", pptable->FanGainEdge); 416 pr_info("FanGainEdge = %d\n", pptable->FanGainEdge);
418 pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot); 417 pr_info("FanGainHotspot = %d\n", pptable->FanGainHotspot);
419 pr_info("FanGainLiquid = %d\n", pptable->FanGainLiquid); 418 pr_info("FanGainLiquid = %d\n", pptable->FanGainLiquid);
420 pr_info("FanGainVrVddc = %d\n", pptable->FanGainVrVddc); 419 pr_info("FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
421 pr_info("FanGainVrMvdd = %d\n", pptable->FanGainVrMvdd); 420 pr_info("FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
422 pr_info("FanGainPlx = %d\n", pptable->FanGainPlx); 421 pr_info("FanGainPlx = %d\n", pptable->FanGainPlx);
423 pr_info("FanGainHbm = %d\n", pptable->FanGainHbm); 422 pr_info("FanGainHbm = %d\n", pptable->FanGainHbm);
424 pr_info("FanPwmMin = %d\n", pptable->FanPwmMin); 423 pr_info("FanPwmMin = %d\n", pptable->FanPwmMin);
@@ -533,23 +532,20 @@ static void dump_pptable(PPTable_t *pptable)
533 pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx); 532 pr_info("MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
534 pr_info("MinVoltageUlvSoc = %d\n", pptable->MinVoltageUlvSoc); 533 pr_info("MinVoltageUlvSoc = %d\n", pptable->MinVoltageUlvSoc);
535 534
536 for (i = 0; i < 14; i++) 535 pr_info("MGpuFanBoostLimitRpm = %d\n", pptable->MGpuFanBoostLimitRpm);
537 pr_info("Reserved[%d] = 0x%x\n", i, pptable->Reserved[i]); 536 pr_info("padding16_Fan = %d\n", pptable->padding16_Fan);
537
538 pr_info("FanGainVrMem0 = %d\n", pptable->FanGainVrMem0);
539 pr_info("FanGainVrMem0 = %d\n", pptable->FanGainVrMem0);
538 540
539 pr_info("Liquid1_I2C_address = 0x%x\n", pptable->Liquid1_I2C_address); 541 pr_info("DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
540 pr_info("Liquid2_I2C_address = 0x%x\n", pptable->Liquid2_I2C_address); 542 pr_info("DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
541 pr_info("Vr_I2C_address = 0x%x\n", pptable->Vr_I2C_address);
542 pr_info("Plx_I2C_address = 0x%x\n", pptable->Plx_I2C_address);
543 543
544 pr_info("Liquid_I2C_LineSCL = 0x%x\n", pptable->Liquid_I2C_LineSCL); 544 for (i = 0; i < 11; i++)
545 pr_info("Liquid_I2C_LineSDA = 0x%x\n", pptable->Liquid_I2C_LineSDA); 545 pr_info("Reserved[%d] = 0x%x\n", i, pptable->Reserved[i]);
546 pr_info("Vr_I2C_LineSCL = 0x%x\n", pptable->Vr_I2C_LineSCL);
547 pr_info("Vr_I2C_LineSDA = 0x%x\n", pptable->Vr_I2C_LineSDA);
548 546
549 pr_info("Plx_I2C_LineSCL = 0x%x\n", pptable->Plx_I2C_LineSCL); 547 for (i = 0; i < 3; i++)
550 pr_info("Plx_I2C_LineSDA = 0x%x\n", pptable->Plx_I2C_LineSDA); 548 pr_info("Padding32[%d] = 0x%x\n", i, pptable->Padding32[i]);
551 pr_info("VrSensorPresent = 0x%x\n", pptable->VrSensorPresent);
552 pr_info("LiquidSensorPresent = 0x%x\n", pptable->LiquidSensorPresent);
553 549
554 pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx); 550 pr_info("MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
555 pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc); 551 pr_info("MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
@@ -611,6 +607,24 @@ static void dump_pptable(PPTable_t *pptable)
611 pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent); 607 pr_info("FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
612 pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq); 608 pr_info("FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
613 609
610 for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) {
611 pr_info("I2cControllers[%d]:\n", i);
612 pr_info(" .Enabled = %d\n",
613 pptable->I2cControllers[i].Enabled);
614 pr_info(" .SlaveAddress = 0x%x\n",
615 pptable->I2cControllers[i].SlaveAddress);
616 pr_info(" .ControllerPort = %d\n",
617 pptable->I2cControllers[i].ControllerPort);
618 pr_info(" .ControllerName = %d\n",
619 pptable->I2cControllers[i].ControllerName);
620 pr_info(" .ThermalThrottler = %d\n",
621 pptable->I2cControllers[i].ThermalThrottler);
622 pr_info(" .I2cProtocol = %d\n",
623 pptable->I2cControllers[i].I2cProtocol);
624 pr_info(" .I2cSpeed = %d\n",
625 pptable->I2cControllers[i].I2cSpeed);
626 }
627
614 for (i = 0; i < 10; i++) 628 for (i = 0; i < 10; i++)
615 pr_info("BoardReserved[%d] = 0x%x\n", i, pptable->BoardReserved[i]); 629 pr_info("BoardReserved[%d] = 0x%x\n", i, pptable->BoardReserved[i]);
616 630
@@ -693,29 +707,19 @@ static int copy_overdrive_feature_capabilities_array(
693 707
694static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable) 708static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable)
695{ 709{
696 struct atom_smc_dpm_info_v4_3 *smc_dpm_table; 710 struct atom_smc_dpm_info_v4_4 *smc_dpm_table;
697 int index = GetIndexIntoMasterDataTable(smc_dpm_info); 711 int index = GetIndexIntoMasterDataTable(smc_dpm_info);
712 int i;
698 713
699 PP_ASSERT_WITH_CODE( 714 PP_ASSERT_WITH_CODE(
700 smc_dpm_table = smu_atom_get_data_table(hwmgr->adev, index, NULL, NULL, NULL), 715 smc_dpm_table = smu_atom_get_data_table(hwmgr->adev, index, NULL, NULL, NULL),
701 "[appendVbiosPPTable] Failed to retrieve Smc Dpm Table from VBIOS!", 716 "[appendVbiosPPTable] Failed to retrieve Smc Dpm Table from VBIOS!",
702 return -1); 717 return -1);
703 718
704 ppsmc_pptable->Liquid1_I2C_address = smc_dpm_table->liquid1_i2c_address; 719 memset(ppsmc_pptable->Padding32,
705 ppsmc_pptable->Liquid2_I2C_address = smc_dpm_table->liquid2_i2c_address; 720 0,
706 ppsmc_pptable->Vr_I2C_address = smc_dpm_table->vr_i2c_address; 721 sizeof(struct atom_smc_dpm_info_v4_4) -
707 ppsmc_pptable->Plx_I2C_address = smc_dpm_table->plx_i2c_address; 722 sizeof(struct atom_common_table_header));
708
709 ppsmc_pptable->Liquid_I2C_LineSCL = smc_dpm_table->liquid_i2c_linescl;
710 ppsmc_pptable->Liquid_I2C_LineSDA = smc_dpm_table->liquid_i2c_linesda;
711 ppsmc_pptable->Vr_I2C_LineSCL = smc_dpm_table->vr_i2c_linescl;
712 ppsmc_pptable->Vr_I2C_LineSDA = smc_dpm_table->vr_i2c_linesda;
713
714 ppsmc_pptable->Plx_I2C_LineSCL = smc_dpm_table->plx_i2c_linescl;
715 ppsmc_pptable->Plx_I2C_LineSDA = smc_dpm_table->plx_i2c_linesda;
716 ppsmc_pptable->VrSensorPresent = smc_dpm_table->vrsensorpresent;
717 ppsmc_pptable->LiquidSensorPresent = smc_dpm_table->liquidsensorpresent;
718
719 ppsmc_pptable->MaxVoltageStepGfx = smc_dpm_table->maxvoltagestepgfx; 723 ppsmc_pptable->MaxVoltageStepGfx = smc_dpm_table->maxvoltagestepgfx;
720 ppsmc_pptable->MaxVoltageStepSoc = smc_dpm_table->maxvoltagestepsoc; 724 ppsmc_pptable->MaxVoltageStepSoc = smc_dpm_table->maxvoltagestepsoc;
721 725
@@ -774,6 +778,24 @@ static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable
774 ppsmc_pptable->FllGfxclkSpreadPercent = smc_dpm_table->fllgfxclkspreadpercent; 778 ppsmc_pptable->FllGfxclkSpreadPercent = smc_dpm_table->fllgfxclkspreadpercent;
775 ppsmc_pptable->FllGfxclkSpreadFreq = smc_dpm_table->fllgfxclkspreadfreq; 779 ppsmc_pptable->FllGfxclkSpreadFreq = smc_dpm_table->fllgfxclkspreadfreq;
776 780
781 if ((smc_dpm_table->table_header.format_revision == 4) &&
782 (smc_dpm_table->table_header.content_revision == 4)) {
783 for (i = 0; i < I2C_CONTROLLER_NAME_COUNT; i++) {
784 ppsmc_pptable->I2cControllers[i].Enabled =
785 smc_dpm_table->i2ccontrollers[i].enabled;
786 ppsmc_pptable->I2cControllers[i].SlaveAddress =
787 smc_dpm_table->i2ccontrollers[i].slaveaddress;
788 ppsmc_pptable->I2cControllers[i].ControllerPort =
789 smc_dpm_table->i2ccontrollers[i].controllerport;
790 ppsmc_pptable->I2cControllers[i].ThermalThrottler =
791 smc_dpm_table->i2ccontrollers[i].thermalthrottler;
792 ppsmc_pptable->I2cControllers[i].I2cProtocol =
793 smc_dpm_table->i2ccontrollers[i].i2cprotocol;
794 ppsmc_pptable->I2cControllers[i].I2cSpeed =
795 smc_dpm_table->i2ccontrollers[i].i2cspeed;
796 }
797 }
798
777 return 0; 799 return 0;
778} 800}
779 801
@@ -860,7 +882,15 @@ static int init_powerplay_table_information(
860 if (pptable_information->smc_pptable == NULL) 882 if (pptable_information->smc_pptable == NULL)
861 return -ENOMEM; 883 return -ENOMEM;
862 884
863 memcpy(pptable_information->smc_pptable, &(powerplay_table->smcPPTable), sizeof(PPTable_t)); 885 if (powerplay_table->smcPPTable.Version <= 2)
886 memcpy(pptable_information->smc_pptable,
887 &(powerplay_table->smcPPTable),
888 sizeof(PPTable_t) -
889 sizeof(I2cControllerConfig_t) * I2C_CONTROLLER_NAME_COUNT);
890 else
891 memcpy(pptable_information->smc_pptable,
892 &(powerplay_table->smcPPTable),
893 sizeof(PPTable_t));
864 894
865 result = append_vbios_pptable(hwmgr, (pptable_information->smc_pptable)); 895 result = append_vbios_pptable(hwmgr, (pptable_information->smc_pptable));
866 896
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
index a002021414ff..2998a49960ed 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if.h
@@ -27,7 +27,7 @@
27// *** IMPORTANT *** 27// *** IMPORTANT ***
28// SMU TEAM: Always increment the interface version if 28// SMU TEAM: Always increment the interface version if
29// any structure is changed in this file 29// any structure is changed in this file
30#define SMU11_DRIVER_IF_VERSION 0x11 30#define SMU11_DRIVER_IF_VERSION 0x12
31 31
32#define PPTABLE_V20_SMU_VERSION 2 32#define PPTABLE_V20_SMU_VERSION 2
33 33
@@ -165,7 +165,7 @@
165#define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT ) 165#define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT )
166#define FEATURE_DS_MP1CLK_MASK (1 << FEATURE_DS_MP1CLK_BIT ) 166#define FEATURE_DS_MP1CLK_MASK (1 << FEATURE_DS_MP1CLK_BIT )
167#define FEATURE_DS_MP0CLK_MASK (1 << FEATURE_DS_MP0CLK_BIT ) 167#define FEATURE_DS_MP0CLK_MASK (1 << FEATURE_DS_MP0CLK_BIT )
168 168#define FEATURE_XGMI_MASK (1 << FEATURE_XGMI_BIT )
169 169
170#define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x00000001 170#define DPM_OVERRIDE_DISABLE_SOCCLK_PID 0x00000001
171#define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002 171#define DPM_OVERRIDE_DISABLE_UCLK_PID 0x00000002
@@ -186,6 +186,9 @@
186#define DPM_OVERRIDE_ENABLE_GFXOFF_UCLK_SWITCH 0x00010000 186#define DPM_OVERRIDE_ENABLE_GFXOFF_UCLK_SWITCH 0x00010000
187#define DPM_OVERRIDE_ENABLE_GFXOFF_FCLK_SWITCH 0x00020000 187#define DPM_OVERRIDE_ENABLE_GFXOFF_FCLK_SWITCH 0x00020000
188 188
189#define I2C_CONTROLLER_ENABLED 1
190#define I2C_CONTROLLER_DISABLED 0
191
189#define VR_MAPPING_VR_SELECT_MASK 0x01 192#define VR_MAPPING_VR_SELECT_MASK 0x01
190#define VR_MAPPING_VR_SELECT_SHIFT 0x00 193#define VR_MAPPING_VR_SELECT_SHIFT 0x00
191 194
@@ -208,15 +211,17 @@
208#define THROTTLER_STATUS_TEMP_HOTSPOT_BIT 2 211#define THROTTLER_STATUS_TEMP_HOTSPOT_BIT 2
209#define THROTTLER_STATUS_TEMP_HBM_BIT 3 212#define THROTTLER_STATUS_TEMP_HBM_BIT 3
210#define THROTTLER_STATUS_TEMP_VR_GFX_BIT 4 213#define THROTTLER_STATUS_TEMP_VR_GFX_BIT 4
211#define THROTTLER_STATUS_TEMP_VR_MEM_BIT 5 214#define THROTTLER_STATUS_TEMP_VR_SOC_BIT 5
212#define THROTTLER_STATUS_TEMP_LIQUID_BIT 6 215#define THROTTLER_STATUS_TEMP_VR_MEM0_BIT 6
213#define THROTTLER_STATUS_TEMP_PLX_BIT 7 216#define THROTTLER_STATUS_TEMP_VR_MEM1_BIT 7
214#define THROTTLER_STATUS_TEMP_SKIN_BIT 8 217#define THROTTLER_STATUS_TEMP_LIQUID_BIT 8
215#define THROTTLER_STATUS_TDC_GFX_BIT 9 218#define THROTTLER_STATUS_TEMP_PLX_BIT 9
216#define THROTTLER_STATUS_TDC_SOC_BIT 10 219#define THROTTLER_STATUS_TEMP_SKIN_BIT 10
217#define THROTTLER_STATUS_PPT_BIT 11 220#define THROTTLER_STATUS_TDC_GFX_BIT 11
218#define THROTTLER_STATUS_FIT_BIT 12 221#define THROTTLER_STATUS_TDC_SOC_BIT 12
219#define THROTTLER_STATUS_PPM_BIT 13 222#define THROTTLER_STATUS_PPT_BIT 13
223#define THROTTLER_STATUS_FIT_BIT 14
224#define THROTTLER_STATUS_PPM_BIT 15
220 225
221 226
222#define TABLE_TRANSFER_OK 0x0 227#define TABLE_TRANSFER_OK 0x0
@@ -236,6 +241,58 @@
236#define XGMI_STATE_D0 1 241#define XGMI_STATE_D0 1
237#define XGMI_STATE_D3 0 242#define XGMI_STATE_D3 0
238 243
244typedef enum {
245 I2C_CONTROLLER_PORT_0 = 0,
246 I2C_CONTROLLER_PORT_1 = 1,
247} I2cControllerPort_e;
248
249typedef enum {
250 I2C_CONTROLLER_NAME_VR_GFX = 0,
251 I2C_CONTROLLER_NAME_VR_SOC,
252 I2C_CONTROLLER_NAME_VR_VDDCI,
253 I2C_CONTROLLER_NAME_VR_HBM,
254 I2C_CONTROLLER_NAME_LIQUID_0,
255 I2C_CONTROLLER_NAME_LIQUID_1,
256 I2C_CONTROLLER_NAME_PLX,
257 I2C_CONTROLLER_NAME_COUNT,
258} I2cControllerName_e;
259
260typedef enum {
261 I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
262 I2C_CONTROLLER_THROTTLER_VR_GFX,
263 I2C_CONTROLLER_THROTTLER_VR_SOC,
264 I2C_CONTROLLER_THROTTLER_VR_VDDCI,
265 I2C_CONTROLLER_THROTTLER_VR_HBM,
266 I2C_CONTROLLER_THROTTLER_LIQUID_0,
267 I2C_CONTROLLER_THROTTLER_LIQUID_1,
268 I2C_CONTROLLER_THROTTLER_PLX,
269} I2cControllerThrottler_e;
270
271typedef enum {
272 I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5,
273 I2C_CONTROLLER_PROTOCOL_VR_IR35217,
274 I2C_CONTROLLER_PROTOCOL_TMP_TMP102A,
275 I2C_CONTROLLER_PROTOCOL_SPARE_0,
276 I2C_CONTROLLER_PROTOCOL_SPARE_1,
277 I2C_CONTROLLER_PROTOCOL_SPARE_2,
278} I2cControllerProtocol_e;
279
280typedef enum {
281 I2C_CONTROLLER_SPEED_SLOW = 0,
282 I2C_CONTROLLER_SPEED_FAST = 1,
283} I2cControllerSpeed_e;
284
285typedef struct {
286 uint32_t Enabled;
287 uint32_t SlaveAddress;
288 uint32_t ControllerPort;
289 uint32_t ControllerName;
290
291 uint32_t ThermalThrottler;
292 uint32_t I2cProtocol;
293 uint32_t I2cSpeed;
294} I2cControllerConfig_t;
295
239typedef struct { 296typedef struct {
240 uint32_t a; 297 uint32_t a;
241 uint32_t b; 298 uint32_t b;
@@ -334,8 +391,8 @@ typedef struct {
334 uint16_t PpmTemperatureThreshold; 391 uint16_t PpmTemperatureThreshold;
335 392
336 uint8_t MemoryOnPackage; 393 uint8_t MemoryOnPackage;
337 uint8_t padding8_limits[3]; 394 uint8_t padding8_limits;
338 395 uint16_t Tvr_SocLimit;
339 396
340 uint16_t UlvVoltageOffsetSoc; 397 uint16_t UlvVoltageOffsetSoc;
341 uint16_t UlvVoltageOffsetGfx; 398 uint16_t UlvVoltageOffsetGfx;
@@ -406,8 +463,8 @@ typedef struct {
406 uint16_t FanGainEdge; 463 uint16_t FanGainEdge;
407 uint16_t FanGainHotspot; 464 uint16_t FanGainHotspot;
408 uint16_t FanGainLiquid; 465 uint16_t FanGainLiquid;
409 uint16_t FanGainVrVddc; 466 uint16_t FanGainVrGfx;
410 uint16_t FanGainVrMvdd; 467 uint16_t FanGainVrSoc;
411 uint16_t FanGainPlx; 468 uint16_t FanGainPlx;
412 uint16_t FanGainHbm; 469 uint16_t FanGainHbm;
413 uint16_t FanPwmMin; 470 uint16_t FanPwmMin;
@@ -444,7 +501,7 @@ typedef struct {
444 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT]; 501 uint8_t DcBtcEnabled[AVFS_VOLTAGE_COUNT];
445 uint8_t Padding8_GfxBtc[2]; 502 uint8_t Padding8_GfxBtc[2];
446 503
447 uint16_t DcBtcMin[AVFS_VOLTAGE_COUNT]; 504 int16_t DcBtcMin[AVFS_VOLTAGE_COUNT];
448 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; 505 uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT];
449 506
450 507
@@ -467,24 +524,14 @@ typedef struct {
467 uint16_t MGpuFanBoostLimitRpm; 524 uint16_t MGpuFanBoostLimitRpm;
468 uint16_t padding16_Fan; 525 uint16_t padding16_Fan;
469 526
470 uint32_t Reserved[13]; 527 uint16_t FanGainVrMem0;
471 528 uint16_t FanGainVrMem1;
472 529
530 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT];
473 531
474 uint8_t Liquid1_I2C_address; 532 uint32_t Reserved[11];
475 uint8_t Liquid2_I2C_address;
476 uint8_t Vr_I2C_address;
477 uint8_t Plx_I2C_address;
478 533
479 uint8_t Liquid_I2C_LineSCL; 534 uint32_t Padding32[3];
480 uint8_t Liquid_I2C_LineSDA;
481 uint8_t Vr_I2C_LineSCL;
482 uint8_t Vr_I2C_LineSDA;
483
484 uint8_t Plx_I2C_LineSCL;
485 uint8_t Plx_I2C_LineSDA;
486 uint8_t VrSensorPresent;
487 uint8_t LiquidSensorPresent;
488 535
489 uint16_t MaxVoltageStepGfx; 536 uint16_t MaxVoltageStepGfx;
490 uint16_t MaxVoltageStepSoc; 537 uint16_t MaxVoltageStepSoc;
@@ -551,6 +598,8 @@ typedef struct {
551 uint8_t FllGfxclkSpreadPercent; 598 uint8_t FllGfxclkSpreadPercent;
552 uint16_t FllGfxclkSpreadFreq; 599 uint16_t FllGfxclkSpreadFreq;
553 600
601 I2cControllerConfig_t I2cControllers[I2C_CONTROLLER_NAME_COUNT];
602
554 uint32_t BoardReserved[10]; 603 uint32_t BoardReserved[10];
555 604
556 605
@@ -607,7 +656,9 @@ typedef struct {
607 uint16_t TemperatureHotspot ; 656 uint16_t TemperatureHotspot ;
608 uint16_t TemperatureHBM ; 657 uint16_t TemperatureHBM ;
609 uint16_t TemperatureVrGfx ; 658 uint16_t TemperatureVrGfx ;
610 uint16_t TemperatureVrMem ; 659 uint16_t TemperatureVrSoc ;
660 uint16_t TemperatureVrMem0 ;
661 uint16_t TemperatureVrMem1 ;
611 uint16_t TemperatureLiquid ; 662 uint16_t TemperatureLiquid ;
612 uint16_t TemperaturePlx ; 663 uint16_t TemperaturePlx ;
613 uint32_t ThrottlerStatus ; 664 uint32_t ThrottlerStatus ;
diff --git a/drivers/gpu/drm/radeon/mkregtable.c b/drivers/gpu/drm/radeon/mkregtable.c
index ba704633b072..52a7246fed9e 100644
--- a/drivers/gpu/drm/radeon/mkregtable.c
+++ b/drivers/gpu/drm/radeon/mkregtable.c
@@ -1,4 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: MIT
2/* utility to create the register check tables 2/* utility to create the register check tables
3 * this includes inlined list.h safe for userspace. 3 * this includes inlined list.h safe for userspace.
4 * 4 *
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h
index ad16a925f8d5..57e2b09784be 100644
--- a/drivers/gpu/drm/radeon/r100_track.h
+++ b/drivers/gpu/drm/radeon/r100_track.h
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: GPL-2.0 */ 1/* SPDX-License-Identifier: MIT */
2 2
3#define R100_TRACK_MAX_TEXTURE 3 3#define R100_TRACK_MAX_TEXTURE 3
4#define R200_TRACK_MAX_TEXTURE 6 4#define R200_TRACK_MAX_TEXTURE 6
diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c b/drivers/gpu/drm/radeon/radeon_dp_mst.c
index f920be236cc9..84b3ad2172a3 100644
--- a/drivers/gpu/drm/radeon/radeon_dp_mst.c
+++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c
@@ -1,4 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: MIT
2 2
3#include <drm/drmP.h> 3#include <drm/drmP.h>
4#include <drm/drm_dp_mst_helper.h> 4#include <drm/drm_dp_mst_helper.h>
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_tv.c b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
index 611cf934b211..4278272e3191 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_tv.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
@@ -1,4 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: MIT
2#include <drm/drmP.h> 2#include <drm/drmP.h>
3#include <drm/drm_crtc_helper.h> 3#include <drm/drm_crtc_helper.h>
4#include "radeon.h" 4#include "radeon.h"
diff --git a/drivers/gpu/drm/radeon/radeon_trace.h b/drivers/gpu/drm/radeon/radeon_trace.h
index bc26efd1793e..0d84b8aafab3 100644
--- a/drivers/gpu/drm/radeon/radeon_trace.h
+++ b/drivers/gpu/drm/radeon/radeon_trace.h
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: GPL-2.0 */ 1/* SPDX-License-Identifier: MIT */
2#if !defined(_RADEON_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) 2#if !defined(_RADEON_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
3#define _RADEON_TRACE_H_ 3#define _RADEON_TRACE_H_
4 4
diff --git a/drivers/gpu/drm/radeon/radeon_trace_points.c b/drivers/gpu/drm/radeon/radeon_trace_points.c
index 66b3d5084662..65e92302f974 100644
--- a/drivers/gpu/drm/radeon/radeon_trace_points.c
+++ b/drivers/gpu/drm/radeon/radeon_trace_points.c
@@ -1,4 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0 1// SPDX-License-Identifier: MIT
2/* Copyright Red Hat Inc 2010. 2/* Copyright Red Hat Inc 2010.
3 * Author : Dave Airlie <airlied@redhat.com> 3 * Author : Dave Airlie <airlied@redhat.com>
4 */ 4 */
diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c
index 4e8505d51795..44fe587aaef9 100644
--- a/drivers/gpu/drm/scheduler/sched_main.c
+++ b/drivers/gpu/drm/scheduler/sched_main.c
@@ -182,6 +182,20 @@ bool drm_sched_dependency_optimized(struct dma_fence* fence,
182} 182}
183EXPORT_SYMBOL(drm_sched_dependency_optimized); 183EXPORT_SYMBOL(drm_sched_dependency_optimized);
184 184
185/**
186 * drm_sched_start_timeout - start timeout for reset worker
187 *
188 * @sched: scheduler instance to start the worker for
189 *
190 * Start the timeout for the given scheduler.
191 */
192static void drm_sched_start_timeout(struct drm_gpu_scheduler *sched)
193{
194 if (sched->timeout != MAX_SCHEDULE_TIMEOUT &&
195 !list_empty(&sched->ring_mirror_list))
196 schedule_delayed_work(&sched->work_tdr, sched->timeout);
197}
198
185/* job_finish is called after hw fence signaled 199/* job_finish is called after hw fence signaled
186 */ 200 */
187static void drm_sched_job_finish(struct work_struct *work) 201static void drm_sched_job_finish(struct work_struct *work)
@@ -203,9 +217,7 @@ static void drm_sched_job_finish(struct work_struct *work)
203 /* remove job from ring_mirror_list */ 217 /* remove job from ring_mirror_list */
204 list_del(&s_job->node); 218 list_del(&s_job->node);
205 /* queue TDR for next job */ 219 /* queue TDR for next job */
206 if (sched->timeout != MAX_SCHEDULE_TIMEOUT && 220 drm_sched_start_timeout(sched);
207 !list_empty(&sched->ring_mirror_list))
208 schedule_delayed_work(&sched->work_tdr, sched->timeout);
209 spin_unlock(&sched->job_list_lock); 221 spin_unlock(&sched->job_list_lock);
210 222
211 dma_fence_put(&s_job->s_fence->finished); 223 dma_fence_put(&s_job->s_fence->finished);
@@ -229,10 +241,7 @@ static void drm_sched_job_begin(struct drm_sched_job *s_job)
229 241
230 spin_lock(&sched->job_list_lock); 242 spin_lock(&sched->job_list_lock);
231 list_add_tail(&s_job->node, &sched->ring_mirror_list); 243 list_add_tail(&s_job->node, &sched->ring_mirror_list);
232 if (sched->timeout != MAX_SCHEDULE_TIMEOUT && 244 drm_sched_start_timeout(sched);
233 list_first_entry_or_null(&sched->ring_mirror_list,
234 struct drm_sched_job, node) == s_job)
235 schedule_delayed_work(&sched->work_tdr, sched->timeout);
236 spin_unlock(&sched->job_list_lock); 245 spin_unlock(&sched->job_list_lock);
237} 246}
238 247
@@ -240,13 +249,41 @@ static void drm_sched_job_timedout(struct work_struct *work)
240{ 249{
241 struct drm_gpu_scheduler *sched; 250 struct drm_gpu_scheduler *sched;
242 struct drm_sched_job *job; 251 struct drm_sched_job *job;
252 int r;
243 253
244 sched = container_of(work, struct drm_gpu_scheduler, work_tdr.work); 254 sched = container_of(work, struct drm_gpu_scheduler, work_tdr.work);
255
256 spin_lock(&sched->job_list_lock);
257 list_for_each_entry_reverse(job, &sched->ring_mirror_list, node) {
258 struct drm_sched_fence *fence = job->s_fence;
259
260 if (!dma_fence_remove_callback(fence->parent, &fence->cb))
261 goto already_signaled;
262 }
263
245 job = list_first_entry_or_null(&sched->ring_mirror_list, 264 job = list_first_entry_or_null(&sched->ring_mirror_list,
246 struct drm_sched_job, node); 265 struct drm_sched_job, node);
266 spin_unlock(&sched->job_list_lock);
247 267
248 if (job) 268 if (job)
249 job->sched->ops->timedout_job(job); 269 sched->ops->timedout_job(job);
270
271 spin_lock(&sched->job_list_lock);
272 list_for_each_entry(job, &sched->ring_mirror_list, node) {
273 struct drm_sched_fence *fence = job->s_fence;
274
275 if (!fence->parent || !list_empty(&fence->cb.node))
276 continue;
277
278 r = dma_fence_add_callback(fence->parent, &fence->cb,
279 drm_sched_process_job);
280 if (r)
281 drm_sched_process_job(fence->parent, &fence->cb);
282
283already_signaled:
284 ;
285 }
286 spin_unlock(&sched->job_list_lock);
250} 287}
251 288
252/** 289/**
@@ -313,11 +350,6 @@ void drm_sched_job_recovery(struct drm_gpu_scheduler *sched)
313 int r; 350 int r;
314 351
315 spin_lock(&sched->job_list_lock); 352 spin_lock(&sched->job_list_lock);
316 s_job = list_first_entry_or_null(&sched->ring_mirror_list,
317 struct drm_sched_job, node);
318 if (s_job && sched->timeout != MAX_SCHEDULE_TIMEOUT)
319 schedule_delayed_work(&sched->work_tdr, sched->timeout);
320
321 list_for_each_entry_safe(s_job, tmp, &sched->ring_mirror_list, node) { 353 list_for_each_entry_safe(s_job, tmp, &sched->ring_mirror_list, node) {
322 struct drm_sched_fence *s_fence = s_job->s_fence; 354 struct drm_sched_fence *s_fence = s_job->s_fence;
323 struct dma_fence *fence; 355 struct dma_fence *fence;
@@ -350,6 +382,7 @@ void drm_sched_job_recovery(struct drm_gpu_scheduler *sched)
350 } 382 }
351 spin_lock(&sched->job_list_lock); 383 spin_lock(&sched->job_list_lock);
352 } 384 }
385 drm_sched_start_timeout(sched);
353 spin_unlock(&sched->job_list_lock); 386 spin_unlock(&sched->job_list_lock);
354} 387}
355EXPORT_SYMBOL(drm_sched_job_recovery); 388EXPORT_SYMBOL(drm_sched_job_recovery);
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index 683742826511..b7e899ce44f0 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -1,4 +1,4 @@
1/* SPDX-License-Identifier: GPL-2.0 */ 1/* SPDX-License-Identifier: MIT */
2#define radeon_PCI_IDS \ 2#define radeon_PCI_IDS \
3 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ 3 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
4 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ 4 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-01 03:13:31 -0400