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-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c87
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_display.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c14
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c26
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c12
-rw-r--r--drivers/gpu/drm/amd/amdgpu/ci_dpm.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v10_0.c25
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v11_0.c25
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v6_0.c33
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v8_0.c27
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c25
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c25
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c363
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si_dpm.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c115
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v3_0.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c6
-rw-r--r--drivers/gpu/drm/amd/powerplay/amd_powerplay.c4
-rw-r--r--drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c2
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c2
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c13
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h1
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c6
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c6
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c6
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c21
-rw-r--r--drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_cursor.c73
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h1
-rw-r--r--drivers/gpu/drm/radeon/si.c1
-rw-r--r--drivers/gpu/drm/radeon/si_dpm.c1
-rw-r--r--include/uapi/drm/amdgpu_drm.h11
41 files changed, 557 insertions, 436 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f53e52f4d672..54ac8a845e9f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -842,6 +842,8 @@ struct amdgpu_gfx_funcs {
842 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 842 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
843 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 843 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
844 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields); 844 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
845 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
846 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
845}; 847};
846 848
847struct amdgpu_gfx { 849struct amdgpu_gfx {
@@ -1330,6 +1332,7 @@ struct amdgpu_device {
1330 1332
1331 /* BIOS */ 1333 /* BIOS */
1332 uint8_t *bios; 1334 uint8_t *bios;
1335 uint32_t bios_size;
1333 bool is_atom_bios; 1336 bool is_atom_bios;
1334 struct amdgpu_bo *stollen_vga_memory; 1337 struct amdgpu_bo *stollen_vga_memory;
1335 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1338 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
@@ -1679,8 +1682,6 @@ uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1679void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 1682void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
1680void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 1683void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
1681void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 1684void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
1682u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev);
1683int amdgpu_ttm_global_init(struct amdgpu_device *adev);
1684int amdgpu_ttm_init(struct amdgpu_device *adev); 1685int amdgpu_ttm_init(struct amdgpu_device *adev);
1685void amdgpu_ttm_fini(struct amdgpu_device *adev); 1686void amdgpu_ttm_fini(struct amdgpu_device *adev);
1686void amdgpu_program_register_sequence(struct amdgpu_device *adev, 1687void amdgpu_program_register_sequence(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index b7e2762fcdd2..4f973a9c7b87 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -74,6 +74,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev)
74 iounmap(bios); 74 iounmap(bios);
75 return false; 75 return false;
76 } 76 }
77 adev->bios_size = size;
77 memcpy_fromio(adev->bios, bios, size); 78 memcpy_fromio(adev->bios, bios, size);
78 iounmap(bios); 79 iounmap(bios);
79 return true; 80 return true;
@@ -103,6 +104,7 @@ bool amdgpu_read_bios(struct amdgpu_device *adev)
103 pci_unmap_rom(adev->pdev, bios); 104 pci_unmap_rom(adev->pdev, bios);
104 return false; 105 return false;
105 } 106 }
107 adev->bios_size = size;
106 memcpy_fromio(adev->bios, bios, size); 108 memcpy_fromio(adev->bios, bios, size);
107 pci_unmap_rom(adev->pdev, bios); 109 pci_unmap_rom(adev->pdev, bios);
108 return true; 110 return true;
@@ -135,6 +137,7 @@ static bool amdgpu_read_bios_from_rom(struct amdgpu_device *adev)
135 DRM_ERROR("no memory to allocate for BIOS\n"); 137 DRM_ERROR("no memory to allocate for BIOS\n");
136 return false; 138 return false;
137 } 139 }
140 adev->bios_size = len;
138 141
139 /* read complete BIOS */ 142 /* read complete BIOS */
140 return amdgpu_asic_read_bios_from_rom(adev, adev->bios, len); 143 return amdgpu_asic_read_bios_from_rom(adev, adev->bios, len);
@@ -159,6 +162,7 @@ static bool amdgpu_read_platform_bios(struct amdgpu_device *adev)
159 if (adev->bios == NULL) { 162 if (adev->bios == NULL) {
160 return false; 163 return false;
161 } 164 }
165 adev->bios_size = size;
162 166
163 return true; 167 return true;
164} 168}
@@ -273,6 +277,7 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)
273 kfree(adev->bios); 277 kfree(adev->bios);
274 return false; 278 return false;
275 } 279 }
280 adev->bios_size = size;
276 return true; 281 return true;
277} 282}
278#else 283#else
@@ -334,6 +339,7 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev)
334 } 339 }
335 340
336 adev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL); 341 adev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL);
342 adev->bios_size = vhdr->ImageLength;
337 ret = !!adev->bios; 343 ret = !!adev->bios;
338 344
339out_unmap: 345out_unmap:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 7ded61e6dd81..9ada56c16a58 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -723,7 +723,7 @@ static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
723 enum cgs_ucode_id type) 723 enum cgs_ucode_id type)
724{ 724{
725 CGS_FUNC_ADEV; 725 CGS_FUNC_ADEV;
726 uint16_t fw_version; 726 uint16_t fw_version = 0;
727 727
728 switch (type) { 728 switch (type) {
729 case CGS_UCODE_ID_SDMA0: 729 case CGS_UCODE_ID_SDMA0:
@@ -753,9 +753,11 @@ static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
753 case CGS_UCODE_ID_RLC_G: 753 case CGS_UCODE_ID_RLC_G:
754 fw_version = adev->gfx.rlc_fw_version; 754 fw_version = adev->gfx.rlc_fw_version;
755 break; 755 break;
756 case CGS_UCODE_ID_STORAGE:
757 break;
756 default: 758 default:
757 DRM_ERROR("firmware type %d do not have version\n", type); 759 DRM_ERROR("firmware type %d do not have version\n", type);
758 fw_version = 0; 760 break;
759 } 761 }
760 return fw_version; 762 return fw_version;
761} 763}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 5a277495d6a3..29d6d84d1c28 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -451,7 +451,7 @@ static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
451 return r; 451 return r;
452 452
453 if (bo->shadow) 453 if (bo->shadow)
454 r = amdgpu_cs_bo_validate(p, bo); 454 r = amdgpu_cs_bo_validate(p, bo->shadow);
455 455
456 return r; 456 return r;
457} 457}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index fc790e5c46fd..53ea782c2c47 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1470,20 +1470,26 @@ static int amdgpu_fini(struct amdgpu_device *adev)
1470 amdgpu_wb_fini(adev); 1470 amdgpu_wb_fini(adev);
1471 amdgpu_vram_scratch_fini(adev); 1471 amdgpu_vram_scratch_fini(adev);
1472 } 1472 }
1473 /* ungate blocks before hw fini so that we can shutdown the blocks safely */ 1473
1474 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, 1474 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1475 AMD_CG_STATE_UNGATE); 1475 adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1476 if (r) { 1476 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1477 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", 1477 r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1478 adev->ip_blocks[i].version->funcs->name, r); 1478 AMD_CG_STATE_UNGATE);
1479 return r; 1479 if (r) {
1480 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1481 adev->ip_blocks[i].version->funcs->name, r);
1482 return r;
1483 }
1480 } 1484 }
1485
1481 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); 1486 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1482 /* XXX handle errors */ 1487 /* XXX handle errors */
1483 if (r) { 1488 if (r) {
1484 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", 1489 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1485 adev->ip_blocks[i].version->funcs->name, r); 1490 adev->ip_blocks[i].version->funcs->name, r);
1486 } 1491 }
1492
1487 adev->ip_blocks[i].status.hw = false; 1493 adev->ip_blocks[i].status.hw = false;
1488 } 1494 }
1489 1495
@@ -2979,6 +2985,66 @@ static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
2979 return result; 2985 return result;
2980} 2986}
2981 2987
2988static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
2989 size_t size, loff_t *pos)
2990{
2991 struct amdgpu_device *adev = f->f_inode->i_private;
2992 int r;
2993 ssize_t result = 0;
2994 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
2995
2996 if (size & 3 || *pos & 3)
2997 return -EINVAL;
2998
2999 /* decode offset */
3000 offset = (*pos & 0xFFF); /* in dwords */
3001 se = ((*pos >> 12) & 0xFF);
3002 sh = ((*pos >> 20) & 0xFF);
3003 cu = ((*pos >> 28) & 0xFF);
3004 wave = ((*pos >> 36) & 0xFF);
3005 simd = ((*pos >> 44) & 0xFF);
3006 thread = ((*pos >> 52) & 0xFF);
3007 bank = ((*pos >> 60) & 1);
3008
3009 data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
3010 if (!data)
3011 return -ENOMEM;
3012
3013 /* switch to the specific se/sh/cu */
3014 mutex_lock(&adev->grbm_idx_mutex);
3015 amdgpu_gfx_select_se_sh(adev, se, sh, cu);
3016
3017 if (bank == 0) {
3018 if (adev->gfx.funcs->read_wave_vgprs)
3019 adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
3020 } else {
3021 if (adev->gfx.funcs->read_wave_sgprs)
3022 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
3023 }
3024
3025 amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3026 mutex_unlock(&adev->grbm_idx_mutex);
3027
3028 while (size) {
3029 uint32_t value;
3030
3031 value = data[offset++];
3032 r = put_user(value, (uint32_t *)buf);
3033 if (r) {
3034 result = r;
3035 goto err;
3036 }
3037
3038 result += 4;
3039 buf += 4;
3040 size -= 4;
3041 }
3042
3043err:
3044 kfree(data);
3045 return result;
3046}
3047
2982static const struct file_operations amdgpu_debugfs_regs_fops = { 3048static const struct file_operations amdgpu_debugfs_regs_fops = {
2983 .owner = THIS_MODULE, 3049 .owner = THIS_MODULE,
2984 .read = amdgpu_debugfs_regs_read, 3050 .read = amdgpu_debugfs_regs_read,
@@ -3021,6 +3087,11 @@ static const struct file_operations amdgpu_debugfs_wave_fops = {
3021 .read = amdgpu_debugfs_wave_read, 3087 .read = amdgpu_debugfs_wave_read,
3022 .llseek = default_llseek 3088 .llseek = default_llseek
3023}; 3089};
3090static const struct file_operations amdgpu_debugfs_gpr_fops = {
3091 .owner = THIS_MODULE,
3092 .read = amdgpu_debugfs_gpr_read,
3093 .llseek = default_llseek
3094};
3024 3095
3025static const struct file_operations *debugfs_regs[] = { 3096static const struct file_operations *debugfs_regs[] = {
3026 &amdgpu_debugfs_regs_fops, 3097 &amdgpu_debugfs_regs_fops,
@@ -3030,6 +3101,7 @@ static const struct file_operations *debugfs_regs[] = {
3030 &amdgpu_debugfs_gca_config_fops, 3101 &amdgpu_debugfs_gca_config_fops,
3031 &amdgpu_debugfs_sensors_fops, 3102 &amdgpu_debugfs_sensors_fops,
3032 &amdgpu_debugfs_wave_fops, 3103 &amdgpu_debugfs_wave_fops,
3104 &amdgpu_debugfs_gpr_fops,
3033}; 3105};
3034 3106
3035static const char *debugfs_regs_names[] = { 3107static const char *debugfs_regs_names[] = {
@@ -3040,6 +3112,7 @@ static const char *debugfs_regs_names[] = {
3040 "amdgpu_gca_config", 3112 "amdgpu_gca_config",
3041 "amdgpu_sensors", 3113 "amdgpu_sensors",
3042 "amdgpu_wave", 3114 "amdgpu_wave",
3115 "amdgpu_gpr",
3043}; 3116};
3044 3117
3045static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) 3118static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 741144fcc7bc..581601ca6b89 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -187,7 +187,7 @@ int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc,
187 goto cleanup; 187 goto cleanup;
188 } 188 }
189 189
190 r = amdgpu_bo_pin_restricted(new_abo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, &base); 190 r = amdgpu_bo_pin(new_abo, AMDGPU_GEM_DOMAIN_VRAM, &base);
191 if (unlikely(r != 0)) { 191 if (unlikely(r != 0)) {
192 r = -EINVAL; 192 r = -EINVAL;
193 DRM_ERROR("failed to pin new abo buffer before flip\n"); 193 DRM_ERROR("failed to pin new abo buffer before flip\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index f1c9e59a7c87..24629bec181a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -171,7 +171,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
171 } 171 }
172 172
173 173
174 ret = amdgpu_bo_pin_restricted(abo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, NULL); 174 ret = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, NULL);
175 if (ret) { 175 if (ret) {
176 amdgpu_bo_unreserve(abo); 176 amdgpu_bo_unreserve(abo);
177 goto out_unref; 177 goto out_unref;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 3c634f02a3d5..00f46b0e076d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -164,8 +164,10 @@ static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man,
164 spin_unlock(&mgr->lock); 164 spin_unlock(&mgr->lock);
165 165
166 node = kzalloc(sizeof(*node), GFP_KERNEL); 166 node = kzalloc(sizeof(*node), GFP_KERNEL);
167 if (!node) 167 if (!node) {
168 return -ENOMEM; 168 r = -ENOMEM;
169 goto err_out;
170 }
169 171
170 node->start = AMDGPU_BO_INVALID_OFFSET; 172 node->start = AMDGPU_BO_INVALID_OFFSET;
171 node->size = mem->num_pages; 173 node->size = mem->num_pages;
@@ -176,12 +178,20 @@ static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man,
176 if (unlikely(r)) { 178 if (unlikely(r)) {
177 kfree(node); 179 kfree(node);
178 mem->mm_node = NULL; 180 mem->mm_node = NULL;
181 r = 0;
182 goto err_out;
179 } 183 }
180 } else { 184 } else {
181 mem->start = node->start; 185 mem->start = node->start;
182 } 186 }
183 187
184 return 0; 188 return 0;
189err_out:
190 spin_lock(&mgr->lock);
191 mgr->available += mem->num_pages;
192 spin_unlock(&mgr->lock);
193
194 return r;
185} 195}
186 196
187/** 197/**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index d1cf9ac0dff1..9af87eaf8ee3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -544,6 +544,32 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
544 return copy_to_user(out, &vce_clk_table, 544 return copy_to_user(out, &vce_clk_table,
545 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 545 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
546 } 546 }
547 case AMDGPU_INFO_VBIOS: {
548 uint32_t bios_size = adev->bios_size;
549
550 switch (info->vbios_info.type) {
551 case AMDGPU_INFO_VBIOS_SIZE:
552 return copy_to_user(out, &bios_size,
553 min((size_t)size, sizeof(bios_size)))
554 ? -EFAULT : 0;
555 case AMDGPU_INFO_VBIOS_IMAGE: {
556 uint8_t *bios;
557 uint32_t bios_offset = info->vbios_info.offset;
558
559 if (bios_offset >= bios_size)
560 return -EINVAL;
561
562 bios = adev->bios + bios_offset;
563 return copy_to_user(out, bios,
564 min((size_t)size, (size_t)(bios_size - bios_offset)))
565 ? -EFAULT : 0;
566 }
567 default:
568 DRM_DEBUG_KMS("Invalid request %d\n",
569 info->vbios_info.type);
570 return -EINVAL;
571 }
572 }
547 default: 573 default:
548 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 574 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
549 return -EINVAL; 575 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 8f18b8ed2b3a..bc70f80260d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -34,7 +34,6 @@
34#include <ttm/ttm_placement.h> 34#include <ttm/ttm_placement.h>
35#include <ttm/ttm_module.h> 35#include <ttm/ttm_module.h>
36#include <ttm/ttm_page_alloc.h> 36#include <ttm/ttm_page_alloc.h>
37#include <ttm/ttm_memory.h>
38#include <drm/drmP.h> 37#include <drm/drmP.h>
39#include <drm/amdgpu_drm.h> 38#include <drm/amdgpu_drm.h>
40#include <linux/seq_file.h> 39#include <linux/seq_file.h>
@@ -65,7 +64,7 @@ static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
65 ttm_mem_global_release(ref->object); 64 ttm_mem_global_release(ref->object);
66} 65}
67 66
68int amdgpu_ttm_global_init(struct amdgpu_device *adev) 67static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
69{ 68{
70 struct drm_global_reference *global_ref; 69 struct drm_global_reference *global_ref;
71 struct amdgpu_ring *ring; 70 struct amdgpu_ring *ring;
@@ -1151,6 +1150,10 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
1151 unsigned i, j; 1150 unsigned i, j;
1152 int r; 1151 int r;
1153 1152
1153 r = amdgpu_ttm_global_init(adev);
1154 if (r) {
1155 return r;
1156 }
1154 /* No others user of address space so set it to 0 */ 1157 /* No others user of address space so set it to 0 */
1155 r = ttm_bo_device_init(&adev->mman.bdev, 1158 r = ttm_bo_device_init(&adev->mman.bdev,
1156 adev->mman.bo_global_ref.ref.object, 1159 adev->mman.bo_global_ref.ref.object,
@@ -1650,8 +1653,3 @@ static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
1650 1653
1651#endif 1654#endif
1652} 1655}
1653
1654u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev)
1655{
1656 return ttm_get_kernel_zone_memory_size(adev->mman.mem_global_ref.object);
1657}
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 1027f92de32b..bda9e3de191e 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -6083,7 +6083,7 @@ ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
6083 activity_percent = activity_percent > 100 ? 100 : activity_percent; 6083 activity_percent = activity_percent > 100 ? 100 : activity_percent;
6084 } 6084 }
6085 6085
6086 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis"); 6086 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");
6087 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis"); 6087 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
6088 seq_printf(m, "power level avg sclk: %u mclk: %u\n", 6088 seq_printf(m, "power level avg sclk: %u mclk: %u\n",
6089 sclk, mclk); 6089 sclk, mclk);
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 075aa0b1b075..9999dc71b998 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -2493,6 +2493,9 @@ static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2493 struct amdgpu_device *adev = crtc->dev->dev_private; 2493 struct amdgpu_device *adev = crtc->dev->dev_private;
2494 int xorigin = 0, yorigin = 0; 2494 int xorigin = 0, yorigin = 0;
2495 2495
2496 amdgpu_crtc->cursor_x = x;
2497 amdgpu_crtc->cursor_y = y;
2498
2496 /* avivo cursor are offset into the total surface */ 2499 /* avivo cursor are offset into the total surface */
2497 x += crtc->x; 2500 x += crtc->x;
2498 y += crtc->y; 2501 y += crtc->y;
@@ -2509,11 +2512,6 @@ static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2509 2512
2510 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2513 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2511 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2514 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2512 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2513 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2514
2515 amdgpu_crtc->cursor_x = x;
2516 amdgpu_crtc->cursor_y = y;
2517 2515
2518 return 0; 2516 return 0;
2519} 2517}
@@ -2539,6 +2537,7 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2539 int32_t hot_y) 2537 int32_t hot_y)
2540{ 2538{
2541 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2539 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2540 struct amdgpu_device *adev = crtc->dev->dev_private;
2542 struct drm_gem_object *obj; 2541 struct drm_gem_object *obj;
2543 struct amdgpu_bo *aobj; 2542 struct amdgpu_bo *aobj;
2544 int ret; 2543 int ret;
@@ -2577,9 +2576,6 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2577 return ret; 2576 return ret;
2578 } 2577 }
2579 2578
2580 amdgpu_crtc->cursor_width = width;
2581 amdgpu_crtc->cursor_height = height;
2582
2583 dce_v10_0_lock_cursor(crtc, true); 2579 dce_v10_0_lock_cursor(crtc, true);
2584 2580
2585 if (hot_x != amdgpu_crtc->cursor_hot_x || 2581 if (hot_x != amdgpu_crtc->cursor_hot_x ||
@@ -2595,6 +2591,14 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2595 amdgpu_crtc->cursor_hot_y = hot_y; 2591 amdgpu_crtc->cursor_hot_y = hot_y;
2596 } 2592 }
2597 2593
2594 if (width != amdgpu_crtc->cursor_width ||
2595 height != amdgpu_crtc->cursor_height) {
2596 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2597 (width - 1) << 16 | (height - 1));
2598 amdgpu_crtc->cursor_width = width;
2599 amdgpu_crtc->cursor_height = height;
2600 }
2601
2598 dce_v10_0_show_cursor(crtc); 2602 dce_v10_0_show_cursor(crtc);
2599 dce_v10_0_lock_cursor(crtc, false); 2603 dce_v10_0_lock_cursor(crtc, false);
2600 2604
@@ -2616,6 +2620,7 @@ unpin:
2616static void dce_v10_0_cursor_reset(struct drm_crtc *crtc) 2620static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2617{ 2621{
2618 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2622 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2623 struct amdgpu_device *adev = crtc->dev->dev_private;
2619 2624
2620 if (amdgpu_crtc->cursor_bo) { 2625 if (amdgpu_crtc->cursor_bo) {
2621 dce_v10_0_lock_cursor(crtc, true); 2626 dce_v10_0_lock_cursor(crtc, true);
@@ -2623,6 +2628,10 @@ static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2623 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2628 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2624 amdgpu_crtc->cursor_y); 2629 amdgpu_crtc->cursor_y);
2625 2630
2631 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2632 (amdgpu_crtc->cursor_width - 1) << 16 |
2633 (amdgpu_crtc->cursor_height - 1));
2634
2626 dce_v10_0_show_cursor(crtc); 2635 dce_v10_0_show_cursor(crtc);
2627 2636
2628 dce_v10_0_lock_cursor(crtc, false); 2637 dce_v10_0_lock_cursor(crtc, false);
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index a6717487ac78..b3d62b909f43 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -2509,6 +2509,9 @@ static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2509 struct amdgpu_device *adev = crtc->dev->dev_private; 2509 struct amdgpu_device *adev = crtc->dev->dev_private;
2510 int xorigin = 0, yorigin = 0; 2510 int xorigin = 0, yorigin = 0;
2511 2511
2512 amdgpu_crtc->cursor_x = x;
2513 amdgpu_crtc->cursor_y = y;
2514
2512 /* avivo cursor are offset into the total surface */ 2515 /* avivo cursor are offset into the total surface */
2513 x += crtc->x; 2516 x += crtc->x;
2514 y += crtc->y; 2517 y += crtc->y;
@@ -2525,11 +2528,6 @@ static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2525 2528
2526 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2529 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2527 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2530 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2528 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2529 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2530
2531 amdgpu_crtc->cursor_x = x;
2532 amdgpu_crtc->cursor_y = y;
2533 2531
2534 return 0; 2532 return 0;
2535} 2533}
@@ -2555,6 +2553,7 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2555 int32_t hot_y) 2553 int32_t hot_y)
2556{ 2554{
2557 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2555 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2556 struct amdgpu_device *adev = crtc->dev->dev_private;
2558 struct drm_gem_object *obj; 2557 struct drm_gem_object *obj;
2559 struct amdgpu_bo *aobj; 2558 struct amdgpu_bo *aobj;
2560 int ret; 2559 int ret;
@@ -2593,9 +2592,6 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2593 return ret; 2592 return ret;
2594 } 2593 }
2595 2594
2596 amdgpu_crtc->cursor_width = width;
2597 amdgpu_crtc->cursor_height = height;
2598
2599 dce_v11_0_lock_cursor(crtc, true); 2595 dce_v11_0_lock_cursor(crtc, true);
2600 2596
2601 if (hot_x != amdgpu_crtc->cursor_hot_x || 2597 if (hot_x != amdgpu_crtc->cursor_hot_x ||
@@ -2611,6 +2607,14 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2611 amdgpu_crtc->cursor_hot_y = hot_y; 2607 amdgpu_crtc->cursor_hot_y = hot_y;
2612 } 2608 }
2613 2609
2610 if (width != amdgpu_crtc->cursor_width ||
2611 height != amdgpu_crtc->cursor_height) {
2612 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2613 (width - 1) << 16 | (height - 1));
2614 amdgpu_crtc->cursor_width = width;
2615 amdgpu_crtc->cursor_height = height;
2616 }
2617
2614 dce_v11_0_show_cursor(crtc); 2618 dce_v11_0_show_cursor(crtc);
2615 dce_v11_0_lock_cursor(crtc, false); 2619 dce_v11_0_lock_cursor(crtc, false);
2616 2620
@@ -2632,6 +2636,7 @@ unpin:
2632static void dce_v11_0_cursor_reset(struct drm_crtc *crtc) 2636static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2633{ 2637{
2634 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2638 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2639 struct amdgpu_device *adev = crtc->dev->dev_private;
2635 2640
2636 if (amdgpu_crtc->cursor_bo) { 2641 if (amdgpu_crtc->cursor_bo) {
2637 dce_v11_0_lock_cursor(crtc, true); 2642 dce_v11_0_lock_cursor(crtc, true);
@@ -2639,6 +2644,10 @@ static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2639 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2644 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2640 amdgpu_crtc->cursor_y); 2645 amdgpu_crtc->cursor_y);
2641 2646
2647 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2648 (amdgpu_crtc->cursor_width - 1) << 16 |
2649 (amdgpu_crtc->cursor_height - 1));
2650
2642 dce_v11_0_show_cursor(crtc); 2651 dce_v11_0_show_cursor(crtc);
2643 2652
2644 dce_v11_0_lock_cursor(crtc, false); 2653 dce_v11_0_lock_cursor(crtc, false);
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 15d98ef696a2..e564442b6393 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -460,9 +460,8 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
460 for (i = 0; i < adev->mode_info.num_crtc; i++) { 460 for (i = 0; i < adev->mode_info.num_crtc; i++) {
461 if (save->crtc_enabled[i]) { 461 if (save->crtc_enabled[i]) {
462 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]); 462 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
463 if ((tmp & 0x7) != 3) { 463 if ((tmp & 0x7) != 0) {
464 tmp &= ~0x7; 464 tmp &= ~0x7;
465 tmp |= 0x3;
466 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp); 465 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
467 } 466 }
468 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 467 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
@@ -1860,7 +1859,8 @@ static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc,
1860 struct amdgpu_device *adev = crtc->dev->dev_private; 1859 struct amdgpu_device *adev = crtc->dev->dev_private;
1861 int xorigin = 0, yorigin = 0; 1860 int xorigin = 0, yorigin = 0;
1862 1861
1863 int w = amdgpu_crtc->cursor_width; 1862 amdgpu_crtc->cursor_x = x;
1863 amdgpu_crtc->cursor_y = y;
1864 1864
1865 /* avivo cursor are offset into the total surface */ 1865 /* avivo cursor are offset into the total surface */
1866 x += crtc->x; 1866 x += crtc->x;
@@ -1878,11 +1878,7 @@ static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc,
1878 1878
1879 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 1879 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
1880 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 1880 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
1881 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
1882 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
1883 1881
1884 amdgpu_crtc->cursor_x = x;
1885 amdgpu_crtc->cursor_y = y;
1886 return 0; 1882 return 0;
1887} 1883}
1888 1884
@@ -1907,6 +1903,7 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
1907 int32_t hot_y) 1903 int32_t hot_y)
1908{ 1904{
1909 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1905 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1906 struct amdgpu_device *adev = crtc->dev->dev_private;
1910 struct drm_gem_object *obj; 1907 struct drm_gem_object *obj;
1911 struct amdgpu_bo *aobj; 1908 struct amdgpu_bo *aobj;
1912 int ret; 1909 int ret;
@@ -1945,12 +1942,11 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
1945 return ret; 1942 return ret;
1946 } 1943 }
1947 1944
1948 amdgpu_crtc->cursor_width = width;
1949 amdgpu_crtc->cursor_height = height;
1950
1951 dce_v6_0_lock_cursor(crtc, true); 1945 dce_v6_0_lock_cursor(crtc, true);
1952 1946
1953 if (hot_x != amdgpu_crtc->cursor_hot_x || 1947 if (width != amdgpu_crtc->cursor_width ||
1948 height != amdgpu_crtc->cursor_height ||
1949 hot_x != amdgpu_crtc->cursor_hot_x ||
1954 hot_y != amdgpu_crtc->cursor_hot_y) { 1950 hot_y != amdgpu_crtc->cursor_hot_y) {
1955 int x, y; 1951 int x, y;
1956 1952
@@ -1959,10 +1955,20 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
1959 1955
1960 dce_v6_0_cursor_move_locked(crtc, x, y); 1956 dce_v6_0_cursor_move_locked(crtc, x, y);
1961 1957
1958 amdgpu_crtc->cursor_width = width;
1959 amdgpu_crtc->cursor_height = height;
1962 amdgpu_crtc->cursor_hot_x = hot_x; 1960 amdgpu_crtc->cursor_hot_x = hot_x;
1963 amdgpu_crtc->cursor_hot_y = hot_y; 1961 amdgpu_crtc->cursor_hot_y = hot_y;
1964 } 1962 }
1965 1963
1964 if (width != amdgpu_crtc->cursor_width ||
1965 height != amdgpu_crtc->cursor_height) {
1966 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
1967 (width - 1) << 16 | (height - 1));
1968 amdgpu_crtc->cursor_width = width;
1969 amdgpu_crtc->cursor_height = height;
1970 }
1971
1966 dce_v6_0_show_cursor(crtc); 1972 dce_v6_0_show_cursor(crtc);
1967 dce_v6_0_lock_cursor(crtc, false); 1973 dce_v6_0_lock_cursor(crtc, false);
1968 1974
@@ -1984,6 +1990,7 @@ unpin:
1984static void dce_v6_0_cursor_reset(struct drm_crtc *crtc) 1990static void dce_v6_0_cursor_reset(struct drm_crtc *crtc)
1985{ 1991{
1986 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1992 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1993 struct amdgpu_device *adev = crtc->dev->dev_private;
1987 1994
1988 if (amdgpu_crtc->cursor_bo) { 1995 if (amdgpu_crtc->cursor_bo) {
1989 dce_v6_0_lock_cursor(crtc, true); 1996 dce_v6_0_lock_cursor(crtc, true);
@@ -1991,6 +1998,10 @@ static void dce_v6_0_cursor_reset(struct drm_crtc *crtc)
1991 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 1998 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
1992 amdgpu_crtc->cursor_y); 1999 amdgpu_crtc->cursor_y);
1993 2000
2001 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2002 (amdgpu_crtc->cursor_width - 1) << 16 |
2003 (amdgpu_crtc->cursor_height - 1));
2004
1994 dce_v6_0_show_cursor(crtc); 2005 dce_v6_0_show_cursor(crtc);
1995 dce_v6_0_lock_cursor(crtc, false); 2006 dce_v6_0_lock_cursor(crtc, false);
1996 } 2007 }
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index a699896eeabc..6ce7fb42dbef 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -2344,6 +2344,9 @@ static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2344 struct amdgpu_device *adev = crtc->dev->dev_private; 2344 struct amdgpu_device *adev = crtc->dev->dev_private;
2345 int xorigin = 0, yorigin = 0; 2345 int xorigin = 0, yorigin = 0;
2346 2346
2347 amdgpu_crtc->cursor_x = x;
2348 amdgpu_crtc->cursor_y = y;
2349
2347 /* avivo cursor are offset into the total surface */ 2350 /* avivo cursor are offset into the total surface */
2348 x += crtc->x; 2351 x += crtc->x;
2349 y += crtc->y; 2352 y += crtc->y;
@@ -2360,11 +2363,6 @@ static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
2360 2363
2361 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2364 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2362 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2365 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2363 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2364 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2365
2366 amdgpu_crtc->cursor_x = x;
2367 amdgpu_crtc->cursor_y = y;
2368 2366
2369 return 0; 2367 return 0;
2370} 2368}
@@ -2390,6 +2388,7 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2390 int32_t hot_y) 2388 int32_t hot_y)
2391{ 2389{
2392 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2390 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2391 struct amdgpu_device *adev = crtc->dev->dev_private;
2393 struct drm_gem_object *obj; 2392 struct drm_gem_object *obj;
2394 struct amdgpu_bo *aobj; 2393 struct amdgpu_bo *aobj;
2395 int ret; 2394 int ret;
@@ -2428,9 +2427,6 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2428 return ret; 2427 return ret;
2429 } 2428 }
2430 2429
2431 amdgpu_crtc->cursor_width = width;
2432 amdgpu_crtc->cursor_height = height;
2433
2434 dce_v8_0_lock_cursor(crtc, true); 2430 dce_v8_0_lock_cursor(crtc, true);
2435 2431
2436 if (hot_x != amdgpu_crtc->cursor_hot_x || 2432 if (hot_x != amdgpu_crtc->cursor_hot_x ||
@@ -2442,10 +2438,20 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2442 2438
2443 dce_v8_0_cursor_move_locked(crtc, x, y); 2439 dce_v8_0_cursor_move_locked(crtc, x, y);
2444 2440
2441 amdgpu_crtc->cursor_width = width;
2442 amdgpu_crtc->cursor_height = height;
2445 amdgpu_crtc->cursor_hot_x = hot_x; 2443 amdgpu_crtc->cursor_hot_x = hot_x;
2446 amdgpu_crtc->cursor_hot_y = hot_y; 2444 amdgpu_crtc->cursor_hot_y = hot_y;
2447 } 2445 }
2448 2446
2447 if (width != amdgpu_crtc->cursor_width ||
2448 height != amdgpu_crtc->cursor_height) {
2449 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2450 (width - 1) << 16 | (height - 1));
2451 amdgpu_crtc->cursor_width = width;
2452 amdgpu_crtc->cursor_height = height;
2453 }
2454
2449 dce_v8_0_show_cursor(crtc); 2455 dce_v8_0_show_cursor(crtc);
2450 dce_v8_0_lock_cursor(crtc, false); 2456 dce_v8_0_lock_cursor(crtc, false);
2451 2457
@@ -2467,6 +2473,7 @@ unpin:
2467static void dce_v8_0_cursor_reset(struct drm_crtc *crtc) 2473static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2468{ 2474{
2469 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2475 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2476 struct amdgpu_device *adev = crtc->dev->dev_private;
2470 2477
2471 if (amdgpu_crtc->cursor_bo) { 2478 if (amdgpu_crtc->cursor_bo) {
2472 dce_v8_0_lock_cursor(crtc, true); 2479 dce_v8_0_lock_cursor(crtc, true);
@@ -2474,6 +2481,10 @@ static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
2474 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2481 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2475 amdgpu_crtc->cursor_y); 2482 amdgpu_crtc->cursor_y);
2476 2483
2484 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2485 (amdgpu_crtc->cursor_width - 1) << 16 |
2486 (amdgpu_crtc->cursor_height - 1));
2487
2477 dce_v8_0_show_cursor(crtc); 2488 dce_v8_0_show_cursor(crtc);
2478 2489
2479 dce_v8_0_lock_cursor(crtc, false); 2490 dce_v8_0_lock_cursor(crtc, false);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 879a94bbfe12..558640aee15a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2827,6 +2827,21 @@ static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_
2827 return RREG32(mmSQ_IND_DATA); 2827 return RREG32(mmSQ_IND_DATA);
2828} 2828}
2829 2829
2830static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
2831 uint32_t wave, uint32_t thread,
2832 uint32_t regno, uint32_t num, uint32_t *out)
2833{
2834 WREG32(mmSQ_IND_INDEX,
2835 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2836 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2837 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
2838 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
2839 (SQ_IND_INDEX__FORCE_READ_MASK) |
2840 (SQ_IND_INDEX__AUTO_INCR_MASK));
2841 while (num--)
2842 *(out++) = RREG32(mmSQ_IND_DATA);
2843}
2844
2830static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 2845static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
2831{ 2846{
2832 /* type 0 wave data */ 2847 /* type 0 wave data */
@@ -2851,10 +2866,20 @@ static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, u
2851 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 2866 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
2852} 2867}
2853 2868
2869static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
2870 uint32_t wave, uint32_t start,
2871 uint32_t size, uint32_t *dst)
2872{
2873 wave_read_regs(
2874 adev, simd, wave, 0,
2875 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
2876}
2877
2854static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { 2878static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
2855 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter, 2879 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
2856 .select_se_sh = &gfx_v6_0_select_se_sh, 2880 .select_se_sh = &gfx_v6_0_select_se_sh,
2857 .read_wave_data = &gfx_v6_0_read_wave_data, 2881 .read_wave_data = &gfx_v6_0_read_wave_data,
2882 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
2858}; 2883};
2859 2884
2860static int gfx_v6_0_early_init(void *handle) 2885static int gfx_v6_0_early_init(void *handle)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 1a745cf93f47..c4e14015ec5b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4380,6 +4380,21 @@ static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_
4380 return RREG32(mmSQ_IND_DATA); 4380 return RREG32(mmSQ_IND_DATA);
4381} 4381}
4382 4382
4383static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
4384 uint32_t wave, uint32_t thread,
4385 uint32_t regno, uint32_t num, uint32_t *out)
4386{
4387 WREG32(mmSQ_IND_INDEX,
4388 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4389 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
4390 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4391 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
4392 (SQ_IND_INDEX__FORCE_READ_MASK) |
4393 (SQ_IND_INDEX__AUTO_INCR_MASK));
4394 while (num--)
4395 *(out++) = RREG32(mmSQ_IND_DATA);
4396}
4397
4383static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4398static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4384{ 4399{
4385 /* type 0 wave data */ 4400 /* type 0 wave data */
@@ -4404,10 +4419,20 @@ static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, u
4404 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 4419 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
4405} 4420}
4406 4421
4422static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4423 uint32_t wave, uint32_t start,
4424 uint32_t size, uint32_t *dst)
4425{
4426 wave_read_regs(
4427 adev, simd, wave, 0,
4428 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
4429}
4430
4407static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = { 4431static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
4408 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter, 4432 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
4409 .select_se_sh = &gfx_v7_0_select_se_sh, 4433 .select_se_sh = &gfx_v7_0_select_se_sh,
4410 .read_wave_data = &gfx_v7_0_read_wave_data, 4434 .read_wave_data = &gfx_v7_0_read_wave_data,
4435 .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs,
4411}; 4436};
4412 4437
4413static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = { 4438static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index a3684891c6e1..6324f67bdb1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -25,6 +25,7 @@
25#include "amdgpu.h" 25#include "amdgpu.h"
26#include "amdgpu_gfx.h" 26#include "amdgpu_gfx.h"
27#include "vi.h" 27#include "vi.h"
28#include "vi_structs.h"
28#include "vid.h" 29#include "vid.h"
29#include "amdgpu_ucode.h" 30#include "amdgpu_ucode.h"
30#include "amdgpu_atombios.h" 31#include "amdgpu_atombios.h"
@@ -167,6 +168,7 @@ static const u32 golden_settings_tonga_a11[] =
167 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, 168 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
168 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc, 169 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
169 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 170 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
171 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
170 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, 172 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
171 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, 173 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
172 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 174 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
@@ -1371,7 +1373,7 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
1371 1373
1372 if (adev->gfx.mec.hpd_eop_obj == NULL) { 1374 if (adev->gfx.mec.hpd_eop_obj == NULL) {
1373 r = amdgpu_bo_create(adev, 1375 r = amdgpu_bo_create(adev,
1374 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2, 1376 adev->gfx.mec.num_queue * MEC_HPD_SIZE,
1375 PAGE_SIZE, true, 1377 PAGE_SIZE, true,
1376 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL, 1378 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
1377 &adev->gfx.mec.hpd_eop_obj); 1379 &adev->gfx.mec.hpd_eop_obj);
@@ -1400,7 +1402,7 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
1400 return r; 1402 return r;
1401 } 1403 }
1402 1404
1403 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2); 1405 memset(hpd, 0, adev->gfx.mec.num_queue * MEC_HPD_SIZE);
1404 1406
1405 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1407 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1406 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1408 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
@@ -4469,267 +4471,6 @@ static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
4469 return 0; 4471 return 0;
4470} 4472}
4471 4473
4472struct vi_mqd {
4473 uint32_t header; /* ordinal0 */
4474 uint32_t compute_dispatch_initiator; /* ordinal1 */
4475 uint32_t compute_dim_x; /* ordinal2 */
4476 uint32_t compute_dim_y; /* ordinal3 */
4477 uint32_t compute_dim_z; /* ordinal4 */
4478 uint32_t compute_start_x; /* ordinal5 */
4479 uint32_t compute_start_y; /* ordinal6 */
4480 uint32_t compute_start_z; /* ordinal7 */
4481 uint32_t compute_num_thread_x; /* ordinal8 */
4482 uint32_t compute_num_thread_y; /* ordinal9 */
4483 uint32_t compute_num_thread_z; /* ordinal10 */
4484 uint32_t compute_pipelinestat_enable; /* ordinal11 */
4485 uint32_t compute_perfcount_enable; /* ordinal12 */
4486 uint32_t compute_pgm_lo; /* ordinal13 */
4487 uint32_t compute_pgm_hi; /* ordinal14 */
4488 uint32_t compute_tba_lo; /* ordinal15 */
4489 uint32_t compute_tba_hi; /* ordinal16 */
4490 uint32_t compute_tma_lo; /* ordinal17 */
4491 uint32_t compute_tma_hi; /* ordinal18 */
4492 uint32_t compute_pgm_rsrc1; /* ordinal19 */
4493 uint32_t compute_pgm_rsrc2; /* ordinal20 */
4494 uint32_t compute_vmid; /* ordinal21 */
4495 uint32_t compute_resource_limits; /* ordinal22 */
4496 uint32_t compute_static_thread_mgmt_se0; /* ordinal23 */
4497 uint32_t compute_static_thread_mgmt_se1; /* ordinal24 */
4498 uint32_t compute_tmpring_size; /* ordinal25 */
4499 uint32_t compute_static_thread_mgmt_se2; /* ordinal26 */
4500 uint32_t compute_static_thread_mgmt_se3; /* ordinal27 */
4501 uint32_t compute_restart_x; /* ordinal28 */
4502 uint32_t compute_restart_y; /* ordinal29 */
4503 uint32_t compute_restart_z; /* ordinal30 */
4504 uint32_t compute_thread_trace_enable; /* ordinal31 */
4505 uint32_t compute_misc_reserved; /* ordinal32 */
4506 uint32_t compute_dispatch_id; /* ordinal33 */
4507 uint32_t compute_threadgroup_id; /* ordinal34 */
4508 uint32_t compute_relaunch; /* ordinal35 */
4509 uint32_t compute_wave_restore_addr_lo; /* ordinal36 */
4510 uint32_t compute_wave_restore_addr_hi; /* ordinal37 */
4511 uint32_t compute_wave_restore_control; /* ordinal38 */
4512 uint32_t reserved9; /* ordinal39 */
4513 uint32_t reserved10; /* ordinal40 */
4514 uint32_t reserved11; /* ordinal41 */
4515 uint32_t reserved12; /* ordinal42 */
4516 uint32_t reserved13; /* ordinal43 */
4517 uint32_t reserved14; /* ordinal44 */
4518 uint32_t reserved15; /* ordinal45 */
4519 uint32_t reserved16; /* ordinal46 */
4520 uint32_t reserved17; /* ordinal47 */
4521 uint32_t reserved18; /* ordinal48 */
4522 uint32_t reserved19; /* ordinal49 */
4523 uint32_t reserved20; /* ordinal50 */
4524 uint32_t reserved21; /* ordinal51 */
4525 uint32_t reserved22; /* ordinal52 */
4526 uint32_t reserved23; /* ordinal53 */
4527 uint32_t reserved24; /* ordinal54 */
4528 uint32_t reserved25; /* ordinal55 */
4529 uint32_t reserved26; /* ordinal56 */
4530 uint32_t reserved27; /* ordinal57 */
4531 uint32_t reserved28; /* ordinal58 */
4532 uint32_t reserved29; /* ordinal59 */
4533 uint32_t reserved30; /* ordinal60 */
4534 uint32_t reserved31; /* ordinal61 */
4535 uint32_t reserved32; /* ordinal62 */
4536 uint32_t reserved33; /* ordinal63 */
4537 uint32_t reserved34; /* ordinal64 */
4538 uint32_t compute_user_data_0; /* ordinal65 */
4539 uint32_t compute_user_data_1; /* ordinal66 */
4540 uint32_t compute_user_data_2; /* ordinal67 */
4541 uint32_t compute_user_data_3; /* ordinal68 */
4542 uint32_t compute_user_data_4; /* ordinal69 */
4543 uint32_t compute_user_data_5; /* ordinal70 */
4544 uint32_t compute_user_data_6; /* ordinal71 */
4545 uint32_t compute_user_data_7; /* ordinal72 */
4546 uint32_t compute_user_data_8; /* ordinal73 */
4547 uint32_t compute_user_data_9; /* ordinal74 */
4548 uint32_t compute_user_data_10; /* ordinal75 */
4549 uint32_t compute_user_data_11; /* ordinal76 */
4550 uint32_t compute_user_data_12; /* ordinal77 */
4551 uint32_t compute_user_data_13; /* ordinal78 */
4552 uint32_t compute_user_data_14; /* ordinal79 */
4553 uint32_t compute_user_data_15; /* ordinal80 */
4554 uint32_t cp_compute_csinvoc_count_lo; /* ordinal81 */
4555 uint32_t cp_compute_csinvoc_count_hi; /* ordinal82 */
4556 uint32_t reserved35; /* ordinal83 */
4557 uint32_t reserved36; /* ordinal84 */
4558 uint32_t reserved37; /* ordinal85 */
4559 uint32_t cp_mqd_query_time_lo; /* ordinal86 */
4560 uint32_t cp_mqd_query_time_hi; /* ordinal87 */
4561 uint32_t cp_mqd_connect_start_time_lo; /* ordinal88 */
4562 uint32_t cp_mqd_connect_start_time_hi; /* ordinal89 */
4563 uint32_t cp_mqd_connect_end_time_lo; /* ordinal90 */
4564 uint32_t cp_mqd_connect_end_time_hi; /* ordinal91 */
4565 uint32_t cp_mqd_connect_end_wf_count; /* ordinal92 */
4566 uint32_t cp_mqd_connect_end_pq_rptr; /* ordinal93 */
4567 uint32_t cp_mqd_connect_end_pq_wptr; /* ordinal94 */
4568 uint32_t cp_mqd_connect_end_ib_rptr; /* ordinal95 */
4569 uint32_t reserved38; /* ordinal96 */
4570 uint32_t reserved39; /* ordinal97 */
4571 uint32_t cp_mqd_save_start_time_lo; /* ordinal98 */
4572 uint32_t cp_mqd_save_start_time_hi; /* ordinal99 */
4573 uint32_t cp_mqd_save_end_time_lo; /* ordinal100 */
4574 uint32_t cp_mqd_save_end_time_hi; /* ordinal101 */
4575 uint32_t cp_mqd_restore_start_time_lo; /* ordinal102 */
4576 uint32_t cp_mqd_restore_start_time_hi; /* ordinal103 */
4577 uint32_t cp_mqd_restore_end_time_lo; /* ordinal104 */
4578 uint32_t cp_mqd_restore_end_time_hi; /* ordinal105 */
4579 uint32_t reserved40; /* ordinal106 */
4580 uint32_t reserved41; /* ordinal107 */
4581 uint32_t gds_cs_ctxsw_cnt0; /* ordinal108 */
4582 uint32_t gds_cs_ctxsw_cnt1; /* ordinal109 */
4583 uint32_t gds_cs_ctxsw_cnt2; /* ordinal110 */
4584 uint32_t gds_cs_ctxsw_cnt3; /* ordinal111 */
4585 uint32_t reserved42; /* ordinal112 */
4586 uint32_t reserved43; /* ordinal113 */
4587 uint32_t cp_pq_exe_status_lo; /* ordinal114 */
4588 uint32_t cp_pq_exe_status_hi; /* ordinal115 */
4589 uint32_t cp_packet_id_lo; /* ordinal116 */
4590 uint32_t cp_packet_id_hi; /* ordinal117 */
4591 uint32_t cp_packet_exe_status_lo; /* ordinal118 */
4592 uint32_t cp_packet_exe_status_hi; /* ordinal119 */
4593 uint32_t gds_save_base_addr_lo; /* ordinal120 */
4594 uint32_t gds_save_base_addr_hi; /* ordinal121 */
4595 uint32_t gds_save_mask_lo; /* ordinal122 */
4596 uint32_t gds_save_mask_hi; /* ordinal123 */
4597 uint32_t ctx_save_base_addr_lo; /* ordinal124 */
4598 uint32_t ctx_save_base_addr_hi; /* ordinal125 */
4599 uint32_t reserved44; /* ordinal126 */
4600 uint32_t reserved45; /* ordinal127 */
4601 uint32_t cp_mqd_base_addr_lo; /* ordinal128 */
4602 uint32_t cp_mqd_base_addr_hi; /* ordinal129 */
4603 uint32_t cp_hqd_active; /* ordinal130 */
4604 uint32_t cp_hqd_vmid; /* ordinal131 */
4605 uint32_t cp_hqd_persistent_state; /* ordinal132 */
4606 uint32_t cp_hqd_pipe_priority; /* ordinal133 */
4607 uint32_t cp_hqd_queue_priority; /* ordinal134 */
4608 uint32_t cp_hqd_quantum; /* ordinal135 */
4609 uint32_t cp_hqd_pq_base_lo; /* ordinal136 */
4610 uint32_t cp_hqd_pq_base_hi; /* ordinal137 */
4611 uint32_t cp_hqd_pq_rptr; /* ordinal138 */
4612 uint32_t cp_hqd_pq_rptr_report_addr_lo; /* ordinal139 */
4613 uint32_t cp_hqd_pq_rptr_report_addr_hi; /* ordinal140 */
4614 uint32_t cp_hqd_pq_wptr_poll_addr; /* ordinal141 */
4615 uint32_t cp_hqd_pq_wptr_poll_addr_hi; /* ordinal142 */
4616 uint32_t cp_hqd_pq_doorbell_control; /* ordinal143 */
4617 uint32_t cp_hqd_pq_wptr; /* ordinal144 */
4618 uint32_t cp_hqd_pq_control; /* ordinal145 */
4619 uint32_t cp_hqd_ib_base_addr_lo; /* ordinal146 */
4620 uint32_t cp_hqd_ib_base_addr_hi; /* ordinal147 */
4621 uint32_t cp_hqd_ib_rptr; /* ordinal148 */
4622 uint32_t cp_hqd_ib_control; /* ordinal149 */
4623 uint32_t cp_hqd_iq_timer; /* ordinal150 */
4624 uint32_t cp_hqd_iq_rptr; /* ordinal151 */
4625 uint32_t cp_hqd_dequeue_request; /* ordinal152 */
4626 uint32_t cp_hqd_dma_offload; /* ordinal153 */
4627 uint32_t cp_hqd_sema_cmd; /* ordinal154 */
4628 uint32_t cp_hqd_msg_type; /* ordinal155 */
4629 uint32_t cp_hqd_atomic0_preop_lo; /* ordinal156 */
4630 uint32_t cp_hqd_atomic0_preop_hi; /* ordinal157 */
4631 uint32_t cp_hqd_atomic1_preop_lo; /* ordinal158 */
4632 uint32_t cp_hqd_atomic1_preop_hi; /* ordinal159 */
4633 uint32_t cp_hqd_hq_status0; /* ordinal160 */
4634 uint32_t cp_hqd_hq_control0; /* ordinal161 */
4635 uint32_t cp_mqd_control; /* ordinal162 */
4636 uint32_t cp_hqd_hq_status1; /* ordinal163 */
4637 uint32_t cp_hqd_hq_control1; /* ordinal164 */
4638 uint32_t cp_hqd_eop_base_addr_lo; /* ordinal165 */
4639 uint32_t cp_hqd_eop_base_addr_hi; /* ordinal166 */
4640 uint32_t cp_hqd_eop_control; /* ordinal167 */
4641 uint32_t cp_hqd_eop_rptr; /* ordinal168 */
4642 uint32_t cp_hqd_eop_wptr; /* ordinal169 */
4643 uint32_t cp_hqd_eop_done_events; /* ordinal170 */
4644 uint32_t cp_hqd_ctx_save_base_addr_lo; /* ordinal171 */
4645 uint32_t cp_hqd_ctx_save_base_addr_hi; /* ordinal172 */
4646 uint32_t cp_hqd_ctx_save_control; /* ordinal173 */
4647 uint32_t cp_hqd_cntl_stack_offset; /* ordinal174 */
4648 uint32_t cp_hqd_cntl_stack_size; /* ordinal175 */
4649 uint32_t cp_hqd_wg_state_offset; /* ordinal176 */
4650 uint32_t cp_hqd_ctx_save_size; /* ordinal177 */
4651 uint32_t cp_hqd_gds_resource_state; /* ordinal178 */
4652 uint32_t cp_hqd_error; /* ordinal179 */
4653 uint32_t cp_hqd_eop_wptr_mem; /* ordinal180 */
4654 uint32_t cp_hqd_eop_dones; /* ordinal181 */
4655 uint32_t reserved46; /* ordinal182 */
4656 uint32_t reserved47; /* ordinal183 */
4657 uint32_t reserved48; /* ordinal184 */
4658 uint32_t reserved49; /* ordinal185 */
4659 uint32_t reserved50; /* ordinal186 */
4660 uint32_t reserved51; /* ordinal187 */
4661 uint32_t reserved52; /* ordinal188 */
4662 uint32_t reserved53; /* ordinal189 */
4663 uint32_t reserved54; /* ordinal190 */
4664 uint32_t reserved55; /* ordinal191 */
4665 uint32_t iqtimer_pkt_header; /* ordinal192 */
4666 uint32_t iqtimer_pkt_dw0; /* ordinal193 */
4667 uint32_t iqtimer_pkt_dw1; /* ordinal194 */
4668 uint32_t iqtimer_pkt_dw2; /* ordinal195 */
4669 uint32_t iqtimer_pkt_dw3; /* ordinal196 */
4670 uint32_t iqtimer_pkt_dw4; /* ordinal197 */
4671 uint32_t iqtimer_pkt_dw5; /* ordinal198 */
4672 uint32_t iqtimer_pkt_dw6; /* ordinal199 */
4673 uint32_t iqtimer_pkt_dw7; /* ordinal200 */
4674 uint32_t iqtimer_pkt_dw8; /* ordinal201 */
4675 uint32_t iqtimer_pkt_dw9; /* ordinal202 */
4676 uint32_t iqtimer_pkt_dw10; /* ordinal203 */
4677 uint32_t iqtimer_pkt_dw11; /* ordinal204 */
4678 uint32_t iqtimer_pkt_dw12; /* ordinal205 */
4679 uint32_t iqtimer_pkt_dw13; /* ordinal206 */
4680 uint32_t iqtimer_pkt_dw14; /* ordinal207 */
4681 uint32_t iqtimer_pkt_dw15; /* ordinal208 */
4682 uint32_t iqtimer_pkt_dw16; /* ordinal209 */
4683 uint32_t iqtimer_pkt_dw17; /* ordinal210 */
4684 uint32_t iqtimer_pkt_dw18; /* ordinal211 */
4685 uint32_t iqtimer_pkt_dw19; /* ordinal212 */
4686 uint32_t iqtimer_pkt_dw20; /* ordinal213 */
4687 uint32_t iqtimer_pkt_dw21; /* ordinal214 */
4688 uint32_t iqtimer_pkt_dw22; /* ordinal215 */
4689 uint32_t iqtimer_pkt_dw23; /* ordinal216 */
4690 uint32_t iqtimer_pkt_dw24; /* ordinal217 */
4691 uint32_t iqtimer_pkt_dw25; /* ordinal218 */
4692 uint32_t iqtimer_pkt_dw26; /* ordinal219 */
4693 uint32_t iqtimer_pkt_dw27; /* ordinal220 */
4694 uint32_t iqtimer_pkt_dw28; /* ordinal221 */
4695 uint32_t iqtimer_pkt_dw29; /* ordinal222 */
4696 uint32_t iqtimer_pkt_dw30; /* ordinal223 */
4697 uint32_t iqtimer_pkt_dw31; /* ordinal224 */
4698 uint32_t reserved56; /* ordinal225 */
4699 uint32_t reserved57; /* ordinal226 */
4700 uint32_t reserved58; /* ordinal227 */
4701 uint32_t set_resources_header; /* ordinal228 */
4702 uint32_t set_resources_dw1; /* ordinal229 */
4703 uint32_t set_resources_dw2; /* ordinal230 */
4704 uint32_t set_resources_dw3; /* ordinal231 */
4705 uint32_t set_resources_dw4; /* ordinal232 */
4706 uint32_t set_resources_dw5; /* ordinal233 */
4707 uint32_t set_resources_dw6; /* ordinal234 */
4708 uint32_t set_resources_dw7; /* ordinal235 */
4709 uint32_t reserved59; /* ordinal236 */
4710 uint32_t reserved60; /* ordinal237 */
4711 uint32_t reserved61; /* ordinal238 */
4712 uint32_t reserved62; /* ordinal239 */
4713 uint32_t reserved63; /* ordinal240 */
4714 uint32_t reserved64; /* ordinal241 */
4715 uint32_t reserved65; /* ordinal242 */
4716 uint32_t reserved66; /* ordinal243 */
4717 uint32_t reserved67; /* ordinal244 */
4718 uint32_t reserved68; /* ordinal245 */
4719 uint32_t reserved69; /* ordinal246 */
4720 uint32_t reserved70; /* ordinal247 */
4721 uint32_t reserved71; /* ordinal248 */
4722 uint32_t reserved72; /* ordinal249 */
4723 uint32_t reserved73; /* ordinal250 */
4724 uint32_t reserved74; /* ordinal251 */
4725 uint32_t reserved75; /* ordinal252 */
4726 uint32_t reserved76; /* ordinal253 */
4727 uint32_t reserved77; /* ordinal254 */
4728 uint32_t reserved78; /* ordinal255 */
4729
4730 uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
4731};
4732
4733static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev) 4474static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
4734{ 4475{
4735 int i, r; 4476 int i, r;
@@ -4763,34 +4504,7 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
4763 u32 *buf; 4504 u32 *buf;
4764 struct vi_mqd *mqd; 4505 struct vi_mqd *mqd;
4765 4506
4766 /* init the pipes */ 4507 /* init the queues. */
4767 mutex_lock(&adev->srbm_mutex);
4768 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
4769 int me = (i < 4) ? 1 : 2;
4770 int pipe = (i < 4) ? i : (i - 4);
4771
4772 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
4773 eop_gpu_addr >>= 8;
4774
4775 vi_srbm_select(adev, me, pipe, 0, 0);
4776
4777 /* write the EOP addr */
4778 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
4779 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
4780
4781 /* set the VMID assigned */
4782 WREG32(mmCP_HQD_VMID, 0);
4783
4784 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
4785 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
4786 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
4787 (order_base_2(MEC_HPD_SIZE / 4) - 1));
4788 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
4789 }
4790 vi_srbm_select(adev, 0, 0, 0, 0);
4791 mutex_unlock(&adev->srbm_mutex);
4792
4793 /* init the queues. Just two for now. */
4794 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4508 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4795 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 4509 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4796 4510
@@ -4842,6 +4556,22 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
4842 ring->pipe, 4556 ring->pipe,
4843 ring->queue, 0); 4557 ring->queue, 0);
4844 4558
4559 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
4560 eop_gpu_addr >>= 8;
4561
4562 /* write the EOP addr */
4563 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
4564 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
4565
4566 /* set the VMID assigned */
4567 WREG32(mmCP_HQD_VMID, 0);
4568
4569 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
4570 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
4571 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
4572 (order_base_2(MEC_HPD_SIZE / 4) - 1));
4573 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
4574
4845 /* disable wptr polling */ 4575 /* disable wptr polling */
4846 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL); 4576 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
4847 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0); 4577 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
@@ -4925,9 +4655,9 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
4925 4655
4926 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 4656 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
4927 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 4657 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4928 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc; 4658 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
4929 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 4659 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4930 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr); 4660 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr_lo);
4931 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 4661 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
4932 mqd->cp_hqd_pq_wptr_poll_addr_hi); 4662 mqd->cp_hqd_pq_wptr_poll_addr_hi);
4933 4663
@@ -5098,6 +4828,10 @@ static int gfx_v8_0_hw_fini(void *handle)
5098 4828
5099 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 4829 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
5100 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 4830 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4831 if (amdgpu_sriov_vf(adev)) {
4832 pr_debug("For SRIOV client, shouldn't do anything.\n");
4833 return 0;
4834 }
5101 gfx_v8_0_cp_enable(adev, false); 4835 gfx_v8_0_cp_enable(adev, false);
5102 gfx_v8_0_rlc_stop(adev); 4836 gfx_v8_0_rlc_stop(adev);
5103 gfx_v8_0_cp_compute_fini(adev); 4837 gfx_v8_0_cp_compute_fini(adev);
@@ -5450,6 +5184,21 @@ static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_
5450 return RREG32(mmSQ_IND_DATA); 5184 return RREG32(mmSQ_IND_DATA);
5451} 5185}
5452 5186
5187static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
5188 uint32_t wave, uint32_t thread,
5189 uint32_t regno, uint32_t num, uint32_t *out)
5190{
5191 WREG32(mmSQ_IND_INDEX,
5192 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5193 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
5194 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
5195 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
5196 (SQ_IND_INDEX__FORCE_READ_MASK) |
5197 (SQ_IND_INDEX__AUTO_INCR_MASK));
5198 while (num--)
5199 *(out++) = RREG32(mmSQ_IND_DATA);
5200}
5201
5453static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 5202static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
5454{ 5203{
5455 /* type 0 wave data */ 5204 /* type 0 wave data */
@@ -5474,11 +5223,21 @@ static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, u
5474 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 5223 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
5475} 5224}
5476 5225
5226static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
5227 uint32_t wave, uint32_t start,
5228 uint32_t size, uint32_t *dst)
5229{
5230 wave_read_regs(
5231 adev, simd, wave, 0,
5232 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
5233}
5234
5477 5235
5478static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = { 5236static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = {
5479 .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter, 5237 .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
5480 .select_se_sh = &gfx_v8_0_select_se_sh, 5238 .select_se_sh = &gfx_v8_0_select_se_sh,
5481 .read_wave_data = &gfx_v8_0_read_wave_data, 5239 .read_wave_data = &gfx_v8_0_read_wave_data,
5240 .read_wave_sgprs = &gfx_v8_0_read_wave_sgprs,
5482}; 5241};
5483 5242
5484static int gfx_v8_0_early_init(void *handle) 5243static int gfx_v8_0_early_init(void *handle)
@@ -5930,29 +5689,24 @@ static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
5930 adev->gfx.rlc.funcs->enter_safe_mode(adev); 5689 adev->gfx.rlc.funcs->enter_safe_mode(adev);
5931 5690
5932 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 5691 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
5933 /* 1 enable cntx_empty_int_enable/cntx_busy_int_enable/
5934 * Cmp_busy/GFX_Idle interrupts
5935 */
5936 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
5937
5938 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 5692 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5939 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK; 5693 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK;
5940 if (temp1 != data1) 5694 if (temp1 != data1)
5941 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1); 5695 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5942 5696
5943 /* 2 wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ 5697 /* : wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5944 gfx_v8_0_wait_for_rlc_serdes(adev); 5698 gfx_v8_0_wait_for_rlc_serdes(adev);
5945 5699
5946 /* 3 - clear cgcg override */ 5700 /* 2 - clear cgcg override */
5947 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD); 5701 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
5948 5702
5949 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */ 5703 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5950 gfx_v8_0_wait_for_rlc_serdes(adev); 5704 gfx_v8_0_wait_for_rlc_serdes(adev);
5951 5705
5952 /* 4 - write cmd to set CGLS */ 5706 /* 3 - write cmd to set CGLS */
5953 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD); 5707 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD);
5954 5708
5955 /* 5 - enable cgcg */ 5709 /* 4 - enable cgcg */
5956 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 5710 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
5957 5711
5958 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 5712 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
@@ -5970,6 +5724,11 @@ static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
5970 5724
5971 if (temp != data) 5725 if (temp != data)
5972 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 5726 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5727
5728 /* 5 enable cntx_empty_int_enable/cntx_busy_int_enable/
5729 * Cmp_busy/GFX_Idle interrupts
5730 */
5731 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
5973 } else { 5732 } else {
5974 /* disable cntx_empty_int_enable & GFX Idle interrupt */ 5733 /* disable cntx_empty_int_enable & GFX Idle interrupt */
5975 gfx_v8_0_enable_gui_idle_interrupt(adev, false); 5734 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 64d3c1e6014c..45a573e63d4a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -335,7 +335,7 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
335 * size equal to the 1024 or vram, whichever is larger. 335 * size equal to the 1024 or vram, whichever is larger.
336 */ 336 */
337 if (amdgpu_gart_size == -1) 337 if (amdgpu_gart_size == -1)
338 adev->mc.gtt_size = amdgpu_ttm_get_gtt_mem_size(adev); 338 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
339 else 339 else
340 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; 340 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
341 341
@@ -795,11 +795,6 @@ static int gmc_v6_0_sw_init(void *handle)
795 return r; 795 return r;
796 } 796 }
797 797
798 r = amdgpu_ttm_global_init(adev);
799 if (r) {
800 return r;
801 }
802
803 r = gmc_v6_0_mc_init(adev); 798 r = gmc_v6_0_mc_init(adev);
804 if (r) 799 if (r)
805 return r; 800 return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index fbe1d9ac500a..273b16fb9459 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -385,7 +385,7 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
385 * size equal to the 1024 or vram, whichever is larger. 385 * size equal to the 1024 or vram, whichever is larger.
386 */ 386 */
387 if (amdgpu_gart_size == -1) 387 if (amdgpu_gart_size == -1)
388 adev->mc.gtt_size = amdgpu_ttm_get_gtt_mem_size(adev); 388 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
389 else 389 else
390 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; 390 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
391 391
@@ -945,11 +945,6 @@ static int gmc_v7_0_sw_init(void *handle)
945 return r; 945 return r;
946 } 946 }
947 947
948 r = amdgpu_ttm_global_init(adev);
949 if (r) {
950 return r;
951 }
952
953 r = gmc_v7_0_mc_init(adev); 948 r = gmc_v7_0_mc_init(adev);
954 if (r) 949 if (r)
955 return r; 950 return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 12ea3404dd65..0daac3a5be79 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -472,7 +472,7 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
472 * size equal to the 1024 or vram, whichever is larger. 472 * size equal to the 1024 or vram, whichever is larger.
473 */ 473 */
474 if (amdgpu_gart_size == -1) 474 if (amdgpu_gart_size == -1)
475 adev->mc.gtt_size = amdgpu_ttm_get_gtt_mem_size(adev); 475 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
476 else 476 else
477 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; 477 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
478 478
@@ -952,11 +952,6 @@ static int gmc_v8_0_sw_init(void *handle)
952 return r; 952 return r;
953 } 953 }
954 954
955 r = amdgpu_ttm_global_init(adev);
956 if (r) {
957 return r;
958 }
959
960 r = gmc_v8_0_mc_init(adev); 955 r = gmc_v8_0_mc_init(adev);
961 if (r) 956 if (r)
962 return r; 957 return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
index f0f2f6c9718e..6c65a1a2de79 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -3506,6 +3506,7 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3506 (adev->pdev->revision == 0x80) || 3506 (adev->pdev->revision == 0x80) ||
3507 (adev->pdev->revision == 0x81) || 3507 (adev->pdev->revision == 0x81) ||
3508 (adev->pdev->revision == 0x83) || 3508 (adev->pdev->revision == 0x83) ||
3509 (adev->pdev->revision == 0x87) ||
3509 (adev->pdev->device == 0x6604) || 3510 (adev->pdev->device == 0x6604) ||
3510 (adev->pdev->device == 0x6605)) { 3511 (adev->pdev->device == 0x6605)) {
3511 max_sclk = 75000; 3512 max_sclk = 75000;
@@ -7715,6 +7716,7 @@ static int si_dpm_init_microcode(struct amdgpu_device *adev)
7715 (adev->pdev->revision == 0x80) || 7716 (adev->pdev->revision == 0x80) ||
7716 (adev->pdev->revision == 0x81) || 7717 (adev->pdev->revision == 0x81) ||
7717 (adev->pdev->revision == 0x83) || 7718 (adev->pdev->revision == 0x83) ||
7719 (adev->pdev->revision == 0x87) ||
7718 (adev->pdev->device == 0x6604) || 7720 (adev->pdev->device == 0x6604) ||
7719 (adev->pdev->device == 0x6605)) 7721 (adev->pdev->device == 0x6605))
7720 chip_name = "oland_k"; 7722 chip_name = "oland_k";
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 95cabeafc18e..a79e283590fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -640,7 +640,7 @@ static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable
640 UVD_SUVD_CGC_GATE__SDB_MASK; 640 UVD_SUVD_CGC_GATE__SDB_MASK;
641 641
642 if (enable) { 642 if (enable) {
643 data3 |= (UVD_CGC_GATE__SYS_MASK | 643 data3 |= (UVD_CGC_GATE__SYS_MASK |
644 UVD_CGC_GATE__UDEC_MASK | 644 UVD_CGC_GATE__UDEC_MASK |
645 UVD_CGC_GATE__MPEG2_MASK | 645 UVD_CGC_GATE__MPEG2_MASK |
646 UVD_CGC_GATE__RBC_MASK | 646 UVD_CGC_GATE__RBC_MASK |
@@ -656,9 +656,11 @@ static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable
656 UVD_CGC_GATE__UDEC_DB_MASK | 656 UVD_CGC_GATE__UDEC_DB_MASK |
657 UVD_CGC_GATE__UDEC_MP_MASK | 657 UVD_CGC_GATE__UDEC_MP_MASK |
658 UVD_CGC_GATE__WCB_MASK | 658 UVD_CGC_GATE__WCB_MASK |
659 UVD_CGC_GATE__VCPU_MASK |
660 UVD_CGC_GATE__JPEG_MASK | 659 UVD_CGC_GATE__JPEG_MASK |
661 UVD_CGC_GATE__SCPU_MASK); 660 UVD_CGC_GATE__SCPU_MASK);
661 /* only in pg enabled, we can gate clock to vcpu*/
662 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
663 data3 |= UVD_CGC_GATE__VCPU_MASK;
662 data3 &= ~UVD_CGC_GATE__REGS_MASK; 664 data3 &= ~UVD_CGC_GATE__REGS_MASK;
663 data1 |= suvd_flags; 665 data1 |= suvd_flags;
664 } else { 666 } else {
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 00fad6951d82..ba0bbf7138dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -42,6 +42,10 @@ static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
42static int uvd_v6_0_start(struct amdgpu_device *adev); 42static int uvd_v6_0_start(struct amdgpu_device *adev);
43static void uvd_v6_0_stop(struct amdgpu_device *adev); 43static void uvd_v6_0_stop(struct amdgpu_device *adev);
44static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev); 44static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
45static int uvd_v6_0_set_clockgating_state(void *handle,
46 enum amd_clockgating_state state);
47static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
48 bool enable);
45 49
46/** 50/**
47 * uvd_v6_0_ring_get_rptr - get read pointer 51 * uvd_v6_0_ring_get_rptr - get read pointer
@@ -151,8 +155,6 @@ static int uvd_v6_0_hw_init(void *handle)
151 uint32_t tmp; 155 uint32_t tmp;
152 int r; 156 int r;
153 157
154 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
155
156 r = uvd_v6_0_start(adev); 158 r = uvd_v6_0_start(adev);
157 if (r) 159 if (r)
158 goto done; 160 goto done;
@@ -395,11 +397,11 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
395 lmi_swap_cntl = 0; 397 lmi_swap_cntl = 0;
396 mp_swap_cntl = 0; 398 mp_swap_cntl = 0;
397 399
400 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
401 uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
402 uvd_v6_0_enable_mgcg(adev, true);
398 uvd_v6_0_mc_resume(adev); 403 uvd_v6_0_mc_resume(adev);
399 404
400 /* disable clock gating */
401 WREG32_FIELD(UVD_CGC_CTRL, DYN_CLOCK_MODE, 0);
402
403 /* disable interupt */ 405 /* disable interupt */
404 WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0); 406 WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0);
405 407
@@ -838,22 +840,72 @@ static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
838 return 0; 840 return 0;
839} 841}
840 842
843static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
844{
845 uint32_t data1, data3;
846
847 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
848 data3 = RREG32(mmUVD_CGC_GATE);
849
850 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
851 UVD_SUVD_CGC_GATE__SIT_MASK |
852 UVD_SUVD_CGC_GATE__SMP_MASK |
853 UVD_SUVD_CGC_GATE__SCM_MASK |
854 UVD_SUVD_CGC_GATE__SDB_MASK |
855 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
856 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
857 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
858 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
859 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
860 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
861 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
862 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
863
864 if (enable) {
865 data3 |= (UVD_CGC_GATE__SYS_MASK |
866 UVD_CGC_GATE__UDEC_MASK |
867 UVD_CGC_GATE__MPEG2_MASK |
868 UVD_CGC_GATE__RBC_MASK |
869 UVD_CGC_GATE__LMI_MC_MASK |
870 UVD_CGC_GATE__LMI_UMC_MASK |
871 UVD_CGC_GATE__IDCT_MASK |
872 UVD_CGC_GATE__MPRD_MASK |
873 UVD_CGC_GATE__MPC_MASK |
874 UVD_CGC_GATE__LBSI_MASK |
875 UVD_CGC_GATE__LRBBM_MASK |
876 UVD_CGC_GATE__UDEC_RE_MASK |
877 UVD_CGC_GATE__UDEC_CM_MASK |
878 UVD_CGC_GATE__UDEC_IT_MASK |
879 UVD_CGC_GATE__UDEC_DB_MASK |
880 UVD_CGC_GATE__UDEC_MP_MASK |
881 UVD_CGC_GATE__WCB_MASK |
882 UVD_CGC_GATE__JPEG_MASK |
883 UVD_CGC_GATE__SCPU_MASK |
884 UVD_CGC_GATE__JPEG2_MASK);
885 /* only in pg enabled, we can gate clock to vcpu*/
886 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
887 data3 |= UVD_CGC_GATE__VCPU_MASK;
888
889 data3 &= ~UVD_CGC_GATE__REGS_MASK;
890 } else {
891 data3 = 0;
892 }
893
894 WREG32(mmUVD_SUVD_CGC_GATE, data1);
895 WREG32(mmUVD_CGC_GATE, data3);
896}
897
841static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev) 898static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
842{ 899{
843 uint32_t data, data1, data2, suvd_flags; 900 uint32_t data, data2;
844 901
845 data = RREG32(mmUVD_CGC_CTRL); 902 data = RREG32(mmUVD_CGC_CTRL);
846 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
847 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 903 data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
848 904
905
849 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 906 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
850 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 907 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
851 908
852 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
853 UVD_SUVD_CGC_GATE__SIT_MASK |
854 UVD_SUVD_CGC_GATE__SMP_MASK |
855 UVD_SUVD_CGC_GATE__SCM_MASK |
856 UVD_SUVD_CGC_GATE__SDB_MASK;
857 909
858 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 910 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
859 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 911 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
@@ -886,11 +938,8 @@ static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
886 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 938 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
887 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 939 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
888 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 940 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
889 data1 |= suvd_flags;
890 941
891 WREG32(mmUVD_CGC_CTRL, data); 942 WREG32(mmUVD_CGC_CTRL, data);
892 WREG32(mmUVD_CGC_GATE, 0);
893 WREG32(mmUVD_SUVD_CGC_GATE, data1);
894 WREG32(mmUVD_SUVD_CGC_CTRL, data2); 943 WREG32(mmUVD_SUVD_CGC_CTRL, data2);
895} 944}
896 945
@@ -937,6 +986,32 @@ static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
937} 986}
938#endif 987#endif
939 988
989static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
990 bool enable)
991{
992 u32 orig, data;
993
994 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
995 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
996 data |= 0xfff;
997 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
998
999 orig = data = RREG32(mmUVD_CGC_CTRL);
1000 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1001 if (orig != data)
1002 WREG32(mmUVD_CGC_CTRL, data);
1003 } else {
1004 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1005 data &= ~0xfff;
1006 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1007
1008 orig = data = RREG32(mmUVD_CGC_CTRL);
1009 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1010 if (orig != data)
1011 WREG32(mmUVD_CGC_CTRL, data);
1012 }
1013}
1014
940static int uvd_v6_0_set_clockgating_state(void *handle, 1015static int uvd_v6_0_set_clockgating_state(void *handle,
941 enum amd_clockgating_state state) 1016 enum amd_clockgating_state state)
942{ 1017{
@@ -947,17 +1022,17 @@ static int uvd_v6_0_set_clockgating_state(void *handle,
947 return 0; 1022 return 0;
948 1023
949 if (enable) { 1024 if (enable) {
950 /* disable HW gating and enable Sw gating */
951 uvd_v6_0_set_sw_clock_gating(adev);
952 } else {
953 /* wait for STATUS to clear */ 1025 /* wait for STATUS to clear */
954 if (uvd_v6_0_wait_for_idle(handle)) 1026 if (uvd_v6_0_wait_for_idle(handle))
955 return -EBUSY; 1027 return -EBUSY;
956 1028 uvd_v6_0_enable_clock_gating(adev, true);
957 /* enable HW gates because UVD is idle */ 1029 /* enable HW gates because UVD is idle */
958/* uvd_v6_0_set_hw_clock_gating(adev); */ 1030/* uvd_v6_0_set_hw_clock_gating(adev); */
1031 } else {
1032 /* disable HW gating and enable Sw gating */
1033 uvd_v6_0_enable_clock_gating(adev, false);
959 } 1034 }
960 1035 uvd_v6_0_set_sw_clock_gating(adev);
961 return 0; 1036 return 0;
962} 1037}
963 1038
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 39f03f137a56..6b3293a1c7b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -134,7 +134,7 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
134 accessible but the firmware will throttle the clocks on the 134 accessible but the firmware will throttle the clocks on the
135 fly as necessary. 135 fly as necessary.
136 */ 136 */
137 if (gated) { 137 if (!gated) {
138 data = RREG32(mmVCE_CLOCK_GATING_B); 138 data = RREG32(mmVCE_CLOCK_GATING_B);
139 data |= 0x1ff; 139 data |= 0x1ff;
140 data &= ~0xef0000; 140 data &= ~0xef0000;
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 243dcf7bae47..9f771f4ffcb7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -937,12 +937,14 @@ static int vi_common_early_init(void *handle)
937 adev->external_rev_id = adev->rev_id + 0x14; 937 adev->external_rev_id = adev->rev_id + 0x14;
938 break; 938 break;
939 case CHIP_POLARIS11: 939 case CHIP_POLARIS11:
940 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG; 940 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
941 AMD_CG_SUPPORT_VCE_MGCG;
941 adev->pg_flags = 0; 942 adev->pg_flags = 0;
942 adev->external_rev_id = adev->rev_id + 0x5A; 943 adev->external_rev_id = adev->rev_id + 0x5A;
943 break; 944 break;
944 case CHIP_POLARIS10: 945 case CHIP_POLARIS10:
945 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG; 946 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
947 AMD_CG_SUPPORT_VCE_MGCG;
946 adev->pg_flags = 0; 948 adev->pg_flags = 0;
947 adev->external_rev_id = adev->rev_id + 0x50; 949 adev->external_rev_id = adev->rev_id + 0x50;
948 break; 950 break;
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 51a36077b993..c81cf1412728 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1004,12 +1004,12 @@ int amd_powerplay_reset(void *handle)
1004 if (ret) 1004 if (ret)
1005 return ret; 1005 return ret;
1006 1006
1007 hw_init_power_state_table(instance->hwmgr);
1008
1009 if ((amdgpu_dpm == 0) 1007 if ((amdgpu_dpm == 0)
1010 || cgs_is_virtualization_enabled(instance->smu_mgr->device)) 1008 || cgs_is_virtualization_enabled(instance->smu_mgr->device))
1011 return 0; 1009 return 0;
1012 1010
1011 hw_init_power_state_table(instance->hwmgr);
1012
1013 if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL) 1013 if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL)
1014 return -EINVAL; 1014 return -EINVAL;
1015 1015
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
index b6f45fd01fa6..ec36c0e28388 100644
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
@@ -154,7 +154,7 @@ int pem_task_powerdown_vce_tasks(struct pp_eventmgr *eventmgr, struct pem_event_
154 154
155int pem_task_disable_clock_power_gatings_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data) 155int pem_task_disable_clock_power_gatings_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
156{ 156{
157 /* TODO */ 157 phm_disable_clock_power_gatings(eventmgr->hwmgr);
158 return 0; 158 return 0;
159} 159}
160 160
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
index a6abe81bc843..71822ae73a12 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
@@ -35,7 +35,7 @@ static int phm_run_table(struct pp_hwmgr *hwmgr,
35 phm_table_function *function; 35 phm_table_function *function;
36 36
37 if (rt_table->function_list == NULL) { 37 if (rt_table->function_list == NULL) {
38 printk(KERN_INFO "[ powerplay ] this function not implement!\n"); 38 pr_debug("[ powerplay ] this function not implement!\n");
39 return 0; 39 return 0;
40 } 40 }
41 41
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index 0723758ed065..c355a0f51663 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -209,6 +209,19 @@ int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
209 return 0; 209 return 0;
210} 210}
211 211
212int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr)
213{
214 PHM_FUNC_CHECK(hwmgr);
215
216 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
217 PHM_PlatformCaps_TablelessHardwareInterface)) {
218 if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating)
219 return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr);
220 }
221 return 0;
222}
223
224
212int phm_display_configuration_changed(struct pp_hwmgr *hwmgr) 225int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
213{ 226{
214 PHM_FUNC_CHECK(hwmgr); 227 PHM_FUNC_CHECK(hwmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
index d4495839c64c..26129972f686 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
@@ -334,6 +334,7 @@ struct phm_clocks {
334 uint32_t clock[MAX_NUM_CLOCKS]; 334 uint32_t clock[MAX_NUM_CLOCKS];
335}; 335};
336 336
337extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);
337extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr); 338extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
338extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate); 339extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate);
339extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate); 340extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
index 34523fe6ed6f..6aeb1d20cc3b 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
@@ -1958,6 +1958,12 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
1958 int res; 1958 int res;
1959 uint64_t tmp64; 1959 uint64_t tmp64;
1960 1960
1961 if (hwmgr->thermal_controller.fanInfo.bNoFan) {
1962 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1963 PHM_PlatformCaps_MicrocodeFanControl);
1964 return 0;
1965 }
1966
1961 if (smu_data->smu7_data.fan_table_start == 0) { 1967 if (smu_data->smu7_data.fan_table_start == 0) {
1962 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1968 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1963 PHM_PlatformCaps_MicrocodeFanControl); 1969 PHM_PlatformCaps_MicrocodeFanControl);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
index b579f0c175e6..a24971a33bfd 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
@@ -2006,6 +2006,12 @@ int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2006 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl)) 2006 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl))
2007 return 0; 2007 return 0;
2008 2008
2009 if (hwmgr->thermal_controller.fanInfo.bNoFan) {
2010 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2011 PHM_PlatformCaps_MicrocodeFanControl);
2012 return 0;
2013 }
2014
2009 if (0 == smu7_data->fan_table_start) { 2015 if (0 == smu7_data->fan_table_start) {
2010 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl); 2016 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
2011 return 0; 2017 return 0;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
index 8db8e209d915..5190e821200c 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
@@ -1885,6 +1885,12 @@ int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
1885 int res; 1885 int res;
1886 uint64_t tmp64; 1886 uint64_t tmp64;
1887 1887
1888 if (hwmgr->thermal_controller.fanInfo.bNoFan) {
1889 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1890 PHM_PlatformCaps_MicrocodeFanControl);
1891 return 0;
1892 }
1893
1888 if (smu_data->smu7_data.fan_table_start == 0) { 1894 if (smu_data->smu7_data.fan_table_start == 0) {
1889 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1895 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1890 PHM_PlatformCaps_MicrocodeFanControl); 1896 PHM_PlatformCaps_MicrocodeFanControl);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index 6df0d6edfdd1..f49b5487b951 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -366,12 +366,16 @@ static int smu7_populate_single_firmware_entry(struct pp_smumgr *smumgr,
366 &info); 366 &info);
367 367
368 if (!result) { 368 if (!result) {
369 entry->version = info.version; 369 entry->version = info.fw_version;
370 entry->id = (uint16_t)fw_type; 370 entry->id = (uint16_t)fw_type;
371 entry->image_addr_high = smu_upper_32_bits(info.mc_addr); 371 entry->image_addr_high = smu_upper_32_bits(info.mc_addr);
372 entry->image_addr_low = smu_lower_32_bits(info.mc_addr); 372 entry->image_addr_low = smu_lower_32_bits(info.mc_addr);
373 entry->meta_data_addr_high = 0; 373 entry->meta_data_addr_high = 0;
374 entry->meta_data_addr_low = 0; 374 entry->meta_data_addr_low = 0;
375
376 /* digest need be excluded out */
377 if (cgs_is_virtualization_enabled(smumgr->device))
378 info.image_size -= 20;
375 entry->data_size_byte = info.image_size; 379 entry->data_size_byte = info.image_size;
376 entry->num_register_entries = 0; 380 entry->num_register_entries = 0;
377 } 381 }
@@ -403,8 +407,14 @@ int smu7_request_smu_load_fw(struct pp_smumgr *smumgr)
403 0x0); 407 0x0);
404 408
405 if (smumgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */ 409 if (smumgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */
406 smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high); 410 if (!cgs_is_virtualization_enabled(smumgr->device)) {
407 smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low); 411 smu7_send_msg_to_smc_with_parameter(smumgr,
412 PPSMC_MSG_SMU_DRAM_ADDR_HI,
413 smu_data->smu_buffer.mc_addr_high);
414 smu7_send_msg_to_smc_with_parameter(smumgr,
415 PPSMC_MSG_SMU_DRAM_ADDR_LO,
416 smu_data->smu_buffer.mc_addr_low);
417 }
408 fw_to_load = UCODE_ID_RLC_G_MASK 418 fw_to_load = UCODE_ID_RLC_G_MASK
409 + UCODE_ID_SDMA0_MASK 419 + UCODE_ID_SDMA0_MASK
410 + UCODE_ID_SDMA1_MASK 420 + UCODE_ID_SDMA1_MASK
@@ -539,7 +549,6 @@ int smu7_init(struct pp_smumgr *smumgr)
539 smu_data = (struct smu7_smumgr *)(smumgr->backend); 549 smu_data = (struct smu7_smumgr *)(smumgr->backend);
540 smu_data->header_buffer.data_size = 550 smu_data->header_buffer.data_size =
541 ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096; 551 ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
542 smu_data->smu_buffer.data_size = 200*4096;
543 552
544/* Allocate FW image data structure and header buffer and 553/* Allocate FW image data structure and header buffer and
545 * send the header buffer address to SMU */ 554 * send the header buffer address to SMU */
@@ -562,6 +571,10 @@ int smu7_init(struct pp_smumgr *smumgr)
562 (cgs_handle_t)smu_data->header_buffer.handle); 571 (cgs_handle_t)smu_data->header_buffer.handle);
563 return -EINVAL); 572 return -EINVAL);
564 573
574 if (cgs_is_virtualization_enabled(smumgr->device))
575 return 0;
576
577 smu_data->smu_buffer.data_size = 200*4096;
565 smu_allocate_memory(smumgr->device, 578 smu_allocate_memory(smumgr->device,
566 smu_data->smu_buffer.data_size, 579 smu_data->smu_buffer.data_size,
567 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, 580 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
index d08f6f19b454..2e1493ce1bb5 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
@@ -2496,6 +2496,12 @@ int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2496 PHM_PlatformCaps_MicrocodeFanControl)) 2496 PHM_PlatformCaps_MicrocodeFanControl))
2497 return 0; 2497 return 0;
2498 2498
2499 if (hwmgr->thermal_controller.fanInfo.bNoFan) {
2500 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2501 PHM_PlatformCaps_MicrocodeFanControl);
2502 return 0;
2503 }
2504
2499 if (0 == smu_data->smu7_data.fan_table_start) { 2505 if (0 == smu_data->smu7_data.fan_table_start) {
2500 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 2506 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2501 PHM_PlatformCaps_MicrocodeFanControl); 2507 PHM_PlatformCaps_MicrocodeFanControl);
diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c
index 2a10e24b34b1..fb16070b266e 100644
--- a/drivers/gpu/drm/radeon/radeon_cursor.c
+++ b/drivers/gpu/drm/radeon/radeon_cursor.c
@@ -90,6 +90,9 @@ static void radeon_show_cursor(struct drm_crtc *crtc)
90 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 90 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
91 struct radeon_device *rdev = crtc->dev->dev_private; 91 struct radeon_device *rdev = crtc->dev->dev_private;
92 92
93 if (radeon_crtc->cursor_out_of_bounds)
94 return;
95
93 if (ASIC_IS_DCE4(rdev)) { 96 if (ASIC_IS_DCE4(rdev)) {
94 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 97 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
95 upper_32_bits(radeon_crtc->cursor_addr)); 98 upper_32_bits(radeon_crtc->cursor_addr));
@@ -143,21 +146,25 @@ static int radeon_cursor_move_locked(struct drm_crtc *crtc, int x, int y)
143 int xorigin = 0, yorigin = 0; 146 int xorigin = 0, yorigin = 0;
144 int w = radeon_crtc->cursor_width; 147 int w = radeon_crtc->cursor_width;
145 148
149 radeon_crtc->cursor_x = x;
150 radeon_crtc->cursor_y = y;
151
146 if (ASIC_IS_AVIVO(rdev)) { 152 if (ASIC_IS_AVIVO(rdev)) {
147 /* avivo cursor are offset into the total surface */ 153 /* avivo cursor are offset into the total surface */
148 x += crtc->x; 154 x += crtc->x;
149 y += crtc->y; 155 y += crtc->y;
150 } 156 }
151 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
152 157
153 if (x < 0) { 158 if (x < 0)
154 xorigin = min(-x, radeon_crtc->max_cursor_width - 1); 159 xorigin = min(-x, radeon_crtc->max_cursor_width - 1);
155 x = 0; 160 if (y < 0)
156 }
157 if (y < 0) {
158 yorigin = min(-y, radeon_crtc->max_cursor_height - 1); 161 yorigin = min(-y, radeon_crtc->max_cursor_height - 1);
159 y = 0; 162
163 if (!ASIC_IS_AVIVO(rdev)) {
164 x += crtc->x;
165 y += crtc->y;
160 } 166 }
167 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
161 168
162 /* fixed on DCE6 and newer */ 169 /* fixed on DCE6 and newer */
163 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE6(rdev)) { 170 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE6(rdev)) {
@@ -180,27 +187,31 @@ static int radeon_cursor_move_locked(struct drm_crtc *crtc, int x, int y)
180 if (i > 1) { 187 if (i > 1) {
181 int cursor_end, frame_end; 188 int cursor_end, frame_end;
182 189
183 cursor_end = x - xorigin + w; 190 cursor_end = x + w;
184 frame_end = crtc->x + crtc->mode.crtc_hdisplay; 191 frame_end = crtc->x + crtc->mode.crtc_hdisplay;
185 if (cursor_end >= frame_end) { 192 if (cursor_end >= frame_end) {
186 w = w - (cursor_end - frame_end); 193 w = w - (cursor_end - frame_end);
187 if (!(frame_end & 0x7f)) 194 if (!(frame_end & 0x7f))
188 w--; 195 w--;
189 } else { 196 } else if (cursor_end <= 0) {
190 if (!(cursor_end & 0x7f)) 197 goto out_of_bounds;
191 w--; 198 } else if (!(cursor_end & 0x7f)) {
199 w--;
192 } 200 }
193 if (w <= 0) { 201 if (w <= 0) {
194 w = 1; 202 goto out_of_bounds;
195 cursor_end = x - xorigin + w;
196 if (!(cursor_end & 0x7f)) {
197 x--;
198 WARN_ON_ONCE(x < 0);
199 }
200 } 203 }
201 } 204 }
202 } 205 }
203 206
207 if (x <= (crtc->x - w) || y <= (crtc->y - radeon_crtc->cursor_height) ||
208 x >= (crtc->x + crtc->mode.crtc_hdisplay) ||
209 y >= (crtc->y + crtc->mode.crtc_vdisplay))
210 goto out_of_bounds;
211
212 x += xorigin;
213 y += yorigin;
214
204 if (ASIC_IS_DCE4(rdev)) { 215 if (ASIC_IS_DCE4(rdev)) {
205 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y); 216 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
206 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); 217 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
@@ -212,6 +223,9 @@ static int radeon_cursor_move_locked(struct drm_crtc *crtc, int x, int y)
212 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, 223 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
213 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1)); 224 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
214 } else { 225 } else {
226 x -= crtc->x;
227 y -= crtc->y;
228
215 if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) 229 if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
216 y *= 2; 230 y *= 2;
217 231
@@ -229,10 +243,20 @@ static int radeon_cursor_move_locked(struct drm_crtc *crtc, int x, int y)
229 yorigin * 256); 243 yorigin * 256);
230 } 244 }
231 245
232 radeon_crtc->cursor_x = x; 246 if (radeon_crtc->cursor_out_of_bounds) {
233 radeon_crtc->cursor_y = y; 247 radeon_crtc->cursor_out_of_bounds = false;
248 if (radeon_crtc->cursor_bo)
249 radeon_show_cursor(crtc);
250 }
234 251
235 return 0; 252 return 0;
253
254 out_of_bounds:
255 if (!radeon_crtc->cursor_out_of_bounds) {
256 radeon_hide_cursor(crtc);
257 radeon_crtc->cursor_out_of_bounds = true;
258 }
259 return 0;
236} 260}
237 261
238int radeon_crtc_cursor_move(struct drm_crtc *crtc, 262int radeon_crtc_cursor_move(struct drm_crtc *crtc,
@@ -297,22 +321,23 @@ int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
297 return ret; 321 return ret;
298 } 322 }
299 323
300 radeon_crtc->cursor_width = width;
301 radeon_crtc->cursor_height = height;
302
303 radeon_lock_cursor(crtc, true); 324 radeon_lock_cursor(crtc, true);
304 325
305 if (hot_x != radeon_crtc->cursor_hot_x || 326 if (width != radeon_crtc->cursor_width ||
327 height != radeon_crtc->cursor_height ||
328 hot_x != radeon_crtc->cursor_hot_x ||
306 hot_y != radeon_crtc->cursor_hot_y) { 329 hot_y != radeon_crtc->cursor_hot_y) {
307 int x, y; 330 int x, y;
308 331
309 x = radeon_crtc->cursor_x + radeon_crtc->cursor_hot_x - hot_x; 332 x = radeon_crtc->cursor_x + radeon_crtc->cursor_hot_x - hot_x;
310 y = radeon_crtc->cursor_y + radeon_crtc->cursor_hot_y - hot_y; 333 y = radeon_crtc->cursor_y + radeon_crtc->cursor_hot_y - hot_y;
311 334
312 radeon_cursor_move_locked(crtc, x, y); 335 radeon_crtc->cursor_width = width;
313 336 radeon_crtc->cursor_height = height;
314 radeon_crtc->cursor_hot_x = hot_x; 337 radeon_crtc->cursor_hot_x = hot_x;
315 radeon_crtc->cursor_hot_y = hot_y; 338 radeon_crtc->cursor_hot_y = hot_y;
339
340 radeon_cursor_move_locked(crtc, x, y);
316 } 341 }
317 342
318 radeon_show_cursor(crtc); 343 radeon_show_cursor(crtc);
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index bb75201a24ba..f1da484864a9 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -330,6 +330,7 @@ struct radeon_crtc {
330 u16 lut_r[256], lut_g[256], lut_b[256]; 330 u16 lut_r[256], lut_g[256], lut_b[256];
331 bool enabled; 331 bool enabled;
332 bool can_tile; 332 bool can_tile;
333 bool cursor_out_of_bounds;
333 uint32_t crtc_offset; 334 uint32_t crtc_offset;
334 struct drm_gem_object *cursor_bo; 335 struct drm_gem_object *cursor_bo;
335 uint64_t cursor_addr; 336 uint64_t cursor_addr;
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 143280dc0851..ad4d7b8b8322 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1714,6 +1714,7 @@ static int si_init_microcode(struct radeon_device *rdev)
1714 (rdev->pdev->revision == 0x80) || 1714 (rdev->pdev->revision == 0x80) ||
1715 (rdev->pdev->revision == 0x81) || 1715 (rdev->pdev->revision == 0x81) ||
1716 (rdev->pdev->revision == 0x83) || 1716 (rdev->pdev->revision == 0x83) ||
1717 (rdev->pdev->revision == 0x87) ||
1717 (rdev->pdev->device == 0x6604) || 1718 (rdev->pdev->device == 0x6604) ||
1718 (rdev->pdev->device == 0x6605)) 1719 (rdev->pdev->device == 0x6605))
1719 new_smc = true; 1720 new_smc = true;
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index c49934527a87..8b5e697f2549 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -3026,6 +3026,7 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
3026 (rdev->pdev->revision == 0x80) || 3026 (rdev->pdev->revision == 0x80) ||
3027 (rdev->pdev->revision == 0x81) || 3027 (rdev->pdev->revision == 0x81) ||
3028 (rdev->pdev->revision == 0x83) || 3028 (rdev->pdev->revision == 0x83) ||
3029 (rdev->pdev->revision == 0x87) ||
3029 (rdev->pdev->device == 0x6604) || 3030 (rdev->pdev->device == 0x6604) ||
3030 (rdev->pdev->device == 0x6605)) { 3031 (rdev->pdev->device == 0x6605)) {
3031 max_sclk = 75000; 3032 max_sclk = 75000;
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 2191a9e4f3db..396183628f3c 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -522,6 +522,12 @@ struct drm_amdgpu_cs_chunk_data {
522#define AMDGPU_INFO_MEMORY 0x19 522#define AMDGPU_INFO_MEMORY 0x19
523/* Query vce clock table */ 523/* Query vce clock table */
524#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 524#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
525/* Query vbios related information */
526#define AMDGPU_INFO_VBIOS 0x1B
527 /* Subquery id: Query vbios size */
528 #define AMDGPU_INFO_VBIOS_SIZE 0x1
529 /* Subquery id: Query vbios image */
530 #define AMDGPU_INFO_VBIOS_IMAGE 0x2
525 531
526#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 532#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
527#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 533#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
@@ -580,6 +586,11 @@ struct drm_amdgpu_info {
580 } read_mmr_reg; 586 } read_mmr_reg;
581 587
582 struct drm_amdgpu_query_fw query_fw; 588 struct drm_amdgpu_query_fw query_fw;
589
590 struct {
591 __u32 type;
592 __u32 offset;
593 } vbios_info;
583 }; 594 };
584}; 595};
585 596
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-26 10:39:36 -0400