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-rw-r--r--drivers/infiniband/hw/hfi1/pcie.c11
-rw-r--r--drivers/pci/pci.c1
-rw-r--r--include/linux/pci.h3
3 files changed, 8 insertions, 7 deletions
diff --git a/drivers/infiniband/hw/hfi1/pcie.c b/drivers/infiniband/hw/hfi1/pcie.c
index eec83757d55f..6c967dde58e7 100644
--- a/drivers/infiniband/hw/hfi1/pcie.c
+++ b/drivers/infiniband/hw/hfi1/pcie.c
@@ -893,14 +893,11 @@ static int trigger_sbr(struct hfi1_devdata *dd)
893 } 893 }
894 894
895 /* 895 /*
896 * A secondary bus reset (SBR) issues a hot reset to our device. 896 * This is an end around to do an SBR during probe time. A new API needs
897 * The following routine does a 1s wait after the reset is dropped 897 * to be implemented to have cleaner interface but this fixes the
898 * per PCI Trhfa (recovery time). PCIe 3.0 section 6.6.1 - 898 * current brokenness
899 * Conventional Reset, paragraph 3, line 35 also says that a 1s
900 * delay after a reset is required. Per spec requirements,
901 * the link is either working or not after that point.
902 */ 899 */
903 return pci_reset_bus(dev); 900 return pci_bridge_secondary_bus_reset(dev->bus->self);
904} 901}
905 902
906/* 903/*
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 30b260332a10..1835f3a7aa8d 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4547,6 +4547,7 @@ int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
4547 4547
4548 return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS); 4548 return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
4549} 4549}
4550EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
4550 4551
4551static int pci_parent_bus_reset(struct pci_dev *dev, int probe) 4552static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
4552{ 4553{
diff --git a/include/linux/pci.h b/include/linux/pci.h
index e72ca8dd6241..6925828f9f25 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1235,6 +1235,9 @@ void pci_bus_remove_resources(struct pci_bus *bus);
1235int devm_request_pci_bus_resources(struct device *dev, 1235int devm_request_pci_bus_resources(struct device *dev,
1236 struct list_head *resources); 1236 struct list_head *resources);
1237 1237
1238/* Temporary until new and working PCI SBR API in place */
1239int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1240
1238#define pci_bus_for_each_resource(bus, res, i) \ 1241#define pci_bus_for_each_resource(bus, res, i) \
1239 for (i = 0; \ 1242 for (i = 0; \
1240 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ 1243 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \