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-rw-r--r--arch/arm64/include/asm/opcodes.h5
-rw-r--r--arch/arm64/include/asm/sysreg.h16
-rw-r--r--arch/arm64/kernel/armv8_deprecated.c5
-rw-r--r--arch/arm64/kernel/insn.c1
4 files changed, 14 insertions, 13 deletions
diff --git a/arch/arm64/include/asm/opcodes.h b/arch/arm64/include/asm/opcodes.h
deleted file mode 100644
index 123f45d92cd1..000000000000
--- a/arch/arm64/include/asm/opcodes.h
+++ /dev/null
@@ -1,5 +0,0 @@
1#ifdef CONFIG_CPU_BIG_ENDIAN
2#define CONFIG_CPU_ENDIAN_BE8 CONFIG_CPU_BIG_ENDIAN
3#endif
4
5#include <../../arm/include/asm/opcodes.h>
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 6c80b3699cb8..9e16a185badb 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -22,8 +22,6 @@
22 22
23#include <linux/stringify.h> 23#include <linux/stringify.h>
24 24
25#include <asm/opcodes.h>
26
27/* 25/*
28 * ARMv8 ARM reserves the following encoding for system registers: 26 * ARMv8 ARM reserves the following encoding for system registers:
29 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 27 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
@@ -37,6 +35,12 @@
37#define sys_reg(op0, op1, crn, crm, op2) \ 35#define sys_reg(op0, op1, crn, crm, op2) \
38 ((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5)) 36 ((((op0)&3)<<19)|((op1)<<16)|((crn)<<12)|((crm)<<8)|((op2)<<5))
39 37
38#ifdef __ASSEMBLY__
39#define __emit_inst(x) .inst (x)
40#else
41#define __emit_inst(x) ".inst " __stringify((x)) "\n\t"
42#endif
43
40#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) 44#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
41#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) 45#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
42#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) 46#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
@@ -81,10 +85,10 @@
81#define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4) 85#define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4)
82#define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3) 86#define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3)
83 87
84#define SET_PSTATE_PAN(x) __inst_arm(0xd5000000 | REG_PSTATE_PAN_IMM |\ 88#define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM | \
85 (!!x)<<8 | 0x1f) 89 (!!x)<<8 | 0x1f)
86#define SET_PSTATE_UAO(x) __inst_arm(0xd5000000 | REG_PSTATE_UAO_IMM |\ 90#define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM | \
87 (!!x)<<8 | 0x1f) 91 (!!x)<<8 | 0x1f)
88 92
89/* Common SCTLR_ELx flags. */ 93/* Common SCTLR_ELx flags. */
90#define SCTLR_ELx_EE (1 << 25) 94#define SCTLR_ELx_EE (1 << 25)
diff --git a/arch/arm64/kernel/armv8_deprecated.c b/arch/arm64/kernel/armv8_deprecated.c
index bdb35b92003e..04de188a36c9 100644
--- a/arch/arm64/kernel/armv8_deprecated.c
+++ b/arch/arm64/kernel/armv8_deprecated.c
@@ -16,7 +16,6 @@
16 16
17#include <asm/cpufeature.h> 17#include <asm/cpufeature.h>
18#include <asm/insn.h> 18#include <asm/insn.h>
19#include <asm/opcodes.h>
20#include <asm/sysreg.h> 19#include <asm/sysreg.h>
21#include <asm/system_misc.h> 20#include <asm/system_misc.h>
22#include <asm/traps.h> 21#include <asm/traps.h>
@@ -351,6 +350,10 @@ static int emulate_swpX(unsigned int address, unsigned int *data,
351 return res; 350 return res;
352} 351}
353 352
353#define ARM_OPCODE_CONDTEST_FAIL 0
354#define ARM_OPCODE_CONDTEST_PASS 1
355#define ARM_OPCODE_CONDTEST_UNCOND 2
356
354#define ARM_OPCODE_CONDITION_UNCOND 0xf 357#define ARM_OPCODE_CONDITION_UNCOND 0xf
355 358
356static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr) 359static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr)
diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
index 6f2ac4fc66ca..94b62c1fa4df 100644
--- a/arch/arm64/kernel/insn.c
+++ b/arch/arm64/kernel/insn.c
@@ -30,7 +30,6 @@
30#include <asm/cacheflush.h> 30#include <asm/cacheflush.h>
31#include <asm/debug-monitors.h> 31#include <asm/debug-monitors.h>
32#include <asm/fixmap.h> 32#include <asm/fixmap.h>
33#include <asm/opcodes.h>
34#include <asm/insn.h> 33#include <asm/insn.h>
35 34
36#define AARCH64_INSN_SF_BIT BIT(31) 35#define AARCH64_INSN_SF_BIT BIT(31)