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-rw-r--r--Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt1
-rw-r--r--Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt90
-rw-r--r--Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt5
-rw-r--r--Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt16
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt63
-rw-r--r--Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt1
-rw-r--r--MAINTAINERS7
-rw-r--r--arch/arm/boot/dts/sama5d2.dtsi14
-rw-r--r--drivers/base/dd.c2
-rw-r--r--drivers/base/pinctrl.c15
-rw-r--r--drivers/pinctrl/Kconfig13
-rw-r--r--drivers/pinctrl/Makefile3
-rw-r--r--drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c131
-rw-r--r--drivers/pinctrl/berlin/Kconfig16
-rw-r--r--drivers/pinctrl/berlin/Makefile1
-rw-r--r--drivers/pinctrl/berlin/berlin-bg2.c4
-rw-r--r--drivers/pinctrl/berlin/berlin-bg2cd.c66
-rw-r--r--drivers/pinctrl/berlin/berlin-bg2q.c4
-rw-r--r--drivers/pinctrl/berlin/berlin-bg4ct.c503
-rw-r--r--drivers/pinctrl/berlin/berlin.c28
-rw-r--r--drivers/pinctrl/berlin/berlin.h6
-rw-r--r--drivers/pinctrl/core.c32
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx.c36
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx.h2
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx7d.c30
-rw-r--r--drivers/pinctrl/freescale/pinctrl-mxs.c2
-rw-r--r--drivers/pinctrl/intel/Kconfig8
-rw-r--r--drivers/pinctrl/intel/Makefile1
-rw-r--r--drivers/pinctrl/intel/pinctrl-baytrail.c2
-rw-r--r--drivers/pinctrl/intel/pinctrl-broxton.c1065
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.c108
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-common.c4
-rw-r--r--drivers/pinctrl/pinconf-generic.c35
-rw-r--r--drivers/pinctrl/pinconf.c13
-rw-r--r--drivers/pinctrl/pinctrl-at91-pio4.c1094
-rw-r--r--drivers/pinctrl/pinctrl-at91.c5
-rw-r--r--drivers/pinctrl/pinctrl-rockchip.c17
-rw-r--r--drivers/pinctrl/pinctrl-tegra-xusb.c9
-rw-r--r--drivers/pinctrl/pinctrl-tz1090-pdc.c4
-rw-r--r--drivers/pinctrl/pinctrl-tz1090.c4
-rw-r--r--drivers/pinctrl/pinctrl-zynq.c16
-rw-r--r--drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c2
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos5440.c2
-rw-r--r--drivers/pinctrl/sh-pfc/Kconfig5
-rw-r--r--drivers/pinctrl/sh-pfc/Makefile1
-rw-r--r--drivers/pinctrl/sh-pfc/core.c16
-rw-r--r--drivers/pinctrl/sh-pfc/core.h3
-rw-r--r--drivers/pinctrl/sh-pfc/gpio.c37
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-emev2.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a73a4.c124
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7740.c68
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7778.c266
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7779.c425
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7790.c1062
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7791.c1103
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7794.c1035
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7795.c2816
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7203.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7264.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7269.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh73a0.c68
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7720.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7722.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7723.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7724.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7734.c782
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7757.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7785.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7786.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-shx3.c4
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h93
-rw-r--r--drivers/pinctrl/sirf/pinctrl-atlas7.c1828
-rw-r--r--drivers/pinctrl/sunxi/Kconfig4
-rw-r--r--drivers/pinctrl/sunxi/Makefile1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c24
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c603
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.c8
-rw-r--r--drivers/pinctrl/uniphier/Kconfig14
-rw-r--r--drivers/pinctrl/uniphier/Makefile2
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c5
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c5
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c11
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c5
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c5
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-proxstream2.c5
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-core.c10
-rw-r--r--drivers/usb/renesas_usbhs/rcar2.c1
-rw-r--r--include/linux/pinctrl/devinfo.h10
-rw-r--r--include/linux/pinctrl/pinconf-generic.h64
-rw-r--r--include/linux/pinctrl/pinctrl-state.h8
91 files changed, 11047 insertions, 3000 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 3c821cda1ad0..b321b26780dc 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -17,6 +17,7 @@ Required properties:
17 "allwinner,sun8i-a23-pinctrl" 17 "allwinner,sun8i-a23-pinctrl"
18 "allwinner,sun8i-a23-r-pinctrl" 18 "allwinner,sun8i-a23-r-pinctrl"
19 "allwinner,sun8i-a33-pinctrl" 19 "allwinner,sun8i-a33-pinctrl"
20 "allwinner,sun8i-a83t-pinctrl"
20 21
21- reg: Should contain the register physical address and length for the 22- reg: Should contain the register physical address and length for the
22 pin controller. 23 pin controller.
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt
new file mode 100644
index 000000000000..61ac75706cc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt
@@ -0,0 +1,90 @@
1* Atmel PIO4 Controller
2
3The Atmel PIO4 controller is used to select the function of a pin and to
4configure it.
5
6Required properties:
7- compatible: "atmel,sama5d2-pinctrl".
8- reg: base address and length of the PIO controller.
9- interrupts: interrupt outputs from the controller, one for each bank.
10- interrupt-controller: mark the device node as an interrupt controller.
11- #interrupt-cells: should be two.
12- gpio-controller: mark the device node as a gpio controller.
13- #gpio-cells: should be two.
14
15Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
16a general description of GPIO and interrupt bindings.
17
18Please refer to pinctrl-bindings.txt in this directory for details of the
19common pinctrl bindings used by client devices.
20
21Subnode format
22Each node (or subnode) will list the pins it needs and how to configured these
23pins.
24
25 node {
26 pinmux = <PIN_NUMBER_PINMUX>;
27 GENERIC_PINCONFIG;
28 };
29
30Required properties:
31- pinmux: integer array. Each integer represents a pin number plus mux and
32ioset settings. Use the macros from boot/dts/<soc>-pinfunc.h file to get the
33right representation of the pin.
34
35Optional properties:
36- GENERIC_PINCONFIG: generic pinconfig options to use, bias-disable,
37bias-pull-down, bias-pull-up, drive-open-drain, input-schmitt-enable,
38input-debounce, output-low, output-high.
39
40Example:
41
42#include <sama5d2-pinfunc.h>
43
44...
45{
46 pioA: pinctrl@fc038000 {
47 compatible = "atmel,sama5d2-pinctrl";
48 reg = <0xfc038000 0x600>;
49 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
50 <68 IRQ_TYPE_LEVEL_HIGH 7>,
51 <69 IRQ_TYPE_LEVEL_HIGH 7>,
52 <70 IRQ_TYPE_LEVEL_HIGH 7>;
53 interrupt-controller;
54 #interrupt-cells = <2>;
55 gpio-controller;
56 #gpio-cells = <2>;
57 clocks = <&pioA_clk>;
58
59 pinctrl_i2c0_default: i2c0_default {
60 pinmux = <PIN_PD21__TWD0>,
61 <PIN_PD22__TWCK0>;
62 bias-disable;
63 };
64
65 pinctrl_led_gpio_default: led_gpio_default {
66 pinmux = <PIN_PB0>,
67 <PIN_PB5>;
68 bias-pull-up;
69 };
70
71 pinctrl_sdmmc1_default: sdmmc1_default {
72 cmd_data {
73 pinmux = <PIN_PA28__SDMMC1_CMD>,
74 <PIN_PA18__SDMMC1_DAT0>,
75 <PIN_PA19__SDMMC1_DAT1>,
76 <PIN_PA20__SDMMC1_DAT2>,
77 <PIN_PA21__SDMMC1_DAT3>;
78 bias-pull-up;
79 };
80
81 ck_cd {
82 pinmux = <PIN_PA22__SDMMC1_CK>,
83 <PIN_PA30__SDMMC1_CD>;
84 bias-disable;
85 };
86 };
87 ...
88 };
89};
90...
diff --git a/Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt
index a8bb5e26019c..f8fa28ce163e 100644
--- a/Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/berlin,pinctrl.txt
@@ -20,7 +20,10 @@ Required properties:
20 "marvell,berlin2cd-soc-pinctrl", 20 "marvell,berlin2cd-soc-pinctrl",
21 "marvell,berlin2cd-system-pinctrl", 21 "marvell,berlin2cd-system-pinctrl",
22 "marvell,berlin2q-soc-pinctrl", 22 "marvell,berlin2q-soc-pinctrl",
23 "marvell,berlin2q-system-pinctrl" 23 "marvell,berlin2q-system-pinctrl",
24 "marvell,berlin4ct-avio-pinctrl",
25 "marvell,berlin4ct-soc-pinctrl",
26 "marvell,berlin4ct-system-pinctrl"
24 27
25Required subnode-properties: 28Required subnode-properties:
26- groups: a list of strings describing the group names. 29- groups: a list of strings describing the group names.
diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt
index 6540ca56be5e..16589fb6f420 100644
--- a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt
+++ b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-gpio.txt
@@ -3,8 +3,8 @@ Broadcom Cygnus GPIO/PINCONF Controller
3Required properties: 3Required properties:
4 4
5- compatible: 5- compatible:
6 Must be "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or 6 Must be "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio",
7 "brcm,cygnus-crmu-gpio" 7 "brcm,cygnus-crmu-gpio" or "brcm,iproc-gpio"
8 8
9- reg: 9- reg:
10 Define the base and range of the I/O address space that contains the Cygnus 10 Define the base and range of the I/O address space that contains the Cygnus
@@ -26,9 +26,13 @@ Optional properties:
26- interrupt-controller: 26- interrupt-controller:
27 Specifies that the node is an interrupt controller 27 Specifies that the node is an interrupt controller
28 28
29- pinmux: 29- gpio-ranges:
30 Specifies the phandle to the IOMUX device, where pins can be individually 30 Specifies the mapping between gpio controller and pin-controllers pins.
31muxed to GPIO 31 This requires 4 fields in cells defined as -
32 1. Phandle of pin-controller.
33 2. GPIO base pin offset.
34 3 Pin-control base pin offset.
35 4. number of gpio pins which are linearly mapped from pin base.
32 36
33Supported generic PINCONF properties in child nodes: 37Supported generic PINCONF properties in child nodes:
34 38
@@ -78,6 +82,8 @@ Example:
78 gpio-controller; 82 gpio-controller;
79 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 83 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
80 interrupt-controller; 84 interrupt-controller;
85 gpio-ranges = <&pinctrl 0 42 1>,
86 <&pinctrl 1 44 3>;
81 }; 87 };
82 88
83 /* 89 /*
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
index 8bbf25d58656..457b2c68d47b 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
@@ -1,16 +1,42 @@
1* Freescale i.MX7 Dual IOMUX Controller 1* Freescale i.MX7 Dual IOMUX Controller
2 2
3iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
4as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
5power state retention capabilities on gpios that are part of iomuxc-lpsr
6(GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for
7mux and pad control settings, it shares the input select register from main
8iomuxc controller for daisy chain settings, the fsl,input-sel property extends
9fsl,imx-pinctrl driver to support iomuxc-lpsr controller.
10
11iomuxc_lpsr: iomuxc-lpsr@302c0000 {
12 compatible = "fsl,imx7d-iomuxc-lpsr";
13 reg = <0x302c0000 0x10000>;
14 fsl,input-sel = <&iomuxc>;
15};
16
17iomuxc: iomuxc@30330000 {
18 compatible = "fsl,imx7d-iomuxc";
19 reg = <0x30330000 0x10000>;
20};
21
22Pheriparials using pads from iomuxc-lpsr support low state retention power
23state, under LPSR mode GPIO's state of pads are retain.
24
3Please refer to fsl,imx-pinctrl.txt in this directory for common binding part 25Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
4and usage. 26and usage.
5 27
6Required properties: 28Required properties:
7- compatible: "fsl,imx7d-iomuxc" 29- compatible: "fsl,imx7d-iomuxc" for main IOMUXC controller, or
30 "fsl,imx7d-iomuxc-lpsr" for Low Power State Retention IOMUXC controller.
8- fsl,pins: each entry consists of 6 integers and represents the mux and config 31- fsl,pins: each entry consists of 6 integers and represents the mux and config
9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val 32 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
10 input_val> are specified using a PIN_FUNC_ID macro, which can be found in 33 input_val> are specified using a PIN_FUNC_ID macro, which can be found in
11 imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is 34 imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is
12 the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual 35 the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual
13 Reference Manual for detailed CONFIG settings. 36 Reference Manual for detailed CONFIG settings.
37- fsl,input-sel: required property for iomuxc-lpsr controller, this property is
38 a phandle for main iomuxc controller which shares the input select register for
39 daisy chain settings.
14 40
15CONFIG bits definition: 41CONFIG bits definition:
16PAD_CTL_PUS_100K_DOWN (0 << 5) 42PAD_CTL_PUS_100K_DOWN (0 << 5)
@@ -25,3 +51,38 @@ PAD_CTL_DSE_X1 (0 << 0)
25PAD_CTL_DSE_X2 (1 << 0) 51PAD_CTL_DSE_X2 (1 << 0)
26PAD_CTL_DSE_X3 (2 << 0) 52PAD_CTL_DSE_X3 (2 << 0)
27PAD_CTL_DSE_X4 (3 << 0) 53PAD_CTL_DSE_X4 (3 << 0)
54
55Examples:
56While iomuxc-lpsr is intended to be used by dedicated peripherals to take
57advantages of LPSR power mode, is also possible that an IP to use pads from
58any of the iomux controllers. For example the I2C1 IP can use SCL pad from
59iomuxc-lpsr controller and SDA pad from iomuxc controller as:
60
61i2c1: i2c@30a20000 {
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_i2c1_1 &pinctrl_i2c1_2>;
64 status = "okay";
65};
66
67iomuxc-lpsr@302c0000 {
68 compatible = "fsl,imx7d-iomuxc-lpsr";
69 reg = <0x302c0000 0x10000>;
70 fsl,input-sel = <&iomuxc>;
71
72 pinctrl_i2c1_1: i2c1grp-1 {
73 fsl,pins = <
74 MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f
75 >;
76 };
77};
78
79iomuxc@30330000 {
80 compatible = "fsl,imx7d-iomuxc";
81 reg = <0x30330000 0x10000>;
82
83 pinctrl_i2c1_2: i2c1grp-2 {
84 fsl,pins = <
85 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
86 >;
87 };
88};
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
index 9496934528bd..ffadb7a371f6 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -19,6 +19,7 @@ Required Properties:
19 - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller. 19 - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
20 - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller. 20 - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
21 - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller. 21 - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
22 - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
22 - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. 23 - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
23 24
24 - reg: Base address and length of each memory resource used by the pin 25 - reg: Base address and length of each memory resource used by the pin
diff --git a/MAINTAINERS b/MAINTAINERS
index 747c65316167..c9c6052b9951 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8181,6 +8181,13 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
8181S: Maintained 8181S: Maintained
8182F: drivers/pinctrl/pinctrl-at91.* 8182F: drivers/pinctrl/pinctrl-at91.*
8183 8183
8184PIN CONTROLLER - ATMEL AT91 PIO4
8185M: Ludovic Desroches <ludovic.desroches@atmel.com>
8186L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
8187L: linux-gpio@vger.kernel.org
8188S: Supported
8189F: drivers/pinctrl/pinctrl-at91-pio4.*
8190
8184PIN CONTROLLER - INTEL 8191PIN CONTROLLER - INTEL
8185M: Mika Westerberg <mika.westerberg@linux.intel.com> 8192M: Mika Westerberg <mika.westerberg@linux.intel.com>
8186M: Heikki Krogerus <heikki.krogerus@linux.intel.com> 8193M: Heikki Krogerus <heikki.krogerus@linux.intel.com>
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 034cd48ae28b..cc05cde0f9a4 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -921,6 +921,20 @@
921 clocks = <&twi1_clk>; 921 clocks = <&twi1_clk>;
922 status = "disabled"; 922 status = "disabled";
923 }; 923 };
924
925 pioA: pinctrl@fc038000 {
926 compatible = "atmel,sama5d2-pinctrl";
927 reg = <0xfc038000 0x600>;
928 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
929 <68 IRQ_TYPE_LEVEL_HIGH 7>,
930 <69 IRQ_TYPE_LEVEL_HIGH 7>,
931 <70 IRQ_TYPE_LEVEL_HIGH 7>;
932 interrupt-controller;
933 #interrupt-cells = <2>;
934 gpio-controller;
935 #gpio-cells = <2>;
936 clocks = <&pioA_clk>;
937 };
924 }; 938 };
925 }; 939 };
926}; 940};
diff --git a/drivers/base/dd.c b/drivers/base/dd.c
index be0eb4639128..a641cf3ccad6 100644
--- a/drivers/base/dd.c
+++ b/drivers/base/dd.c
@@ -322,6 +322,8 @@ static int really_probe(struct device *dev, struct device_driver *drv)
322 goto probe_failed; 322 goto probe_failed;
323 } 323 }
324 324
325 pinctrl_init_done(dev);
326
325 if (dev->pm_domain && dev->pm_domain->sync) 327 if (dev->pm_domain && dev->pm_domain->sync)
326 dev->pm_domain->sync(dev); 328 dev->pm_domain->sync(dev);
327 329
diff --git a/drivers/base/pinctrl.c b/drivers/base/pinctrl.c
index 5fb74b43848e..076297592754 100644
--- a/drivers/base/pinctrl.c
+++ b/drivers/base/pinctrl.c
@@ -42,9 +42,20 @@ int pinctrl_bind_pins(struct device *dev)
42 goto cleanup_get; 42 goto cleanup_get;
43 } 43 }
44 44
45 ret = pinctrl_select_state(dev->pins->p, dev->pins->default_state); 45 dev->pins->init_state = pinctrl_lookup_state(dev->pins->p,
46 PINCTRL_STATE_INIT);
47 if (IS_ERR(dev->pins->init_state)) {
48 /* Not supplying this state is perfectly legal */
49 dev_dbg(dev, "no init pinctrl state\n");
50
51 ret = pinctrl_select_state(dev->pins->p,
52 dev->pins->default_state);
53 } else {
54 ret = pinctrl_select_state(dev->pins->p, dev->pins->init_state);
55 }
56
46 if (ret) { 57 if (ret) {
47 dev_dbg(dev, "failed to activate default pinctrl state\n"); 58 dev_dbg(dev, "failed to activate initial pinctrl state\n");
48 goto cleanup_get; 59 goto cleanup_get;
49 } 60 }
50 61
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 84dd2ed47a92..b422e4ed73f4 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -67,6 +67,19 @@ config PINCTRL_AT91
67 help 67 help
68 Say Y here to enable the at91 pinctrl driver 68 Say Y here to enable the at91 pinctrl driver
69 69
70config PINCTRL_AT91PIO4
71 bool "AT91 PIO4 pinctrl driver"
72 depends on OF
73 depends on ARCH_AT91
74 select PINMUX
75 select GENERIC_PINCONF
76 select GPIOLIB
77 select GPIOLIB_IRQCHIP
78 select OF_GPIO
79 help
80 Say Y here to enable the at91 pinctrl/gpio driver for Atmel PIO4
81 controller available on sama5d2 SoC.
82
70config PINCTRL_AMD 83config PINCTRL_AMD
71 bool "AMD GPIO pin control" 84 bool "AMD GPIO pin control"
72 depends on GPIOLIB 85 depends on GPIOLIB
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index cad077c43fb7..738cb4929a49 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o
12obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o 12obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o
13obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o 13obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o
14obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o 14obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
15obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
15obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o 16obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
16obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o 17obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
17obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o 18obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
@@ -50,6 +51,6 @@ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
50obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/ 51obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/
51obj-$(CONFIG_PLAT_SPEAR) += spear/ 52obj-$(CONFIG_PLAT_SPEAR) += spear/
52obj-$(CONFIG_ARCH_SUNXI) += sunxi/ 53obj-$(CONFIG_ARCH_SUNXI) += sunxi/
53obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/ 54obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
54obj-$(CONFIG_ARCH_VT8500) += vt8500/ 55obj-$(CONFIG_ARCH_VT8500) += vt8500/
55obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ 56obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c
index 1ca783098e47..12a48f498b75 100644
--- a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c
+++ b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c
@@ -29,7 +29,6 @@
29#include <linux/of_device.h> 29#include <linux/of_device.h>
30#include <linux/of_irq.h> 30#include <linux/of_irq.h>
31#include <linux/pinctrl/pinctrl.h> 31#include <linux/pinctrl/pinctrl.h>
32#include <linux/pinctrl/pinmux.h>
33#include <linux/pinctrl/pinconf.h> 32#include <linux/pinctrl/pinconf.h>
34#include <linux/pinctrl/pinconf-generic.h> 33#include <linux/pinctrl/pinconf-generic.h>
35 34
@@ -597,127 +596,6 @@ static const struct pinconf_ops cygnus_pconf_ops = {
597}; 596};
598 597
599/* 598/*
600 * Map a GPIO in the local gpio_chip pin space to a pin in the Cygnus IOMUX
601 * pinctrl pin space
602 */
603struct cygnus_gpio_pin_range {
604 unsigned offset;
605 unsigned pin_base;
606 unsigned num_pins;
607};
608
609#define CYGNUS_PINRANGE(o, p, n) { .offset = o, .pin_base = p, .num_pins = n }
610
611/*
612 * Pin mapping table for mapping local GPIO pins to Cygnus IOMUX pinctrl pins
613 */
614static const struct cygnus_gpio_pin_range cygnus_gpio_pintable[] = {
615 CYGNUS_PINRANGE(0, 42, 1),
616 CYGNUS_PINRANGE(1, 44, 3),
617 CYGNUS_PINRANGE(4, 48, 1),
618 CYGNUS_PINRANGE(5, 50, 3),
619 CYGNUS_PINRANGE(8, 126, 1),
620 CYGNUS_PINRANGE(9, 155, 1),
621 CYGNUS_PINRANGE(10, 152, 1),
622 CYGNUS_PINRANGE(11, 154, 1),
623 CYGNUS_PINRANGE(12, 153, 1),
624 CYGNUS_PINRANGE(13, 127, 3),
625 CYGNUS_PINRANGE(16, 140, 1),
626 CYGNUS_PINRANGE(17, 145, 7),
627 CYGNUS_PINRANGE(24, 130, 10),
628 CYGNUS_PINRANGE(34, 141, 4),
629 CYGNUS_PINRANGE(38, 54, 1),
630 CYGNUS_PINRANGE(39, 56, 3),
631 CYGNUS_PINRANGE(42, 60, 3),
632 CYGNUS_PINRANGE(45, 64, 3),
633 CYGNUS_PINRANGE(48, 68, 2),
634 CYGNUS_PINRANGE(50, 84, 6),
635 CYGNUS_PINRANGE(56, 94, 6),
636 CYGNUS_PINRANGE(62, 72, 1),
637 CYGNUS_PINRANGE(63, 70, 1),
638 CYGNUS_PINRANGE(64, 80, 1),
639 CYGNUS_PINRANGE(65, 74, 3),
640 CYGNUS_PINRANGE(68, 78, 1),
641 CYGNUS_PINRANGE(69, 82, 1),
642 CYGNUS_PINRANGE(70, 156, 17),
643 CYGNUS_PINRANGE(87, 104, 12),
644 CYGNUS_PINRANGE(99, 102, 2),
645 CYGNUS_PINRANGE(101, 90, 4),
646 CYGNUS_PINRANGE(105, 116, 6),
647 CYGNUS_PINRANGE(111, 100, 2),
648 CYGNUS_PINRANGE(113, 122, 4),
649 CYGNUS_PINRANGE(123, 11, 1),
650 CYGNUS_PINRANGE(124, 38, 4),
651 CYGNUS_PINRANGE(128, 43, 1),
652 CYGNUS_PINRANGE(129, 47, 1),
653 CYGNUS_PINRANGE(130, 49, 1),
654 CYGNUS_PINRANGE(131, 53, 1),
655 CYGNUS_PINRANGE(132, 55, 1),
656 CYGNUS_PINRANGE(133, 59, 1),
657 CYGNUS_PINRANGE(134, 63, 1),
658 CYGNUS_PINRANGE(135, 67, 1),
659 CYGNUS_PINRANGE(136, 71, 1),
660 CYGNUS_PINRANGE(137, 73, 1),
661 CYGNUS_PINRANGE(138, 77, 1),
662 CYGNUS_PINRANGE(139, 79, 1),
663 CYGNUS_PINRANGE(140, 81, 1),
664 CYGNUS_PINRANGE(141, 83, 1),
665 CYGNUS_PINRANGE(142, 10, 1)
666};
667
668/*
669 * The Cygnus IOMUX controller mainly supports group based mux configuration,
670 * but certain pins can be muxed to GPIO individually. Only the ASIU GPIO
671 * controller can support this, so it's an optional configuration
672 *
673 * Return -ENODEV means no support and that's fine
674 */
675static int cygnus_gpio_pinmux_add_range(struct cygnus_gpio *chip)
676{
677 struct device_node *node = chip->dev->of_node;
678 struct device_node *pinmux_node;
679 struct platform_device *pinmux_pdev;
680 struct gpio_chip *gc = &chip->gc;
681 int i, ret = 0;
682
683 /* parse DT to find the phandle to the pinmux controller */
684 pinmux_node = of_parse_phandle(node, "pinmux", 0);
685 if (!pinmux_node)
686 return -ENODEV;
687
688 pinmux_pdev = of_find_device_by_node(pinmux_node);
689 /* no longer need the pinmux node */
690 of_node_put(pinmux_node);
691 if (!pinmux_pdev) {
692 dev_err(chip->dev, "failed to get pinmux device\n");
693 return -EINVAL;
694 }
695
696 /* now need to create the mapping between local GPIO and PINMUX pins */
697 for (i = 0; i < ARRAY_SIZE(cygnus_gpio_pintable); i++) {
698 ret = gpiochip_add_pin_range(gc, dev_name(&pinmux_pdev->dev),
699 cygnus_gpio_pintable[i].offset,
700 cygnus_gpio_pintable[i].pin_base,
701 cygnus_gpio_pintable[i].num_pins);
702 if (ret) {
703 dev_err(chip->dev, "unable to add GPIO pin range\n");
704 goto err_put_device;
705 }
706 }
707
708 chip->pinmux_is_supported = true;
709
710 /* no need for pinmux_pdev device reference anymore */
711 put_device(&pinmux_pdev->dev);
712 return 0;
713
714err_put_device:
715 put_device(&pinmux_pdev->dev);
716 gpiochip_remove_pin_ranges(gc);
717 return ret;
718}
719
720/*
721 * Cygnus GPIO controller supports some PINCONF related configurations such as 599 * Cygnus GPIO controller supports some PINCONF related configurations such as
722 * pull up, pull down, and drive strength, when the pin is configured to GPIO 600 * pull up, pull down, and drive strength, when the pin is configured to GPIO
723 * 601 *
@@ -851,18 +729,15 @@ static int cygnus_gpio_probe(struct platform_device *pdev)
851 gc->set = cygnus_gpio_set; 729 gc->set = cygnus_gpio_set;
852 gc->get = cygnus_gpio_get; 730 gc->get = cygnus_gpio_get;
853 731
732 chip->pinmux_is_supported = of_property_read_bool(dev->of_node,
733 "gpio-ranges");
734
854 ret = gpiochip_add(gc); 735 ret = gpiochip_add(gc);
855 if (ret < 0) { 736 if (ret < 0) {
856 dev_err(dev, "unable to add GPIO chip\n"); 737 dev_err(dev, "unable to add GPIO chip\n");
857 return ret; 738 return ret;
858 } 739 }
859 740
860 ret = cygnus_gpio_pinmux_add_range(chip);
861 if (ret && ret != -ENODEV) {
862 dev_err(dev, "unable to add GPIO pin range\n");
863 goto err_rm_gpiochip;
864 }
865
866 ret = cygnus_gpio_register_pinconf(chip); 741 ret = cygnus_gpio_register_pinconf(chip);
867 if (ret) { 742 if (ret) {
868 dev_err(dev, "unable to register pinconf\n"); 743 dev_err(dev, "unable to register pinconf\n");
diff --git a/drivers/pinctrl/berlin/Kconfig b/drivers/pinctrl/berlin/Kconfig
index b18322bc7bf9..8fe6ad7795dc 100644
--- a/drivers/pinctrl/berlin/Kconfig
+++ b/drivers/pinctrl/berlin/Kconfig
@@ -1,4 +1,4 @@
1if ARCH_BERLIN 1if (ARCH_BERLIN || COMPILE_TEST)
2 2
3config PINCTRL_BERLIN 3config PINCTRL_BERLIN
4 bool 4 bool
@@ -6,15 +6,23 @@ config PINCTRL_BERLIN
6 select REGMAP_MMIO 6 select REGMAP_MMIO
7 7
8config PINCTRL_BERLIN_BG2 8config PINCTRL_BERLIN_BG2
9 bool 9 def_bool MACH_BERLIN_BG2
10 depends on OF
10 select PINCTRL_BERLIN 11 select PINCTRL_BERLIN
11 12
12config PINCTRL_BERLIN_BG2CD 13config PINCTRL_BERLIN_BG2CD
13 bool 14 def_bool MACH_BERLIN_BG2CD
15 depends on OF
14 select PINCTRL_BERLIN 16 select PINCTRL_BERLIN
15 17
16config PINCTRL_BERLIN_BG2Q 18config PINCTRL_BERLIN_BG2Q
17 bool 19 def_bool MACH_BERLIN_BG2Q
20 depends on OF
21 select PINCTRL_BERLIN
22
23config PINCTRL_BERLIN_BG4CT
24 bool "Marvell berlin4ct pin controller driver"
25 depends on OF
18 select PINCTRL_BERLIN 26 select PINCTRL_BERLIN
19 27
20endif 28endif
diff --git a/drivers/pinctrl/berlin/Makefile b/drivers/pinctrl/berlin/Makefile
index deb0c6baf316..06f94029ad66 100644
--- a/drivers/pinctrl/berlin/Makefile
+++ b/drivers/pinctrl/berlin/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_PINCTRL_BERLIN) += berlin.o
2obj-$(CONFIG_PINCTRL_BERLIN_BG2) += berlin-bg2.o 2obj-$(CONFIG_PINCTRL_BERLIN_BG2) += berlin-bg2.o
3obj-$(CONFIG_PINCTRL_BERLIN_BG2CD) += berlin-bg2cd.o 3obj-$(CONFIG_PINCTRL_BERLIN_BG2CD) += berlin-bg2cd.o
4obj-$(CONFIG_PINCTRL_BERLIN_BG2Q) += berlin-bg2q.o 4obj-$(CONFIG_PINCTRL_BERLIN_BG2Q) += berlin-bg2q.o
5obj-$(CONFIG_PINCTRL_BERLIN_BG4CT) += berlin-bg4ct.o
diff --git a/drivers/pinctrl/berlin/berlin-bg2.c b/drivers/pinctrl/berlin/berlin-bg2.c
index 274c5535b531..fabe728ae268 100644
--- a/drivers/pinctrl/berlin/berlin-bg2.c
+++ b/drivers/pinctrl/berlin/berlin-bg2.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 2014 Marvell Technology Group Ltd. 4 * Copyright (C) 2014 Marvell Technology Group Ltd.
5 * 5 *
6 * Antoine Ténart <antoine.tenart@free-electrons.com> 6 * Antoine Ténart <antoine.tenart@free-electrons.com>
7 * 7 *
8 * This file is licensed under the terms of the GNU General Public 8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any 9 * License version 2. This program is licensed "as is" without any
@@ -246,6 +246,6 @@ static struct platform_driver berlin2_pinctrl_driver = {
246}; 246};
247module_platform_driver(berlin2_pinctrl_driver); 247module_platform_driver(berlin2_pinctrl_driver);
248 248
249MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>"); 249MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>");
250MODULE_DESCRIPTION("Marvell Berlin BG2 pinctrl driver"); 250MODULE_DESCRIPTION("Marvell Berlin BG2 pinctrl driver");
251MODULE_LICENSE("GPL"); 251MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/berlin/berlin-bg2cd.c b/drivers/pinctrl/berlin/berlin-bg2cd.c
index 0cb793a3552a..ad8c75861373 100644
--- a/drivers/pinctrl/berlin/berlin-bg2cd.c
+++ b/drivers/pinctrl/berlin/berlin-bg2cd.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 2014 Marvell Technology Group Ltd. 4 * Copyright (C) 2014 Marvell Technology Group Ltd.
5 * 5 *
6 * Antoine Ténart <antoine.tenart@free-electrons.com> 6 * Antoine Ténart <antoine.tenart@free-electrons.com>
7 * 7 *
8 * This file is licensed under the terms of the GNU General Public 8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any 9 * License version 2. This program is licensed "as is" without any
@@ -19,24 +19,24 @@
19 19
20static const struct berlin_desc_group berlin2cd_soc_pinctrl_groups[] = { 20static const struct berlin_desc_group berlin2cd_soc_pinctrl_groups[] = {
21 /* G */ 21 /* G */
22 BERLIN_PINCTRL_GROUP("G0", 0x00, 0x1, 0x00, 22 BERLIN_PINCTRL_GROUP("G0", 0x00, 0x3, 0x00,
23 BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), 23 BERLIN_PINCTRL_FUNCTION(0x0, "jtag"),
24 BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), 24 BERLIN_PINCTRL_FUNCTION(0x1, "gpio"),
25 BERLIN_PINCTRL_FUNCTION(0x2, "led"), 25 BERLIN_PINCTRL_FUNCTION(0x2, "led"),
26 BERLIN_PINCTRL_FUNCTION(0x3, "pwm")), 26 BERLIN_PINCTRL_FUNCTION(0x3, "pwm")),
27 BERLIN_PINCTRL_GROUP("G1", 0x00, 0x2, 0x01, 27 BERLIN_PINCTRL_GROUP("G1", 0x00, 0x3, 0x03,
28 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), 28 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
29 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), 29 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
30 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), 30 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
31 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), 31 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
32 BERLIN_PINCTRL_GROUP("G2", 0x00, 0x2, 0x02, 32 BERLIN_PINCTRL_GROUP("G2", 0x00, 0x3, 0x06,
33 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), 33 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
34 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), 34 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
35 BERLIN_PINCTRL_FUNCTION(0x2, "fe"), 35 BERLIN_PINCTRL_FUNCTION(0x2, "fe"),
36 BERLIN_PINCTRL_FUNCTION(0x3, "pll"), 36 BERLIN_PINCTRL_FUNCTION(0x3, "pll"),
37 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), 37 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
38 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), 38 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
39 BERLIN_PINCTRL_GROUP("G3", 0x00, 0x2, 0x04, 39 BERLIN_PINCTRL_GROUP("G3", 0x00, 0x3, 0x09,
40 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), 40 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
41 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), 41 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
42 BERLIN_PINCTRL_FUNCTION(0x2, "twsi2"), 42 BERLIN_PINCTRL_FUNCTION(0x2, "twsi2"),
@@ -44,7 +44,7 @@ static const struct berlin_desc_group berlin2cd_soc_pinctrl_groups[] = {
44 BERLIN_PINCTRL_FUNCTION(0x4, "fe"), 44 BERLIN_PINCTRL_FUNCTION(0x4, "fe"),
45 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), 45 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
46 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), 46 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
47 BERLIN_PINCTRL_GROUP("G4", 0x00, 0x2, 0x06, 47 BERLIN_PINCTRL_GROUP("G4", 0x00, 0x3, 0x0c,
48 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), 48 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
49 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), 49 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
50 BERLIN_PINCTRL_FUNCTION(0x2, "twsi3"), 50 BERLIN_PINCTRL_FUNCTION(0x2, "twsi3"),
@@ -52,7 +52,7 @@ static const struct berlin_desc_group berlin2cd_soc_pinctrl_groups[] = {
52 BERLIN_PINCTRL_FUNCTION(0x4, "pwm"), 52 BERLIN_PINCTRL_FUNCTION(0x4, "pwm"),
53 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), 53 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
54 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), 54 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
55 BERLIN_PINCTRL_GROUP("G5", 0x00, 0x3, 0x08, 55 BERLIN_PINCTRL_GROUP("G5", 0x00, 0x3, 0x0f,
56 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), 56 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
57 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), 57 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
58 BERLIN_PINCTRL_FUNCTION(0x2, "twsi3"), 58 BERLIN_PINCTRL_FUNCTION(0x2, "twsi3"),
@@ -60,64 +60,66 @@ static const struct berlin_desc_group berlin2cd_soc_pinctrl_groups[] = {
60 BERLIN_PINCTRL_FUNCTION(0x4, "pwm"), 60 BERLIN_PINCTRL_FUNCTION(0x4, "pwm"),
61 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"), 61 BERLIN_PINCTRL_FUNCTION(0x6, "usb0_dbg"),
62 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")), 62 BERLIN_PINCTRL_FUNCTION(0x7, "usb1_dbg")),
63 BERLIN_PINCTRL_GROUP("G6", 0x00, 0x2, 0x0b, 63 BERLIN_PINCTRL_GROUP("G6", 0x00, 0x3, 0x12,
64 BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RX/TX */ 64 BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RX/TX */
65 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), 65 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
66 BERLIN_PINCTRL_GROUP("G7", 0x00, 0x3, 0x0d, 66 BERLIN_PINCTRL_GROUP("G7", 0x00, 0x3, 0x15,
67 BERLIN_PINCTRL_FUNCTION(0x0, "eddc"), 67 BERLIN_PINCTRL_FUNCTION(0x0, "eddc"),
68 BERLIN_PINCTRL_FUNCTION(0x1, "twsi1"), 68 BERLIN_PINCTRL_FUNCTION(0x1, "twsi1"),
69 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")), 69 BERLIN_PINCTRL_FUNCTION(0x2, "gpio")),
70 BERLIN_PINCTRL_GROUP("G8", 0x00, 0x3, 0x10, 70 BERLIN_PINCTRL_GROUP("G8", 0x00, 0x3, 0x18,
71 BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS0n */ 71 BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS0n */
72 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), 72 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
73 BERLIN_PINCTRL_GROUP("G9", 0x00, 0x3, 0x13, 73 BERLIN_PINCTRL_GROUP("G9", 0x00, 0x3, 0x1b,
74 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), 74 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"),
75 BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS1n/SS2n */ 75 BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS1n/SS2n */
76 BERLIN_PINCTRL_FUNCTION(0x2, "twsi0")), 76 BERLIN_PINCTRL_FUNCTION(0x3, "twsi0")),
77 BERLIN_PINCTRL_GROUP("G10", 0x00, 0x2, 0x16, 77 BERLIN_PINCTRL_GROUP("G10", 0x00, 0x2, 0x1e,
78 BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* CLK */ 78 BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* CLK */
79 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), 79 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
80 BERLIN_PINCTRL_GROUP("G11", 0x00, 0x2, 0x18, 80 BERLIN_PINCTRL_GROUP("G11", 0x04, 0x2, 0x00,
81 BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SDI/SDO */ 81 BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SDI/SDO */
82 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), 82 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
83 BERLIN_PINCTRL_GROUP("G12", 0x00, 0x3, 0x1a, 83 BERLIN_PINCTRL_GROUP("G12", 0x04, 0x3, 0x02,
84 BERLIN_PINCTRL_FUNCTION(0x0, "usb1"), 84 BERLIN_PINCTRL_FUNCTION(0x0, "usb1"),
85 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), 85 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
86 BERLIN_PINCTRL_GROUP("G13", 0x04, 0x3, 0x00, 86 BERLIN_PINCTRL_GROUP("G13", 0x04, 0x3, 0x05,
87 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), 87 BERLIN_PINCTRL_FUNCTION(0x0, "nand"),
88 BERLIN_PINCTRL_FUNCTION(0x1, "usb0_dbg"), 88 BERLIN_PINCTRL_FUNCTION(0x1, "usb0_dbg"),
89 BERLIN_PINCTRL_FUNCTION(0x2, "usb1_dbg")), 89 BERLIN_PINCTRL_FUNCTION(0x2, "usb1_dbg")),
90 BERLIN_PINCTRL_GROUP("G14", 0x04, 0x1, 0x03, 90 BERLIN_PINCTRL_GROUP("G14", 0x04, 0x1, 0x08,
91 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), 91 BERLIN_PINCTRL_FUNCTION(0x0, "nand"),
92 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), 92 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
93 BERLIN_PINCTRL_GROUP("G15", 0x04, 0x2, 0x04, 93 BERLIN_PINCTRL_GROUP("G15", 0x04, 0x3, 0x09,
94 BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), 94 BERLIN_PINCTRL_FUNCTION(0x0, "jtag"),
95 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), 95 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
96 BERLIN_PINCTRL_GROUP("G16", 0x04, 0x3, 0x06, 96 BERLIN_PINCTRL_GROUP("G16", 0x04, 0x3, 0x0c,
97 BERLIN_PINCTRL_FUNCTION_UNKNOWN), 97 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
98 BERLIN_PINCTRL_GROUP("G17", 0x04, 0x3, 0x09, 98 BERLIN_PINCTRL_GROUP("G17", 0x04, 0x3, 0x0f,
99 BERLIN_PINCTRL_FUNCTION_UNKNOWN), 99 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
100 BERLIN_PINCTRL_GROUP("G18", 0x04, 0x1, 0x0c, 100 BERLIN_PINCTRL_GROUP("G18", 0x04, 0x2, 0x12,
101 BERLIN_PINCTRL_FUNCTION_UNKNOWN), 101 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
102 BERLIN_PINCTRL_GROUP("G19", 0x04, 0x1, 0x0d, 102 BERLIN_PINCTRL_GROUP("G19", 0x04, 0x2, 0x14,
103 BERLIN_PINCTRL_FUNCTION_UNKNOWN), 103 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
104 BERLIN_PINCTRL_GROUP("G20", 0x04, 0x1, 0x0e, 104 BERLIN_PINCTRL_GROUP("G20", 0x04, 0x2, 0x16,
105 BERLIN_PINCTRL_FUNCTION_UNKNOWN), 105 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
106 BERLIN_PINCTRL_GROUP("G21", 0x04, 0x3, 0x0f, 106 BERLIN_PINCTRL_GROUP("G21", 0x04, 0x3, 0x18,
107 BERLIN_PINCTRL_FUNCTION_UNKNOWN), 107 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
108 BERLIN_PINCTRL_GROUP("G22", 0x04, 0x3, 0x12, 108 BERLIN_PINCTRL_GROUP("G22", 0x04, 0x3, 0x1b,
109 BERLIN_PINCTRL_FUNCTION_UNKNOWN), 109 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
110 BERLIN_PINCTRL_GROUP("G23", 0x04, 0x3, 0x15, 110 BERLIN_PINCTRL_GROUP("G23", 0x08, 0x3, 0x00,
111 BERLIN_PINCTRL_FUNCTION_UNKNOWN), 111 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
112 BERLIN_PINCTRL_GROUP("G24", 0x04, 0x2, 0x18, 112 BERLIN_PINCTRL_GROUP("G24", 0x08, 0x2, 0x03,
113 BERLIN_PINCTRL_FUNCTION_UNKNOWN), 113 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
114 BERLIN_PINCTRL_GROUP("G25", 0x04, 0x2, 0x1a, 114 BERLIN_PINCTRL_GROUP("G25", 0x08, 0x2, 0x05,
115 BERLIN_PINCTRL_FUNCTION_UNKNOWN), 115 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
116 BERLIN_PINCTRL_GROUP("G26", 0x04, 0x1, 0x1c, 116 BERLIN_PINCTRL_GROUP("G26", 0x08, 0x1, 0x07,
117 BERLIN_PINCTRL_FUNCTION_UNKNOWN), 117 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
118 BERLIN_PINCTRL_GROUP("G27", 0x04, 0x1, 0x1d, 118 BERLIN_PINCTRL_GROUP("G27", 0x08, 0x2, 0x08,
119 BERLIN_PINCTRL_FUNCTION_UNKNOWN), 119 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
120 BERLIN_PINCTRL_GROUP("G28", 0x04, 0x2, 0x1e, 120 BERLIN_PINCTRL_GROUP("G28", 0x08, 0x3, 0x0a,
121 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
122 BERLIN_PINCTRL_GROUP("G29", 0x08, 0x3, 0x0d,
121 BERLIN_PINCTRL_FUNCTION_UNKNOWN), 123 BERLIN_PINCTRL_FUNCTION_UNKNOWN),
122}; 124};
123 125
@@ -189,6 +191,6 @@ static struct platform_driver berlin2cd_pinctrl_driver = {
189}; 191};
190module_platform_driver(berlin2cd_pinctrl_driver); 192module_platform_driver(berlin2cd_pinctrl_driver);
191 193
192MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>"); 194MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>");
193MODULE_DESCRIPTION("Marvell Berlin BG2CD pinctrl driver"); 195MODULE_DESCRIPTION("Marvell Berlin BG2CD pinctrl driver");
194MODULE_LICENSE("GPL"); 196MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/berlin/berlin-bg2q.c b/drivers/pinctrl/berlin/berlin-bg2q.c
index a466054a8206..cd171aea8ca8 100644
--- a/drivers/pinctrl/berlin/berlin-bg2q.c
+++ b/drivers/pinctrl/berlin/berlin-bg2q.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 2014 Marvell Technology Group Ltd. 4 * Copyright (C) 2014 Marvell Technology Group Ltd.
5 * 5 *
6 * Antoine Ténart <antoine.tenart@free-electrons.com> 6 * Antoine Ténart <antoine.tenart@free-electrons.com>
7 * 7 *
8 * This file is licensed under the terms of the GNU General Public 8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any 9 * License version 2. This program is licensed "as is" without any
@@ -408,6 +408,6 @@ static struct platform_driver berlin2q_pinctrl_driver = {
408}; 408};
409module_platform_driver(berlin2q_pinctrl_driver); 409module_platform_driver(berlin2q_pinctrl_driver);
410 410
411MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>"); 411MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>");
412MODULE_DESCRIPTION("Marvell Berlin BG2Q pinctrl driver"); 412MODULE_DESCRIPTION("Marvell Berlin BG2Q pinctrl driver");
413MODULE_LICENSE("GPL"); 413MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/berlin/berlin-bg4ct.c b/drivers/pinctrl/berlin/berlin-bg4ct.c
new file mode 100644
index 000000000000..09172043d589
--- /dev/null
+++ b/drivers/pinctrl/berlin/berlin-bg4ct.c
@@ -0,0 +1,503 @@
1/*
2 * Marvell berlin4ct pinctrl driver
3 *
4 * Copyright (C) 2015 Marvell Technology Group Ltd.
5 *
6 * Author: Jisheng Zhang <jszhang@marvell.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/module.h>
22#include <linux/of_device.h>
23#include <linux/platform_device.h>
24#include <linux/regmap.h>
25
26#include "berlin.h"
27
28static const struct berlin_desc_group berlin4ct_soc_pinctrl_groups[] = {
29 BERLIN_PINCTRL_GROUP("EMMC_RSTn", 0x0, 0x3, 0x00,
30 BERLIN_PINCTRL_FUNCTION(0x0, "emmc"), /* RSTn */
31 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* GPIO47 */
32 BERLIN_PINCTRL_GROUP("NAND_IO0", 0x0, 0x3, 0x03,
33 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO0 */
34 BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXD0 */
35 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* CLK */
36 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO0 */
37 BERLIN_PINCTRL_GROUP("NAND_IO1", 0x0, 0x3, 0x06,
38 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO1 */
39 BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXD1 */
40 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* CDn */
41 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO1 */
42 BERLIN_PINCTRL_GROUP("NAND_IO2", 0x0, 0x3, 0x09,
43 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO2 */
44 BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXD2 */
45 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* DAT0 */
46 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO2 */
47 BERLIN_PINCTRL_GROUP("NAND_IO3", 0x0, 0x3, 0x0c,
48 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO3 */
49 BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXD3 */
50 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* DAT1 */
51 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO3 */
52 BERLIN_PINCTRL_GROUP("NAND_IO4", 0x0, 0x3, 0x0f,
53 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO4 */
54 BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXC */
55 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* DAT2 */
56 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO4 */
57 BERLIN_PINCTRL_GROUP("NAND_IO5", 0x0, 0x3, 0x12,
58 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO5 */
59 BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* RXCTL */
60 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* DAT3 */
61 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO5 */
62 BERLIN_PINCTRL_GROUP("NAND_IO6", 0x0, 0x3, 0x15,
63 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO6 */
64 BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* MDC */
65 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* CMD */
66 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO6 */
67 BERLIN_PINCTRL_GROUP("NAND_IO7", 0x0, 0x3, 0x18,
68 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* IO7 */
69 BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* MDIO */
70 BERLIN_PINCTRL_FUNCTION(0x2, "sd1"), /* WP */
71 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO7 */
72 BERLIN_PINCTRL_GROUP("NAND_ALE", 0x0, 0x3, 0x1b,
73 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* ALE */
74 BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXD0 */
75 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO8 */
76 BERLIN_PINCTRL_GROUP("NAND_CLE", 0x4, 0x3, 0x00,
77 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* CLE */
78 BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXD1 */
79 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO9 */
80 BERLIN_PINCTRL_GROUP("NAND_WEn", 0x4, 0x3, 0x03,
81 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* WEn */
82 BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXD2 */
83 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO10 */
84 BERLIN_PINCTRL_GROUP("NAND_REn", 0x4, 0x3, 0x06,
85 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* REn */
86 BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXD3 */
87 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO11 */
88 BERLIN_PINCTRL_GROUP("NAND_WPn", 0x4, 0x3, 0x09,
89 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* WPn */
90 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO12 */
91 BERLIN_PINCTRL_GROUP("NAND_CEn", 0x4, 0x3, 0x0c,
92 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* CEn */
93 BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXC */
94 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO13 */
95 BERLIN_PINCTRL_GROUP("NAND_RDY", 0x4, 0x3, 0x0f,
96 BERLIN_PINCTRL_FUNCTION(0x0, "nand"), /* RDY */
97 BERLIN_PINCTRL_FUNCTION(0x1, "rgmii"), /* TXCTL */
98 BERLIN_PINCTRL_FUNCTION(0x3, "gpio")), /* GPIO14 */
99 BERLIN_PINCTRL_GROUP("SD0_CLK", 0x4, 0x3, 0x12,
100 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO29 */
101 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* CLK*/
102 BERLIN_PINCTRL_FUNCTION(0x2, "sts4"), /* CLK */
103 BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG8 */
104 BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG8 */
105 BERLIN_PINCTRL_GROUP("SD0_DAT0", 0x4, 0x3, 0x15,
106 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO30 */
107 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT0 */
108 BERLIN_PINCTRL_FUNCTION(0x2, "sts4"), /* SOP */
109 BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG9 */
110 BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG9 */
111 BERLIN_PINCTRL_GROUP("SD0_DAT1", 0x4, 0x3, 0x18,
112 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO31 */
113 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT1 */
114 BERLIN_PINCTRL_FUNCTION(0x2, "sts4"), /* SD */
115 BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG10 */
116 BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG10 */
117 BERLIN_PINCTRL_GROUP("SD0_DAT2", 0x4, 0x3, 0x1b,
118 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO32 */
119 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT2 */
120 BERLIN_PINCTRL_FUNCTION(0x2, "sts4"), /* VALD */
121 BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG11 */
122 BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG11 */
123 BERLIN_PINCTRL_GROUP("SD0_DAT3", 0x8, 0x3, 0x00,
124 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO33 */
125 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* DAT3 */
126 BERLIN_PINCTRL_FUNCTION(0x2, "sts5"), /* CLK */
127 BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG12 */
128 BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG12 */
129 BERLIN_PINCTRL_GROUP("SD0_CDn", 0x8, 0x3, 0x03,
130 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO34 */
131 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* CDn */
132 BERLIN_PINCTRL_FUNCTION(0x2, "sts5"), /* SOP */
133 BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG13 */
134 BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG13 */
135 BERLIN_PINCTRL_GROUP("SD0_CMD", 0x8, 0x3, 0x06,
136 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO35 */
137 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* CMD */
138 BERLIN_PINCTRL_FUNCTION(0x2, "sts5"), /* SD */
139 BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG14 */
140 BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG14 */
141 BERLIN_PINCTRL_GROUP("SD0_WP", 0x8, 0x3, 0x09,
142 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO36 */
143 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"), /* WP */
144 BERLIN_PINCTRL_FUNCTION(0x2, "sts5"), /* VALD */
145 BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG15 */
146 BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG15 */
147 BERLIN_PINCTRL_GROUP("STS0_CLK", 0x8, 0x3, 0x0c,
148 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO21 */
149 BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), /* CLK */
150 BERLIN_PINCTRL_FUNCTION(0x2, "cpupll"), /* CLKO */
151 BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG0 */
152 BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG0 */
153 BERLIN_PINCTRL_GROUP("STS0_SOP", 0x8, 0x3, 0x0f,
154 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO22 */
155 BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), /* SOP */
156 BERLIN_PINCTRL_FUNCTION(0x2, "syspll"), /* CLKO */
157 BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG1 */
158 BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG1 */
159 BERLIN_PINCTRL_GROUP("STS0_SD", 0x8, 0x3, 0x12,
160 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO23 */
161 BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), /* SD */
162 BERLIN_PINCTRL_FUNCTION(0x2, "mempll"), /* CLKO */
163 BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG2 */
164 BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG2 */
165 BERLIN_PINCTRL_GROUP("STS0_VALD", 0x8, 0x3, 0x15,
166 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO24 */
167 BERLIN_PINCTRL_FUNCTION(0x1, "sts0"), /* VALD */
168 BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG3 */
169 BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG3 */
170 BERLIN_PINCTRL_GROUP("STS1_CLK", 0x8, 0x3, 0x18,
171 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO25 */
172 BERLIN_PINCTRL_FUNCTION(0x1, "sts1"), /* CLK */
173 BERLIN_PINCTRL_FUNCTION(0x2, "pwm0"),
174 BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG4 */
175 BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG4 */
176 BERLIN_PINCTRL_GROUP("STS1_SOP", 0x8, 0x3, 0x1b,
177 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO26 */
178 BERLIN_PINCTRL_FUNCTION(0x1, "sts1"), /* SOP */
179 BERLIN_PINCTRL_FUNCTION(0x2, "pwm1"),
180 BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG5 */
181 BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG5 */
182 BERLIN_PINCTRL_GROUP("STS1_SD", 0xc, 0x3, 0x00,
183 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO27 */
184 BERLIN_PINCTRL_FUNCTION(0x1, "sts1"), /* SD */
185 BERLIN_PINCTRL_FUNCTION(0x2, "pwm2"),
186 BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG6 */
187 BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG6 */
188 BERLIN_PINCTRL_GROUP("STS1_VALD", 0xc, 0x3, 0x03,
189 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO28 */
190 BERLIN_PINCTRL_FUNCTION(0x1, "sts1"), /* VALD */
191 BERLIN_PINCTRL_FUNCTION(0x2, "pwm3"),
192 BERLIN_PINCTRL_FUNCTION(0x5, "v4g"), /* DBG7 */
193 BERLIN_PINCTRL_FUNCTION(0x7, "phy")), /* DBG7 */
194 BERLIN_PINCTRL_GROUP("SCRD0_RST", 0xc, 0x3, 0x06,
195 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO15 */
196 BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* RST */
197 BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* CLK */
198 BERLIN_PINCTRL_GROUP("SCRD0_DCLK", 0xc, 0x3, 0x09,
199 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO16 */
200 BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* DCLK */
201 BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* CMD */
202 BERLIN_PINCTRL_GROUP("SCRD0_GPIO0", 0xc, 0x3, 0x0c,
203 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO17 */
204 BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* SCRD0 GPIO0 */
205 BERLIN_PINCTRL_FUNCTION(0x2, "sif"), /* DIO */
206 BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* DAT0 */
207 BERLIN_PINCTRL_GROUP("SCRD0_GPIO1", 0xc, 0x3, 0x0f,
208 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO18 */
209 BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* SCRD0 GPIO1 */
210 BERLIN_PINCTRL_FUNCTION(0x2, "sif"), /* CLK */
211 BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* DAT1 */
212 BERLIN_PINCTRL_GROUP("SCRD0_DIO", 0xc, 0x3, 0x12,
213 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO19 */
214 BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* DIO */
215 BERLIN_PINCTRL_FUNCTION(0x2, "sif"), /* DEN */
216 BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* DAT2 */
217 BERLIN_PINCTRL_GROUP("SCRD0_CRD_PRES", 0xc, 0x3, 0x15,
218 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO20 */
219 BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* crd pres */
220 BERLIN_PINCTRL_FUNCTION(0x1, "sd1a")), /* DAT3 */
221 BERLIN_PINCTRL_GROUP("SPI1_SS0n", 0xc, 0x3, 0x18,
222 BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS0n */
223 BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO37 */
224 BERLIN_PINCTRL_FUNCTION(0x2, "sts2")), /* CLK */
225 BERLIN_PINCTRL_GROUP("SPI1_SS1n", 0xc, 0x3, 0x1b,
226 BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS1n */
227 BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO38 */
228 BERLIN_PINCTRL_FUNCTION(0x2, "sts2"), /* SOP */
229 BERLIN_PINCTRL_FUNCTION(0x4, "pwm1")),
230 BERLIN_PINCTRL_GROUP("SPI1_SS2n", 0x10, 0x3, 0x00,
231 BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS2n */
232 BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO39 */
233 BERLIN_PINCTRL_FUNCTION(0x2, "sts2"), /* SD */
234 BERLIN_PINCTRL_FUNCTION(0x4, "pwm0")),
235 BERLIN_PINCTRL_GROUP("SPI1_SS3n", 0x10, 0x3, 0x03,
236 BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS3n */
237 BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO40 */
238 BERLIN_PINCTRL_FUNCTION(0x2, "sts2")), /* VALD */
239 BERLIN_PINCTRL_GROUP("SPI1_SCLK", 0x10, 0x3, 0x06,
240 BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SCLK */
241 BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO41 */
242 BERLIN_PINCTRL_FUNCTION(0x2, "sts3")), /* CLK */
243 BERLIN_PINCTRL_GROUP("SPI1_SDO", 0x10, 0x3, 0x09,
244 BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SDO */
245 BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO42 */
246 BERLIN_PINCTRL_FUNCTION(0x2, "sts3")), /* SOP */
247 BERLIN_PINCTRL_GROUP("SPI1_SDI", 0x10, 0x3, 0x0c,
248 BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SDI */
249 BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO43 */
250 BERLIN_PINCTRL_FUNCTION(0x2, "sts3")), /* SD */
251 BERLIN_PINCTRL_GROUP("USB0_DRV_VBUS", 0x10, 0x3, 0x0f,
252 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO44 */
253 BERLIN_PINCTRL_FUNCTION(0x1, "usb0"), /* VBUS */
254 BERLIN_PINCTRL_FUNCTION(0x2, "sts3")), /* VALD */
255 BERLIN_PINCTRL_GROUP("TW0_SCL", 0x10, 0x3, 0x12,
256 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO45 */
257 BERLIN_PINCTRL_FUNCTION(0x1, "tw0")), /* SCL */
258 BERLIN_PINCTRL_GROUP("TW0_SDA", 0x10, 0x3, 0x15,
259 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO46 */
260 BERLIN_PINCTRL_FUNCTION(0x1, "tw0")), /* SDA */
261};
262
263static const struct berlin_desc_group berlin4ct_avio_pinctrl_groups[] = {
264 BERLIN_PINCTRL_GROUP("TX_EDDC_SCL", 0x0, 0x3, 0x00,
265 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO0 */
266 BERLIN_PINCTRL_FUNCTION(0x1, "tx_eddc"), /* SCL */
267 BERLIN_PINCTRL_FUNCTION(0x2, "tw1")), /* SCL */
268 BERLIN_PINCTRL_GROUP("TX_EDDC_SDA", 0x0, 0x3, 0x03,
269 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO1 */
270 BERLIN_PINCTRL_FUNCTION(0x1, "tx_eddc"), /* SDA */
271 BERLIN_PINCTRL_FUNCTION(0x2, "tw1")), /* SDA */
272 BERLIN_PINCTRL_GROUP("I2S1_LRCKO", 0x0, 0x3, 0x06,
273 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO2 */
274 BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* LRCKO */
275 BERLIN_PINCTRL_FUNCTION(0x3, "sts6"), /* CLK */
276 BERLIN_PINCTRL_FUNCTION(0x4, "adac"), /* DBG0 */
277 BERLIN_PINCTRL_FUNCTION(0x6, "sd1b"), /* CLK */
278 BERLIN_PINCTRL_FUNCTION(0x7, "avio")), /* DBG0 */
279 BERLIN_PINCTRL_GROUP("I2S1_BCLKO", 0x0, 0x3, 0x09,
280 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO3 */
281 BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* BCLKO */
282 BERLIN_PINCTRL_FUNCTION(0x3, "sts6"), /* SOP */
283 BERLIN_PINCTRL_FUNCTION(0x4, "adac"), /* DBG1 */
284 BERLIN_PINCTRL_FUNCTION(0x6, "sd1b"), /* CMD */
285 BERLIN_PINCTRL_FUNCTION(0x7, "avio")), /* DBG1 */
286 BERLIN_PINCTRL_GROUP("I2S1_DO", 0x0, 0x3, 0x0c,
287 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO4 */
288 BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* DO */
289 BERLIN_PINCTRL_FUNCTION(0x3, "sts6"), /* SD */
290 BERLIN_PINCTRL_FUNCTION(0x4, "adac"), /* DBG2 */
291 BERLIN_PINCTRL_FUNCTION(0x6, "sd1b"), /* DAT0 */
292 BERLIN_PINCTRL_FUNCTION(0x7, "avio")), /* DBG2 */
293 BERLIN_PINCTRL_GROUP("I2S1_MCLK", 0x0, 0x3, 0x0f,
294 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO5 */
295 BERLIN_PINCTRL_FUNCTION(0x1, "i2s1"), /* MCLK */
296 BERLIN_PINCTRL_FUNCTION(0x3, "sts6"), /* VALD */
297 BERLIN_PINCTRL_FUNCTION(0x4, "adac_test"), /* MCLK */
298 BERLIN_PINCTRL_FUNCTION(0x6, "sd1b"), /* DAT1 */
299 BERLIN_PINCTRL_FUNCTION(0x7, "avio")), /* DBG3 */
300 BERLIN_PINCTRL_GROUP("SPDIFO", 0x0, 0x3, 0x12,
301 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO6 */
302 BERLIN_PINCTRL_FUNCTION(0x1, "spdifo"),
303 BERLIN_PINCTRL_FUNCTION(0x2, "avpll"), /* CLKO */
304 BERLIN_PINCTRL_FUNCTION(0x4, "adac")), /* DBG3 */
305 BERLIN_PINCTRL_GROUP("I2S2_MCLK", 0x0, 0x3, 0x15,
306 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO7 */
307 BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* MCLK */
308 BERLIN_PINCTRL_FUNCTION(0x4, "hdmi"), /* FBCLK */
309 BERLIN_PINCTRL_FUNCTION(0x5, "pdm")), /* CLKO */
310 BERLIN_PINCTRL_GROUP("I2S2_LRCKI", 0x0, 0x3, 0x18,
311 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO8 */
312 BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* LRCKI */
313 BERLIN_PINCTRL_FUNCTION(0x2, "pwm0"),
314 BERLIN_PINCTRL_FUNCTION(0x3, "sts7"), /* CLK */
315 BERLIN_PINCTRL_FUNCTION(0x4, "adac_test"), /* LRCK */
316 BERLIN_PINCTRL_FUNCTION(0x6, "sd1b")), /* DAT2 */
317 BERLIN_PINCTRL_GROUP("I2S2_BCLKI", 0x0, 0x3, 0x1b,
318 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO9 */
319 BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* BCLKI */
320 BERLIN_PINCTRL_FUNCTION(0x2, "pwm1"),
321 BERLIN_PINCTRL_FUNCTION(0x3, "sts7"), /* SOP */
322 BERLIN_PINCTRL_FUNCTION(0x4, "adac_test"), /* BCLK */
323 BERLIN_PINCTRL_FUNCTION(0x6, "sd1b")), /* DAT3 */
324 BERLIN_PINCTRL_GROUP("I2S2_DI0", 0x4, 0x3, 0x00,
325 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO10 */
326 BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI0 */
327 BERLIN_PINCTRL_FUNCTION(0x2, "pwm2"),
328 BERLIN_PINCTRL_FUNCTION(0x3, "sts7"), /* SD */
329 BERLIN_PINCTRL_FUNCTION(0x4, "adac_test"), /* SDIN */
330 BERLIN_PINCTRL_FUNCTION(0x5, "pdm"), /* DI0 */
331 BERLIN_PINCTRL_FUNCTION(0x6, "sd1b")), /* CDn */
332 BERLIN_PINCTRL_GROUP("I2S2_DI1", 0x4, 0x3, 0x03,
333 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* AVIO GPIO11 */
334 BERLIN_PINCTRL_FUNCTION(0x1, "i2s2"), /* DI1 */
335 BERLIN_PINCTRL_FUNCTION(0x2, "pwm3"),
336 BERLIN_PINCTRL_FUNCTION(0x3, "sts7"), /* VALD */
337 BERLIN_PINCTRL_FUNCTION(0x4, "adac_test"), /* PWMCLK */
338 BERLIN_PINCTRL_FUNCTION(0x5, "pdm"), /* DI1 */
339 BERLIN_PINCTRL_FUNCTION(0x6, "sd1b")), /* WP */
340};
341
342static const struct berlin_desc_group berlin4ct_sysmgr_pinctrl_groups[] = {
343 BERLIN_PINCTRL_GROUP("SM_TW2_SCL", 0x0, 0x3, 0x00,
344 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO19 */
345 BERLIN_PINCTRL_FUNCTION(0x1, "tw2")), /* SCL */
346 BERLIN_PINCTRL_GROUP("SM_TW2_SDA", 0x0, 0x3, 0x03,
347 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO20 */
348 BERLIN_PINCTRL_FUNCTION(0x1, "tw2")), /* SDA */
349 BERLIN_PINCTRL_GROUP("SM_TW3_SCL", 0x0, 0x3, 0x06,
350 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO21 */
351 BERLIN_PINCTRL_FUNCTION(0x1, "tw3")), /* SCL */
352 BERLIN_PINCTRL_GROUP("SM_TW3_SDA", 0x0, 0x3, 0x09,
353 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO22 */
354 BERLIN_PINCTRL_FUNCTION(0x1, "tw3")), /* SDA */
355 BERLIN_PINCTRL_GROUP("SM_TMS", 0x0, 0x3, 0x0c,
356 BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TMS */
357 BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* SM GPIO0 */
358 BERLIN_PINCTRL_FUNCTION(0x2, "pwm0")),
359 BERLIN_PINCTRL_GROUP("SM_TDI", 0x0, 0x3, 0x0f,
360 BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TDI */
361 BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* SM GPIO1 */
362 BERLIN_PINCTRL_FUNCTION(0x2, "pwm1")),
363 BERLIN_PINCTRL_GROUP("SM_TDO", 0x0, 0x3, 0x12,
364 BERLIN_PINCTRL_FUNCTION(0x0, "jtag"), /* TDO */
365 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO2 */
366 BERLIN_PINCTRL_GROUP("SM_URT0_TXD", 0x0, 0x3, 0x15,
367 BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* TXD */
368 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO3 */
369 BERLIN_PINCTRL_GROUP("SM_URT0_RXD", 0x0, 0x3, 0x18,
370 BERLIN_PINCTRL_FUNCTION(0x0, "uart0"), /* RXD */
371 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO4 */
372 BERLIN_PINCTRL_GROUP("SM_URT1_TXD", 0x0, 0x3, 0x1b,
373 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO5 */
374 BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* TXD */
375 BERLIN_PINCTRL_FUNCTION(0x2, "eth1"), /* RXCLK */
376 BERLIN_PINCTRL_FUNCTION(0x3, "pwm2"),
377 BERLIN_PINCTRL_FUNCTION(0x4, "timer0"),
378 BERLIN_PINCTRL_FUNCTION(0x5, "clk_25m")),
379 BERLIN_PINCTRL_GROUP("SM_URT1_RXD", 0x4, 0x3, 0x00,
380 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO6 */
381 BERLIN_PINCTRL_FUNCTION(0x1, "uart1"), /* RXD */
382 BERLIN_PINCTRL_FUNCTION(0x3, "pwm3"),
383 BERLIN_PINCTRL_FUNCTION(0x4, "timer1")),
384 BERLIN_PINCTRL_GROUP("SM_SPI2_SS0n", 0x4, 0x3, 0x03,
385 BERLIN_PINCTRL_FUNCTION(0x0, "spi2"), /* SS0 n*/
386 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO7 */
387 BERLIN_PINCTRL_GROUP("SM_SPI2_SS1n", 0x4, 0x3, 0x06,
388 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO8 */
389 BERLIN_PINCTRL_FUNCTION(0x1, "spi2")), /* SS1n */
390 BERLIN_PINCTRL_GROUP("SM_SPI2_SS2n", 0x4, 0x3, 0x09,
391 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO9 */
392 BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS2n */
393 BERLIN_PINCTRL_FUNCTION(0x2, "eth1"), /* MDC */
394 BERLIN_PINCTRL_FUNCTION(0x3, "pwm0"),
395 BERLIN_PINCTRL_FUNCTION(0x4, "timer0"),
396 BERLIN_PINCTRL_FUNCTION(0x5, "clk_25m")),
397 BERLIN_PINCTRL_GROUP("SM_SPI2_SS3n", 0x4, 0x3, 0x0c,
398 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO10 */
399 BERLIN_PINCTRL_FUNCTION(0x1, "spi2"), /* SS3n */
400 BERLIN_PINCTRL_FUNCTION(0x2, "eth1"), /* MDIO */
401 BERLIN_PINCTRL_FUNCTION(0x3, "pwm1"),
402 BERLIN_PINCTRL_FUNCTION(0x4, "timer1")),
403 BERLIN_PINCTRL_GROUP("SM_SPI2_SDO", 0x4, 0x3, 0x0f,
404 BERLIN_PINCTRL_FUNCTION(0x0, "spi2"), /* SDO */
405 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO11 */
406 BERLIN_PINCTRL_GROUP("SM_SPI2_SDI", 0x4, 0x3, 0x12,
407 BERLIN_PINCTRL_FUNCTION(0x0, "spi2"), /* SDI */
408 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO12 */
409 BERLIN_PINCTRL_GROUP("SM_SPI2_SCLK", 0x4, 0x3, 0x15,
410 BERLIN_PINCTRL_FUNCTION(0x0, "spi2"), /* SCLK */
411 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")), /* SM GPIO13 */
412 BERLIN_PINCTRL_GROUP("SM_FE_LED0", 0x4, 0x3, 0x18,
413 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO14 */
414 BERLIN_PINCTRL_FUNCTION(0x2, "led")), /* LED0 */
415 BERLIN_PINCTRL_GROUP("SM_FE_LED1", 0x4, 0x3, 0x1b,
416 BERLIN_PINCTRL_FUNCTION(0x0, "pwr"),
417 BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* SM GPIO 15 */
418 BERLIN_PINCTRL_FUNCTION(0x2, "led")), /* LED1 */
419 BERLIN_PINCTRL_GROUP("SM_FE_LED2", 0x8, 0x3, 0x00,
420 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO16 */
421 BERLIN_PINCTRL_FUNCTION(0x2, "led")), /* LED2 */
422 BERLIN_PINCTRL_GROUP("SM_HDMI_HPD", 0x8, 0x3, 0x03,
423 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO17 */
424 BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), /* HPD */
425 BERLIN_PINCTRL_GROUP("SM_HDMI_CEC", 0x8, 0x3, 0x06,
426 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* SM GPIO18 */
427 BERLIN_PINCTRL_FUNCTION(0x1, "hdmi")), /* CEC */
428};
429
430static const struct berlin_pinctrl_desc berlin4ct_soc_pinctrl_data = {
431 .groups = berlin4ct_soc_pinctrl_groups,
432 .ngroups = ARRAY_SIZE(berlin4ct_soc_pinctrl_groups),
433};
434
435static const struct berlin_pinctrl_desc berlin4ct_avio_pinctrl_data = {
436 .groups = berlin4ct_avio_pinctrl_groups,
437 .ngroups = ARRAY_SIZE(berlin4ct_avio_pinctrl_groups),
438};
439
440static const struct berlin_pinctrl_desc berlin4ct_sysmgr_pinctrl_data = {
441 .groups = berlin4ct_sysmgr_pinctrl_groups,
442 .ngroups = ARRAY_SIZE(berlin4ct_sysmgr_pinctrl_groups),
443};
444
445static const struct of_device_id berlin4ct_pinctrl_match[] = {
446 {
447 .compatible = "marvell,berlin4ct-soc-pinctrl",
448 .data = &berlin4ct_soc_pinctrl_data,
449 },
450 {
451 .compatible = "marvell,berlin4ct-avio-pinctrl",
452 .data = &berlin4ct_avio_pinctrl_data,
453 },
454 {
455 .compatible = "marvell,berlin4ct-system-pinctrl",
456 .data = &berlin4ct_sysmgr_pinctrl_data,
457 },
458 {}
459};
460MODULE_DEVICE_TABLE(of, berlin4ct_pinctrl_match);
461
462static int berlin4ct_pinctrl_probe(struct platform_device *pdev)
463{
464 const struct of_device_id *match =
465 of_match_device(berlin4ct_pinctrl_match, &pdev->dev);
466 struct regmap_config *rmconfig;
467 struct regmap *regmap;
468 struct resource *res;
469 void __iomem *base;
470
471 rmconfig = devm_kzalloc(&pdev->dev, sizeof(*rmconfig), GFP_KERNEL);
472 if (!rmconfig)
473 return -ENOMEM;
474
475 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
476 base = devm_ioremap_resource(&pdev->dev, res);
477 if (IS_ERR(base))
478 return PTR_ERR(base);
479
480 rmconfig->reg_bits = 32,
481 rmconfig->val_bits = 32,
482 rmconfig->reg_stride = 4,
483 rmconfig->max_register = resource_size(res);
484
485 regmap = devm_regmap_init_mmio(&pdev->dev, base, rmconfig);
486 if (IS_ERR(regmap))
487 return PTR_ERR(regmap);
488
489 return berlin_pinctrl_probe_regmap(pdev, match->data, regmap);
490}
491
492static struct platform_driver berlin4ct_pinctrl_driver = {
493 .probe = berlin4ct_pinctrl_probe,
494 .driver = {
495 .name = "berlin4ct-pinctrl",
496 .of_match_table = berlin4ct_pinctrl_match,
497 },
498};
499module_platform_driver(berlin4ct_pinctrl_driver);
500
501MODULE_AUTHOR("Jisheng Zhang <jszhang@marvell.com>");
502MODULE_DESCRIPTION("Marvell berlin4ct pinctrl driver");
503MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c
index f49580617055..46f2b4818da3 100644
--- a/drivers/pinctrl/berlin/berlin.c
+++ b/drivers/pinctrl/berlin/berlin.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 2014 Marvell Technology Group Ltd. 4 * Copyright (C) 2014 Marvell Technology Group Ltd.
5 * 5 *
6 * Antoine Ténart <antoine.tenart@free-electrons.com> 6 * Antoine Ténart <antoine.tenart@free-electrons.com>
7 * 7 *
8 * This file is licensed under the terms of the GNU General Public 8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any 9 * License version 2. This program is licensed "as is" without any
@@ -292,20 +292,14 @@ static struct pinctrl_desc berlin_pctrl_desc = {
292 .owner = THIS_MODULE, 292 .owner = THIS_MODULE,
293}; 293};
294 294
295int berlin_pinctrl_probe(struct platform_device *pdev, 295int berlin_pinctrl_probe_regmap(struct platform_device *pdev,
296 const struct berlin_pinctrl_desc *desc) 296 const struct berlin_pinctrl_desc *desc,
297 struct regmap *regmap)
297{ 298{
298 struct device *dev = &pdev->dev; 299 struct device *dev = &pdev->dev;
299 struct device_node *parent_np = of_get_parent(dev->of_node);
300 struct berlin_pinctrl *pctrl; 300 struct berlin_pinctrl *pctrl;
301 struct regmap *regmap;
302 int ret; 301 int ret;
303 302
304 regmap = syscon_node_to_regmap(parent_np);
305 of_node_put(parent_np);
306 if (IS_ERR(regmap))
307 return PTR_ERR(regmap);
308
309 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); 303 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
310 if (!pctrl) 304 if (!pctrl)
311 return -ENOMEM; 305 return -ENOMEM;
@@ -330,3 +324,17 @@ int berlin_pinctrl_probe(struct platform_device *pdev,
330 324
331 return 0; 325 return 0;
332} 326}
327
328int berlin_pinctrl_probe(struct platform_device *pdev,
329 const struct berlin_pinctrl_desc *desc)
330{
331 struct device *dev = &pdev->dev;
332 struct device_node *parent_np = of_get_parent(dev->of_node);
333 struct regmap *regmap = syscon_node_to_regmap(parent_np);
334
335 of_node_put(parent_np);
336 if (IS_ERR(regmap))
337 return PTR_ERR(regmap);
338
339 return berlin_pinctrl_probe_regmap(pdev, desc, regmap);
340}
diff --git a/drivers/pinctrl/berlin/berlin.h b/drivers/pinctrl/berlin/berlin.h
index e1aa84145194..e9b30f95b03e 100644
--- a/drivers/pinctrl/berlin/berlin.h
+++ b/drivers/pinctrl/berlin/berlin.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 2014 Marvell Technology Group Ltd. 4 * Copyright (C) 2014 Marvell Technology Group Ltd.
5 * 5 *
6 * Antoine Ténart <antoine.tenart@free-electrons.com> 6 * Antoine Ténart <antoine.tenart@free-electrons.com>
7 * 7 *
8 * This file is licensed under the terms of the GNU General Public 8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any 9 * License version 2. This program is licensed "as is" without any
@@ -58,4 +58,8 @@ struct berlin_pinctrl_function {
58int berlin_pinctrl_probe(struct platform_device *pdev, 58int berlin_pinctrl_probe(struct platform_device *pdev,
59 const struct berlin_pinctrl_desc *desc); 59 const struct berlin_pinctrl_desc *desc);
60 60
61int berlin_pinctrl_probe_regmap(struct platform_device *pdev,
62 const struct berlin_pinctrl_desc *desc,
63 struct regmap *regmap);
64
61#endif /* __PINCTRL_BERLIN_H */ 65#endif /* __PINCTRL_BERLIN_H */
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 9638a00c67c2..2686a4450dfc 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -1240,6 +1240,38 @@ int pinctrl_force_default(struct pinctrl_dev *pctldev)
1240} 1240}
1241EXPORT_SYMBOL_GPL(pinctrl_force_default); 1241EXPORT_SYMBOL_GPL(pinctrl_force_default);
1242 1242
1243/**
1244 * pinctrl_init_done() - tell pinctrl probe is done
1245 *
1246 * We'll use this time to switch the pins from "init" to "default" unless the
1247 * driver selected some other state.
1248 *
1249 * @dev: device to that's done probing
1250 */
1251int pinctrl_init_done(struct device *dev)
1252{
1253 struct dev_pin_info *pins = dev->pins;
1254 int ret;
1255
1256 if (!pins)
1257 return 0;
1258
1259 if (IS_ERR(pins->init_state))
1260 return 0; /* No such state */
1261
1262 if (pins->p->state != pins->init_state)
1263 return 0; /* Not at init anyway */
1264
1265 if (IS_ERR(pins->default_state))
1266 return 0; /* No default state */
1267
1268 ret = pinctrl_select_state(pins->p, pins->default_state);
1269 if (ret)
1270 dev_err(dev, "failed to activate default pinctrl state\n");
1271
1272 return ret;
1273}
1274
1243#ifdef CONFIG_PM 1275#ifdef CONFIG_PM
1244 1276
1245/** 1277/**
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index d7b98ba36825..a5bb93987378 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -18,6 +18,7 @@
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/of.h> 19#include <linux/of.h>
20#include <linux/of_device.h> 20#include <linux/of_device.h>
21#include <linux/of_address.h>
21#include <linux/pinctrl/machine.h> 22#include <linux/pinctrl/machine.h>
22#include <linux/pinctrl/pinconf.h> 23#include <linux/pinctrl/pinconf.h>
23#include <linux/pinctrl/pinctrl.h> 24#include <linux/pinctrl/pinctrl.h>
@@ -39,6 +40,7 @@ struct imx_pinctrl {
39 struct device *dev; 40 struct device *dev;
40 struct pinctrl_dev *pctl; 41 struct pinctrl_dev *pctl;
41 void __iomem *base; 42 void __iomem *base;
43 void __iomem *input_sel_base;
42 const struct imx_pinctrl_soc_info *info; 44 const struct imx_pinctrl_soc_info *info;
43}; 45};
44 46
@@ -254,7 +256,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
254 * Regular select input register can never be at offset 256 * Regular select input register can never be at offset
255 * 0, and we only print register value for regular case. 257 * 0, and we only print register value for regular case.
256 */ 258 */
257 writel(pin->input_val, ipctl->base + pin->input_reg); 259 if (ipctl->input_sel_base)
260 writel(pin->input_val, ipctl->input_sel_base +
261 pin->input_reg);
262 else
263 writel(pin->input_val, ipctl->base +
264 pin->input_reg);
258 dev_dbg(ipctl->dev, 265 dev_dbg(ipctl->dev,
259 "==>select_input: offset 0x%x val 0x%x\n", 266 "==>select_input: offset 0x%x val 0x%x\n",
260 pin->input_reg, pin->input_val); 267 pin->input_reg, pin->input_val);
@@ -542,6 +549,9 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
542 struct imx_pin_reg *pin_reg; 549 struct imx_pin_reg *pin_reg;
543 struct imx_pin *pin = &grp->pins[i]; 550 struct imx_pin *pin = &grp->pins[i];
544 551
552 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
553 mux_reg = -1;
554
545 if (info->flags & SHARE_MUX_CONF_REG) { 555 if (info->flags & SHARE_MUX_CONF_REG) {
546 conf_reg = mux_reg; 556 conf_reg = mux_reg;
547 } else { 557 } else {
@@ -550,7 +560,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
550 conf_reg = -1; 560 conf_reg = -1;
551 } 561 }
552 562
553 pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4; 563 pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
554 pin_reg = &info->pin_regs[pin_id]; 564 pin_reg = &info->pin_regs[pin_id];
555 pin->pin = pin_id; 565 pin->pin = pin_id;
556 grp->pin_ids[i] = pin_id; 566 grp->pin_ids[i] = pin_id;
@@ -580,7 +590,6 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
580 struct device_node *child; 590 struct device_node *child;
581 struct imx_pmx_func *func; 591 struct imx_pmx_func *func;
582 struct imx_pin_group *grp; 592 struct imx_pin_group *grp;
583 static u32 grp_index;
584 u32 i = 0; 593 u32 i = 0;
585 594
586 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); 595 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
@@ -599,7 +608,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
599 608
600 for_each_child_of_node(np, child) { 609 for_each_child_of_node(np, child) {
601 func->groups[i] = child->name; 610 func->groups[i] = child->name;
602 grp = &info->groups[grp_index++]; 611 grp = &info->groups[info->group_index++];
603 imx_pinctrl_parse_groups(child, grp, info, i++); 612 imx_pinctrl_parse_groups(child, grp, info, i++);
604 } 613 }
605 614
@@ -683,6 +692,8 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev,
683int imx_pinctrl_probe(struct platform_device *pdev, 692int imx_pinctrl_probe(struct platform_device *pdev,
684 struct imx_pinctrl_soc_info *info) 693 struct imx_pinctrl_soc_info *info)
685{ 694{
695 struct device_node *dev_np = pdev->dev.of_node;
696 struct device_node *np;
686 struct imx_pinctrl *ipctl; 697 struct imx_pinctrl *ipctl;
687 struct resource *res; 698 struct resource *res;
688 int ret, i; 699 int ret, i;
@@ -713,6 +724,23 @@ int imx_pinctrl_probe(struct platform_device *pdev,
713 if (IS_ERR(ipctl->base)) 724 if (IS_ERR(ipctl->base))
714 return PTR_ERR(ipctl->base); 725 return PTR_ERR(ipctl->base);
715 726
727 if (of_property_read_bool(dev_np, "fsl,input-sel")) {
728 np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
729 if (np) {
730 ipctl->input_sel_base = of_iomap(np, 0);
731 if (IS_ERR(ipctl->input_sel_base)) {
732 of_node_put(np);
733 dev_err(&pdev->dev,
734 "iomuxc input select base address not found\n");
735 return PTR_ERR(ipctl->input_sel_base);
736 }
737 } else {
738 dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
739 return -EINVAL;
740 }
741 of_node_put(np);
742 }
743
716 imx_pinctrl_desc.name = dev_name(&pdev->dev); 744 imx_pinctrl_desc.name = dev_name(&pdev->dev);
717 imx_pinctrl_desc.pins = info->pins; 745 imx_pinctrl_desc.pins = info->pins;
718 imx_pinctrl_desc.npins = info->npins; 746 imx_pinctrl_desc.npins = info->npins;
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
index 49e55d39f7c8..2a592f657c18 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -78,12 +78,14 @@ struct imx_pinctrl_soc_info {
78 struct imx_pin_reg *pin_regs; 78 struct imx_pin_reg *pin_regs;
79 struct imx_pin_group *groups; 79 struct imx_pin_group *groups;
80 unsigned int ngroups; 80 unsigned int ngroups;
81 unsigned int group_index;
81 struct imx_pmx_func *functions; 82 struct imx_pmx_func *functions;
82 unsigned int nfunctions; 83 unsigned int nfunctions;
83 unsigned int flags; 84 unsigned int flags;
84}; 85};
85 86
86#define SHARE_MUX_CONF_REG 0x1 87#define SHARE_MUX_CONF_REG 0x1
88#define ZERO_OFFSET_VALID 0x2
87 89
88#define NO_MUX 0x0 90#define NO_MUX 0x0
89#define NO_PAD 0x0 91#define NO_PAD 0x0
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c b/drivers/pinctrl/freescale/pinctrl-imx7d.c
index 1fa7530530dd..16dc925117de 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7d.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c
@@ -174,6 +174,17 @@ enum imx7d_pads {
174 MX7D_PAD_ENET1_COL = 154, 174 MX7D_PAD_ENET1_COL = 154,
175}; 175};
176 176
177enum imx7d_lpsr_pads {
178 MX7D_PAD_GPIO1_IO00 = 0,
179 MX7D_PAD_GPIO1_IO01 = 1,
180 MX7D_PAD_GPIO1_IO02 = 2,
181 MX7D_PAD_GPIO1_IO03 = 3,
182 MX7D_PAD_GPIO1_IO04 = 4,
183 MX7D_PAD_GPIO1_IO05 = 5,
184 MX7D_PAD_GPIO1_IO06 = 6,
185 MX7D_PAD_GPIO1_IO07 = 7,
186};
187
177/* Pad names for the pinmux subsystem */ 188/* Pad names for the pinmux subsystem */
178static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = { 189static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = {
179 IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0), 190 IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0),
@@ -333,13 +344,32 @@ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = {
333 IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL), 344 IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL),
334}; 345};
335 346
347/* Pad names for the pinmux subsystem */
348static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = {
349 IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00),
350 IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01),
351 IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02),
352 IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03),
353 IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04),
354 IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05),
355 IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06),
356 IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07),
357};
358
336static struct imx_pinctrl_soc_info imx7d_pinctrl_info = { 359static struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
337 .pins = imx7d_pinctrl_pads, 360 .pins = imx7d_pinctrl_pads,
338 .npins = ARRAY_SIZE(imx7d_pinctrl_pads), 361 .npins = ARRAY_SIZE(imx7d_pinctrl_pads),
339}; 362};
340 363
364static struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = {
365 .pins = imx7d_lpsr_pinctrl_pads,
366 .npins = ARRAY_SIZE(imx7d_lpsr_pinctrl_pads),
367 .flags = ZERO_OFFSET_VALID,
368};
369
341static struct of_device_id imx7d_pinctrl_of_match[] = { 370static struct of_device_id imx7d_pinctrl_of_match[] = {
342 { .compatible = "fsl,imx7d-iomuxc", .data = &imx7d_pinctrl_info, }, 371 { .compatible = "fsl,imx7d-iomuxc", .data = &imx7d_pinctrl_info, },
372 { .compatible = "fsl,imx7d-iomuxc-lpsr", .data = &imx7d_lpsr_pinctrl_info },
343 { /* sentinel */ } 373 { /* sentinel */ }
344}; 374};
345 375
diff --git a/drivers/pinctrl/freescale/pinctrl-mxs.c b/drivers/pinctrl/freescale/pinctrl-mxs.c
index f64eecb24755..6bbda6b4ab50 100644
--- a/drivers/pinctrl/freescale/pinctrl-mxs.c
+++ b/drivers/pinctrl/freescale/pinctrl-mxs.c
@@ -474,7 +474,7 @@ static int mxs_pinctrl_probe_dt(struct platform_device *pdev,
474 f->name = fn = child->name; 474 f->name = fn = child->name;
475 } 475 }
476 f->ngroups++; 476 f->ngroups++;
477 }; 477 }
478 478
479 /* Get groups for each function */ 479 /* Get groups for each function */
480 idxf = 0; 480 idxf = 0;
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index fe5e07db0a95..4d2efad6553c 100644
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -34,6 +34,14 @@ config PINCTRL_INTEL
34 select GPIOLIB 34 select GPIOLIB
35 select GPIOLIB_IRQCHIP 35 select GPIOLIB_IRQCHIP
36 36
37config PINCTRL_BROXTON
38 tristate "Intel Broxton pinctrl and GPIO driver"
39 depends on ACPI
40 select PINCTRL_INTEL
41 help
42 Broxton pinctrl driver provides an interface that allows
43 configuring of SoC pins and using them as GPIOs.
44
37config PINCTRL_SUNRISEPOINT 45config PINCTRL_SUNRISEPOINT
38 tristate "Intel Sunrisepoint pinctrl and GPIO driver" 46 tristate "Intel Sunrisepoint pinctrl and GPIO driver"
39 depends on ACPI 47 depends on ACPI
diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile
index fee756e1255b..03bc68e3546c 100644
--- a/drivers/pinctrl/intel/Makefile
+++ b/drivers/pinctrl/intel/Makefile
@@ -3,4 +3,5 @@
3obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o 3obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
4obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o 4obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o
5obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o 5obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o
6obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o
6obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o 7obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o
diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c
index f79ea430f651..b59ce75b1947 100644
--- a/drivers/pinctrl/intel/pinctrl-baytrail.c
+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c
@@ -696,6 +696,7 @@ static int byt_gpio_resume(struct device *dev)
696} 696}
697#endif 697#endif
698 698
699#ifdef CONFIG_PM
699static int byt_gpio_runtime_suspend(struct device *dev) 700static int byt_gpio_runtime_suspend(struct device *dev)
700{ 701{
701 return 0; 702 return 0;
@@ -705,6 +706,7 @@ static int byt_gpio_runtime_resume(struct device *dev)
705{ 706{
706 return 0; 707 return 0;
707} 708}
709#endif
708 710
709static const struct dev_pm_ops byt_gpio_pm_ops = { 711static const struct dev_pm_ops byt_gpio_pm_ops = {
710 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume) 712 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
diff --git a/drivers/pinctrl/intel/pinctrl-broxton.c b/drivers/pinctrl/intel/pinctrl-broxton.c
new file mode 100644
index 000000000000..e42d5d4183f5
--- /dev/null
+++ b/drivers/pinctrl/intel/pinctrl-broxton.c
@@ -0,0 +1,1065 @@
1/*
2 * Intel Broxton SoC pinctrl/GPIO driver
3 *
4 * Copyright (C) 2015, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/acpi.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/pm.h>
16#include <linux/pinctrl/pinctrl.h>
17
18#include "pinctrl-intel.h"
19
20#define BXT_PAD_OWN 0x020
21#define BXT_HOSTSW_OWN 0x080
22#define BXT_PADCFGLOCK 0x090
23#define BXT_GPI_IE 0x110
24
25#define BXT_COMMUNITY(s, e) \
26 { \
27 .padown_offset = BXT_PAD_OWN, \
28 .padcfglock_offset = BXT_PADCFGLOCK, \
29 .hostown_offset = BXT_HOSTSW_OWN, \
30 .ie_offset = BXT_GPI_IE, \
31 .pin_base = (s), \
32 .npins = ((e) - (s) + 1), \
33 }
34
35/* BXT */
36static const struct pinctrl_pin_desc bxt_north_pins[] = {
37 PINCTRL_PIN(0, "GPIO_0"),
38 PINCTRL_PIN(1, "GPIO_1"),
39 PINCTRL_PIN(2, "GPIO_2"),
40 PINCTRL_PIN(3, "GPIO_3"),
41 PINCTRL_PIN(4, "GPIO_4"),
42 PINCTRL_PIN(5, "GPIO_5"),
43 PINCTRL_PIN(6, "GPIO_6"),
44 PINCTRL_PIN(7, "GPIO_7"),
45 PINCTRL_PIN(8, "GPIO_8"),
46 PINCTRL_PIN(9, "GPIO_9"),
47 PINCTRL_PIN(10, "GPIO_10"),
48 PINCTRL_PIN(11, "GPIO_11"),
49 PINCTRL_PIN(12, "GPIO_12"),
50 PINCTRL_PIN(13, "GPIO_13"),
51 PINCTRL_PIN(14, "GPIO_14"),
52 PINCTRL_PIN(15, "GPIO_15"),
53 PINCTRL_PIN(16, "GPIO_16"),
54 PINCTRL_PIN(17, "GPIO_17"),
55 PINCTRL_PIN(18, "GPIO_18"),
56 PINCTRL_PIN(19, "GPIO_19"),
57 PINCTRL_PIN(20, "GPIO_20"),
58 PINCTRL_PIN(21, "GPIO_21"),
59 PINCTRL_PIN(22, "GPIO_22"),
60 PINCTRL_PIN(23, "GPIO_23"),
61 PINCTRL_PIN(24, "GPIO_24"),
62 PINCTRL_PIN(25, "GPIO_25"),
63 PINCTRL_PIN(26, "GPIO_26"),
64 PINCTRL_PIN(27, "GPIO_27"),
65 PINCTRL_PIN(28, "GPIO_28"),
66 PINCTRL_PIN(29, "GPIO_29"),
67 PINCTRL_PIN(30, "GPIO_30"),
68 PINCTRL_PIN(31, "GPIO_31"),
69 PINCTRL_PIN(32, "GPIO_32"),
70 PINCTRL_PIN(33, "GPIO_33"),
71 PINCTRL_PIN(34, "PWM0"),
72 PINCTRL_PIN(35, "PWM1"),
73 PINCTRL_PIN(36, "PWM2"),
74 PINCTRL_PIN(37, "PWM3"),
75 PINCTRL_PIN(38, "LPSS_UART0_RXD"),
76 PINCTRL_PIN(39, "LPSS_UART0_TXD"),
77 PINCTRL_PIN(40, "LPSS_UART0_RTS_B"),
78 PINCTRL_PIN(41, "LPSS_UART0_CTS_B"),
79 PINCTRL_PIN(42, "LPSS_UART1_RXD"),
80 PINCTRL_PIN(43, "LPSS_UART1_TXD"),
81 PINCTRL_PIN(44, "LPSS_UART1_RTS_B"),
82 PINCTRL_PIN(45, "LPSS_UART1_CTS_B"),
83 PINCTRL_PIN(46, "LPSS_UART2_RXD"),
84 PINCTRL_PIN(47, "LPSS_UART2_TXD"),
85 PINCTRL_PIN(48, "LPSS_UART2_RTS_B"),
86 PINCTRL_PIN(49, "LPSS_UART2_CTS_B"),
87 PINCTRL_PIN(50, "ISH_UART0_RXD"),
88 PINCTRL_PIN(51, "ISH_UART0_TXT"),
89 PINCTRL_PIN(52, "ISH_UART0_RTS_B"),
90 PINCTRL_PIN(53, "ISH_UART0_CTS_B"),
91 PINCTRL_PIN(54, "ISH_UART1_RXD"),
92 PINCTRL_PIN(55, "ISH_UART1_TXT"),
93 PINCTRL_PIN(56, "ISH_UART1_RTS_B"),
94 PINCTRL_PIN(57, "ISH_UART1_CTS_B"),
95 PINCTRL_PIN(58, "ISH_UART2_RXD"),
96 PINCTRL_PIN(59, "ISH_UART2_TXD"),
97 PINCTRL_PIN(60, "ISH_UART2_RTS_B"),
98 PINCTRL_PIN(61, "ISH_UART2_CTS_B"),
99 PINCTRL_PIN(62, "GP_CAMERASB00"),
100 PINCTRL_PIN(63, "GP_CAMERASB01"),
101 PINCTRL_PIN(64, "GP_CAMERASB02"),
102 PINCTRL_PIN(65, "GP_CAMERASB03"),
103 PINCTRL_PIN(66, "GP_CAMERASB04"),
104 PINCTRL_PIN(67, "GP_CAMERASB05"),
105 PINCTRL_PIN(68, "GP_CAMERASB06"),
106 PINCTRL_PIN(69, "GP_CAMERASB07"),
107 PINCTRL_PIN(70, "GP_CAMERASB08"),
108 PINCTRL_PIN(71, "GP_CAMERASB09"),
109 PINCTRL_PIN(72, "GP_CAMERASB10"),
110 PINCTRL_PIN(73, "GP_CAMERASB11"),
111 PINCTRL_PIN(74, "TCK"),
112 PINCTRL_PIN(75, "TRST_B"),
113 PINCTRL_PIN(76, "TMS"),
114 PINCTRL_PIN(77, "TDI"),
115 PINCTRL_PIN(78, "CX_PMODE"),
116 PINCTRL_PIN(79, "CX_PREQ_B"),
117 PINCTRL_PIN(80, "JTAGX"),
118 PINCTRL_PIN(81, "CX_PRDY_B"),
119 PINCTRL_PIN(82, "TDO"),
120};
121
122static const unsigned bxt_north_pwm0_pins[] = { 34 };
123static const unsigned bxt_north_pwm1_pins[] = { 35 };
124static const unsigned bxt_north_pwm2_pins[] = { 36 };
125static const unsigned bxt_north_pwm3_pins[] = { 37 };
126static const unsigned bxt_north_uart0_pins[] = { 38, 39, 40, 41 };
127static const unsigned bxt_north_uart1_pins[] = { 42, 43, 44, 45 };
128static const unsigned bxt_north_uart2_pins[] = { 46, 47, 48, 49 };
129static const unsigned bxt_north_uart0b_pins[] = { 50, 51, 52, 53 };
130static const unsigned bxt_north_uart1b_pins[] = { 54, 55, 56, 57 };
131static const unsigned bxt_north_uart2b_pins[] = { 58, 59, 60, 61 };
132static const unsigned bxt_north_uart3_pins[] = { 58, 59, 60, 61 };
133
134static const struct intel_pingroup bxt_north_groups[] = {
135 PIN_GROUP("pwm0_grp", bxt_north_pwm0_pins, 1),
136 PIN_GROUP("pwm1_grp", bxt_north_pwm1_pins, 1),
137 PIN_GROUP("pwm2_grp", bxt_north_pwm2_pins, 1),
138 PIN_GROUP("pwm3_grp", bxt_north_pwm3_pins, 1),
139 PIN_GROUP("uart0_grp", bxt_north_uart0_pins, 1),
140 PIN_GROUP("uart1_grp", bxt_north_uart1_pins, 1),
141 PIN_GROUP("uart2_grp", bxt_north_uart2_pins, 1),
142 PIN_GROUP("uart0b_grp", bxt_north_uart0b_pins, 2),
143 PIN_GROUP("uart1b_grp", bxt_north_uart1b_pins, 2),
144 PIN_GROUP("uart2b_grp", bxt_north_uart2b_pins, 2),
145 PIN_GROUP("uart3_grp", bxt_north_uart3_pins, 3),
146};
147
148static const char * const bxt_north_pwm0_groups[] = { "pwm0_grp" };
149static const char * const bxt_north_pwm1_groups[] = { "pwm1_grp" };
150static const char * const bxt_north_pwm2_groups[] = { "pwm2_grp" };
151static const char * const bxt_north_pwm3_groups[] = { "pwm3_grp" };
152static const char * const bxt_north_uart0_groups[] = {
153 "uart0_grp", "uart0b_grp",
154};
155static const char * const bxt_north_uart1_groups[] = {
156 "uart1_grp", "uart1b_grp",
157};
158static const char * const bxt_north_uart2_groups[] = {
159 "uart2_grp", "uart2b_grp",
160};
161static const char * const bxt_north_uart3_groups[] = { "uart3_grp" };
162
163static const struct intel_function bxt_north_functions[] = {
164 FUNCTION("pwm0", bxt_north_pwm0_groups),
165 FUNCTION("pwm1", bxt_north_pwm1_groups),
166 FUNCTION("pwm2", bxt_north_pwm2_groups),
167 FUNCTION("pwm3", bxt_north_pwm3_groups),
168 FUNCTION("uart0", bxt_north_uart0_groups),
169 FUNCTION("uart1", bxt_north_uart1_groups),
170 FUNCTION("uart2", bxt_north_uart2_groups),
171 FUNCTION("uart3", bxt_north_uart3_groups),
172};
173
174static const struct intel_community bxt_north_communities[] = {
175 BXT_COMMUNITY(0, 82),
176};
177
178static const struct intel_pinctrl_soc_data bxt_north_soc_data = {
179 .uid = "1",
180 .pins = bxt_north_pins,
181 .npins = ARRAY_SIZE(bxt_north_pins),
182 .groups = bxt_north_groups,
183 .ngroups = ARRAY_SIZE(bxt_north_groups),
184 .functions = bxt_north_functions,
185 .nfunctions = ARRAY_SIZE(bxt_north_functions),
186 .communities = bxt_north_communities,
187 .ncommunities = ARRAY_SIZE(bxt_north_communities),
188};
189
190static const struct pinctrl_pin_desc bxt_northwest_pins[] = {
191 PINCTRL_PIN(0, "PMC_SPI_FS0"),
192 PINCTRL_PIN(1, "PMC_SPI_FS1"),
193 PINCTRL_PIN(2, "PMC_SPI_FS2"),
194 PINCTRL_PIN(3, "PMC_SPI_RXD"),
195 PINCTRL_PIN(4, "PMC_SPI_TXD"),
196 PINCTRL_PIN(5, "PMC_SPI_CLK"),
197 PINCTRL_PIN(6, "PMC_UART_RXD"),
198 PINCTRL_PIN(7, "PMC_UART_TXD"),
199 PINCTRL_PIN(8, "PMIC_PWRGOOD"),
200 PINCTRL_PIN(9, "PMIC_RESET_B"),
201 PINCTRL_PIN(10, "RTC_CLK"),
202 PINCTRL_PIN(11, "PMIC_SDWN_B"),
203 PINCTRL_PIN(12, "PMIC_BCUDISW2"),
204 PINCTRL_PIN(13, "PMIC_BCUDISCRIT"),
205 PINCTRL_PIN(14, "PMIC_THERMTRIP_B"),
206 PINCTRL_PIN(15, "PMIC_STDBY"),
207 PINCTRL_PIN(16, "SVID0_ALERT_B"),
208 PINCTRL_PIN(17, "SVID0_DATA"),
209 PINCTRL_PIN(18, "SVID0_CLK"),
210 PINCTRL_PIN(19, "PMIC_I2C_SCL"),
211 PINCTRL_PIN(20, "PMIC_I2C_SDA"),
212 PINCTRL_PIN(21, "AVS_I2S1_MCLK"),
213 PINCTRL_PIN(22, "AVS_I2S1_BCLK"),
214 PINCTRL_PIN(23, "AVS_I2S1_WS_SYNC"),
215 PINCTRL_PIN(24, "AVS_I2S1_SDI"),
216 PINCTRL_PIN(25, "AVS_I2S1_SDO"),
217 PINCTRL_PIN(26, "AVS_M_CLK_A1"),
218 PINCTRL_PIN(27, "AVS_M_CLK_B1"),
219 PINCTRL_PIN(28, "AVS_M_DATA_1"),
220 PINCTRL_PIN(29, "AVS_M_CLK_AB2"),
221 PINCTRL_PIN(30, "AVS_M_DATA_2"),
222 PINCTRL_PIN(31, "AVS_I2S2_MCLK"),
223 PINCTRL_PIN(32, "AVS_I2S2_BCLK"),
224 PINCTRL_PIN(33, "AVS_I2S2_WS_SYNC"),
225 PINCTRL_PIN(34, "AVS_I2S2_SDI"),
226 PINCTRL_PIN(35, "AVS_I2S2_SDOK"),
227 PINCTRL_PIN(36, "AVS_I2S3_BCLK"),
228 PINCTRL_PIN(37, "AVS_I2S3_WS_SYNC"),
229 PINCTRL_PIN(38, "AVS_I2S3_SDI"),
230 PINCTRL_PIN(39, "AVS_I2S3_SDO"),
231 PINCTRL_PIN(40, "AVS_I2S4_BCLK"),
232 PINCTRL_PIN(41, "AVS_I2S4_WS_SYNC"),
233 PINCTRL_PIN(42, "AVS_I2S4_SDI"),
234 PINCTRL_PIN(43, "AVS_I2S4_SDO"),
235 PINCTRL_PIN(44, "PROCHOT_B"),
236 PINCTRL_PIN(45, "FST_SPI_CS0_B"),
237 PINCTRL_PIN(46, "FST_SPI_CS1_B"),
238 PINCTRL_PIN(47, "FST_SPI_MOSI_IO0"),
239 PINCTRL_PIN(48, "FST_SPI_MISO_IO1"),
240 PINCTRL_PIN(49, "FST_SPI_IO2"),
241 PINCTRL_PIN(50, "FST_SPI_IO3"),
242 PINCTRL_PIN(51, "FST_SPI_CLK"),
243 PINCTRL_PIN(52, "FST_SPI_CLK_FB"),
244 PINCTRL_PIN(53, "GP_SSP_0_CLK"),
245 PINCTRL_PIN(54, "GP_SSP_0_FS0"),
246 PINCTRL_PIN(55, "GP_SSP_0_FS1"),
247 PINCTRL_PIN(56, "GP_SSP_0_FS2"),
248 PINCTRL_PIN(57, "GP_SSP_0_RXD"),
249 PINCTRL_PIN(58, "GP_SSP_0_TXD"),
250 PINCTRL_PIN(59, "GP_SSP_1_CLK"),
251 PINCTRL_PIN(60, "GP_SSP_1_FS0"),
252 PINCTRL_PIN(61, "GP_SSP_1_FS1"),
253 PINCTRL_PIN(62, "GP_SSP_1_FS2"),
254 PINCTRL_PIN(63, "GP_SSP_1_FS3"),
255 PINCTRL_PIN(64, "GP_SSP_1_RXD"),
256 PINCTRL_PIN(65, "GP_SSP_1_TXD"),
257 PINCTRL_PIN(66, "GP_SSP_2_CLK"),
258 PINCTRL_PIN(67, "GP_SSP_2_FS0"),
259 PINCTRL_PIN(68, "GP_SSP_2_FS1"),
260 PINCTRL_PIN(69, "GP_SSP_2_FS2"),
261 PINCTRL_PIN(70, "GP_SSP_2_RXD"),
262 PINCTRL_PIN(71, "GP_SSP_2_TXD"),
263};
264
265static const unsigned bxt_northwest_ssp0_pins[] = { 53, 54, 55, 56, 57, 58 };
266static const unsigned bxt_northwest_ssp1_pins[] = {
267 59, 60, 61, 62, 63, 64, 65
268};
269static const unsigned bxt_northwest_ssp2_pins[] = { 66, 67, 68, 69, 70, 71 };
270static const unsigned bxt_northwest_uart3_pins[] = { 67, 68, 69, 70 };
271
272static const struct intel_pingroup bxt_northwest_groups[] = {
273 PIN_GROUP("ssp0_grp", bxt_northwest_ssp0_pins, 1),
274 PIN_GROUP("ssp1_grp", bxt_northwest_ssp1_pins, 1),
275 PIN_GROUP("ssp2_grp", bxt_northwest_ssp2_pins, 1),
276 PIN_GROUP("uart3_grp", bxt_northwest_uart3_pins, 2),
277};
278
279static const char * const bxt_northwest_ssp0_groups[] = { "ssp0_grp" };
280static const char * const bxt_northwest_ssp1_groups[] = { "ssp1_grp" };
281static const char * const bxt_northwest_ssp2_groups[] = { "ssp2_grp" };
282static const char * const bxt_northwest_uart3_groups[] = { "uart3_grp" };
283
284static const struct intel_function bxt_northwest_functions[] = {
285 FUNCTION("ssp0", bxt_northwest_ssp0_groups),
286 FUNCTION("ssp1", bxt_northwest_ssp1_groups),
287 FUNCTION("ssp2", bxt_northwest_ssp2_groups),
288 FUNCTION("uart3", bxt_northwest_uart3_groups),
289};
290
291static const struct intel_community bxt_northwest_communities[] = {
292 BXT_COMMUNITY(0, 71),
293};
294
295static const struct intel_pinctrl_soc_data bxt_northwest_soc_data = {
296 .uid = "2",
297 .pins = bxt_northwest_pins,
298 .npins = ARRAY_SIZE(bxt_northwest_pins),
299 .groups = bxt_northwest_groups,
300 .ngroups = ARRAY_SIZE(bxt_northwest_groups),
301 .functions = bxt_northwest_functions,
302 .nfunctions = ARRAY_SIZE(bxt_northwest_functions),
303 .communities = bxt_northwest_communities,
304 .ncommunities = ARRAY_SIZE(bxt_northwest_communities),
305};
306
307static const struct pinctrl_pin_desc bxt_west_pins[] = {
308 PINCTRL_PIN(0, "LPSS_I2C0_SDA"),
309 PINCTRL_PIN(1, "LPSS_I2C0_SCL"),
310 PINCTRL_PIN(2, "LPSS_I2C1_SDA"),
311 PINCTRL_PIN(3, "LPSS_I2C1_SCL"),
312 PINCTRL_PIN(4, "LPSS_I2C2_SDA"),
313 PINCTRL_PIN(5, "LPSS_I2C2_SCL"),
314 PINCTRL_PIN(6, "LPSS_I2C3_SDA"),
315 PINCTRL_PIN(7, "LPSS_I2C3_SCL"),
316 PINCTRL_PIN(8, "LPSS_I2C4_SDA"),
317 PINCTRL_PIN(9, "LPSS_I2C4_SCL"),
318 PINCTRL_PIN(10, "LPSS_I2C5_SDA"),
319 PINCTRL_PIN(11, "LPSS_I2C5_SCL"),
320 PINCTRL_PIN(12, "LPSS_I2C6_SDA"),
321 PINCTRL_PIN(13, "LPSS_I2C6_SCL"),
322 PINCTRL_PIN(14, "LPSS_I2C7_SDA"),
323 PINCTRL_PIN(15, "LPSS_I2C7_SCL"),
324 PINCTRL_PIN(16, "ISH_I2C0_SDA"),
325 PINCTRL_PIN(17, "ISH_I2C0_SCL"),
326 PINCTRL_PIN(18, "ISH_I2C1_SDA"),
327 PINCTRL_PIN(19, "ISH_I2C1_SCL"),
328 PINCTRL_PIN(20, "ISH_I2C2_SDA"),
329 PINCTRL_PIN(21, "ISH_I2C2_SCL"),
330 PINCTRL_PIN(22, "ISH_GPIO_0"),
331 PINCTRL_PIN(23, "ISH_GPIO_1"),
332 PINCTRL_PIN(24, "ISH_GPIO_2"),
333 PINCTRL_PIN(25, "ISH_GPIO_3"),
334 PINCTRL_PIN(26, "ISH_GPIO_4"),
335 PINCTRL_PIN(27, "ISH_GPIO_5"),
336 PINCTRL_PIN(28, "ISH_GPIO_6"),
337 PINCTRL_PIN(29, "ISH_GPIO_7"),
338 PINCTRL_PIN(30, "ISH_GPIO_8"),
339 PINCTRL_PIN(31, "ISH_GPIO_9"),
340 PINCTRL_PIN(32, "MODEM_CLKREQ"),
341 PINCTRL_PIN(33, "DGCLKDBG_PMC_0"),
342 PINCTRL_PIN(34, "DGCLKDBG_PMC_1"),
343 PINCTRL_PIN(35, "DGCLKDBG_PMC_2"),
344 PINCTRL_PIN(36, "DGCLKDBG_ICLK_0"),
345 PINCTRL_PIN(37, "DGCLKDBG_ICLK_1"),
346 PINCTRL_PIN(38, "OSC_CLK_OUT_0"),
347 PINCTRL_PIN(39, "OSC_CLK_OUT_1"),
348 PINCTRL_PIN(40, "OSC_CLK_OUT_2"),
349 PINCTRL_PIN(41, "OSC_CLK_OUT_3"),
350};
351
352static const unsigned bxt_west_i2c0_pins[] = { 0, 1 };
353static const unsigned bxt_west_i2c1_pins[] = { 2, 3 };
354static const unsigned bxt_west_i2c2_pins[] = { 4, 5 };
355static const unsigned bxt_west_i2c3_pins[] = { 6, 7 };
356static const unsigned bxt_west_i2c4_pins[] = { 8, 9 };
357static const unsigned bxt_west_i2c5_pins[] = { 10, 11 };
358static const unsigned bxt_west_i2c6_pins[] = { 12, 13 };
359static const unsigned bxt_west_i2c7_pins[] = { 14, 15 };
360static const unsigned bxt_west_i2c5b_pins[] = { 16, 17 };
361static const unsigned bxt_west_i2c6b_pins[] = { 18, 19 };
362static const unsigned bxt_west_i2c7b_pins[] = { 20, 21 };
363
364static const struct intel_pingroup bxt_west_groups[] = {
365 PIN_GROUP("i2c0_grp", bxt_west_i2c0_pins, 1),
366 PIN_GROUP("i2c1_grp", bxt_west_i2c1_pins, 1),
367 PIN_GROUP("i2c2_grp", bxt_west_i2c2_pins, 1),
368 PIN_GROUP("i2c3_grp", bxt_west_i2c3_pins, 1),
369 PIN_GROUP("i2c4_grp", bxt_west_i2c4_pins, 1),
370 PIN_GROUP("i2c5_grp", bxt_west_i2c5_pins, 1),
371 PIN_GROUP("i2c6_grp", bxt_west_i2c6_pins, 1),
372 PIN_GROUP("i2c7_grp", bxt_west_i2c7_pins, 1),
373 PIN_GROUP("i2c5b_grp", bxt_west_i2c5b_pins, 2),
374 PIN_GROUP("i2c6b_grp", bxt_west_i2c6b_pins, 2),
375 PIN_GROUP("i2c7b_grp", bxt_west_i2c7b_pins, 2),
376};
377
378static const char * const bxt_west_i2c0_groups[] = { "i2c0_grp" };
379static const char * const bxt_west_i2c1_groups[] = { "i2c1_grp" };
380static const char * const bxt_west_i2c2_groups[] = { "i2c2_grp" };
381static const char * const bxt_west_i2c3_groups[] = { "i2c3_grp" };
382static const char * const bxt_west_i2c4_groups[] = { "i2c4_grp" };
383static const char * const bxt_west_i2c5_groups[] = { "i2c5_grp", "i2c5b_grp" };
384static const char * const bxt_west_i2c6_groups[] = { "i2c6_grp", "i2c6b_grp" };
385static const char * const bxt_west_i2c7_groups[] = { "i2c7_grp", "i2c7b_grp" };
386
387static const struct intel_function bxt_west_functions[] = {
388 FUNCTION("i2c0", bxt_west_i2c0_groups),
389 FUNCTION("i2c1", bxt_west_i2c1_groups),
390 FUNCTION("i2c2", bxt_west_i2c2_groups),
391 FUNCTION("i2c3", bxt_west_i2c3_groups),
392 FUNCTION("i2c4", bxt_west_i2c4_groups),
393 FUNCTION("i2c5", bxt_west_i2c5_groups),
394 FUNCTION("i2c6", bxt_west_i2c6_groups),
395 FUNCTION("i2c7", bxt_west_i2c7_groups),
396};
397
398static const struct intel_community bxt_west_communities[] = {
399 BXT_COMMUNITY(0, 41),
400};
401
402static const struct intel_pinctrl_soc_data bxt_west_soc_data = {
403 .uid = "3",
404 .pins = bxt_west_pins,
405 .npins = ARRAY_SIZE(bxt_west_pins),
406 .groups = bxt_west_groups,
407 .ngroups = ARRAY_SIZE(bxt_west_groups),
408 .functions = bxt_west_functions,
409 .nfunctions = ARRAY_SIZE(bxt_west_functions),
410 .communities = bxt_west_communities,
411 .ncommunities = ARRAY_SIZE(bxt_west_communities),
412};
413
414static const struct pinctrl_pin_desc bxt_southwest_pins[] = {
415 PINCTRL_PIN(0, "EMMC0_CLK"),
416 PINCTRL_PIN(1, "EMMC0_D0"),
417 PINCTRL_PIN(2, "EMMC0_D1"),
418 PINCTRL_PIN(3, "EMMC0_D2"),
419 PINCTRL_PIN(4, "EMMC0_D3"),
420 PINCTRL_PIN(5, "EMMC0_D4"),
421 PINCTRL_PIN(6, "EMMC0_D5"),
422 PINCTRL_PIN(7, "EMMC0_D6"),
423 PINCTRL_PIN(8, "EMMC0_D7"),
424 PINCTRL_PIN(9, "EMMC0_CMD"),
425 PINCTRL_PIN(10, "SDIO_CLK"),
426 PINCTRL_PIN(11, "SDIO_D0"),
427 PINCTRL_PIN(12, "SDIO_D1"),
428 PINCTRL_PIN(13, "SDIO_D2"),
429 PINCTRL_PIN(14, "SDIO_D3"),
430 PINCTRL_PIN(15, "SDIO_CMD"),
431 PINCTRL_PIN(16, "SDCARD_CLK"),
432 PINCTRL_PIN(17, "SDCARD_D0"),
433 PINCTRL_PIN(18, "SDCARD_D1"),
434 PINCTRL_PIN(19, "SDCARD_D2"),
435 PINCTRL_PIN(20, "SDCARD_D3"),
436 PINCTRL_PIN(21, "SDCARD_CD_B"),
437 PINCTRL_PIN(22, "SDCARD_CMD"),
438 PINCTRL_PIN(23, "SDCARD_LVL_CLK_FB"),
439 PINCTRL_PIN(24, "SDCARD_LVL_CMD_DIR"),
440 PINCTRL_PIN(25, "SDCARD_LVL_DAT_DIR"),
441 PINCTRL_PIN(26, "EMMC0_STROBE"),
442 PINCTRL_PIN(27, "SDIO_PWR_DOWN_B"),
443 PINCTRL_PIN(28, "SDCARD_PWR_DOWN_B"),
444 PINCTRL_PIN(29, "SDCARD_LVL_SEL"),
445 PINCTRL_PIN(30, "SDCARD_LVL_WP"),
446};
447
448static const unsigned bxt_southwest_emmc0_pins[] = {
449 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 26,
450};
451static const unsigned bxt_southwest_sdio_pins[] = {
452 10, 11, 12, 13, 14, 15, 27,
453};
454static const unsigned bxt_southwest_sdcard_pins[] = {
455 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
456};
457
458static const struct intel_pingroup bxt_southwest_groups[] = {
459 PIN_GROUP("emmc0_grp", bxt_southwest_emmc0_pins, 1),
460 PIN_GROUP("sdio_grp", bxt_southwest_sdio_pins, 1),
461 PIN_GROUP("sdcard_grp", bxt_southwest_sdcard_pins, 1),
462};
463
464static const char * const bxt_southwest_emmc0_groups[] = { "emmc0_grp" };
465static const char * const bxt_southwest_sdio_groups[] = { "sdio_grp" };
466static const char * const bxt_southwest_sdcard_groups[] = { "sdcard_grp" };
467
468static const struct intel_function bxt_southwest_functions[] = {
469 FUNCTION("emmc0", bxt_southwest_emmc0_groups),
470 FUNCTION("sdio", bxt_southwest_sdio_groups),
471 FUNCTION("sdcard", bxt_southwest_sdcard_groups),
472};
473
474static const struct intel_community bxt_southwest_communities[] = {
475 BXT_COMMUNITY(0, 30),
476};
477
478static const struct intel_pinctrl_soc_data bxt_southwest_soc_data = {
479 .uid = "4",
480 .pins = bxt_southwest_pins,
481 .npins = ARRAY_SIZE(bxt_southwest_pins),
482 .groups = bxt_southwest_groups,
483 .ngroups = ARRAY_SIZE(bxt_southwest_groups),
484 .functions = bxt_southwest_functions,
485 .nfunctions = ARRAY_SIZE(bxt_southwest_functions),
486 .communities = bxt_southwest_communities,
487 .ncommunities = ARRAY_SIZE(bxt_southwest_communities),
488};
489
490static const struct pinctrl_pin_desc bxt_south_pins[] = {
491 PINCTRL_PIN(0, "HV_DDI0_DDC_SDA"),
492 PINCTRL_PIN(1, "HV_DDI0_DDC_SCL"),
493 PINCTRL_PIN(2, "HV_DDI1_DDC_SDA"),
494 PINCTRL_PIN(3, "HV_DDI1_DDC_SCL"),
495 PINCTRL_PIN(4, "DBI_SDA"),
496 PINCTRL_PIN(5, "DBI_SCL"),
497 PINCTRL_PIN(6, "PANEL0_VDDEN"),
498 PINCTRL_PIN(7, "PANEL0_BKLTEN"),
499 PINCTRL_PIN(8, "PANEL0_BKLTCTL"),
500 PINCTRL_PIN(9, "PANEL1_VDDEN"),
501 PINCTRL_PIN(10, "PANEL1_BKLTEN"),
502 PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
503 PINCTRL_PIN(12, "DBI_CSX"),
504 PINCTRL_PIN(13, "DBI_RESX"),
505 PINCTRL_PIN(14, "GP_INTD_DSI_TE1"),
506 PINCTRL_PIN(15, "GP_INTD_DSI_TE2"),
507 PINCTRL_PIN(16, "USB_OC0_B"),
508 PINCTRL_PIN(17, "USB_OC1_B"),
509 PINCTRL_PIN(18, "MEX_WAKE0_B"),
510 PINCTRL_PIN(19, "MEX_WAKE1_B"),
511};
512
513static const struct intel_community bxt_south_communities[] = {
514 BXT_COMMUNITY(0, 19),
515};
516
517static const struct intel_pinctrl_soc_data bxt_south_soc_data = {
518 .uid = "5",
519 .pins = bxt_south_pins,
520 .npins = ARRAY_SIZE(bxt_south_pins),
521 .communities = bxt_south_communities,
522 .ncommunities = ARRAY_SIZE(bxt_south_communities),
523};
524
525static const struct intel_pinctrl_soc_data *bxt_pinctrl_soc_data[] = {
526 &bxt_north_soc_data,
527 &bxt_northwest_soc_data,
528 &bxt_west_soc_data,
529 &bxt_southwest_soc_data,
530 &bxt_south_soc_data,
531 NULL,
532};
533
534/* APL */
535static const struct pinctrl_pin_desc apl_north_pins[] = {
536 PINCTRL_PIN(0, "GPIO_0"),
537 PINCTRL_PIN(1, "GPIO_1"),
538 PINCTRL_PIN(2, "GPIO_2"),
539 PINCTRL_PIN(3, "GPIO_3"),
540 PINCTRL_PIN(4, "GPIO_4"),
541 PINCTRL_PIN(5, "GPIO_5"),
542 PINCTRL_PIN(6, "GPIO_6"),
543 PINCTRL_PIN(7, "GPIO_7"),
544 PINCTRL_PIN(8, "GPIO_8"),
545 PINCTRL_PIN(9, "GPIO_9"),
546 PINCTRL_PIN(10, "GPIO_10"),
547 PINCTRL_PIN(11, "GPIO_11"),
548 PINCTRL_PIN(12, "GPIO_12"),
549 PINCTRL_PIN(13, "GPIO_13"),
550 PINCTRL_PIN(14, "GPIO_14"),
551 PINCTRL_PIN(15, "GPIO_15"),
552 PINCTRL_PIN(16, "GPIO_16"),
553 PINCTRL_PIN(17, "GPIO_17"),
554 PINCTRL_PIN(18, "GPIO_18"),
555 PINCTRL_PIN(19, "GPIO_19"),
556 PINCTRL_PIN(20, "GPIO_20"),
557 PINCTRL_PIN(21, "GPIO_21"),
558 PINCTRL_PIN(22, "GPIO_22"),
559 PINCTRL_PIN(23, "GPIO_23"),
560 PINCTRL_PIN(24, "GPIO_24"),
561 PINCTRL_PIN(25, "GPIO_25"),
562 PINCTRL_PIN(26, "GPIO_26"),
563 PINCTRL_PIN(27, "GPIO_27"),
564 PINCTRL_PIN(28, "GPIO_28"),
565 PINCTRL_PIN(29, "GPIO_29"),
566 PINCTRL_PIN(30, "GPIO_30"),
567 PINCTRL_PIN(31, "GPIO_31"),
568 PINCTRL_PIN(32, "GPIO_32"),
569 PINCTRL_PIN(33, "GPIO_33"),
570 PINCTRL_PIN(34, "PWM0"),
571 PINCTRL_PIN(35, "PWM1"),
572 PINCTRL_PIN(36, "PWM2"),
573 PINCTRL_PIN(37, "PWM3"),
574 PINCTRL_PIN(38, "LPSS_UART0_RXD"),
575 PINCTRL_PIN(39, "LPSS_UART0_TXD"),
576 PINCTRL_PIN(40, "LPSS_UART0_RTS_B"),
577 PINCTRL_PIN(41, "LPSS_UART0_CTS_B"),
578 PINCTRL_PIN(42, "LPSS_UART1_RXD"),
579 PINCTRL_PIN(43, "LPSS_UART1_TXD"),
580 PINCTRL_PIN(44, "LPSS_UART1_RTS_B"),
581 PINCTRL_PIN(45, "LPSS_UART1_CTS_B"),
582 PINCTRL_PIN(46, "LPSS_UART2_RXD"),
583 PINCTRL_PIN(47, "LPSS_UART2_TXD"),
584 PINCTRL_PIN(48, "LPSS_UART2_RTS_B"),
585 PINCTRL_PIN(49, "LPSS_UART2_CTS_B"),
586 PINCTRL_PIN(50, "GP_CAMERASB00"),
587 PINCTRL_PIN(51, "GP_CAMERASB01"),
588 PINCTRL_PIN(52, "GP_CAMERASB02"),
589 PINCTRL_PIN(53, "GP_CAMERASB03"),
590 PINCTRL_PIN(54, "GP_CAMERASB04"),
591 PINCTRL_PIN(55, "GP_CAMERASB05"),
592 PINCTRL_PIN(56, "GP_CAMERASB06"),
593 PINCTRL_PIN(57, "GP_CAMERASB07"),
594 PINCTRL_PIN(58, "GP_CAMERASB08"),
595 PINCTRL_PIN(59, "GP_CAMERASB09"),
596 PINCTRL_PIN(60, "GP_CAMERASB10"),
597 PINCTRL_PIN(61, "GP_CAMERASB11"),
598 PINCTRL_PIN(62, "TCK"),
599 PINCTRL_PIN(63, "TRST_B"),
600 PINCTRL_PIN(64, "TMS"),
601 PINCTRL_PIN(65, "TDI"),
602 PINCTRL_PIN(66, "CX_PMODE"),
603 PINCTRL_PIN(67, "CX_PREQ_B"),
604 PINCTRL_PIN(68, "JTAGX"),
605 PINCTRL_PIN(69, "CX_PRDY_B"),
606 PINCTRL_PIN(70, "TDO"),
607 PINCTRL_PIN(71, "CNV_BRI_DT"),
608 PINCTRL_PIN(72, "CNV_BRI_RSP"),
609 PINCTRL_PIN(73, "CNV_RGI_DT"),
610 PINCTRL_PIN(74, "CNV_RGI_RSP"),
611 PINCTRL_PIN(75, "SVID0_ALERT_B"),
612 PINCTRL_PIN(76, "SVID0_DATA"),
613 PINCTRL_PIN(77, "SVID0_CLK"),
614};
615
616static const unsigned apl_north_pwm0_pins[] = { 34 };
617static const unsigned apl_north_pwm1_pins[] = { 35 };
618static const unsigned apl_north_pwm2_pins[] = { 36 };
619static const unsigned apl_north_pwm3_pins[] = { 37 };
620static const unsigned apl_north_uart0_pins[] = { 38, 39, 40, 41 };
621static const unsigned apl_north_uart1_pins[] = { 42, 43, 44, 45 };
622static const unsigned apl_north_uart2_pins[] = { 46, 47, 48, 49 };
623
624static const struct intel_pingroup apl_north_groups[] = {
625 PIN_GROUP("pwm0_grp", apl_north_pwm0_pins, 1),
626 PIN_GROUP("pwm1_grp", apl_north_pwm1_pins, 1),
627 PIN_GROUP("pwm2_grp", apl_north_pwm2_pins, 1),
628 PIN_GROUP("pwm3_grp", apl_north_pwm3_pins, 1),
629 PIN_GROUP("uart0_grp", apl_north_uart0_pins, 1),
630 PIN_GROUP("uart1_grp", apl_north_uart1_pins, 1),
631 PIN_GROUP("uart2_grp", apl_north_uart2_pins, 1),
632};
633
634static const char * const apl_north_pwm0_groups[] = { "pwm0_grp" };
635static const char * const apl_north_pwm1_groups[] = { "pwm1_grp" };
636static const char * const apl_north_pwm2_groups[] = { "pwm2_grp" };
637static const char * const apl_north_pwm3_groups[] = { "pwm3_grp" };
638static const char * const apl_north_uart0_groups[] = { "uart0_grp" };
639static const char * const apl_north_uart1_groups[] = { "uart1_grp" };
640static const char * const apl_north_uart2_groups[] = { "uart2_grp" };
641
642static const struct intel_function apl_north_functions[] = {
643 FUNCTION("pwm0", apl_north_pwm0_groups),
644 FUNCTION("pwm1", apl_north_pwm1_groups),
645 FUNCTION("pwm2", apl_north_pwm2_groups),
646 FUNCTION("pwm3", apl_north_pwm3_groups),
647 FUNCTION("uart0", apl_north_uart0_groups),
648 FUNCTION("uart1", apl_north_uart1_groups),
649 FUNCTION("uart2", apl_north_uart2_groups),
650};
651
652static const struct intel_community apl_north_communities[] = {
653 BXT_COMMUNITY(0, 77),
654};
655
656static const struct intel_pinctrl_soc_data apl_north_soc_data = {
657 .uid = "1",
658 .pins = apl_north_pins,
659 .npins = ARRAY_SIZE(apl_north_pins),
660 .groups = apl_north_groups,
661 .ngroups = ARRAY_SIZE(apl_north_groups),
662 .functions = apl_north_functions,
663 .nfunctions = ARRAY_SIZE(apl_north_functions),
664 .communities = apl_north_communities,
665 .ncommunities = ARRAY_SIZE(apl_north_communities),
666};
667
668static const struct pinctrl_pin_desc apl_northwest_pins[] = {
669 PINCTRL_PIN(0, "HV_DDI0_DDC_SDA"),
670 PINCTRL_PIN(1, "HV_DDI0_DDC_SCL"),
671 PINCTRL_PIN(2, "HV_DDI1_DDC_SDA"),
672 PINCTRL_PIN(3, "HV_DDI1_DDC_SCL"),
673 PINCTRL_PIN(4, "DBI_SDA"),
674 PINCTRL_PIN(5, "DBI_SCL"),
675 PINCTRL_PIN(6, "PANEL0_VDDEN"),
676 PINCTRL_PIN(7, "PANEL0_BKLTEN"),
677 PINCTRL_PIN(8, "PANEL0_BKLTCTL"),
678 PINCTRL_PIN(9, "PANEL1_VDDEN"),
679 PINCTRL_PIN(10, "PANEL1_BKLTEN"),
680 PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
681 PINCTRL_PIN(12, "DBI_CSX"),
682 PINCTRL_PIN(13, "DBI_RESX"),
683 PINCTRL_PIN(14, "GP_INTD_DSI_TE1"),
684 PINCTRL_PIN(15, "GP_INTD_DSI_TE2"),
685 PINCTRL_PIN(16, "USB_OC0_B"),
686 PINCTRL_PIN(17, "USB_OC1_B"),
687 PINCTRL_PIN(18, "PMC_SPI_FS0"),
688 PINCTRL_PIN(19, "PMC_SPI_FS1"),
689 PINCTRL_PIN(20, "PMC_SPI_FS2"),
690 PINCTRL_PIN(21, "PMC_SPI_RXD"),
691 PINCTRL_PIN(22, "PMC_SPI_TXD"),
692 PINCTRL_PIN(23, "PMC_SPI_CLK"),
693 PINCTRL_PIN(24, "PMIC_PWRGOOD"),
694 PINCTRL_PIN(25, "PMIC_RESET_B"),
695 PINCTRL_PIN(26, "PMIC_SDWN_B"),
696 PINCTRL_PIN(27, "PMIC_BCUDISW2"),
697 PINCTRL_PIN(28, "PMIC_BCUDISCRIT"),
698 PINCTRL_PIN(29, "PMIC_THERMTRIP_B"),
699 PINCTRL_PIN(30, "PMIC_STDBY"),
700 PINCTRL_PIN(31, "PROCHOT_B"),
701 PINCTRL_PIN(32, "PMIC_I2C_SCL"),
702 PINCTRL_PIN(33, "PMIC_I2C_SDA"),
703 PINCTRL_PIN(34, "AVS_I2S1_MCLK"),
704 PINCTRL_PIN(35, "AVS_I2S1_BCLK"),
705 PINCTRL_PIN(36, "AVS_I2S1_WS_SYNC"),
706 PINCTRL_PIN(37, "AVS_I2S1_SDI"),
707 PINCTRL_PIN(38, "AVS_I2S1_SDO"),
708 PINCTRL_PIN(39, "AVS_M_CLK_A1"),
709 PINCTRL_PIN(40, "AVS_M_CLK_B1"),
710 PINCTRL_PIN(41, "AVS_M_DATA_1"),
711 PINCTRL_PIN(42, "AVS_M_CLK_AB2"),
712 PINCTRL_PIN(43, "AVS_M_DATA_2"),
713 PINCTRL_PIN(44, "AVS_I2S2_MCLK"),
714 PINCTRL_PIN(45, "AVS_I2S2_BCLK"),
715 PINCTRL_PIN(46, "AVS_I2S2_WS_SYNC"),
716 PINCTRL_PIN(47, "AVS_I2S2_SDI"),
717 PINCTRL_PIN(48, "AVS_I2S2_SDO"),
718 PINCTRL_PIN(49, "AVS_I2S3_BCLK"),
719 PINCTRL_PIN(50, "AVS_I2S3_WS_SYNC"),
720 PINCTRL_PIN(51, "AVS_I2S3_SDI"),
721 PINCTRL_PIN(52, "AVS_I2S3_SDO"),
722 PINCTRL_PIN(53, "FST_SPI_CS0_B"),
723 PINCTRL_PIN(54, "FST_SPI_CS1_B"),
724 PINCTRL_PIN(55, "FST_SPI_MOSI_IO0"),
725 PINCTRL_PIN(56, "FST_SPI_MISO_IO1"),
726 PINCTRL_PIN(57, "FST_SPI_IO2"),
727 PINCTRL_PIN(58, "FST_SPI_IO3"),
728 PINCTRL_PIN(59, "FST_SPI_CLK"),
729 PINCTRL_PIN(60, "FST_SPI_CLK_FB"),
730 PINCTRL_PIN(61, "GP_SSP_0_CLK"),
731 PINCTRL_PIN(62, "GP_SSP_0_FS0"),
732 PINCTRL_PIN(63, "GP_SSP_0_FS1"),
733 PINCTRL_PIN(64, "GP_SSP_0_RXD"),
734 PINCTRL_PIN(65, "GP_SSP_0_TXD"),
735 PINCTRL_PIN(66, "GP_SSP_1_CLK"),
736 PINCTRL_PIN(67, "GP_SSP_1_FS0"),
737 PINCTRL_PIN(68, "GP_SSP_1_FS1"),
738 PINCTRL_PIN(69, "GP_SSP_1_RXD"),
739 PINCTRL_PIN(70, "GP_SSP_1_TXD"),
740 PINCTRL_PIN(71, "GP_SSP_2_CLK"),
741 PINCTRL_PIN(72, "GP_SSP_2_FS0"),
742 PINCTRL_PIN(73, "GP_SSP_2_FS1"),
743 PINCTRL_PIN(74, "GP_SSP_2_FS2"),
744 PINCTRL_PIN(75, "GP_SSP_2_RXD"),
745 PINCTRL_PIN(76, "GP_SSP_2_TXD"),
746};
747
748static const unsigned apl_northwest_ssp0_pins[] = { 61, 62, 63, 64, 65 };
749static const unsigned apl_northwest_ssp1_pins[] = { 66, 67, 68, 69, 70 };
750static const unsigned apl_northwest_ssp2_pins[] = { 71, 72, 73, 74, 75, 76 };
751static const unsigned apl_northwest_uart3_pins[] = { 67, 68, 69, 70 };
752
753static const struct intel_pingroup apl_northwest_groups[] = {
754 PIN_GROUP("ssp0_grp", apl_northwest_ssp0_pins, 1),
755 PIN_GROUP("ssp1_grp", apl_northwest_ssp1_pins, 1),
756 PIN_GROUP("ssp2_grp", apl_northwest_ssp2_pins, 1),
757 PIN_GROUP("uart3_grp", apl_northwest_uart3_pins, 2),
758};
759
760static const char * const apl_northwest_ssp0_groups[] = { "ssp0_grp" };
761static const char * const apl_northwest_ssp1_groups[] = { "ssp1_grp" };
762static const char * const apl_northwest_ssp2_groups[] = { "ssp2_grp" };
763static const char * const apl_northwest_uart3_groups[] = { "uart3_grp" };
764
765static const struct intel_function apl_northwest_functions[] = {
766 FUNCTION("ssp0", apl_northwest_ssp0_groups),
767 FUNCTION("ssp1", apl_northwest_ssp1_groups),
768 FUNCTION("ssp2", apl_northwest_ssp2_groups),
769 FUNCTION("uart3", apl_northwest_uart3_groups),
770};
771
772static const struct intel_community apl_northwest_communities[] = {
773 BXT_COMMUNITY(0, 76),
774};
775
776static const struct intel_pinctrl_soc_data apl_northwest_soc_data = {
777 .uid = "2",
778 .pins = apl_northwest_pins,
779 .npins = ARRAY_SIZE(apl_northwest_pins),
780 .groups = apl_northwest_groups,
781 .ngroups = ARRAY_SIZE(apl_northwest_groups),
782 .functions = apl_northwest_functions,
783 .nfunctions = ARRAY_SIZE(apl_northwest_functions),
784 .communities = apl_northwest_communities,
785 .ncommunities = ARRAY_SIZE(apl_northwest_communities),
786};
787
788static const struct pinctrl_pin_desc apl_west_pins[] = {
789 PINCTRL_PIN(0, "LPSS_I2C0_SDA"),
790 PINCTRL_PIN(1, "LPSS_I2C0_SCL"),
791 PINCTRL_PIN(2, "LPSS_I2C1_SDA"),
792 PINCTRL_PIN(3, "LPSS_I2C1_SCL"),
793 PINCTRL_PIN(4, "LPSS_I2C2_SDA"),
794 PINCTRL_PIN(5, "LPSS_I2C2_SCL"),
795 PINCTRL_PIN(6, "LPSS_I2C3_SDA"),
796 PINCTRL_PIN(7, "LPSS_I2C3_SCL"),
797 PINCTRL_PIN(8, "LPSS_I2C4_SDA"),
798 PINCTRL_PIN(9, "LPSS_I2C4_SCL"),
799 PINCTRL_PIN(10, "LPSS_I2C5_SDA"),
800 PINCTRL_PIN(11, "LPSS_I2C5_SCL"),
801 PINCTRL_PIN(12, "LPSS_I2C6_SDA"),
802 PINCTRL_PIN(13, "LPSS_I2C6_SCL"),
803 PINCTRL_PIN(14, "LPSS_I2C7_SDA"),
804 PINCTRL_PIN(15, "LPSS_I2C7_SCL"),
805 PINCTRL_PIN(16, "ISH_GPIO_0"),
806 PINCTRL_PIN(17, "ISH_GPIO_1"),
807 PINCTRL_PIN(18, "ISH_GPIO_2"),
808 PINCTRL_PIN(19, "ISH_GPIO_3"),
809 PINCTRL_PIN(20, "ISH_GPIO_4"),
810 PINCTRL_PIN(21, "ISH_GPIO_5"),
811 PINCTRL_PIN(22, "ISH_GPIO_6"),
812 PINCTRL_PIN(23, "ISH_GPIO_7"),
813 PINCTRL_PIN(24, "ISH_GPIO_8"),
814 PINCTRL_PIN(25, "ISH_GPIO_9"),
815 PINCTRL_PIN(26, "PCIE_CLKREQ0_B"),
816 PINCTRL_PIN(27, "PCIE_CLKREQ1_B"),
817 PINCTRL_PIN(28, "PCIE_CLKREQ2_B"),
818 PINCTRL_PIN(29, "PCIE_CLKREQ3_B"),
819 PINCTRL_PIN(30, "OSC_CLK_OUT_0"),
820 PINCTRL_PIN(31, "OSC_CLK_OUT_1"),
821 PINCTRL_PIN(32, "OSC_CLK_OUT_2"),
822 PINCTRL_PIN(33, "OSC_CLK_OUT_3"),
823 PINCTRL_PIN(34, "OSC_CLK_OUT_4"),
824 PINCTRL_PIN(35, "PMU_AC_PRESENT"),
825 PINCTRL_PIN(36, "PMU_BATLOW_B"),
826 PINCTRL_PIN(37, "PMU_PLTRST_B"),
827 PINCTRL_PIN(38, "PMU_PWRBTN_B"),
828 PINCTRL_PIN(39, "PMU_RESETBUTTON_B"),
829 PINCTRL_PIN(40, "PMU_SLP_S0_B"),
830 PINCTRL_PIN(41, "PMU_SLP_S3_B"),
831 PINCTRL_PIN(42, "PMU_SLP_S4_B"),
832 PINCTRL_PIN(43, "PMU_SUSCLK"),
833 PINCTRL_PIN(44, "PMU_WAKE_B"),
834 PINCTRL_PIN(45, "SUS_STAT_B"),
835 PINCTRL_PIN(46, "SUSPWRDNACK"),
836};
837
838static const unsigned apl_west_i2c0_pins[] = { 0, 1 };
839static const unsigned apl_west_i2c1_pins[] = { 2, 3 };
840static const unsigned apl_west_i2c2_pins[] = { 4, 5 };
841static const unsigned apl_west_i2c3_pins[] = { 6, 7 };
842static const unsigned apl_west_i2c4_pins[] = { 8, 9 };
843static const unsigned apl_west_i2c5_pins[] = { 10, 11 };
844static const unsigned apl_west_i2c6_pins[] = { 12, 13 };
845static const unsigned apl_west_i2c7_pins[] = { 14, 15 };
846static const unsigned apl_west_uart2_pins[] = { 20, 21, 22, 34 };
847
848static const struct intel_pingroup apl_west_groups[] = {
849 PIN_GROUP("i2c0_grp", apl_west_i2c0_pins, 1),
850 PIN_GROUP("i2c1_grp", apl_west_i2c1_pins, 1),
851 PIN_GROUP("i2c2_grp", apl_west_i2c2_pins, 1),
852 PIN_GROUP("i2c3_grp", apl_west_i2c3_pins, 1),
853 PIN_GROUP("i2c4_grp", apl_west_i2c4_pins, 1),
854 PIN_GROUP("i2c5_grp", apl_west_i2c5_pins, 1),
855 PIN_GROUP("i2c6_grp", apl_west_i2c6_pins, 1),
856 PIN_GROUP("i2c7_grp", apl_west_i2c7_pins, 1),
857 PIN_GROUP("uart2_grp", apl_west_uart2_pins, 3),
858};
859
860static const char * const apl_west_i2c0_groups[] = { "i2c0_grp" };
861static const char * const apl_west_i2c1_groups[] = { "i2c1_grp" };
862static const char * const apl_west_i2c2_groups[] = { "i2c2_grp" };
863static const char * const apl_west_i2c3_groups[] = { "i2c3_grp" };
864static const char * const apl_west_i2c4_groups[] = { "i2c4_grp" };
865static const char * const apl_west_i2c5_groups[] = { "i2c5_grp" };
866static const char * const apl_west_i2c6_groups[] = { "i2c6_grp" };
867static const char * const apl_west_i2c7_groups[] = { "i2c7_grp" };
868static const char * const apl_west_uart2_groups[] = { "uart2_grp" };
869
870static const struct intel_function apl_west_functions[] = {
871 FUNCTION("i2c0", apl_west_i2c0_groups),
872 FUNCTION("i2c1", apl_west_i2c1_groups),
873 FUNCTION("i2c2", apl_west_i2c2_groups),
874 FUNCTION("i2c3", apl_west_i2c3_groups),
875 FUNCTION("i2c4", apl_west_i2c4_groups),
876 FUNCTION("i2c5", apl_west_i2c5_groups),
877 FUNCTION("i2c6", apl_west_i2c6_groups),
878 FUNCTION("i2c7", apl_west_i2c7_groups),
879 FUNCTION("uart2", apl_west_uart2_groups),
880};
881
882static const struct intel_community apl_west_communities[] = {
883 BXT_COMMUNITY(0, 46),
884};
885
886static const struct intel_pinctrl_soc_data apl_west_soc_data = {
887 .uid = "3",
888 .pins = apl_west_pins,
889 .npins = ARRAY_SIZE(apl_west_pins),
890 .groups = apl_west_groups,
891 .ngroups = ARRAY_SIZE(apl_west_groups),
892 .functions = apl_west_functions,
893 .nfunctions = ARRAY_SIZE(apl_west_functions),
894 .communities = apl_west_communities,
895 .ncommunities = ARRAY_SIZE(apl_west_communities),
896};
897
898static const struct pinctrl_pin_desc apl_southwest_pins[] = {
899 PINCTRL_PIN(0, "PCIE_WAKE0_B"),
900 PINCTRL_PIN(1, "PCIE_WAKE1_B"),
901 PINCTRL_PIN(2, "PCIE_WAKE2_B"),
902 PINCTRL_PIN(3, "PCIE_WAKE3_B"),
903 PINCTRL_PIN(4, "EMMC0_CLK"),
904 PINCTRL_PIN(5, "EMMC0_D0"),
905 PINCTRL_PIN(6, "EMMC0_D1"),
906 PINCTRL_PIN(7, "EMMC0_D2"),
907 PINCTRL_PIN(8, "EMMC0_D3"),
908 PINCTRL_PIN(9, "EMMC0_D4"),
909 PINCTRL_PIN(10, "EMMC0_D5"),
910 PINCTRL_PIN(11, "EMMC0_D6"),
911 PINCTRL_PIN(12, "EMMC0_D7"),
912 PINCTRL_PIN(13, "EMMC0_CMD"),
913 PINCTRL_PIN(14, "SDIO_CLK"),
914 PINCTRL_PIN(15, "SDIO_D0"),
915 PINCTRL_PIN(16, "SDIO_D1"),
916 PINCTRL_PIN(17, "SDIO_D2"),
917 PINCTRL_PIN(18, "SDIO_D3"),
918 PINCTRL_PIN(19, "SDIO_CMD"),
919 PINCTRL_PIN(20, "SDCARD_CLK"),
920 PINCTRL_PIN(21, "SDCARD_CLK_FB"),
921 PINCTRL_PIN(22, "SDCARD_D0"),
922 PINCTRL_PIN(23, "SDCARD_D1"),
923 PINCTRL_PIN(24, "SDCARD_D2"),
924 PINCTRL_PIN(25, "SDCARD_D3"),
925 PINCTRL_PIN(26, "SDCARD_CD_B"),
926 PINCTRL_PIN(27, "SDCARD_CMD"),
927 PINCTRL_PIN(28, "SDCARD_LVL_WP"),
928 PINCTRL_PIN(29, "EMMC0_STROBE"),
929 PINCTRL_PIN(30, "SDIO_PWR_DOWN_B"),
930 PINCTRL_PIN(31, "SMB_ALERTB"),
931 PINCTRL_PIN(32, "SMB_CLK"),
932 PINCTRL_PIN(33, "SMB_DATA"),
933 PINCTRL_PIN(34, "LPC_ILB_SERIRQ"),
934 PINCTRL_PIN(35, "LPC_CLKOUT0"),
935 PINCTRL_PIN(36, "LPC_CLKOUT1"),
936 PINCTRL_PIN(37, "LPC_AD0"),
937 PINCTRL_PIN(38, "LPC_AD1"),
938 PINCTRL_PIN(39, "LPC_AD2"),
939 PINCTRL_PIN(40, "LPC_AD3"),
940 PINCTRL_PIN(41, "LPC_CLKRUNB"),
941 PINCTRL_PIN(42, "LPC_FRAMEB"),
942};
943
944static const unsigned apl_southwest_emmc0_pins[] = {
945 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 29,
946};
947static const unsigned apl_southwest_sdio_pins[] = {
948 14, 15, 16, 17, 18, 19, 30,
949};
950static const unsigned apl_southwest_sdcard_pins[] = {
951 20, 21, 22, 23, 24, 25, 26, 27, 28,
952};
953static const unsigned apl_southwest_i2c7_pins[] = { 32, 33 };
954
955static const struct intel_pingroup apl_southwest_groups[] = {
956 PIN_GROUP("emmc0_grp", apl_southwest_emmc0_pins, 1),
957 PIN_GROUP("sdio_grp", apl_southwest_sdio_pins, 1),
958 PIN_GROUP("sdcard_grp", apl_southwest_sdcard_pins, 1),
959 PIN_GROUP("i2c7_grp", apl_southwest_i2c7_pins, 2),
960};
961
962static const char * const apl_southwest_emmc0_groups[] = { "emmc0_grp" };
963static const char * const apl_southwest_sdio_groups[] = { "sdio_grp" };
964static const char * const apl_southwest_sdcard_groups[] = { "sdcard_grp" };
965static const char * const apl_southwest_i2c7_groups[] = { "i2c7_grp" };
966
967static const struct intel_function apl_southwest_functions[] = {
968 FUNCTION("emmc0", apl_southwest_emmc0_groups),
969 FUNCTION("sdio", apl_southwest_sdio_groups),
970 FUNCTION("sdcard", apl_southwest_sdcard_groups),
971 FUNCTION("i2c7", apl_southwest_i2c7_groups),
972};
973
974static const struct intel_community apl_southwest_communities[] = {
975 BXT_COMMUNITY(0, 42),
976};
977
978static const struct intel_pinctrl_soc_data apl_southwest_soc_data = {
979 .uid = "4",
980 .pins = apl_southwest_pins,
981 .npins = ARRAY_SIZE(apl_southwest_pins),
982 .groups = apl_southwest_groups,
983 .ngroups = ARRAY_SIZE(apl_southwest_groups),
984 .functions = apl_southwest_functions,
985 .nfunctions = ARRAY_SIZE(apl_southwest_functions),
986 .communities = apl_southwest_communities,
987 .ncommunities = ARRAY_SIZE(apl_southwest_communities),
988};
989
990static const struct intel_pinctrl_soc_data *apl_pinctrl_soc_data[] = {
991 &apl_north_soc_data,
992 &apl_northwest_soc_data,
993 &apl_west_soc_data,
994 &apl_southwest_soc_data,
995 NULL,
996};
997
998static const struct acpi_device_id bxt_pinctrl_acpi_match[] = {
999 { "INT3452", (kernel_ulong_t)apl_pinctrl_soc_data },
1000 { "INT34D1", (kernel_ulong_t)bxt_pinctrl_soc_data },
1001 { }
1002};
1003MODULE_DEVICE_TABLE(acpi, bxt_pinctrl_acpi_match);
1004
1005static int bxt_pinctrl_probe(struct platform_device *pdev)
1006{
1007 const struct intel_pinctrl_soc_data *soc_data = NULL;
1008 const struct intel_pinctrl_soc_data **soc_table;
1009 const struct acpi_device_id *id;
1010 struct acpi_device *adev;
1011 int i;
1012
1013 adev = ACPI_COMPANION(&pdev->dev);
1014 if (!adev)
1015 return -ENODEV;
1016
1017 id = acpi_match_device(bxt_pinctrl_acpi_match, &pdev->dev);
1018 if (!id)
1019 return -ENODEV;
1020
1021 soc_table = (const struct intel_pinctrl_soc_data **)id->driver_data;
1022
1023 for (i = 0; soc_table[i]; i++) {
1024 if (!strcmp(adev->pnp.unique_id, soc_table[i]->uid)) {
1025 soc_data = soc_table[i];
1026 break;
1027 }
1028 }
1029
1030 if (!soc_data)
1031 return -ENODEV;
1032
1033 return intel_pinctrl_probe(pdev, soc_data);
1034}
1035
1036static const struct dev_pm_ops bxt_pinctrl_pm_ops = {
1037 SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
1038 intel_pinctrl_resume)
1039};
1040
1041static struct platform_driver bxt_pinctrl_driver = {
1042 .probe = bxt_pinctrl_probe,
1043 .remove = intel_pinctrl_remove,
1044 .driver = {
1045 .name = "broxton-pinctrl",
1046 .acpi_match_table = bxt_pinctrl_acpi_match,
1047 .pm = &bxt_pinctrl_pm_ops,
1048 },
1049};
1050
1051static int __init bxt_pinctrl_init(void)
1052{
1053 return platform_driver_register(&bxt_pinctrl_driver);
1054}
1055subsys_initcall(bxt_pinctrl_init);
1056
1057static void __exit bxt_pinctrl_exit(void)
1058{
1059 platform_driver_unregister(&bxt_pinctrl_driver);
1060}
1061module_exit(bxt_pinctrl_exit);
1062
1063MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1064MODULE_DESCRIPTION("Intel Broxton SoC pinctrl/GPIO driver");
1065MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 54848b8decef..c4274542a5a0 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -12,6 +12,7 @@
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/interrupt.h>
15#include <linux/acpi.h> 16#include <linux/acpi.h>
16#include <linux/gpio.h> 17#include <linux/gpio.h>
17#include <linux/gpio/driver.h> 18#include <linux/gpio/driver.h>
@@ -159,8 +160,7 @@ static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
159 return !(readl(padown) & PADOWN_MASK(padno)); 160 return !(readl(padown) & PADOWN_MASK(padno));
160} 161}
161 162
162static bool intel_pad_reserved_for_acpi(struct intel_pinctrl *pctrl, 163static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
163 unsigned pin)
164{ 164{
165 const struct intel_community *community; 165 const struct intel_community *community;
166 unsigned padno, gpp, offset; 166 unsigned padno, gpp, offset;
@@ -216,7 +216,6 @@ static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
216static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin) 216static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
217{ 217{
218 return intel_pad_owned_by_host(pctrl, pin) && 218 return intel_pad_owned_by_host(pctrl, pin) &&
219 !intel_pad_reserved_for_acpi(pctrl, pin) &&
220 !intel_pad_locked(pctrl, pin); 219 !intel_pad_locked(pctrl, pin);
221} 220}
222 221
@@ -269,7 +268,7 @@ static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
269 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1); 268 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
270 269
271 locked = intel_pad_locked(pctrl, pin); 270 locked = intel_pad_locked(pctrl, pin);
272 acpi = intel_pad_reserved_for_acpi(pctrl, pin); 271 acpi = intel_pad_acpi_mode(pctrl, pin);
273 272
274 if (locked || acpi) { 273 if (locked || acpi) {
275 seq_puts(s, " ["); 274 seq_puts(s, " [");
@@ -736,6 +735,16 @@ static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
736 if (!reg) 735 if (!reg)
737 return -EINVAL; 736 return -EINVAL;
738 737
738 /*
739 * If the pin is in ACPI mode it is still usable as a GPIO but it
740 * cannot be used as IRQ because GPI_IS status bit will not be
741 * updated by the host controller hardware.
742 */
743 if (intel_pad_acpi_mode(pctrl, pin)) {
744 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
745 return -EPERM;
746 }
747
739 spin_lock_irqsave(&pctrl->lock, flags); 748 spin_lock_irqsave(&pctrl->lock, flags);
740 749
741 value = readl(reg); 750 value = readl(reg);
@@ -803,9 +812,11 @@ static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
803 return 0; 812 return 0;
804} 813}
805 814
806static void intel_gpio_community_irq_handler(struct gpio_chip *gc, 815static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
807 const struct intel_community *community) 816 const struct intel_community *community)
808{ 817{
818 struct gpio_chip *gc = &pctrl->chip;
819 irqreturn_t ret = IRQ_NONE;
809 int gpp; 820 int gpp;
810 821
811 for (gpp = 0; gpp < community->ngpps; gpp++) { 822 for (gpp = 0; gpp < community->ngpps; gpp++) {
@@ -832,24 +843,28 @@ static void intel_gpio_community_irq_handler(struct gpio_chip *gc,
832 irq = irq_find_mapping(gc->irqdomain, 843 irq = irq_find_mapping(gc->irqdomain,
833 community->pin_base + padno); 844 community->pin_base + padno);
834 generic_handle_irq(irq); 845 generic_handle_irq(irq);
846
847 ret |= IRQ_HANDLED;
835 } 848 }
836 } 849 }
850
851 return ret;
837} 852}
838 853
839static void intel_gpio_irq_handler(struct irq_desc *desc) 854static irqreturn_t intel_gpio_irq(int irq, void *data)
840{ 855{
841 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 856 const struct intel_community *community;
842 struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc); 857 struct intel_pinctrl *pctrl = data;
843 struct irq_chip *chip = irq_desc_get_chip(desc); 858 irqreturn_t ret = IRQ_NONE;
844 int i; 859 int i;
845 860
846 chained_irq_enter(chip, desc);
847
848 /* Need to check all communities for pending interrupts */ 861 /* Need to check all communities for pending interrupts */
849 for (i = 0; i < pctrl->ncommunities; i++) 862 for (i = 0; i < pctrl->ncommunities; i++) {
850 intel_gpio_community_irq_handler(gc, &pctrl->communities[i]); 863 community = &pctrl->communities[i];
864 ret |= intel_gpio_community_irq_handler(pctrl, community);
865 }
851 866
852 chained_irq_exit(chip, desc); 867 return ret;
853} 868}
854 869
855static struct irq_chip intel_gpio_irqchip = { 870static struct irq_chip intel_gpio_irqchip = {
@@ -861,26 +876,6 @@ static struct irq_chip intel_gpio_irqchip = {
861 .irq_set_wake = intel_gpio_irq_wake, 876 .irq_set_wake = intel_gpio_irq_wake,
862}; 877};
863 878
864static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
865{
866 size_t i;
867
868 for (i = 0; i < pctrl->ncommunities; i++) {
869 const struct intel_community *community;
870 void __iomem *base;
871 unsigned gpp;
872
873 community = &pctrl->communities[i];
874 base = community->regs;
875
876 for (gpp = 0; gpp < community->ngpps; gpp++) {
877 /* Mask and clear all interrupts */
878 writel(0, base + community->ie_offset + gpp * 4);
879 writel(0xffff, base + GPI_IS + gpp * 4);
880 }
881 }
882}
883
884static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) 879static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
885{ 880{
886 int ret; 881 int ret;
@@ -902,21 +897,36 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
902 0, 0, pctrl->soc->npins); 897 0, 0, pctrl->soc->npins);
903 if (ret) { 898 if (ret) {
904 dev_err(pctrl->dev, "failed to add GPIO pin range\n"); 899 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
905 gpiochip_remove(&pctrl->chip); 900 goto fail;
906 return ret; 901 }
902
903 /*
904 * We need to request the interrupt here (instead of providing chip
905 * to the irq directly) because on some platforms several GPIO
906 * controllers share the same interrupt line.
907 */
908 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, IRQF_SHARED,
909 dev_name(pctrl->dev), pctrl);
910 if (ret) {
911 dev_err(pctrl->dev, "failed to request interrupt\n");
912 goto fail;
907 } 913 }
908 914
909 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0, 915 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
910 handle_simple_irq, IRQ_TYPE_NONE); 916 handle_simple_irq, IRQ_TYPE_NONE);
911 if (ret) { 917 if (ret) {
912 dev_err(pctrl->dev, "failed to add irqchip\n"); 918 dev_err(pctrl->dev, "failed to add irqchip\n");
913 gpiochip_remove(&pctrl->chip); 919 goto fail;
914 return ret;
915 } 920 }
916 921
917 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq, 922 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
918 intel_gpio_irq_handler); 923 NULL);
919 return 0; 924 return 0;
925
926fail:
927 gpiochip_remove(&pctrl->chip);
928
929 return ret;
920} 930}
921 931
922static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) 932static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
@@ -1087,6 +1097,26 @@ int intel_pinctrl_suspend(struct device *dev)
1087} 1097}
1088EXPORT_SYMBOL_GPL(intel_pinctrl_suspend); 1098EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1089 1099
1100static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1101{
1102 size_t i;
1103
1104 for (i = 0; i < pctrl->ncommunities; i++) {
1105 const struct intel_community *community;
1106 void __iomem *base;
1107 unsigned gpp;
1108
1109 community = &pctrl->communities[i];
1110 base = community->regs;
1111
1112 for (gpp = 0; gpp < community->ngpps; gpp++) {
1113 /* Mask and clear all interrupts */
1114 writel(0, base + community->ie_offset + gpp * 4);
1115 writel(0xffff, base + GPI_IS + gpp * 4);
1116 }
1117 }
1118}
1119
1090int intel_pinctrl_resume(struct device *dev) 1120int intel_pinctrl_resume(struct device *dev)
1091{ 1121{
1092 struct platform_device *pdev = to_platform_device(dev); 1122 struct platform_device *pdev = to_platform_device(dev);
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index 1b22f96ba839..5279e230e1b5 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -899,7 +899,7 @@ static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq)
899 int start_level, curr_level; 899 int start_level, curr_level;
900 unsigned int reg_offset; 900 unsigned int reg_offset;
901 const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets); 901 const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets);
902 u32 mask = 1 << (hwirq & 0x1f); 902 u32 mask = BIT(hwirq & 0x1f);
903 u32 port = (hwirq >> 5) & eint_offsets->port_mask; 903 u32 port = (hwirq >> 5) & eint_offsets->port_mask;
904 void __iomem *reg = pctl->eint_reg_base + (port << 2); 904 void __iomem *reg = pctl->eint_reg_base + (port << 2);
905 const struct mtk_desc_pin *pin; 905 const struct mtk_desc_pin *pin;
@@ -1436,7 +1436,7 @@ int mtk_pctrl_init(struct platform_device *pdev,
1436 irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip, 1436 irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip,
1437 handle_level_irq); 1437 handle_level_irq);
1438 irq_set_chip_data(virq, pctl); 1438 irq_set_chip_data(virq, pctl);
1439 }; 1439 }
1440 1440
1441 irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl); 1441 irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl);
1442 return 0; 1442 return 0;
diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c
index e63ad9fbd388..099a3442ff42 100644
--- a/drivers/pinctrl/pinconf-generic.c
+++ b/drivers/pinctrl/pinconf-generic.c
@@ -28,25 +28,25 @@
28 28
29#ifdef CONFIG_DEBUG_FS 29#ifdef CONFIG_DEBUG_FS
30static const struct pin_config_item conf_items[] = { 30static const struct pin_config_item conf_items[] = {
31 PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL, false),
31 PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL, false), 32 PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL, false),
32 PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL, false), 33 PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL, false),
33 PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL, false),
34 PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL, false),
35 PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", NULL, false), 34 PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", NULL, false),
36 PCONFDUMP(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 35 PCONFDUMP(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT,
37 "input bias pull to pin specific state", NULL, false), 36 "input bias pull to pin specific state", NULL, false),
38 PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL, false), 37 PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL, false),
39 PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL, false), 38 PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL, false),
40 PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL, false), 39 PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL, false),
40 PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL, false),
41 PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH, "output drive strength", "mA", true), 41 PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH, "output drive strength", "mA", true),
42 PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec", true),
42 PCONFDUMP(PIN_CONFIG_INPUT_ENABLE, "input enabled", NULL, false), 43 PCONFDUMP(PIN_CONFIG_INPUT_ENABLE, "input enabled", NULL, false),
43 PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL, false),
44 PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL, false), 44 PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL, false),
45 PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec", true), 45 PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL, false),
46 PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true),
47 PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true),
48 PCONFDUMP(PIN_CONFIG_LOW_POWER_MODE, "pin low power", "mode", true), 46 PCONFDUMP(PIN_CONFIG_LOW_POWER_MODE, "pin low power", "mode", true),
49 PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level", true), 47 PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level", true),
48 PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true),
49 PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true),
50}; 50};
51 51
52static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev, 52static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev,
@@ -150,27 +150,28 @@ EXPORT_SYMBOL_GPL(pinconf_generic_dump_config);
150 150
151#ifdef CONFIG_OF 151#ifdef CONFIG_OF
152static const struct pinconf_generic_params dt_params[] = { 152static const struct pinconf_generic_params dt_params[] = {
153 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
153 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 154 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
154 { "bias-high-impedance", PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0 }, 155 { "bias-high-impedance", PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0 },
155 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
156 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 156 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
157 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
158 { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 }, 157 { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
159 { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 }, 158 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
160 { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 }, 159 { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 },
161 { "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 }, 160 { "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 },
161 { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 },
162 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 162 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
163 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, 163 { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 },
164 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, 164 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
165 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 165 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
166 { "input-schmitt", PIN_CONFIG_INPUT_SCHMITT, 0 },
166 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 167 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
167 { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, 168 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
168 { "power-source", PIN_CONFIG_POWER_SOURCE, 0 },
169 { "low-power-enable", PIN_CONFIG_LOW_POWER_MODE, 1 },
170 { "low-power-disable", PIN_CONFIG_LOW_POWER_MODE, 0 }, 169 { "low-power-disable", PIN_CONFIG_LOW_POWER_MODE, 0 },
171 { "output-low", PIN_CONFIG_OUTPUT, 0, }, 170 { "low-power-enable", PIN_CONFIG_LOW_POWER_MODE, 1 },
172 { "output-high", PIN_CONFIG_OUTPUT, 1, }, 171 { "output-high", PIN_CONFIG_OUTPUT, 1, },
173 { "slew-rate", PIN_CONFIG_SLEW_RATE, 0}, 172 { "output-low", PIN_CONFIG_OUTPUT, 0, },
173 { "power-source", PIN_CONFIG_POWER_SOURCE, 0 },
174 { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
174}; 175};
175 176
176/** 177/**
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index 29a7bb17a42f..4dd7722f9935 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -411,7 +411,7 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d)
411 const struct pinctrl_map *found = NULL; 411 const struct pinctrl_map *found = NULL;
412 struct pinctrl_dev *pctldev; 412 struct pinctrl_dev *pctldev;
413 struct dbg_cfg *dbg = &pinconf_dbg_conf; 413 struct dbg_cfg *dbg = &pinconf_dbg_conf;
414 int i, j; 414 int i;
415 415
416 mutex_lock(&pinctrl_maps_mutex); 416 mutex_lock(&pinctrl_maps_mutex);
417 417
@@ -424,13 +424,10 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d)
424 if (strcmp(map->name, dbg->state_name)) 424 if (strcmp(map->name, dbg->state_name))
425 continue; 425 continue;
426 426
427 for (j = 0; j < map->data.configs.num_configs; j++) { 427 if (!strcmp(map->data.configs.group_or_pin, dbg->pin_name)) {
428 if (!strcmp(map->data.configs.group_or_pin, 428 /* We found the right pin */
429 dbg->pin_name)) { 429 found = map;
430 /* We found the right pin / state */ 430 break;
431 found = map;
432 break;
433 }
434 } 431 }
435 } 432 }
436 433
diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c
new file mode 100644
index 000000000000..33edd07d9149
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-at91-pio4.c
@@ -0,0 +1,1094 @@
1/*
2 * Driver for the Atmel PIO4 controller
3 *
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk.h>
18#include <linux/gpio.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/platform_device.h>
24#include <linux/pinctrl/pinconf.h>
25#include <linux/pinctrl/pinconf-generic.h>
26#include <linux/pinctrl/pinctrl.h>
27#include <linux/pinctrl/pinmux.h>
28#include <linux/slab.h>
29#include "core.h"
30#include "pinconf.h"
31#include "pinctrl-utils.h"
32
33/*
34 * Warning:
35 * In order to not introduce confusion between Atmel PIO groups and pinctrl
36 * framework groups, Atmel PIO groups will be called banks, line is kept to
37 * designed the pin id into this bank.
38 */
39
40#define ATMEL_PIO_MSKR 0x0000
41#define ATMEL_PIO_CFGR 0x0004
42#define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0)
43#define ATMEL_PIO_DIR_MASK BIT(8)
44#define ATMEL_PIO_PUEN_MASK BIT(9)
45#define ATMEL_PIO_PDEN_MASK BIT(10)
46#define ATMEL_PIO_IFEN_MASK BIT(12)
47#define ATMEL_PIO_IFSCEN_MASK BIT(13)
48#define ATMEL_PIO_OPD_MASK BIT(14)
49#define ATMEL_PIO_SCHMITT_MASK BIT(15)
50#define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24)
51#define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24)
52#define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24)
53#define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24)
54#define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24)
55#define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24)
56#define ATMEL_PIO_PDSR 0x0008
57#define ATMEL_PIO_LOCKSR 0x000C
58#define ATMEL_PIO_SODR 0x0010
59#define ATMEL_PIO_CODR 0x0014
60#define ATMEL_PIO_ODSR 0x0018
61#define ATMEL_PIO_IER 0x0020
62#define ATMEL_PIO_IDR 0x0024
63#define ATMEL_PIO_IMR 0x0028
64#define ATMEL_PIO_ISR 0x002C
65#define ATMEL_PIO_IOFR 0x003C
66
67#define ATMEL_PIO_NPINS_PER_BANK 32
68#define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK)
69#define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK)
70#define ATMEL_PIO_BANK_OFFSET 0x40
71
72#define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff)
73#define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf)
74#define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf)
75
76struct atmel_pioctrl_data {
77 unsigned nbanks;
78};
79
80struct atmel_group {
81 const char *name;
82 u32 pin;
83};
84
85struct atmel_pin {
86 unsigned pin_id;
87 unsigned mux;
88 unsigned ioset;
89 unsigned bank;
90 unsigned line;
91 const char *device;
92};
93
94/**
95 * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
96 * @reg_base: base address of the controller.
97 * @clk: clock of the controller.
98 * @nbanks: number of PIO groups, it can vary depending on the SoC.
99 * @pinctrl_dev: pinctrl device registered.
100 * @groups: groups table to provide group name and pin in the group to pinctrl.
101 * @group_names: group names table to provide all the group/pin names to
102 * pinctrl or gpio.
103 * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line
104 * fields are set at probe time. Other ones are set when parsing dt
105 * pinctrl.
106 * @npins: number of pins.
107 * @gpio_chip: gpio chip registered.
108 * @irq_domain: irq domain for the gpio controller.
109 * @irqs: table containing the hw irq number of the bank. The index of the
110 * table is the bank id.
111 * @dev: device entry for the Atmel PIO controller.
112 * @node: node of the Atmel PIO controller.
113 */
114struct atmel_pioctrl {
115 void __iomem *reg_base;
116 struct clk *clk;
117 unsigned nbanks;
118 struct pinctrl_dev *pinctrl_dev;
119 struct atmel_group *groups;
120 const char * const *group_names;
121 struct atmel_pin **pins;
122 unsigned npins;
123 struct gpio_chip *gpio_chip;
124 struct irq_domain *irq_domain;
125 int *irqs;
126 unsigned *pm_wakeup_sources;
127 unsigned *pm_suspend_backup;
128 struct device *dev;
129 struct device_node *node;
130};
131
132static const char * const atmel_functions[] = {
133 "GPIO", "A", "B", "C", "D", "E", "F", "G"
134};
135
136/* --- GPIO --- */
137static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl,
138 unsigned int bank, unsigned int reg)
139{
140 return readl_relaxed(atmel_pioctrl->reg_base
141 + ATMEL_PIO_BANK_OFFSET * bank + reg);
142}
143
144static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl,
145 unsigned int bank, unsigned int reg,
146 unsigned int val)
147{
148 writel_relaxed(val, atmel_pioctrl->reg_base
149 + ATMEL_PIO_BANK_OFFSET * bank + reg);
150}
151
152static void atmel_gpio_irq_ack(struct irq_data *d)
153{
154 /*
155 * Nothing to do, interrupt is cleared when reading the status
156 * register.
157 */
158}
159
160static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type)
161{
162 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
163 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
164 unsigned reg;
165
166 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
167 BIT(pin->line));
168 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
169 reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK);
170
171 switch (type) {
172 case IRQ_TYPE_EDGE_RISING:
173 irq_set_handler_locked(d, handle_edge_irq);
174 reg |= ATMEL_PIO_CFGR_EVTSEL_RISING;
175 break;
176 case IRQ_TYPE_EDGE_FALLING:
177 irq_set_handler_locked(d, handle_edge_irq);
178 reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING;
179 break;
180 case IRQ_TYPE_EDGE_BOTH:
181 irq_set_handler_locked(d, handle_edge_irq);
182 reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH;
183 break;
184 case IRQ_TYPE_LEVEL_LOW:
185 irq_set_handler_locked(d, handle_level_irq);
186 reg |= ATMEL_PIO_CFGR_EVTSEL_LOW;
187 break;
188 case IRQ_TYPE_LEVEL_HIGH:
189 irq_set_handler_locked(d, handle_level_irq);
190 reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH;
191 break;
192 case IRQ_TYPE_NONE:
193 default:
194 return -EINVAL;
195 }
196
197 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
198
199 return 0;
200}
201
202static void atmel_gpio_irq_mask(struct irq_data *d)
203{
204 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
205 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
206
207 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR,
208 BIT(pin->line));
209}
210
211static void atmel_gpio_irq_unmask(struct irq_data *d)
212{
213 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
214 struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
215
216 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER,
217 BIT(pin->line));
218}
219
220#ifdef CONFIG_PM_SLEEP
221
222static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
223{
224 struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
225 int bank = ATMEL_PIO_BANK(d->hwirq);
226 int line = ATMEL_PIO_LINE(d->hwirq);
227
228 /* The gpio controller has one interrupt line per bank. */
229 irq_set_irq_wake(atmel_pioctrl->irqs[bank], on);
230
231 if (on)
232 atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line);
233 else
234 atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line));
235
236 return 0;
237}
238#else
239#define atmel_gpio_irq_set_wake NULL
240#endif /* CONFIG_PM_SLEEP */
241
242static struct irq_chip atmel_gpio_irq_chip = {
243 .name = "GPIO",
244 .irq_ack = atmel_gpio_irq_ack,
245 .irq_mask = atmel_gpio_irq_mask,
246 .irq_unmask = atmel_gpio_irq_unmask,
247 .irq_set_type = atmel_gpio_irq_set_type,
248 .irq_set_wake = atmel_gpio_irq_set_wake,
249};
250
251static void atmel_gpio_irq_handler(struct irq_desc *desc)
252{
253 unsigned int irq = irq_desc_get_irq(desc);
254 struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc);
255 struct irq_chip *chip = irq_desc_get_chip(desc);
256 unsigned long isr;
257 int n, bank = -1;
258
259 /* Find from which bank is the irq received. */
260 for (n = 0; n < atmel_pioctrl->nbanks; n++) {
261 if (atmel_pioctrl->irqs[n] == irq) {
262 bank = n;
263 break;
264 }
265 }
266
267 if (bank < 0) {
268 dev_err(atmel_pioctrl->dev,
269 "no bank associated to irq %u\n", irq);
270 return;
271 }
272
273 chained_irq_enter(chip, desc);
274
275 for (;;) {
276 isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
277 ATMEL_PIO_ISR);
278 isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
279 ATMEL_PIO_IMR);
280 if (!isr)
281 break;
282
283 for_each_set_bit(n, &isr, BITS_PER_LONG)
284 generic_handle_irq(gpio_to_irq(bank *
285 ATMEL_PIO_NPINS_PER_BANK + n));
286 }
287
288 chained_irq_exit(chip, desc);
289}
290
291static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
292{
293 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev);
294 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
295 unsigned reg;
296
297 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
298 BIT(pin->line));
299 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
300 reg &= ~ATMEL_PIO_DIR_MASK;
301 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
302
303 return 0;
304}
305
306static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset)
307{
308 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev);
309 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
310 unsigned reg;
311
312 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
313
314 return !!(reg & BIT(pin->line));
315}
316
317static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
318 int value)
319{
320 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev);
321 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
322 unsigned reg;
323
324 atmel_gpio_write(atmel_pioctrl, pin->bank,
325 value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
326 BIT(pin->line));
327
328 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
329 BIT(pin->line));
330 reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
331 reg |= ATMEL_PIO_DIR_MASK;
332 atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
333
334 return 0;
335}
336
337static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
338{
339 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev);
340 struct atmel_pin *pin = atmel_pioctrl->pins[offset];
341
342 atmel_gpio_write(atmel_pioctrl, pin->bank,
343 val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
344 BIT(pin->line));
345}
346
347static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
348{
349 struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(chip->dev);
350
351 return irq_find_mapping(atmel_pioctrl->irq_domain, offset);
352}
353
354static struct gpio_chip atmel_gpio_chip = {
355 .direction_input = atmel_gpio_direction_input,
356 .get = atmel_gpio_get,
357 .direction_output = atmel_gpio_direction_output,
358 .set = atmel_gpio_set,
359 .to_irq = atmel_gpio_to_irq,
360 .base = 0,
361};
362
363/* --- PINCTRL --- */
364static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
365 unsigned pin_id)
366{
367 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
368 unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
369 unsigned line = atmel_pioctrl->pins[pin_id]->line;
370 void __iomem *addr = atmel_pioctrl->reg_base
371 + bank * ATMEL_PIO_BANK_OFFSET;
372
373 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
374 /* Have to set MSKR first, to access the right pin CFGR. */
375 wmb();
376
377 return readl_relaxed(addr + ATMEL_PIO_CFGR);
378}
379
380static void atmel_pin_config_write(struct pinctrl_dev *pctldev,
381 unsigned pin_id, u32 conf)
382{
383 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
384 unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
385 unsigned line = atmel_pioctrl->pins[pin_id]->line;
386 void __iomem *addr = atmel_pioctrl->reg_base
387 + bank * ATMEL_PIO_BANK_OFFSET;
388
389 writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
390 /* Have to set MSKR first, to access the right pin CFGR. */
391 wmb();
392 writel_relaxed(conf, addr + ATMEL_PIO_CFGR);
393}
394
395static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev)
396{
397 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
398
399 return atmel_pioctrl->npins;
400}
401
402static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,
403 unsigned selector)
404{
405 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
406
407 return atmel_pioctrl->groups[selector].name;
408}
409
410static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
411 unsigned selector, const unsigned **pins,
412 unsigned *num_pins)
413{
414 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
415
416 *pins = (unsigned *)&atmel_pioctrl->groups[selector].pin;
417 *num_pins = 1;
418
419 return 0;
420}
421
422struct atmel_group *atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev,
423 unsigned pin)
424{
425 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
426 int i;
427
428 for (i = 0; i < atmel_pioctrl->npins; i++) {
429 struct atmel_group *grp = atmel_pioctrl->groups + i;
430
431 if (grp->pin == pin)
432 return grp;
433 }
434
435 return NULL;
436}
437
438static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev,
439 struct device_node *np,
440 u32 pinfunc, const char **grp_name,
441 const char **func_name)
442{
443 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
444 unsigned pin_id, func_id;
445 struct atmel_group *grp;
446
447 pin_id = ATMEL_GET_PIN_NO(pinfunc);
448 func_id = ATMEL_GET_PIN_FUNC(pinfunc);
449
450 if (func_id >= ARRAY_SIZE(atmel_functions))
451 return -EINVAL;
452
453 *func_name = atmel_functions[func_id];
454
455 grp = atmel_pctl_find_group_by_pin(pctldev, pin_id);
456 if (!grp)
457 return -EINVAL;
458 *grp_name = grp->name;
459
460 atmel_pioctrl->pins[pin_id]->mux = func_id;
461 atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc);
462 /* Want the device name not the group one. */
463 if (np->parent == atmel_pioctrl->node)
464 atmel_pioctrl->pins[pin_id]->device = np->name;
465 else
466 atmel_pioctrl->pins[pin_id]->device = np->parent->name;
467
468 return 0;
469}
470
471static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
472 struct device_node *np,
473 struct pinctrl_map **map,
474 unsigned *reserved_maps,
475 unsigned *num_maps)
476{
477 unsigned num_pins, num_configs, reserve;
478 unsigned long *configs;
479 struct property *pins;
480 bool has_config;
481 u32 pinfunc;
482 int ret, i;
483
484 pins = of_find_property(np, "pinmux", NULL);
485 if (!pins)
486 return -EINVAL;
487
488 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
489 &num_configs);
490 if (ret < 0) {
491 dev_err(pctldev->dev, "%s: could not parse node property\n",
492 of_node_full_name(np));
493 return ret;
494 }
495
496 if (num_configs)
497 has_config = true;
498
499 num_pins = pins->length / sizeof(u32);
500 if (!num_pins) {
501 dev_err(pctldev->dev, "no pins found in node %s\n",
502 of_node_full_name(np));
503 return -EINVAL;
504 }
505
506 /*
507 * Reserve maps, at least there is a mux map and an optional conf
508 * map for each pin.
509 */
510 reserve = 1;
511 if (has_config && num_pins >= 1)
512 reserve++;
513 reserve *= num_pins;
514 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
515 reserve);
516 if (ret < 0)
517 return ret;
518
519 for (i = 0; i < num_pins; i++) {
520 const char *group, *func;
521
522 ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc);
523 if (ret)
524 return ret;
525
526 ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group,
527 &func);
528 if (ret)
529 return ret;
530
531 pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
532 group, func);
533
534 if (has_config) {
535 ret = pinctrl_utils_add_map_configs(pctldev, map,
536 reserved_maps, num_maps, group,
537 configs, num_configs,
538 PIN_MAP_TYPE_CONFIGS_GROUP);
539 if (ret < 0)
540 return ret;
541 }
542 }
543
544 return 0;
545}
546
547static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
548 struct device_node *np_config,
549 struct pinctrl_map **map,
550 unsigned *num_maps)
551{
552 struct device_node *np;
553 unsigned reserved_maps;
554 int ret;
555
556 *map = NULL;
557 *num_maps = 0;
558 reserved_maps = 0;
559
560 /*
561 * If all the pins of a device have the same configuration (or no one),
562 * it is useless to add a subnode, so directly parse node referenced by
563 * phandle.
564 */
565 ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map,
566 &reserved_maps, num_maps);
567 if (ret) {
568 for_each_child_of_node(np_config, np) {
569 ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map,
570 &reserved_maps, num_maps);
571 if (ret < 0)
572 break;
573 }
574 }
575
576 if (ret < 0) {
577 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
578 dev_err(pctldev->dev, "can't create maps for node %s\n",
579 np_config->full_name);
580 }
581
582 return ret;
583}
584
585static const struct pinctrl_ops atmel_pctlops = {
586 .get_groups_count = atmel_pctl_get_groups_count,
587 .get_group_name = atmel_pctl_get_group_name,
588 .get_group_pins = atmel_pctl_get_group_pins,
589 .dt_node_to_map = atmel_pctl_dt_node_to_map,
590 .dt_free_map = pinctrl_utils_dt_free_map,
591};
592
593static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev)
594{
595 return ARRAY_SIZE(atmel_functions);
596}
597
598static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,
599 unsigned selector)
600{
601 return atmel_functions[selector];
602}
603
604static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
605 unsigned selector,
606 const char * const **groups,
607 unsigned * const num_groups)
608{
609 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
610
611 *groups = atmel_pioctrl->group_names;
612 *num_groups = atmel_pioctrl->npins;
613
614 return 0;
615}
616
617static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,
618 unsigned function,
619 unsigned group)
620{
621 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
622 unsigned pin;
623 u32 conf;
624
625 dev_dbg(pctldev->dev, "enable function %s group %s\n",
626 atmel_functions[function], atmel_pioctrl->groups[group].name);
627
628 pin = atmel_pioctrl->groups[group].pin;
629 conf = atmel_pin_config_read(pctldev, pin);
630 conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
631 conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK);
632 dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf);
633 atmel_pin_config_write(pctldev, pin, conf);
634
635 return 0;
636}
637
638static const struct pinmux_ops atmel_pmxops = {
639 .get_functions_count = atmel_pmx_get_functions_count,
640 .get_function_name = atmel_pmx_get_function_name,
641 .get_function_groups = atmel_pmx_get_function_groups,
642 .set_mux = atmel_pmx_set_mux,
643};
644
645static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
646 unsigned group,
647 unsigned long *config)
648{
649 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
650 unsigned param = pinconf_to_config_param(*config), arg = 0;
651 struct atmel_group *grp = atmel_pioctrl->groups + group;
652 unsigned pin_id = grp->pin;
653 u32 res;
654
655 res = atmel_pin_config_read(pctldev, pin_id);
656
657 switch (param) {
658 case PIN_CONFIG_BIAS_PULL_UP:
659 if (!(res & ATMEL_PIO_PUEN_MASK))
660 return -EINVAL;
661 arg = 1;
662 break;
663 case PIN_CONFIG_BIAS_PULL_DOWN:
664 if ((res & ATMEL_PIO_PUEN_MASK) ||
665 (!(res & ATMEL_PIO_PDEN_MASK)))
666 return -EINVAL;
667 arg = 1;
668 break;
669 case PIN_CONFIG_BIAS_DISABLE:
670 if ((res & ATMEL_PIO_PUEN_MASK) ||
671 ((res & ATMEL_PIO_PDEN_MASK)))
672 return -EINVAL;
673 arg = 1;
674 break;
675 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
676 if (!(res & ATMEL_PIO_OPD_MASK))
677 return -EINVAL;
678 arg = 1;
679 break;
680 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
681 if (!(res & ATMEL_PIO_SCHMITT_MASK))
682 return -EINVAL;
683 arg = 1;
684 break;
685 default:
686 return -ENOTSUPP;
687 }
688
689 *config = pinconf_to_config_packed(param, arg);
690 return 0;
691}
692
693static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
694 unsigned group,
695 unsigned long *configs,
696 unsigned num_configs)
697{
698 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
699 struct atmel_group *grp = atmel_pioctrl->groups + group;
700 unsigned bank, pin, pin_id = grp->pin;
701 u32 mask, conf = 0;
702 int i;
703
704 conf = atmel_pin_config_read(pctldev, pin_id);
705
706 for (i = 0; i < num_configs; i++) {
707 unsigned param = pinconf_to_config_param(configs[i]);
708 unsigned arg = pinconf_to_config_argument(configs[i]);
709
710 dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
711 __func__, pin_id, configs[i]);
712
713 switch (param) {
714 case PIN_CONFIG_BIAS_DISABLE:
715 conf &= (~ATMEL_PIO_PUEN_MASK);
716 conf &= (~ATMEL_PIO_PDEN_MASK);
717 break;
718 case PIN_CONFIG_BIAS_PULL_UP:
719 conf |= ATMEL_PIO_PUEN_MASK;
720 break;
721 case PIN_CONFIG_BIAS_PULL_DOWN:
722 conf |= ATMEL_PIO_PDEN_MASK;
723 break;
724 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
725 if (arg == 0)
726 conf &= (~ATMEL_PIO_OPD_MASK);
727 else
728 conf |= ATMEL_PIO_OPD_MASK;
729 break;
730 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
731 if (arg == 0)
732 conf |= ATMEL_PIO_SCHMITT_MASK;
733 else
734 conf &= (~ATMEL_PIO_SCHMITT_MASK);
735 break;
736 case PIN_CONFIG_INPUT_DEBOUNCE:
737 if (arg == 0) {
738 conf &= (~ATMEL_PIO_IFEN_MASK);
739 conf &= (~ATMEL_PIO_IFSCEN_MASK);
740 } else {
741 /*
742 * We don't care about the debounce value for several reasons:
743 * - can't have different debounce periods inside a same group,
744 * - the register to configure this period is a secure register.
745 * The debouncing filter can filter a pulse with a duration of less
746 * than 1/2 slow clock period.
747 */
748 conf |= ATMEL_PIO_IFEN_MASK;
749 conf |= ATMEL_PIO_IFSCEN_MASK;
750 }
751 break;
752 case PIN_CONFIG_OUTPUT:
753 conf |= ATMEL_PIO_DIR_MASK;
754 bank = ATMEL_PIO_BANK(pin_id);
755 pin = ATMEL_PIO_LINE(pin_id);
756 mask = 1 << pin;
757
758 if (arg == 0) {
759 writel_relaxed(mask, atmel_pioctrl->reg_base +
760 bank * ATMEL_PIO_BANK_OFFSET +
761 ATMEL_PIO_CODR);
762 } else {
763 writel_relaxed(mask, atmel_pioctrl->reg_base +
764 bank * ATMEL_PIO_BANK_OFFSET +
765 ATMEL_PIO_SODR);
766 }
767 break;
768 default:
769 dev_warn(pctldev->dev,
770 "unsupported configuration parameter: %u\n",
771 param);
772 continue;
773 }
774 }
775
776 dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf);
777 atmel_pin_config_write(pctldev, pin_id, conf);
778
779 return 0;
780}
781
782static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
783 struct seq_file *s, unsigned pin_id)
784{
785 struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
786 u32 conf;
787
788 if (!atmel_pioctrl->pins[pin_id]->device)
789 return;
790
791 if (atmel_pioctrl->pins[pin_id])
792 seq_printf(s, " (%s, ioset %u) ",
793 atmel_pioctrl->pins[pin_id]->device,
794 atmel_pioctrl->pins[pin_id]->ioset);
795
796 conf = atmel_pin_config_read(pctldev, pin_id);
797 if (conf & ATMEL_PIO_PUEN_MASK)
798 seq_printf(s, "%s ", "pull-up");
799 if (conf & ATMEL_PIO_PDEN_MASK)
800 seq_printf(s, "%s ", "pull-down");
801 if (conf & ATMEL_PIO_IFEN_MASK)
802 seq_printf(s, "%s ", "debounce");
803 if (conf & ATMEL_PIO_OPD_MASK)
804 seq_printf(s, "%s ", "open-drain");
805 if (conf & ATMEL_PIO_SCHMITT_MASK)
806 seq_printf(s, "%s ", "schmitt");
807}
808
809static const struct pinconf_ops atmel_confops = {
810 .pin_config_group_get = atmel_conf_pin_config_group_get,
811 .pin_config_group_set = atmel_conf_pin_config_group_set,
812 .pin_config_dbg_show = atmel_conf_pin_config_dbg_show,
813};
814
815static struct pinctrl_desc atmel_pinctrl_desc = {
816 .name = "atmel_pinctrl",
817 .confops = &atmel_confops,
818 .pctlops = &atmel_pctlops,
819 .pmxops = &atmel_pmxops,
820};
821
822static int atmel_pctrl_suspend(struct device *dev)
823{
824 struct platform_device *pdev = to_platform_device(dev);
825 struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
826 int i;
827
828 /*
829 * For each bank, save IMR to restore it later and disable all GPIO
830 * interrupts excepting the ones marked as wakeup sources.
831 */
832 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
833 atmel_pioctrl->pm_suspend_backup[i] =
834 atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR);
835 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR,
836 ~atmel_pioctrl->pm_wakeup_sources[i]);
837 }
838
839 return 0;
840}
841
842static int atmel_pctrl_resume(struct device *dev)
843{
844 struct platform_device *pdev = to_platform_device(dev);
845 struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
846 int i;
847
848 for (i = 0; i < atmel_pioctrl->nbanks; i++)
849 atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER,
850 atmel_pioctrl->pm_suspend_backup[i]);
851
852 return 0;
853}
854
855static const struct dev_pm_ops atmel_pctrl_pm_ops = {
856 SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume)
857};
858
859/*
860 * The number of banks can be different from a SoC to another one.
861 * We can have up to 16 banks.
862 */
863static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
864 .nbanks = 4,
865};
866
867static const struct of_device_id atmel_pctrl_of_match[] = {
868 {
869 .compatible = "atmel,sama5d2-pinctrl",
870 .data = &atmel_sama5d2_pioctrl_data,
871 }, {
872 /* sentinel */
873 }
874};
875MODULE_DEVICE_TABLE(of, atmel_pctrl_of_match);
876
877static int atmel_pinctrl_probe(struct platform_device *pdev)
878{
879 struct device *dev = &pdev->dev;
880 struct pinctrl_pin_desc *pin_desc;
881 const char **group_names;
882 const struct of_device_id *match;
883 int i, ret;
884 struct resource *res;
885 struct atmel_pioctrl *atmel_pioctrl;
886 struct atmel_pioctrl_data *atmel_pioctrl_data;
887
888 atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL);
889 if (!atmel_pioctrl)
890 return -ENOMEM;
891 atmel_pioctrl->dev = dev;
892 atmel_pioctrl->node = dev->of_node;
893 platform_set_drvdata(pdev, atmel_pioctrl);
894
895 match = of_match_node(atmel_pctrl_of_match, dev->of_node);
896 if (!match) {
897 dev_err(dev, "unknown compatible string\n");
898 return -ENODEV;
899 }
900 atmel_pioctrl_data = (struct atmel_pioctrl_data *)match->data;
901 atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
902 atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
903
904 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
905 if (!res) {
906 dev_err(dev, "unable to get atmel pinctrl resource\n");
907 return -EINVAL;
908 }
909 atmel_pioctrl->reg_base = devm_ioremap_resource(dev, res);
910 if (IS_ERR(atmel_pioctrl->reg_base))
911 return -EINVAL;
912
913 atmel_pioctrl->clk = devm_clk_get(dev, NULL);
914 if (IS_ERR(atmel_pioctrl->clk)) {
915 dev_err(dev, "failed to get clock\n");
916 return PTR_ERR(atmel_pioctrl->clk);
917 }
918
919 atmel_pioctrl->pins = devm_kzalloc(dev, sizeof(*atmel_pioctrl->pins)
920 * atmel_pioctrl->npins, GFP_KERNEL);
921 if (!atmel_pioctrl->pins)
922 return -ENOMEM;
923
924 pin_desc = devm_kzalloc(dev, sizeof(*pin_desc)
925 * atmel_pioctrl->npins, GFP_KERNEL);
926 if (!pin_desc)
927 return -ENOMEM;
928 atmel_pinctrl_desc.pins = pin_desc;
929 atmel_pinctrl_desc.npins = atmel_pioctrl->npins;
930
931 /* One pin is one group since a pin can achieve all functions. */
932 group_names = devm_kzalloc(dev, sizeof(*group_names)
933 * atmel_pioctrl->npins, GFP_KERNEL);
934 if (!group_names)
935 return -ENOMEM;
936 atmel_pioctrl->group_names = group_names;
937
938 atmel_pioctrl->groups = devm_kzalloc(&pdev->dev,
939 sizeof(*atmel_pioctrl->groups) * atmel_pioctrl->npins,
940 GFP_KERNEL);
941 if (!atmel_pioctrl->groups)
942 return -ENOMEM;
943 for (i = 0 ; i < atmel_pioctrl->npins; i++) {
944 struct atmel_group *group = atmel_pioctrl->groups + i;
945 unsigned bank = ATMEL_PIO_BANK(i);
946 unsigned line = ATMEL_PIO_LINE(i);
947
948 atmel_pioctrl->pins[i] = devm_kzalloc(dev,
949 sizeof(**atmel_pioctrl->pins), GFP_KERNEL);
950 if (!atmel_pioctrl->pins[i])
951 return -ENOMEM;
952
953 atmel_pioctrl->pins[i]->pin_id = i;
954 atmel_pioctrl->pins[i]->bank = bank;
955 atmel_pioctrl->pins[i]->line = line;
956
957 pin_desc[i].number = i;
958 /* Pin naming convention: P(bank_name)(bank_pin_number). */
959 pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
960 bank + 'A', line);
961
962 group->name = group_names[i] = pin_desc[i].name;
963 group->pin = pin_desc[i].number;
964
965 dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line);
966 }
967
968 atmel_pioctrl->gpio_chip = &atmel_gpio_chip;
969 atmel_pioctrl->gpio_chip->of_node = dev->of_node;
970 atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins;
971 atmel_pioctrl->gpio_chip->label = dev_name(dev);
972 atmel_pioctrl->gpio_chip->dev = dev;
973 atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names;
974
975 atmel_pioctrl->pm_wakeup_sources = devm_kzalloc(dev,
976 sizeof(*atmel_pioctrl->pm_wakeup_sources)
977 * atmel_pioctrl->nbanks, GFP_KERNEL);
978 if (!atmel_pioctrl->pm_wakeup_sources)
979 return -ENOMEM;
980
981 atmel_pioctrl->pm_suspend_backup = devm_kzalloc(dev,
982 sizeof(*atmel_pioctrl->pm_suspend_backup)
983 * atmel_pioctrl->nbanks, GFP_KERNEL);
984 if (!atmel_pioctrl->pm_suspend_backup)
985 return -ENOMEM;
986
987 atmel_pioctrl->irqs = devm_kzalloc(dev, sizeof(*atmel_pioctrl->irqs)
988 * atmel_pioctrl->nbanks, GFP_KERNEL);
989 if (!atmel_pioctrl->irqs)
990 return -ENOMEM;
991
992 /* There is one controller but each bank has its own irq line. */
993 for (i = 0; i < atmel_pioctrl->nbanks; i++) {
994 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
995 if (!res) {
996 dev_err(dev, "missing irq resource for group %c\n",
997 'A' + i);
998 return -EINVAL;
999 }
1000 atmel_pioctrl->irqs[i] = res->start;
1001 irq_set_chained_handler(res->start, atmel_gpio_irq_handler);
1002 irq_set_handler_data(res->start, atmel_pioctrl);
1003 dev_dbg(dev, "bank %i: hwirq=%u\n", i, res->start);
1004 }
1005
1006 atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
1007 atmel_pioctrl->gpio_chip->ngpio,
1008 &irq_domain_simple_ops, NULL);
1009 if (!atmel_pioctrl->irq_domain) {
1010 dev_err(dev, "can't add the irq domain\n");
1011 return -ENODEV;
1012 }
1013 atmel_pioctrl->irq_domain->name = "atmel gpio";
1014
1015 for (i = 0; i < atmel_pioctrl->npins; i++) {
1016 int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);
1017
1018 irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip,
1019 handle_simple_irq);
1020 irq_set_chip_data(irq, atmel_pioctrl);
1021 dev_dbg(dev,
1022 "atmel gpio irq domain: hwirq: %d, linux irq: %d\n",
1023 i, irq);
1024 }
1025
1026 ret = clk_prepare_enable(atmel_pioctrl->clk);
1027 if (ret) {
1028 dev_err(dev, "failed to prepare and enable clock\n");
1029 goto clk_prepare_enable_error;
1030 }
1031
1032 atmel_pioctrl->pinctrl_dev = pinctrl_register(&atmel_pinctrl_desc,
1033 &pdev->dev,
1034 atmel_pioctrl);
1035 if (!atmel_pioctrl->pinctrl_dev) {
1036 dev_err(dev, "pinctrl registration failed\n");
1037 goto pinctrl_register_error;
1038 }
1039
1040 ret = gpiochip_add(atmel_pioctrl->gpio_chip);
1041 if (ret) {
1042 dev_err(dev, "failed to add gpiochip\n");
1043 goto gpiochip_add_error;
1044 }
1045
1046 ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev),
1047 0, 0, atmel_pioctrl->gpio_chip->ngpio);
1048 if (ret) {
1049 dev_err(dev, "failed to add gpio pin range\n");
1050 goto gpiochip_add_pin_range_error;
1051 }
1052
1053 dev_info(&pdev->dev, "atmel pinctrl initialized\n");
1054
1055 return 0;
1056
1057clk_prepare_enable_error:
1058 irq_domain_remove(atmel_pioctrl->irq_domain);
1059pinctrl_register_error:
1060 clk_disable_unprepare(atmel_pioctrl->clk);
1061gpiochip_add_error:
1062 pinctrl_unregister(atmel_pioctrl->pinctrl_dev);
1063gpiochip_add_pin_range_error:
1064 gpiochip_remove(atmel_pioctrl->gpio_chip);
1065
1066 return ret;
1067}
1068
1069int atmel_pinctrl_remove(struct platform_device *pdev)
1070{
1071 struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
1072
1073 irq_domain_remove(atmel_pioctrl->irq_domain);
1074 clk_disable_unprepare(atmel_pioctrl->clk);
1075 pinctrl_unregister(atmel_pioctrl->pinctrl_dev);
1076 gpiochip_remove(atmel_pioctrl->gpio_chip);
1077
1078 return 0;
1079}
1080
1081static struct platform_driver atmel_pinctrl_driver = {
1082 .driver = {
1083 .name = "pinctrl-at91-pio4",
1084 .of_match_table = atmel_pctrl_of_match,
1085 .pm = &atmel_pctrl_pm_ops,
1086 },
1087 .probe = atmel_pinctrl_probe,
1088 .remove = atmel_pinctrl_remove,
1089};
1090module_platform_driver(atmel_pinctrl_driver);
1091
1092MODULE_AUTHOR(Ludovic Desroches <ludovic.desroches@atmel.com>);
1093MODULE_DESCRIPTION("Atmel PIO4 pinctrl driver");
1094MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index b0fde0f385e6..7a828ae6716b 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -1122,8 +1122,10 @@ static int at91_pinctrl_parse_functions(struct device_node *np,
1122 func->groups[i] = child->name; 1122 func->groups[i] = child->name;
1123 grp = &info->groups[grp_index++]; 1123 grp = &info->groups[grp_index++];
1124 ret = at91_pinctrl_parse_groups(child, grp, info, i++); 1124 ret = at91_pinctrl_parse_groups(child, grp, info, i++);
1125 if (ret) 1125 if (ret) {
1126 of_node_put(child);
1126 return ret; 1127 return ret;
1128 }
1127 } 1129 }
1128 1130
1129 return 0; 1131 return 0;
@@ -1196,6 +1198,7 @@ static int at91_pinctrl_probe_dt(struct platform_device *pdev,
1196 ret = at91_pinctrl_parse_functions(child, info, i++); 1198 ret = at91_pinctrl_parse_functions(child, info, i++);
1197 if (ret) { 1199 if (ret) {
1198 dev_err(&pdev->dev, "failed to parse function\n"); 1200 dev_err(&pdev->dev, "failed to parse function\n");
1201 of_node_put(child);
1199 return ret; 1202 return ret;
1200 } 1203 }
1201 } 1204 }
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 88bb707e107a..3d020fdc7bb6 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2089,6 +2089,21 @@ static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2089 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2089 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2090}; 2090};
2091 2091
2092static struct rockchip_pin_bank rk3036_pin_banks[] = {
2093 PIN_BANK(0, 32, "gpio0"),
2094 PIN_BANK(1, 32, "gpio1"),
2095 PIN_BANK(2, 32, "gpio2"),
2096};
2097
2098static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2099 .pin_banks = rk3036_pin_banks,
2100 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
2101 .label = "RK3036-GPIO",
2102 .type = RK2928,
2103 .grf_mux_offset = 0xa8,
2104 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2105};
2106
2092static struct rockchip_pin_bank rk3066a_pin_banks[] = { 2107static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2093 PIN_BANK(0, 32, "gpio0"), 2108 PIN_BANK(0, 32, "gpio0"),
2094 PIN_BANK(1, 32, "gpio1"), 2109 PIN_BANK(1, 32, "gpio1"),
@@ -2207,6 +2222,8 @@ static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
2207static const struct of_device_id rockchip_pinctrl_dt_match[] = { 2222static const struct of_device_id rockchip_pinctrl_dt_match[] = {
2208 { .compatible = "rockchip,rk2928-pinctrl", 2223 { .compatible = "rockchip,rk2928-pinctrl",
2209 .data = (void *)&rk2928_pin_ctrl }, 2224 .data = (void *)&rk2928_pin_ctrl },
2225 { .compatible = "rockchip,rk3036-pinctrl",
2226 .data = (void *)&rk3036_pin_ctrl },
2210 { .compatible = "rockchip,rk3066a-pinctrl", 2227 { .compatible = "rockchip,rk3066a-pinctrl",
2211 .data = (void *)&rk3066a_pin_ctrl }, 2228 .data = (void *)&rk3066a_pin_ctrl },
2212 { .compatible = "rockchip,rk3066b-pinctrl", 2229 { .compatible = "rockchip,rk3066b-pinctrl",
diff --git a/drivers/pinctrl/pinctrl-tegra-xusb.c b/drivers/pinctrl/pinctrl-tegra-xusb.c
index 2651d04bd1be..84a43e612952 100644
--- a/drivers/pinctrl/pinctrl-tegra-xusb.c
+++ b/drivers/pinctrl/pinctrl-tegra-xusb.c
@@ -760,24 +760,15 @@ static const char * const tegra124_pcie_groups[] = {
760 "pcie-2", 760 "pcie-2",
761 "pcie-3", 761 "pcie-3",
762 "pcie-4", 762 "pcie-4",
763 "sata-0",
764}; 763};
765 764
766static const char * const tegra124_usb3_groups[] = { 765static const char * const tegra124_usb3_groups[] = {
767 "pcie-0", 766 "pcie-0",
768 "pcie-1", 767 "pcie-1",
769 "pcie-2",
770 "pcie-3",
771 "pcie-4",
772 "sata-0", 768 "sata-0",
773}; 769};
774 770
775static const char * const tegra124_sata_groups[] = { 771static const char * const tegra124_sata_groups[] = {
776 "pcie-0",
777 "pcie-1",
778 "pcie-2",
779 "pcie-3",
780 "pcie-4",
781 "sata-0", 772 "sata-0",
782}; 773};
783 774
diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c
index c349911708ef..b89ad3c0c731 100644
--- a/drivers/pinctrl/pinctrl-tz1090-pdc.c
+++ b/drivers/pinctrl/pinctrl-tz1090-pdc.c
@@ -668,7 +668,7 @@ static int tz1090_pdc_pinconf_reg(struct pinctrl_dev *pctldev,
668 break; 668 break;
669 default: 669 default:
670 return -ENOTSUPP; 670 return -ENOTSUPP;
671 }; 671 }
672 672
673 /* Only input bias parameters supported */ 673 /* Only input bias parameters supported */
674 *reg = REG_GPIO_CONTROL2; 674 *reg = REG_GPIO_CONTROL2;
@@ -801,7 +801,7 @@ static int tz1090_pdc_pinconf_group_reg(struct pinctrl_dev *pctldev,
801 break; 801 break;
802 default: 802 default:
803 return -ENOTSUPP; 803 return -ENOTSUPP;
804 }; 804 }
805 805
806 /* Calculate field information */ 806 /* Calculate field information */
807 *mask = (BIT(*width) - 1) << *shift; 807 *mask = (BIT(*width) - 1) << *shift;
diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c
index 6d07a2f64d97..5425299d759d 100644
--- a/drivers/pinctrl/pinctrl-tz1090.c
+++ b/drivers/pinctrl/pinctrl-tz1090.c
@@ -1661,7 +1661,7 @@ static int tz1090_pinconf_reg(struct pinctrl_dev *pctldev,
1661 break; 1661 break;
1662 default: 1662 default:
1663 return -ENOTSUPP; 1663 return -ENOTSUPP;
1664 }; 1664 }
1665 1665
1666 /* Only input bias parameters supported */ 1666 /* Only input bias parameters supported */
1667 pu = &tz1090_pinconf_pullup[pin]; 1667 pu = &tz1090_pinconf_pullup[pin];
@@ -1790,7 +1790,7 @@ static int tz1090_pinconf_group_reg(struct pinctrl_dev *pctldev,
1790 break; 1790 break;
1791 default: 1791 default:
1792 return -ENOTSUPP; 1792 return -ENOTSUPP;
1793 }; 1793 }
1794 1794
1795 /* Calculate field information */ 1795 /* Calculate field information */
1796 *shift = g->slw_bit * *width; 1796 *shift = g->slw_bit * *width;
diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c
index 5aafea8c6590..d57b5eca7b98 100644
--- a/drivers/pinctrl/pinctrl-zynq.c
+++ b/drivers/pinctrl/pinctrl-zynq.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 2014 Xilinx 4 * Copyright (C) 2014 Xilinx
5 * 5 *
6 * Sören Brinkmann <soren.brinkmann@xilinx.com> 6 * Sören Brinkmann <soren.brinkmann@xilinx.com>
7 * 7 *
8 * This program is free software: you can redistribute it and/or modify 8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -1230,8 +1230,18 @@ static struct platform_driver zynq_pinctrl_driver = {
1230 .remove = zynq_pinctrl_remove, 1230 .remove = zynq_pinctrl_remove,
1231}; 1231};
1232 1232
1233module_platform_driver(zynq_pinctrl_driver); 1233static int __init zynq_pinctrl_init(void)
1234{
1235 return platform_driver_register(&zynq_pinctrl_driver);
1236}
1237arch_initcall(zynq_pinctrl_init);
1238
1239static void __exit zynq_pinctrl_exit(void)
1240{
1241 platform_driver_unregister(&zynq_pinctrl_driver);
1242}
1243module_exit(zynq_pinctrl_exit);
1234 1244
1235MODULE_AUTHOR("Sören Brinkmann <soren.brinkmann@xilinx.com>"); 1245MODULE_AUTHOR("Sören Brinkmann <soren.brinkmann@xilinx.com>");
1236MODULE_DESCRIPTION("Xilinx Zynq pinctrl driver"); 1246MODULE_DESCRIPTION("Xilinx Zynq pinctrl driver");
1237MODULE_LICENSE("GPL"); 1247MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
index e1a3721bc8e5..d809c9eaa323 100644
--- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
+++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
@@ -584,7 +584,7 @@ static void pm8xxx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
584} 584}
585 585
586#else 586#else
587#define msm_gpio_dbg_show NULL 587#define pm8xxx_gpio_dbg_show NULL
588#endif 588#endif
589 589
590static struct gpio_chip pm8xxx_gpio_template = { 590static struct gpio_chip pm8xxx_gpio_template = {
diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
index 6652b8d7f707..8982027de8e8 100644
--- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
+++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
@@ -639,7 +639,7 @@ static void pm8xxx_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip)
639} 639}
640 640
641#else 641#else
642#define msm_mpp_dbg_show NULL 642#define pm8xxx_mpp_dbg_show NULL
643#endif 643#endif
644 644
645static struct gpio_chip pm8xxx_mpp_template = { 645static struct gpio_chip pm8xxx_mpp_template = {
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos5440.c b/drivers/pinctrl/samsung/pinctrl-exynos5440.c
index 9ce0b8619d4c..82dc109f7ed4 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos5440.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos5440.c
@@ -284,7 +284,7 @@ static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev,
284 if (!idx) 284 if (!idx)
285 kfree(map[idx].data.configs.group_or_pin); 285 kfree(map[idx].data.configs.group_or_pin);
286 } 286 }
287 }; 287 }
288 288
289 kfree(map); 289 kfree(map);
290} 290}
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index 8e024c9c9115..35d6e95fa21f 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -65,6 +65,11 @@ config PINCTRL_PFC_R8A7794
65 depends on ARCH_R8A7794 65 depends on ARCH_R8A7794
66 select PINCTRL_SH_PFC 66 select PINCTRL_SH_PFC
67 67
68config PINCTRL_PFC_R8A7795
69 def_bool y
70 depends on ARCH_R8A7795
71 select PINCTRL_SH_PFC
72
68config PINCTRL_PFC_SH7203 73config PINCTRL_PFC_SH7203
69 def_bool y 74 def_bool y
70 depends on CPU_SUBTYPE_SH7203 75 depends on CPU_SUBTYPE_SH7203
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index ea2a60ef122a..173305fa3811 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
12obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o 12obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
13obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o 13obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
14obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o 14obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
15obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
15obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o 16obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
16obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o 17obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
17obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o 18obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index fb9c44805234..181ea98a63b7 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -272,7 +272,7 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
272static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos, 272static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
273 u16 *enum_idp) 273 u16 *enum_idp)
274{ 274{
275 const u16 *data = pfc->info->gpio_data; 275 const u16 *data = pfc->info->pinmux_data;
276 unsigned int k; 276 unsigned int k;
277 277
278 if (pos) { 278 if (pos) {
@@ -280,7 +280,7 @@ static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
280 return pos + 1; 280 return pos + 1;
281 } 281 }
282 282
283 for (k = 0; k < pfc->info->gpio_data_size; k++) { 283 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
284 if (data[k] == mark) { 284 if (data[k] == mark) {
285 *enum_idp = data[k + 1]; 285 *enum_idp = data[k + 1];
286 return k + 1; 286 return k + 1;
@@ -489,6 +489,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
489 .data = &r8a7794_pinmux_info, 489 .data = &r8a7794_pinmux_info,
490 }, 490 },
491#endif 491#endif
492#ifdef CONFIG_PINCTRL_PFC_R8A7795
493 {
494 .compatible = "renesas,pfc-r8a7795",
495 .data = &r8a7795_pinmux_info,
496 },
497#endif
492#ifdef CONFIG_PINCTRL_PFC_SH73A0 498#ifdef CONFIG_PINCTRL_PFC_SH73A0
493 { 499 {
494 .compatible = "renesas,pfc-sh73a0", 500 .compatible = "renesas,pfc-sh73a0",
@@ -587,12 +593,6 @@ static int sh_pfc_remove(struct platform_device *pdev)
587} 593}
588 594
589static const struct platform_device_id sh_pfc_id_table[] = { 595static const struct platform_device_id sh_pfc_id_table[] = {
590#ifdef CONFIG_PINCTRL_PFC_R8A7778
591 { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
592#endif
593#ifdef CONFIG_PINCTRL_PFC_R8A7779
594 { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
595#endif
596#ifdef CONFIG_PINCTRL_PFC_SH7203 596#ifdef CONFIG_PINCTRL_PFC_SH7203
597 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info }, 597 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
598#endif 598#endif
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 4c3c37bf7161..62f53b22ae85 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -46,7 +46,9 @@ struct sh_pfc {
46 unsigned int nr_gpio_pins; 46 unsigned int nr_gpio_pins;
47 47
48 struct sh_pfc_chip *gpio; 48 struct sh_pfc_chip *gpio;
49#ifdef CONFIG_SUPERH
49 struct sh_pfc_chip *func; 50 struct sh_pfc_chip *func;
51#endif
50 52
51 struct sh_pfc_pinctrl *pinctrl; 53 struct sh_pfc_pinctrl *pinctrl;
52}; 54};
@@ -73,6 +75,7 @@ extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
73extern const struct sh_pfc_soc_info r8a7791_pinmux_info; 75extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
74extern const struct sh_pfc_soc_info r8a7793_pinmux_info; 76extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
75extern const struct sh_pfc_soc_info r8a7794_pinmux_info; 77extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
78extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
76extern const struct sh_pfc_soc_info sh7203_pinmux_info; 79extern const struct sh_pfc_soc_info sh7203_pinmux_info;
77extern const struct sh_pfc_soc_info sh7264_pinmux_info; 80extern const struct sh_pfc_soc_info sh7264_pinmux_info;
78extern const struct sh_pfc_soc_info sh7269_pinmux_info; 81extern const struct sh_pfc_soc_info sh7269_pinmux_info;
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index ba353735ecf2..db3f09aa8993 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -219,10 +219,7 @@ static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
219 return -ENOSYS; 219 return -ENOSYS;
220 220
221found: 221found:
222 if (pfc->num_irqs) 222 return pfc->irqs[i];
223 return pfc->irqs[i];
224 else
225 return pfc->info->gpio_irq[i].irq;
226} 223}
227 224
228static int gpio_pin_setup(struct sh_pfc_chip *chip) 225static int gpio_pin_setup(struct sh_pfc_chip *chip)
@@ -261,6 +258,7 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip)
261 * Function GPIOs 258 * Function GPIOs
262 */ 259 */
263 260
261#ifdef CONFIG_SUPERH
264static int gpio_function_request(struct gpio_chip *gc, unsigned offset) 262static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
265{ 263{
266 static bool __print_once; 264 static bool __print_once;
@@ -286,17 +284,12 @@ static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
286 return ret; 284 return ret;
287} 285}
288 286
289static void gpio_function_free(struct gpio_chip *gc, unsigned offset)
290{
291}
292
293static int gpio_function_setup(struct sh_pfc_chip *chip) 287static int gpio_function_setup(struct sh_pfc_chip *chip)
294{ 288{
295 struct sh_pfc *pfc = chip->pfc; 289 struct sh_pfc *pfc = chip->pfc;
296 struct gpio_chip *gc = &chip->gpio_chip; 290 struct gpio_chip *gc = &chip->gpio_chip;
297 291
298 gc->request = gpio_function_request; 292 gc->request = gpio_function_request;
299 gc->free = gpio_function_free;
300 293
301 gc->label = pfc->info->name; 294 gc->label = pfc->info->name;
302 gc->owner = THIS_MODULE; 295 gc->owner = THIS_MODULE;
@@ -305,6 +298,7 @@ static int gpio_function_setup(struct sh_pfc_chip *chip)
305 298
306 return 0; 299 return 0;
307} 300}
301#endif
308 302
309/* ----------------------------------------------------------------------------- 303/* -----------------------------------------------------------------------------
310 * Register/unregister 304 * Register/unregister
@@ -344,7 +338,6 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
344 struct sh_pfc_chip *chip; 338 struct sh_pfc_chip *chip;
345 phys_addr_t address; 339 phys_addr_t address;
346 unsigned int i; 340 unsigned int i;
347 int ret;
348 341
349 if (pfc->info->data_regs == NULL) 342 if (pfc->info->data_regs == NULL)
350 return 0; 343 return 0;
@@ -367,7 +360,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
367 return 0; 360 return 0;
368 361
369 /* If we have IRQ resources make sure their number is correct. */ 362 /* If we have IRQ resources make sure their number is correct. */
370 if (pfc->num_irqs && pfc->num_irqs != pfc->info->gpio_irq_size) { 363 if (pfc->num_irqs != pfc->info->gpio_irq_size) {
371 dev_err(pfc->dev, "invalid number of IRQ resources\n"); 364 dev_err(pfc->dev, "invalid number of IRQ resources\n");
372 return -EINVAL; 365 return -EINVAL;
373 } 366 }
@@ -379,20 +372,26 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
379 372
380 pfc->gpio = chip; 373 pfc->gpio = chip;
381 374
382 /* Register the GPIO to pin mappings. As pins with GPIO ports must come 375 if (IS_ENABLED(CONFIG_OF) && pfc->dev->of_node)
383 * first in the ranges, skip the pins without GPIO ports by stopping at 376 return 0;
384 * the first range that contains such a pin. 377
378#ifdef CONFIG_SUPERH
379 /*
380 * Register the GPIO to pin mappings. As pins with GPIO ports
381 * must come first in the ranges, skip the pins without GPIO
382 * ports by stopping at the first range that contains such a
383 * pin.
385 */ 384 */
386 for (i = 0; i < pfc->nr_ranges; ++i) { 385 for (i = 0; i < pfc->nr_ranges; ++i) {
387 const struct sh_pfc_pin_range *range = &pfc->ranges[i]; 386 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
387 int ret;
388 388
389 if (range->start >= pfc->nr_gpio_pins) 389 if (range->start >= pfc->nr_gpio_pins)
390 break; 390 break;
391 391
392 ret = gpiochip_add_pin_range(&chip->gpio_chip, 392 ret = gpiochip_add_pin_range(&chip->gpio_chip,
393 dev_name(pfc->dev), 393 dev_name(pfc->dev), range->start, range->start,
394 range->start, range->start, 394 range->end - range->start + 1);
395 range->end - range->start + 1);
396 if (ret < 0) 395 if (ret < 0)
397 return ret; 396 return ret;
398 } 397 }
@@ -406,6 +405,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
406 return PTR_ERR(chip); 405 return PTR_ERR(chip);
407 406
408 pfc->func = chip; 407 pfc->func = chip;
408#endif /* CONFIG_SUPERH */
409 409
410 return 0; 410 return 0;
411} 411}
@@ -413,7 +413,8 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
413int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc) 413int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc)
414{ 414{
415 gpiochip_remove(&pfc->gpio->gpio_chip); 415 gpiochip_remove(&pfc->gpio->gpio_chip);
416#ifdef CONFIG_SUPERH
416 gpiochip_remove(&pfc->func->gpio_chip); 417 gpiochip_remove(&pfc->func->gpio_chip);
417 418#endif
418 return 0; 419 return 0;
419} 420}
diff --git a/drivers/pinctrl/sh-pfc/pfc-emev2.c b/drivers/pinctrl/sh-pfc/pfc-emev2.c
index 849c6943ed30..02118ab336fc 100644
--- a/drivers/pinctrl/sh-pfc/pfc-emev2.c
+++ b/drivers/pinctrl/sh-pfc/pfc-emev2.c
@@ -1706,6 +1706,6 @@ const struct sh_pfc_soc_info emev2_pinmux_info = {
1706 1706
1707 .cfg_regs = pinmux_config_regs, 1707 .cfg_regs = pinmux_config_regs,
1708 1708
1709 .gpio_data = pinmux_data, 1709 .pinmux_data = pinmux_data,
1710 .gpio_data_size = ARRAY_SIZE(pinmux_data), 1710 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
1711}; 1711};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index ba18d2e65e67..d9d9228b15fa 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -2603,64 +2603,64 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
2603}; 2603};
2604 2604
2605static const struct pinmux_irq pinmux_irqs[] = { 2605static const struct pinmux_irq pinmux_irqs[] = {
2606 PINMUX_IRQ(irq_pin(0), 0), 2606 PINMUX_IRQ(0), /* IRQ0 */
2607 PINMUX_IRQ(irq_pin(1), 1), 2607 PINMUX_IRQ(1), /* IRQ1 */
2608 PINMUX_IRQ(irq_pin(2), 2), 2608 PINMUX_IRQ(2), /* IRQ2 */
2609 PINMUX_IRQ(irq_pin(3), 3), 2609 PINMUX_IRQ(3), /* IRQ3 */
2610 PINMUX_IRQ(irq_pin(4), 4), 2610 PINMUX_IRQ(4), /* IRQ4 */
2611 PINMUX_IRQ(irq_pin(5), 5), 2611 PINMUX_IRQ(5), /* IRQ5 */
2612 PINMUX_IRQ(irq_pin(6), 6), 2612 PINMUX_IRQ(6), /* IRQ6 */
2613 PINMUX_IRQ(irq_pin(7), 7), 2613 PINMUX_IRQ(7), /* IRQ7 */
2614 PINMUX_IRQ(irq_pin(8), 8), 2614 PINMUX_IRQ(8), /* IRQ8 */
2615 PINMUX_IRQ(irq_pin(9), 9), 2615 PINMUX_IRQ(9), /* IRQ9 */
2616 PINMUX_IRQ(irq_pin(10), 10), 2616 PINMUX_IRQ(10), /* IRQ10 */
2617 PINMUX_IRQ(irq_pin(11), 11), 2617 PINMUX_IRQ(11), /* IRQ11 */
2618 PINMUX_IRQ(irq_pin(12), 12), 2618 PINMUX_IRQ(12), /* IRQ12 */
2619 PINMUX_IRQ(irq_pin(13), 13), 2619 PINMUX_IRQ(13), /* IRQ13 */
2620 PINMUX_IRQ(irq_pin(14), 14), 2620 PINMUX_IRQ(14), /* IRQ14 */
2621 PINMUX_IRQ(irq_pin(15), 15), 2621 PINMUX_IRQ(15), /* IRQ15 */
2622 PINMUX_IRQ(irq_pin(16), 320), 2622 PINMUX_IRQ(320), /* IRQ16 */
2623 PINMUX_IRQ(irq_pin(17), 321), 2623 PINMUX_IRQ(321), /* IRQ17 */
2624 PINMUX_IRQ(irq_pin(18), 85), 2624 PINMUX_IRQ(85), /* IRQ18 */
2625 PINMUX_IRQ(irq_pin(19), 84), 2625 PINMUX_IRQ(84), /* IRQ19 */
2626 PINMUX_IRQ(irq_pin(20), 160), 2626 PINMUX_IRQ(160), /* IRQ20 */
2627 PINMUX_IRQ(irq_pin(21), 161), 2627 PINMUX_IRQ(161), /* IRQ21 */
2628 PINMUX_IRQ(irq_pin(22), 162), 2628 PINMUX_IRQ(162), /* IRQ22 */
2629 PINMUX_IRQ(irq_pin(23), 163), 2629 PINMUX_IRQ(163), /* IRQ23 */
2630 PINMUX_IRQ(irq_pin(24), 175), 2630 PINMUX_IRQ(175), /* IRQ24 */
2631 PINMUX_IRQ(irq_pin(25), 176), 2631 PINMUX_IRQ(176), /* IRQ25 */
2632 PINMUX_IRQ(irq_pin(26), 177), 2632 PINMUX_IRQ(177), /* IRQ26 */
2633 PINMUX_IRQ(irq_pin(27), 178), 2633 PINMUX_IRQ(178), /* IRQ27 */
2634 PINMUX_IRQ(irq_pin(28), 322), 2634 PINMUX_IRQ(322), /* IRQ28 */
2635 PINMUX_IRQ(irq_pin(29), 323), 2635 PINMUX_IRQ(323), /* IRQ29 */
2636 PINMUX_IRQ(irq_pin(30), 324), 2636 PINMUX_IRQ(324), /* IRQ30 */
2637 PINMUX_IRQ(irq_pin(31), 192), 2637 PINMUX_IRQ(192), /* IRQ31 */
2638 PINMUX_IRQ(irq_pin(32), 193), 2638 PINMUX_IRQ(193), /* IRQ32 */
2639 PINMUX_IRQ(irq_pin(33), 194), 2639 PINMUX_IRQ(194), /* IRQ33 */
2640 PINMUX_IRQ(irq_pin(34), 195), 2640 PINMUX_IRQ(195), /* IRQ34 */
2641 PINMUX_IRQ(irq_pin(35), 196), 2641 PINMUX_IRQ(196), /* IRQ35 */
2642 PINMUX_IRQ(irq_pin(36), 197), 2642 PINMUX_IRQ(197), /* IRQ36 */
2643 PINMUX_IRQ(irq_pin(37), 198), 2643 PINMUX_IRQ(198), /* IRQ37 */
2644 PINMUX_IRQ(irq_pin(38), 199), 2644 PINMUX_IRQ(199), /* IRQ38 */
2645 PINMUX_IRQ(irq_pin(39), 200), 2645 PINMUX_IRQ(200), /* IRQ39 */
2646 PINMUX_IRQ(irq_pin(40), 66), 2646 PINMUX_IRQ(66), /* IRQ40 */
2647 PINMUX_IRQ(irq_pin(41), 102), 2647 PINMUX_IRQ(102), /* IRQ41 */
2648 PINMUX_IRQ(irq_pin(42), 103), 2648 PINMUX_IRQ(103), /* IRQ42 */
2649 PINMUX_IRQ(irq_pin(43), 109), 2649 PINMUX_IRQ(109), /* IRQ43 */
2650 PINMUX_IRQ(irq_pin(44), 110), 2650 PINMUX_IRQ(110), /* IRQ44 */
2651 PINMUX_IRQ(irq_pin(45), 111), 2651 PINMUX_IRQ(111), /* IRQ45 */
2652 PINMUX_IRQ(irq_pin(46), 112), 2652 PINMUX_IRQ(112), /* IRQ46 */
2653 PINMUX_IRQ(irq_pin(47), 113), 2653 PINMUX_IRQ(113), /* IRQ47 */
2654 PINMUX_IRQ(irq_pin(48), 114), 2654 PINMUX_IRQ(114), /* IRQ48 */
2655 PINMUX_IRQ(irq_pin(49), 115), 2655 PINMUX_IRQ(115), /* IRQ49 */
2656 PINMUX_IRQ(irq_pin(50), 301), 2656 PINMUX_IRQ(301), /* IRQ50 */
2657 PINMUX_IRQ(irq_pin(51), 290), 2657 PINMUX_IRQ(290), /* IRQ51 */
2658 PINMUX_IRQ(irq_pin(52), 296), 2658 PINMUX_IRQ(296), /* IRQ52 */
2659 PINMUX_IRQ(irq_pin(53), 325), 2659 PINMUX_IRQ(325), /* IRQ53 */
2660 PINMUX_IRQ(irq_pin(54), 326), 2660 PINMUX_IRQ(326), /* IRQ54 */
2661 PINMUX_IRQ(irq_pin(55), 327), 2661 PINMUX_IRQ(327), /* IRQ55 */
2662 PINMUX_IRQ(irq_pin(56), 328), 2662 PINMUX_IRQ(328), /* IRQ56 */
2663 PINMUX_IRQ(irq_pin(57), 329), 2663 PINMUX_IRQ(329), /* IRQ57 */
2664}; 2664};
2665 2665
2666#define PORTCR_PULMD_OFF (0 << 6) 2666#define PORTCR_PULMD_OFF (0 << 6)
@@ -2734,11 +2734,11 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
2734 .functions = pinmux_functions, 2734 .functions = pinmux_functions,
2735 .nr_functions = ARRAY_SIZE(pinmux_functions), 2735 .nr_functions = ARRAY_SIZE(pinmux_functions),
2736 2736
2737 .cfg_regs = pinmux_config_regs, 2737 .cfg_regs = pinmux_config_regs,
2738 .data_regs = pinmux_data_regs, 2738 .data_regs = pinmux_data_regs,
2739 2739
2740 .gpio_data = pinmux_data, 2740 .pinmux_data = pinmux_data,
2741 .gpio_data_size = ARRAY_SIZE(pinmux_data), 2741 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2742 2742
2743 .gpio_irq = pinmux_irqs, 2743 .gpio_irq = pinmux_irqs,
2744 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs), 2744 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 82ef1862dd1b..279e9dd442e4 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -3651,38 +3651,38 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
3651}; 3651};
3652 3652
3653static const struct pinmux_irq pinmux_irqs[] = { 3653static const struct pinmux_irq pinmux_irqs[] = {
3654 PINMUX_IRQ(irq_pin(0), 2, 13), /* IRQ0A */ 3654 PINMUX_IRQ(2, 13), /* IRQ0A */
3655 PINMUX_IRQ(irq_pin(1), 20), /* IRQ1A */ 3655 PINMUX_IRQ(20), /* IRQ1A */
3656 PINMUX_IRQ(irq_pin(2), 11, 12), /* IRQ2A */ 3656 PINMUX_IRQ(11, 12), /* IRQ2A */
3657 PINMUX_IRQ(irq_pin(3), 10, 14), /* IRQ3A */ 3657 PINMUX_IRQ(10, 14), /* IRQ3A */
3658 PINMUX_IRQ(irq_pin(4), 15, 172), /* IRQ4A */ 3658 PINMUX_IRQ(15, 172), /* IRQ4A */
3659 PINMUX_IRQ(irq_pin(5), 0, 1), /* IRQ5A */ 3659 PINMUX_IRQ(0, 1), /* IRQ5A */
3660 PINMUX_IRQ(irq_pin(6), 121, 173), /* IRQ6A */ 3660 PINMUX_IRQ(121, 173), /* IRQ6A */
3661 PINMUX_IRQ(irq_pin(7), 120, 209), /* IRQ7A */ 3661 PINMUX_IRQ(120, 209), /* IRQ7A */
3662 PINMUX_IRQ(irq_pin(8), 119), /* IRQ8A */ 3662 PINMUX_IRQ(119), /* IRQ8A */
3663 PINMUX_IRQ(irq_pin(9), 118, 210), /* IRQ9A */ 3663 PINMUX_IRQ(118, 210), /* IRQ9A */
3664 PINMUX_IRQ(irq_pin(10), 19), /* IRQ10A */ 3664 PINMUX_IRQ(19), /* IRQ10A */
3665 PINMUX_IRQ(irq_pin(11), 104), /* IRQ11A */ 3665 PINMUX_IRQ(104), /* IRQ11A */
3666 PINMUX_IRQ(irq_pin(12), 42, 97), /* IRQ12A */ 3666 PINMUX_IRQ(42, 97), /* IRQ12A */
3667 PINMUX_IRQ(irq_pin(13), 64, 98), /* IRQ13A */ 3667 PINMUX_IRQ(64, 98), /* IRQ13A */
3668 PINMUX_IRQ(irq_pin(14), 63, 99), /* IRQ14A */ 3668 PINMUX_IRQ(63, 99), /* IRQ14A */
3669 PINMUX_IRQ(irq_pin(15), 62, 100), /* IRQ15A */ 3669 PINMUX_IRQ(62, 100), /* IRQ15A */
3670 PINMUX_IRQ(irq_pin(16), 68, 211), /* IRQ16A */ 3670 PINMUX_IRQ(68, 211), /* IRQ16A */
3671 PINMUX_IRQ(irq_pin(17), 69), /* IRQ17A */ 3671 PINMUX_IRQ(69), /* IRQ17A */
3672 PINMUX_IRQ(irq_pin(18), 70), /* IRQ18A */ 3672 PINMUX_IRQ(70), /* IRQ18A */
3673 PINMUX_IRQ(irq_pin(19), 71), /* IRQ19A */ 3673 PINMUX_IRQ(71), /* IRQ19A */
3674 PINMUX_IRQ(irq_pin(20), 67), /* IRQ20A */ 3674 PINMUX_IRQ(67), /* IRQ20A */
3675 PINMUX_IRQ(irq_pin(21), 202), /* IRQ21A */ 3675 PINMUX_IRQ(202), /* IRQ21A */
3676 PINMUX_IRQ(irq_pin(22), 95), /* IRQ22A */ 3676 PINMUX_IRQ(95), /* IRQ22A */
3677 PINMUX_IRQ(irq_pin(23), 96), /* IRQ23A */ 3677 PINMUX_IRQ(96), /* IRQ23A */
3678 PINMUX_IRQ(irq_pin(24), 180), /* IRQ24A */ 3678 PINMUX_IRQ(180), /* IRQ24A */
3679 PINMUX_IRQ(irq_pin(25), 38), /* IRQ25A */ 3679 PINMUX_IRQ(38), /* IRQ25A */
3680 PINMUX_IRQ(irq_pin(26), 58, 81), /* IRQ26A */ 3680 PINMUX_IRQ(58, 81), /* IRQ26A */
3681 PINMUX_IRQ(irq_pin(27), 57, 168), /* IRQ27A */ 3681 PINMUX_IRQ(57, 168), /* IRQ27A */
3682 PINMUX_IRQ(irq_pin(28), 56, 169), /* IRQ28A */ 3682 PINMUX_IRQ(56, 169), /* IRQ28A */
3683 PINMUX_IRQ(irq_pin(29), 50, 170), /* IRQ29A */ 3683 PINMUX_IRQ(50, 170), /* IRQ29A */
3684 PINMUX_IRQ(irq_pin(30), 49, 171), /* IRQ30A */ 3684 PINMUX_IRQ(49, 171), /* IRQ30A */
3685 PINMUX_IRQ(irq_pin(31), 41, 167), /* IRQ31A */ 3685 PINMUX_IRQ(41, 167), /* IRQ31A */
3686}; 3686};
3687 3687
3688#define PORTnCR_PULMD_OFF (0 << 6) 3688#define PORTnCR_PULMD_OFF (0 << 6)
@@ -3774,8 +3774,8 @@ const struct sh_pfc_soc_info r8a7740_pinmux_info = {
3774 .cfg_regs = pinmux_config_regs, 3774 .cfg_regs = pinmux_config_regs,
3775 .data_regs = pinmux_data_regs, 3775 .data_regs = pinmux_data_regs,
3776 3776
3777 .gpio_data = pinmux_data, 3777 .pinmux_data = pinmux_data,
3778 .gpio_data_size = ARRAY_SIZE(pinmux_data), 3778 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3779 3779
3780 .gpio_irq = pinmux_irqs, 3780 .gpio_irq = pinmux_irqs,
3781 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs), 3781 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index c7d610d1f3ef..bbd35dc1a0c4 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -4,6 +4,7 @@
4 * Copyright (C) 2013 Renesas Solutions Corp. 4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * Copyright (C) 2013 Cogent Embedded, Inc. 6 * Copyright (C) 2013 Cogent Embedded, Inc.
7 * Copyright (C) 2015 Ulrich Hecht
7 * 8 *
8 * based on 9 * based on
9 * Copyright (C) 2011 Renesas Solutions Corp. 10 * Copyright (C) 2011 Renesas Solutions Corp.
@@ -19,32 +20,37 @@
19 * GNU General Public License for more details. 20 * GNU General Public License for more details.
20 */ 21 */
21 22
22#include <linux/platform_data/gpio-rcar.h> 23#include <linux/io.h>
23#include <linux/kernel.h> 24#include <linux/kernel.h>
25#include <linux/pinctrl/pinconf-generic.h>
26#include "core.h"
24#include "sh_pfc.h" 27#include "sh_pfc.h"
25 28
26#define PORT_GP_27(bank, fn, sfx) \ 29#define PORT_GP_PUP_1(bank, pin, fn, sfx) \
27 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ 30 PORT_GP_CFG_1(bank, pin, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
28 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ 31
29 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ 32#define PORT_GP_PUP_27(bank, fn, sfx) \
30 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ 33 PORT_GP_PUP_1(bank, 0, fn, sfx), PORT_GP_PUP_1(bank, 1, fn, sfx), \
31 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ 34 PORT_GP_PUP_1(bank, 2, fn, sfx), PORT_GP_PUP_1(bank, 3, fn, sfx), \
32 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ 35 PORT_GP_PUP_1(bank, 4, fn, sfx), PORT_GP_PUP_1(bank, 5, fn, sfx), \
33 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ 36 PORT_GP_PUP_1(bank, 6, fn, sfx), PORT_GP_PUP_1(bank, 7, fn, sfx), \
34 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ 37 PORT_GP_PUP_1(bank, 8, fn, sfx), PORT_GP_PUP_1(bank, 9, fn, sfx), \
35 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ 38 PORT_GP_PUP_1(bank, 10, fn, sfx), PORT_GP_PUP_1(bank, 11, fn, sfx), \
36 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ 39 PORT_GP_PUP_1(bank, 12, fn, sfx), PORT_GP_PUP_1(bank, 13, fn, sfx), \
37 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ 40 PORT_GP_PUP_1(bank, 14, fn, sfx), PORT_GP_PUP_1(bank, 15, fn, sfx), \
38 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ 41 PORT_GP_PUP_1(bank, 16, fn, sfx), PORT_GP_PUP_1(bank, 17, fn, sfx), \
39 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ 42 PORT_GP_PUP_1(bank, 18, fn, sfx), PORT_GP_PUP_1(bank, 19, fn, sfx), \
40 PORT_GP_1(bank, 26, fn, sfx) 43 PORT_GP_PUP_1(bank, 20, fn, sfx), PORT_GP_PUP_1(bank, 21, fn, sfx), \
44 PORT_GP_PUP_1(bank, 22, fn, sfx), PORT_GP_PUP_1(bank, 23, fn, sfx), \
45 PORT_GP_PUP_1(bank, 24, fn, sfx), PORT_GP_PUP_1(bank, 25, fn, sfx), \
46 PORT_GP_PUP_1(bank, 26, fn, sfx)
41 47
42#define CPU_ALL_PORT(fn, sfx) \ 48#define CPU_ALL_PORT(fn, sfx) \
43 PORT_GP_32(0, fn, sfx), \ 49 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
44 PORT_GP_32(1, fn, sfx), \ 50 PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
45 PORT_GP_32(2, fn, sfx), \ 51 PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
46 PORT_GP_32(3, fn, sfx), \ 52 PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
47 PORT_GP_27(4, fn, sfx) 53 PORT_GP_PUP_27(4, fn, sfx)
48 54
49enum { 55enum {
50 PINMUX_RESERVED = 0, 56 PINMUX_RESERVED = 0,
@@ -2905,8 +2911,222 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2905 { }, 2911 { },
2906}; 2912};
2907 2913
2914#define PUPR0 0x100
2915#define PUPR1 0x104
2916#define PUPR2 0x108
2917#define PUPR3 0x10c
2918#define PUPR4 0x110
2919#define PUPR5 0x114
2920
2921static const struct {
2922 u16 reg : 11;
2923 u16 bit : 5;
2924} pullups[] = {
2925 [RCAR_GP_PIN(0, 6)] = { PUPR0, 0 }, /* A0 */
2926 [RCAR_GP_PIN(0, 7)] = { PUPR0, 1 }, /* A1 */
2927 [RCAR_GP_PIN(0, 8)] = { PUPR0, 2 }, /* A2 */
2928 [RCAR_GP_PIN(0, 9)] = { PUPR0, 3 }, /* A3 */
2929 [RCAR_GP_PIN(0, 10)] = { PUPR0, 4 }, /* A4 */
2930 [RCAR_GP_PIN(0, 11)] = { PUPR0, 5 }, /* A5 */
2931 [RCAR_GP_PIN(0, 12)] = { PUPR0, 6 }, /* A6 */
2932 [RCAR_GP_PIN(0, 13)] = { PUPR0, 7 }, /* A7 */
2933 [RCAR_GP_PIN(0, 14)] = { PUPR0, 8 }, /* A8 */
2934 [RCAR_GP_PIN(0, 15)] = { PUPR0, 9 }, /* A9 */
2935 [RCAR_GP_PIN(0, 16)] = { PUPR0, 10 }, /* A10 */
2936 [RCAR_GP_PIN(0, 17)] = { PUPR0, 11 }, /* A11 */
2937 [RCAR_GP_PIN(0, 18)] = { PUPR0, 12 }, /* A12 */
2938 [RCAR_GP_PIN(0, 19)] = { PUPR0, 13 }, /* A13 */
2939 [RCAR_GP_PIN(0, 20)] = { PUPR0, 14 }, /* A14 */
2940 [RCAR_GP_PIN(0, 21)] = { PUPR0, 15 }, /* A15 */
2941 [RCAR_GP_PIN(0, 22)] = { PUPR0, 16 }, /* A16 */
2942 [RCAR_GP_PIN(0, 23)] = { PUPR0, 17 }, /* A17 */
2943 [RCAR_GP_PIN(0, 24)] = { PUPR0, 18 }, /* A18 */
2944 [RCAR_GP_PIN(0, 25)] = { PUPR0, 19 }, /* A19 */
2945 [RCAR_GP_PIN(0, 26)] = { PUPR0, 20 }, /* A20 */
2946 [RCAR_GP_PIN(0, 27)] = { PUPR0, 21 }, /* A21 */
2947 [RCAR_GP_PIN(0, 28)] = { PUPR0, 22 }, /* A22 */
2948 [RCAR_GP_PIN(0, 29)] = { PUPR0, 23 }, /* A23 */
2949 [RCAR_GP_PIN(0, 30)] = { PUPR0, 24 }, /* A24 */
2950 [RCAR_GP_PIN(0, 31)] = { PUPR0, 25 }, /* A25 */
2951 [RCAR_GP_PIN(1, 3)] = { PUPR0, 26 }, /* /EX_CS0 */
2952 [RCAR_GP_PIN(1, 4)] = { PUPR0, 27 }, /* /EX_CS1 */
2953 [RCAR_GP_PIN(1, 5)] = { PUPR0, 28 }, /* /EX_CS2 */
2954 [RCAR_GP_PIN(1, 6)] = { PUPR0, 29 }, /* /EX_CS3 */
2955 [RCAR_GP_PIN(1, 7)] = { PUPR0, 30 }, /* /EX_CS4 */
2956 [RCAR_GP_PIN(1, 8)] = { PUPR0, 31 }, /* /EX_CS5 */
2957
2958 [RCAR_GP_PIN(0, 0)] = { PUPR1, 0 }, /* /PRESETOUT */
2959 [RCAR_GP_PIN(0, 5)] = { PUPR1, 1 }, /* /BS */
2960 [RCAR_GP_PIN(1, 0)] = { PUPR1, 2 }, /* RD//WR */
2961 [RCAR_GP_PIN(1, 1)] = { PUPR1, 3 }, /* /WE0 */
2962 [RCAR_GP_PIN(1, 2)] = { PUPR1, 4 }, /* /WE1 */
2963 [RCAR_GP_PIN(1, 11)] = { PUPR1, 5 }, /* EX_WAIT0 */
2964 [RCAR_GP_PIN(1, 9)] = { PUPR1, 6 }, /* DREQ0 */
2965 [RCAR_GP_PIN(1, 10)] = { PUPR1, 7 }, /* DACK0 */
2966 [RCAR_GP_PIN(1, 12)] = { PUPR1, 8 }, /* IRQ0 */
2967 [RCAR_GP_PIN(1, 13)] = { PUPR1, 9 }, /* IRQ1 */
2968
2969 [RCAR_GP_PIN(1, 22)] = { PUPR2, 0 }, /* DU0_DR0 */
2970 [RCAR_GP_PIN(1, 23)] = { PUPR2, 1 }, /* DU0_DR1 */
2971 [RCAR_GP_PIN(1, 24)] = { PUPR2, 2 }, /* DU0_DR2 */
2972 [RCAR_GP_PIN(1, 25)] = { PUPR2, 3 }, /* DU0_DR3 */
2973 [RCAR_GP_PIN(1, 26)] = { PUPR2, 4 }, /* DU0_DR4 */
2974 [RCAR_GP_PIN(1, 27)] = { PUPR2, 5 }, /* DU0_DR5 */
2975 [RCAR_GP_PIN(1, 28)] = { PUPR2, 6 }, /* DU0_DR6 */
2976 [RCAR_GP_PIN(1, 29)] = { PUPR2, 7 }, /* DU0_DR7 */
2977 [RCAR_GP_PIN(1, 30)] = { PUPR2, 8 }, /* DU0_DG0 */
2978 [RCAR_GP_PIN(1, 31)] = { PUPR2, 9 }, /* DU0_DG1 */
2979 [RCAR_GP_PIN(2, 0)] = { PUPR2, 10 }, /* DU0_DG2 */
2980 [RCAR_GP_PIN(2, 1)] = { PUPR2, 11 }, /* DU0_DG3 */
2981 [RCAR_GP_PIN(2, 2)] = { PUPR2, 12 }, /* DU0_DG4 */
2982 [RCAR_GP_PIN(2, 3)] = { PUPR2, 13 }, /* DU0_DG5 */
2983 [RCAR_GP_PIN(2, 4)] = { PUPR2, 14 }, /* DU0_DG6 */
2984 [RCAR_GP_PIN(2, 5)] = { PUPR2, 15 }, /* DU0_DG7 */
2985 [RCAR_GP_PIN(2, 6)] = { PUPR2, 16 }, /* DU0_DB0 */
2986 [RCAR_GP_PIN(2, 7)] = { PUPR2, 17 }, /* DU0_DB1 */
2987 [RCAR_GP_PIN(2, 8)] = { PUPR2, 18 }, /* DU0_DB2 */
2988 [RCAR_GP_PIN(2, 9)] = { PUPR2, 19 }, /* DU0_DB3 */
2989 [RCAR_GP_PIN(2, 10)] = { PUPR2, 20 }, /* DU0_DB4 */
2990 [RCAR_GP_PIN(2, 11)] = { PUPR2, 21 }, /* DU0_DB5 */
2991 [RCAR_GP_PIN(2, 12)] = { PUPR2, 22 }, /* DU0_DB6 */
2992 [RCAR_GP_PIN(2, 13)] = { PUPR2, 23 }, /* DU0_DB7 */
2993 [RCAR_GP_PIN(2, 14)] = { PUPR2, 24 }, /* DU0_DOTCLKIN */
2994 [RCAR_GP_PIN(2, 15)] = { PUPR2, 25 }, /* DU0_DOTCLKOUT0 */
2995 [RCAR_GP_PIN(2, 17)] = { PUPR2, 26 }, /* DU0_HSYNC */
2996 [RCAR_GP_PIN(2, 18)] = { PUPR2, 27 }, /* DU0_VSYNC */
2997 [RCAR_GP_PIN(2, 19)] = { PUPR2, 28 }, /* DU0_EXODDF */
2998 [RCAR_GP_PIN(2, 20)] = { PUPR2, 29 }, /* DU0_DISP */
2999 [RCAR_GP_PIN(2, 21)] = { PUPR2, 30 }, /* DU0_CDE */
3000 [RCAR_GP_PIN(2, 16)] = { PUPR2, 31 }, /* DU0_DOTCLKOUT1 */
3001
3002 [RCAR_GP_PIN(3, 24)] = { PUPR3, 0 }, /* VI0_CLK */
3003 [RCAR_GP_PIN(3, 25)] = { PUPR3, 1 }, /* VI0_CLKENB */
3004 [RCAR_GP_PIN(3, 26)] = { PUPR3, 2 }, /* VI0_FIELD */
3005 [RCAR_GP_PIN(3, 27)] = { PUPR3, 3 }, /* /VI0_HSYNC */
3006 [RCAR_GP_PIN(3, 28)] = { PUPR3, 4 }, /* /VI0_VSYNC */
3007 [RCAR_GP_PIN(3, 29)] = { PUPR3, 5 }, /* VI0_DATA0 */
3008 [RCAR_GP_PIN(3, 30)] = { PUPR3, 6 }, /* VI0_DATA1 */
3009 [RCAR_GP_PIN(3, 31)] = { PUPR3, 7 }, /* VI0_DATA2 */
3010 [RCAR_GP_PIN(4, 0)] = { PUPR3, 8 }, /* VI0_DATA3 */
3011 [RCAR_GP_PIN(4, 1)] = { PUPR3, 9 }, /* VI0_DATA4 */
3012 [RCAR_GP_PIN(4, 2)] = { PUPR3, 10 }, /* VI0_DATA5 */
3013 [RCAR_GP_PIN(4, 3)] = { PUPR3, 11 }, /* VI0_DATA6 */
3014 [RCAR_GP_PIN(4, 4)] = { PUPR3, 12 }, /* VI0_DATA7 */
3015 [RCAR_GP_PIN(4, 5)] = { PUPR3, 13 }, /* VI0_G2 */
3016 [RCAR_GP_PIN(4, 6)] = { PUPR3, 14 }, /* VI0_G3 */
3017 [RCAR_GP_PIN(4, 7)] = { PUPR3, 15 }, /* VI0_G4 */
3018 [RCAR_GP_PIN(4, 8)] = { PUPR3, 16 }, /* VI0_G5 */
3019 [RCAR_GP_PIN(4, 21)] = { PUPR3, 17 }, /* VI1_DATA12 */
3020 [RCAR_GP_PIN(4, 22)] = { PUPR3, 18 }, /* VI1_DATA13 */
3021 [RCAR_GP_PIN(4, 23)] = { PUPR3, 19 }, /* VI1_DATA14 */
3022 [RCAR_GP_PIN(4, 24)] = { PUPR3, 20 }, /* VI1_DATA15 */
3023 [RCAR_GP_PIN(4, 9)] = { PUPR3, 21 }, /* ETH_REF_CLK */
3024 [RCAR_GP_PIN(4, 10)] = { PUPR3, 22 }, /* ETH_TXD0 */
3025 [RCAR_GP_PIN(4, 11)] = { PUPR3, 23 }, /* ETH_TXD1 */
3026 [RCAR_GP_PIN(4, 12)] = { PUPR3, 24 }, /* ETH_CRS_DV */
3027 [RCAR_GP_PIN(4, 13)] = { PUPR3, 25 }, /* ETH_TX_EN */
3028 [RCAR_GP_PIN(4, 14)] = { PUPR3, 26 }, /* ETH_RX_ER */
3029 [RCAR_GP_PIN(4, 15)] = { PUPR3, 27 }, /* ETH_RXD0 */
3030 [RCAR_GP_PIN(4, 16)] = { PUPR3, 28 }, /* ETH_RXD1 */
3031 [RCAR_GP_PIN(4, 17)] = { PUPR3, 29 }, /* ETH_MDC */
3032 [RCAR_GP_PIN(4, 18)] = { PUPR3, 30 }, /* ETH_MDIO */
3033 [RCAR_GP_PIN(4, 19)] = { PUPR3, 31 }, /* ETH_LINK */
3034
3035 [RCAR_GP_PIN(3, 6)] = { PUPR4, 0 }, /* SSI_SCK012 */
3036 [RCAR_GP_PIN(3, 7)] = { PUPR4, 1 }, /* SSI_WS012 */
3037 [RCAR_GP_PIN(3, 10)] = { PUPR4, 2 }, /* SSI_SDATA0 */
3038 [RCAR_GP_PIN(3, 9)] = { PUPR4, 3 }, /* SSI_SDATA1 */
3039 [RCAR_GP_PIN(3, 8)] = { PUPR4, 4 }, /* SSI_SDATA2 */
3040 [RCAR_GP_PIN(3, 2)] = { PUPR4, 5 }, /* SSI_SCK34 */
3041 [RCAR_GP_PIN(3, 3)] = { PUPR4, 6 }, /* SSI_WS34 */
3042 [RCAR_GP_PIN(3, 5)] = { PUPR4, 7 }, /* SSI_SDATA3 */
3043 [RCAR_GP_PIN(3, 4)] = { PUPR4, 8 }, /* SSI_SDATA4 */
3044 [RCAR_GP_PIN(2, 31)] = { PUPR4, 9 }, /* SSI_SCK5 */
3045 [RCAR_GP_PIN(3, 0)] = { PUPR4, 10 }, /* SSI_WS5 */
3046 [RCAR_GP_PIN(3, 1)] = { PUPR4, 11 }, /* SSI_SDATA5 */
3047 [RCAR_GP_PIN(2, 28)] = { PUPR4, 12 }, /* SSI_SCK6 */
3048 [RCAR_GP_PIN(2, 29)] = { PUPR4, 13 }, /* SSI_WS6 */
3049 [RCAR_GP_PIN(2, 30)] = { PUPR4, 14 }, /* SSI_SDATA6 */
3050 [RCAR_GP_PIN(2, 24)] = { PUPR4, 15 }, /* SSI_SCK78 */
3051 [RCAR_GP_PIN(2, 25)] = { PUPR4, 16 }, /* SSI_WS78 */
3052 [RCAR_GP_PIN(2, 27)] = { PUPR4, 17 }, /* SSI_SDATA7 */
3053 [RCAR_GP_PIN(2, 26)] = { PUPR4, 18 }, /* SSI_SDATA8 */
3054 [RCAR_GP_PIN(3, 23)] = { PUPR4, 19 }, /* TCLK0 */
3055 [RCAR_GP_PIN(3, 11)] = { PUPR4, 20 }, /* SD0_CLK */
3056 [RCAR_GP_PIN(3, 12)] = { PUPR4, 21 }, /* SD0_CMD */
3057 [RCAR_GP_PIN(3, 13)] = { PUPR4, 22 }, /* SD0_DAT0 */
3058 [RCAR_GP_PIN(3, 14)] = { PUPR4, 23 }, /* SD0_DAT1 */
3059 [RCAR_GP_PIN(3, 15)] = { PUPR4, 24 }, /* SD0_DAT2 */
3060 [RCAR_GP_PIN(3, 16)] = { PUPR4, 25 }, /* SD0_DAT3 */
3061 [RCAR_GP_PIN(3, 17)] = { PUPR4, 26 }, /* SD0_CD */
3062 [RCAR_GP_PIN(3, 18)] = { PUPR4, 27 }, /* SD0_WP */
3063 [RCAR_GP_PIN(2, 22)] = { PUPR4, 28 }, /* AUDIO_CLKA */
3064 [RCAR_GP_PIN(2, 23)] = { PUPR4, 29 }, /* AUDIO_CLKB */
3065 [RCAR_GP_PIN(1, 14)] = { PUPR4, 30 }, /* IRQ2 */
3066 [RCAR_GP_PIN(1, 15)] = { PUPR4, 31 }, /* IRQ3 */
3067
3068 [RCAR_GP_PIN(0, 1)] = { PUPR5, 0 }, /* PENC0 */
3069 [RCAR_GP_PIN(0, 2)] = { PUPR5, 1 }, /* PENC1 */
3070 [RCAR_GP_PIN(0, 3)] = { PUPR5, 2 }, /* USB_OVC0 */
3071 [RCAR_GP_PIN(0, 4)] = { PUPR5, 3 }, /* USB_OVC1 */
3072 [RCAR_GP_PIN(1, 16)] = { PUPR5, 4 }, /* SCIF_CLK */
3073 [RCAR_GP_PIN(1, 17)] = { PUPR5, 5 }, /* TX0 */
3074 [RCAR_GP_PIN(1, 18)] = { PUPR5, 6 }, /* RX0 */
3075 [RCAR_GP_PIN(1, 19)] = { PUPR5, 7 }, /* SCK0 */
3076 [RCAR_GP_PIN(1, 20)] = { PUPR5, 8 }, /* /CTS0 */
3077 [RCAR_GP_PIN(1, 21)] = { PUPR5, 9 }, /* /RTS0 */
3078 [RCAR_GP_PIN(3, 19)] = { PUPR5, 10 }, /* HSPI_CLK0 */
3079 [RCAR_GP_PIN(3, 20)] = { PUPR5, 11 }, /* /HSPI_CS0 */
3080 [RCAR_GP_PIN(3, 21)] = { PUPR5, 12 }, /* HSPI_RX0 */
3081 [RCAR_GP_PIN(3, 22)] = { PUPR5, 13 }, /* HSPI_TX0 */
3082 [RCAR_GP_PIN(4, 20)] = { PUPR5, 14 }, /* ETH_MAGIC */
3083 [RCAR_GP_PIN(4, 25)] = { PUPR5, 15 }, /* AVS1 */
3084 [RCAR_GP_PIN(4, 26)] = { PUPR5, 16 }, /* AVS2 */
3085};
3086
3087static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc,
3088 unsigned int pin)
3089{
3090 void __iomem *addr;
3091
3092 if (WARN_ON_ONCE(!pullups[pin].reg))
3093 return PIN_CONFIG_BIAS_DISABLE;
3094
3095 addr = pfc->windows->virt + pullups[pin].reg;
3096
3097 if (ioread32(addr) & BIT(pullups[pin].bit))
3098 return PIN_CONFIG_BIAS_PULL_UP;
3099 else
3100 return PIN_CONFIG_BIAS_DISABLE;
3101}
3102
3103static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3104 unsigned int bias)
3105{
3106 void __iomem *addr;
3107 u32 value;
3108 u32 bit;
3109
3110 if (WARN_ON_ONCE(!pullups[pin].reg))
3111 return;
3112
3113 addr = pfc->windows->virt + pullups[pin].reg;
3114 bit = BIT(pullups[pin].bit);
3115
3116 value = ioread32(addr) & ~bit;
3117 if (bias == PIN_CONFIG_BIAS_PULL_UP)
3118 value |= bit;
3119 iowrite32(value, addr);
3120}
3121
3122static const struct sh_pfc_soc_operations r8a7778_pfc_ops = {
3123 .get_bias = r8a7778_pinmux_get_bias,
3124 .set_bias = r8a7778_pinmux_set_bias,
3125};
3126
2908const struct sh_pfc_soc_info r8a7778_pinmux_info = { 3127const struct sh_pfc_soc_info r8a7778_pinmux_info = {
2909 .name = "r8a7778_pfc", 3128 .name = "r8a7778_pfc",
3129 .ops = &r8a7778_pfc_ops,
2910 3130
2911 .unlock_reg = 0xfffc0000, /* PMMR */ 3131 .unlock_reg = 0xfffc0000, /* PMMR */
2912 3132
@@ -2923,6 +3143,6 @@ const struct sh_pfc_soc_info r8a7778_pinmux_info = {
2923 3143
2924 .cfg_regs = pinmux_config_regs, 3144 .cfg_regs = pinmux_config_regs,
2925 3145
2926 .gpio_data = pinmux_data, 3146 .pinmux_data = pinmux_data,
2927 .gpio_data_size = ARRAY_SIZE(pinmux_data), 3147 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2928}; 3148};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index f5c01e1e2615..ed4e0788035c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -20,7 +20,6 @@
20 */ 20 */
21 21
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/platform_data/gpio-rcar.h>
24 23
25#include "sh_pfc.h" 24#include "sh_pfc.h"
26 25
@@ -620,18 +619,18 @@ static const u16 pinmux_data[] = {
620 PINMUX_DATA(USB_PENC1_MARK, FN_USB_PENC1), 619 PINMUX_DATA(USB_PENC1_MARK, FN_USB_PENC1),
621 620
622 PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2), 621 PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
623 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0), 622 PINMUX_IPSR_MSEL(IP0_2_0, SCK0, SEL_SCIF0_0),
624 PINMUX_IPSR_DATA(IP0_2_0, PWM1), 623 PINMUX_IPSR_DATA(IP0_2_0, PWM1),
625 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0), 624 PINMUX_IPSR_MSEL(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
626 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCIF_CLK, SEL_SCIF_0), 625 PINMUX_IPSR_MSEL(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
627 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, TCLK0_C, SEL_TMU0_2), 626 PINMUX_IPSR_MSEL(IP0_2_0, TCLK0_C, SEL_TMU0_2),
628 PINMUX_IPSR_DATA(IP0_5_3, BS), 627 PINMUX_IPSR_DATA(IP0_5_3, BS),
629 PINMUX_IPSR_DATA(IP0_5_3, SD1_DAT2), 628 PINMUX_IPSR_DATA(IP0_5_3, SD1_DAT2),
630 PINMUX_IPSR_DATA(IP0_5_3, MMC0_D2), 629 PINMUX_IPSR_DATA(IP0_5_3, MMC0_D2),
631 PINMUX_IPSR_DATA(IP0_5_3, FD2), 630 PINMUX_IPSR_DATA(IP0_5_3, FD2),
632 PINMUX_IPSR_DATA(IP0_5_3, ATADIR0), 631 PINMUX_IPSR_DATA(IP0_5_3, ATADIR0),
633 PINMUX_IPSR_DATA(IP0_5_3, SDSELF), 632 PINMUX_IPSR_DATA(IP0_5_3, SDSELF),
634 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, HCTS1, SEL_HSCIF1_0), 633 PINMUX_IPSR_MSEL(IP0_5_3, HCTS1, SEL_HSCIF1_0),
635 PINMUX_IPSR_DATA(IP0_5_3, TX4_C), 634 PINMUX_IPSR_DATA(IP0_5_3, TX4_C),
636 PINMUX_IPSR_DATA(IP0_7_6, A0), 635 PINMUX_IPSR_DATA(IP0_7_6, A0),
637 PINMUX_IPSR_DATA(IP0_7_6, SD1_DAT3), 636 PINMUX_IPSR_DATA(IP0_7_6, SD1_DAT3),
@@ -641,37 +640,37 @@ static const u16 pinmux_data[] = {
641 PINMUX_IPSR_DATA(IP0_9_8, TX5_D), 640 PINMUX_IPSR_DATA(IP0_9_8, TX5_D),
642 PINMUX_IPSR_DATA(IP0_9_8, HSPI_TX2_B), 641 PINMUX_IPSR_DATA(IP0_9_8, HSPI_TX2_B),
643 PINMUX_IPSR_DATA(IP0_11_10, A21), 642 PINMUX_IPSR_DATA(IP0_11_10, A21),
644 PINMUX_IPSR_MODSEL_DATA(IP0_11_10, SCK5_D, SEL_SCIF5_3), 643 PINMUX_IPSR_MSEL(IP0_11_10, SCK5_D, SEL_SCIF5_3),
645 PINMUX_IPSR_MODSEL_DATA(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1), 644 PINMUX_IPSR_MSEL(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
646 PINMUX_IPSR_DATA(IP0_13_12, A22), 645 PINMUX_IPSR_DATA(IP0_13_12, A22),
647 PINMUX_IPSR_MODSEL_DATA(IP0_13_12, RX5_D, SEL_SCIF5_3), 646 PINMUX_IPSR_MSEL(IP0_13_12, RX5_D, SEL_SCIF5_3),
648 PINMUX_IPSR_MODSEL_DATA(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1), 647 PINMUX_IPSR_MSEL(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
649 PINMUX_IPSR_DATA(IP0_13_12, VI1_R0), 648 PINMUX_IPSR_DATA(IP0_13_12, VI1_R0),
650 PINMUX_IPSR_DATA(IP0_15_14, A23), 649 PINMUX_IPSR_DATA(IP0_15_14, A23),
651 PINMUX_IPSR_DATA(IP0_15_14, FCLE), 650 PINMUX_IPSR_DATA(IP0_15_14, FCLE),
652 PINMUX_IPSR_MODSEL_DATA(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0), 651 PINMUX_IPSR_MSEL(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
653 PINMUX_IPSR_DATA(IP0_15_14, VI1_R1), 652 PINMUX_IPSR_DATA(IP0_15_14, VI1_R1),
654 PINMUX_IPSR_DATA(IP0_18_16, A24), 653 PINMUX_IPSR_DATA(IP0_18_16, A24),
655 PINMUX_IPSR_DATA(IP0_18_16, SD1_CD), 654 PINMUX_IPSR_DATA(IP0_18_16, SD1_CD),
656 PINMUX_IPSR_DATA(IP0_18_16, MMC0_D4), 655 PINMUX_IPSR_DATA(IP0_18_16, MMC0_D4),
657 PINMUX_IPSR_DATA(IP0_18_16, FD4), 656 PINMUX_IPSR_DATA(IP0_18_16, FD4),
658 PINMUX_IPSR_MODSEL_DATA(IP0_18_16, HSPI_CS2, SEL_HSPI2_0), 657 PINMUX_IPSR_MSEL(IP0_18_16, HSPI_CS2, SEL_HSPI2_0),
659 PINMUX_IPSR_DATA(IP0_18_16, VI1_R2), 658 PINMUX_IPSR_DATA(IP0_18_16, VI1_R2),
660 PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SSI_WS78_B, SEL_SSI7_1), 659 PINMUX_IPSR_MSEL(IP0_18_16, SSI_WS78_B, SEL_SSI7_1),
661 PINMUX_IPSR_DATA(IP0_22_19, A25), 660 PINMUX_IPSR_DATA(IP0_22_19, A25),
662 PINMUX_IPSR_DATA(IP0_22_19, SD1_WP), 661 PINMUX_IPSR_DATA(IP0_22_19, SD1_WP),
663 PINMUX_IPSR_DATA(IP0_22_19, MMC0_D5), 662 PINMUX_IPSR_DATA(IP0_22_19, MMC0_D5),
664 PINMUX_IPSR_DATA(IP0_22_19, FD5), 663 PINMUX_IPSR_DATA(IP0_22_19, FD5),
665 PINMUX_IPSR_MODSEL_DATA(IP0_22_19, HSPI_RX2, SEL_HSPI2_0), 664 PINMUX_IPSR_MSEL(IP0_22_19, HSPI_RX2, SEL_HSPI2_0),
666 PINMUX_IPSR_DATA(IP0_22_19, VI1_R3), 665 PINMUX_IPSR_DATA(IP0_22_19, VI1_R3),
667 PINMUX_IPSR_DATA(IP0_22_19, TX5_B), 666 PINMUX_IPSR_DATA(IP0_22_19, TX5_B),
668 PINMUX_IPSR_MODSEL_DATA(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1), 667 PINMUX_IPSR_MSEL(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1),
669 PINMUX_IPSR_MODSEL_DATA(IP0_22_19, CTS0_B, SEL_SCIF0_1), 668 PINMUX_IPSR_MSEL(IP0_22_19, CTS0_B, SEL_SCIF0_1),
670 PINMUX_IPSR_DATA(IP0_24_23, CLKOUT), 669 PINMUX_IPSR_DATA(IP0_24_23, CLKOUT),
671 PINMUX_IPSR_DATA(IP0_24_23, TX3C_IRDA_TX_C), 670 PINMUX_IPSR_DATA(IP0_24_23, TX3C_IRDA_TX_C),
672 PINMUX_IPSR_DATA(IP0_24_23, PWM0_B), 671 PINMUX_IPSR_DATA(IP0_24_23, PWM0_B),
673 PINMUX_IPSR_DATA(IP0_25, CS0), 672 PINMUX_IPSR_DATA(IP0_25, CS0),
674 PINMUX_IPSR_MODSEL_DATA(IP0_25, HSPI_CS2_B, SEL_HSPI2_1), 673 PINMUX_IPSR_MSEL(IP0_25, HSPI_CS2_B, SEL_HSPI2_1),
675 PINMUX_IPSR_DATA(IP0_27_26, CS1_A26), 674 PINMUX_IPSR_DATA(IP0_27_26, CS1_A26),
676 PINMUX_IPSR_DATA(IP0_27_26, HSPI_TX2), 675 PINMUX_IPSR_DATA(IP0_27_26, HSPI_TX2),
677 PINMUX_IPSR_DATA(IP0_27_26, SDSELF_B), 676 PINMUX_IPSR_DATA(IP0_27_26, SDSELF_B),
@@ -679,11 +678,11 @@ static const u16 pinmux_data[] = {
679 PINMUX_IPSR_DATA(IP0_30_28, FWE), 678 PINMUX_IPSR_DATA(IP0_30_28, FWE),
680 PINMUX_IPSR_DATA(IP0_30_28, ATAG0), 679 PINMUX_IPSR_DATA(IP0_30_28, ATAG0),
681 PINMUX_IPSR_DATA(IP0_30_28, VI1_R7), 680 PINMUX_IPSR_DATA(IP0_30_28, VI1_R7),
682 PINMUX_IPSR_MODSEL_DATA(IP0_30_28, HRTS1, SEL_HSCIF1_0), 681 PINMUX_IPSR_MSEL(IP0_30_28, HRTS1, SEL_HSCIF1_0),
683 PINMUX_IPSR_MODSEL_DATA(IP0_30_28, RX4_C, SEL_SCIF4_2), 682 PINMUX_IPSR_MSEL(IP0_30_28, RX4_C, SEL_SCIF4_2),
684 683
685 PINMUX_IPSR_DATA(IP1_1_0, EX_CS0), 684 PINMUX_IPSR_DATA(IP1_1_0, EX_CS0),
686 PINMUX_IPSR_MODSEL_DATA(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2), 685 PINMUX_IPSR_MSEL(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2),
687 PINMUX_IPSR_DATA(IP1_1_0, MMC0_D6), 686 PINMUX_IPSR_DATA(IP1_1_0, MMC0_D6),
688 PINMUX_IPSR_DATA(IP1_1_0, FD6), 687 PINMUX_IPSR_DATA(IP1_1_0, FD6),
689 PINMUX_IPSR_DATA(IP1_3_2, EX_CS1), 688 PINMUX_IPSR_DATA(IP1_3_2, EX_CS1),
@@ -700,45 +699,45 @@ static const u16 pinmux_data[] = {
700 PINMUX_IPSR_DATA(IP1_10_7, FRE), 699 PINMUX_IPSR_DATA(IP1_10_7, FRE),
701 PINMUX_IPSR_DATA(IP1_10_7, ATACS10), 700 PINMUX_IPSR_DATA(IP1_10_7, ATACS10),
702 PINMUX_IPSR_DATA(IP1_10_7, VI1_R4), 701 PINMUX_IPSR_DATA(IP1_10_7, VI1_R4),
703 PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RX5_B, SEL_SCIF5_1), 702 PINMUX_IPSR_MSEL(IP1_10_7, RX5_B, SEL_SCIF5_1),
704 PINMUX_IPSR_MODSEL_DATA(IP1_10_7, HSCK1, SEL_HSCIF1_0), 703 PINMUX_IPSR_MSEL(IP1_10_7, HSCK1, SEL_HSCIF1_0),
705 PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1), 704 PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1),
706 PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1), 705 PINMUX_IPSR_MSEL(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1),
707 PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA9, SEL_SSI9_0), 706 PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA9, SEL_SSI9_0),
708 PINMUX_IPSR_DATA(IP1_14_11, EX_CS4), 707 PINMUX_IPSR_DATA(IP1_14_11, EX_CS4),
709 PINMUX_IPSR_DATA(IP1_14_11, SD1_DAT0), 708 PINMUX_IPSR_DATA(IP1_14_11, SD1_DAT0),
710 PINMUX_IPSR_DATA(IP1_14_11, MMC0_D0), 709 PINMUX_IPSR_DATA(IP1_14_11, MMC0_D0),
711 PINMUX_IPSR_DATA(IP1_14_11, FD0), 710 PINMUX_IPSR_DATA(IP1_14_11, FD0),
712 PINMUX_IPSR_DATA(IP1_14_11, ATARD0), 711 PINMUX_IPSR_DATA(IP1_14_11, ATARD0),
713 PINMUX_IPSR_DATA(IP1_14_11, VI1_R5), 712 PINMUX_IPSR_DATA(IP1_14_11, VI1_R5),
714 PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SCK5_B, SEL_SCIF5_1), 713 PINMUX_IPSR_MSEL(IP1_14_11, SCK5_B, SEL_SCIF5_1),
715 PINMUX_IPSR_DATA(IP1_14_11, HTX1), 714 PINMUX_IPSR_DATA(IP1_14_11, HTX1),
716 PINMUX_IPSR_DATA(IP1_14_11, TX2_E), 715 PINMUX_IPSR_DATA(IP1_14_11, TX2_E),
717 PINMUX_IPSR_DATA(IP1_14_11, TX0_B), 716 PINMUX_IPSR_DATA(IP1_14_11, TX0_B),
718 PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SSI_SCK9, SEL_SSI9_0), 717 PINMUX_IPSR_MSEL(IP1_14_11, SSI_SCK9, SEL_SSI9_0),
719 PINMUX_IPSR_DATA(IP1_18_15, EX_CS5), 718 PINMUX_IPSR_DATA(IP1_18_15, EX_CS5),
720 PINMUX_IPSR_DATA(IP1_18_15, SD1_DAT1), 719 PINMUX_IPSR_DATA(IP1_18_15, SD1_DAT1),
721 PINMUX_IPSR_DATA(IP1_18_15, MMC0_D1), 720 PINMUX_IPSR_DATA(IP1_18_15, MMC0_D1),
722 PINMUX_IPSR_DATA(IP1_18_15, FD1), 721 PINMUX_IPSR_DATA(IP1_18_15, FD1),
723 PINMUX_IPSR_DATA(IP1_18_15, ATAWR0), 722 PINMUX_IPSR_DATA(IP1_18_15, ATAWR0),
724 PINMUX_IPSR_DATA(IP1_18_15, VI1_R6), 723 PINMUX_IPSR_DATA(IP1_18_15, VI1_R6),
725 PINMUX_IPSR_MODSEL_DATA(IP1_18_15, HRX1, SEL_HSCIF1_0), 724 PINMUX_IPSR_MSEL(IP1_18_15, HRX1, SEL_HSCIF1_0),
726 PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX2_E, SEL_SCIF2_4), 725 PINMUX_IPSR_MSEL(IP1_18_15, RX2_E, SEL_SCIF2_4),
727 PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX0_B, SEL_SCIF0_1), 726 PINMUX_IPSR_MSEL(IP1_18_15, RX0_B, SEL_SCIF0_1),
728 PINMUX_IPSR_MODSEL_DATA(IP1_18_15, SSI_WS9, SEL_SSI9_0), 727 PINMUX_IPSR_MSEL(IP1_18_15, SSI_WS9, SEL_SSI9_0),
729 PINMUX_IPSR_DATA(IP1_20_19, MLB_CLK), 728 PINMUX_IPSR_DATA(IP1_20_19, MLB_CLK),
730 PINMUX_IPSR_DATA(IP1_20_19, PWM2), 729 PINMUX_IPSR_DATA(IP1_20_19, PWM2),
731 PINMUX_IPSR_MODSEL_DATA(IP1_20_19, SCK4, SEL_SCIF4_0), 730 PINMUX_IPSR_MSEL(IP1_20_19, SCK4, SEL_SCIF4_0),
732 PINMUX_IPSR_DATA(IP1_22_21, MLB_SIG), 731 PINMUX_IPSR_DATA(IP1_22_21, MLB_SIG),
733 PINMUX_IPSR_DATA(IP1_22_21, PWM3), 732 PINMUX_IPSR_DATA(IP1_22_21, PWM3),
734 PINMUX_IPSR_DATA(IP1_22_21, TX4), 733 PINMUX_IPSR_DATA(IP1_22_21, TX4),
735 PINMUX_IPSR_DATA(IP1_24_23, MLB_DAT), 734 PINMUX_IPSR_DATA(IP1_24_23, MLB_DAT),
736 PINMUX_IPSR_DATA(IP1_24_23, PWM4), 735 PINMUX_IPSR_DATA(IP1_24_23, PWM4),
737 PINMUX_IPSR_MODSEL_DATA(IP1_24_23, RX4, SEL_SCIF4_0), 736 PINMUX_IPSR_MSEL(IP1_24_23, RX4, SEL_SCIF4_0),
738 PINMUX_IPSR_DATA(IP1_28_25, HTX0), 737 PINMUX_IPSR_DATA(IP1_28_25, HTX0),
739 PINMUX_IPSR_DATA(IP1_28_25, TX1), 738 PINMUX_IPSR_DATA(IP1_28_25, TX1),
740 PINMUX_IPSR_DATA(IP1_28_25, SDATA), 739 PINMUX_IPSR_DATA(IP1_28_25, SDATA),
741 PINMUX_IPSR_MODSEL_DATA(IP1_28_25, CTS0_C, SEL_SCIF0_2), 740 PINMUX_IPSR_MSEL(IP1_28_25, CTS0_C, SEL_SCIF0_2),
742 PINMUX_IPSR_DATA(IP1_28_25, SUB_TCK), 741 PINMUX_IPSR_DATA(IP1_28_25, SUB_TCK),
743 PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE2), 742 PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE2),
744 PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE10), 743 PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE10),
@@ -746,39 +745,39 @@ static const u16 pinmux_data[] = {
746 PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE26), 745 PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE26),
747 PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE34), 746 PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE34),
748 747
749 PINMUX_IPSR_MODSEL_DATA(IP2_3_0, HRX0, SEL_HSCIF0_0), 748 PINMUX_IPSR_MSEL(IP2_3_0, HRX0, SEL_HSCIF0_0),
750 PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RX1, SEL_SCIF1_0), 749 PINMUX_IPSR_MSEL(IP2_3_0, RX1, SEL_SCIF1_0),
751 PINMUX_IPSR_DATA(IP2_3_0, SCKZ), 750 PINMUX_IPSR_DATA(IP2_3_0, SCKZ),
752 PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2), 751 PINMUX_IPSR_MSEL(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2),
753 PINMUX_IPSR_DATA(IP2_3_0, SUB_TDI), 752 PINMUX_IPSR_DATA(IP2_3_0, SUB_TDI),
754 PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE3), 753 PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE3),
755 PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE11), 754 PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE11),
756 PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE19), 755 PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE19),
757 PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE27), 756 PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE27),
758 PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE35), 757 PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE35),
759 PINMUX_IPSR_MODSEL_DATA(IP2_7_4, HSCK0, SEL_HSCIF0_0), 758 PINMUX_IPSR_MSEL(IP2_7_4, HSCK0, SEL_HSCIF0_0),
760 PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK1, SEL_SCIF1_0), 759 PINMUX_IPSR_MSEL(IP2_7_4, SCK1, SEL_SCIF1_0),
761 PINMUX_IPSR_DATA(IP2_7_4, MTS), 760 PINMUX_IPSR_DATA(IP2_7_4, MTS),
762 PINMUX_IPSR_DATA(IP2_7_4, PWM5), 761 PINMUX_IPSR_DATA(IP2_7_4, PWM5),
763 PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK0_C, SEL_SCIF0_2), 762 PINMUX_IPSR_MSEL(IP2_7_4, SCK0_C, SEL_SCIF0_2),
764 PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1), 763 PINMUX_IPSR_MSEL(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1),
765 PINMUX_IPSR_DATA(IP2_7_4, SUB_TDO), 764 PINMUX_IPSR_DATA(IP2_7_4, SUB_TDO),
766 PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE0), 765 PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE0),
767 PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE8), 766 PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE8),
768 PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE16), 767 PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE16),
769 PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE24), 768 PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE24),
770 PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE32), 769 PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE32),
771 PINMUX_IPSR_MODSEL_DATA(IP2_11_8, HCTS0, SEL_HSCIF0_0), 770 PINMUX_IPSR_MSEL(IP2_11_8, HCTS0, SEL_HSCIF0_0),
772 PINMUX_IPSR_MODSEL_DATA(IP2_11_8, CTS1, SEL_SCIF1_0), 771 PINMUX_IPSR_MSEL(IP2_11_8, CTS1, SEL_SCIF1_0),
773 PINMUX_IPSR_DATA(IP2_11_8, STM), 772 PINMUX_IPSR_DATA(IP2_11_8, STM),
774 PINMUX_IPSR_DATA(IP2_11_8, PWM0_D), 773 PINMUX_IPSR_DATA(IP2_11_8, PWM0_D),
775 PINMUX_IPSR_MODSEL_DATA(IP2_11_8, RX0_C, SEL_SCIF0_2), 774 PINMUX_IPSR_MSEL(IP2_11_8, RX0_C, SEL_SCIF0_2),
776 PINMUX_IPSR_MODSEL_DATA(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2), 775 PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2),
777 PINMUX_IPSR_DATA(IP2_11_8, SUB_TRST), 776 PINMUX_IPSR_DATA(IP2_11_8, SUB_TRST),
778 PINMUX_IPSR_MODSEL_DATA(IP2_11_8, TCLK1_B, SEL_TMU1_1), 777 PINMUX_IPSR_MSEL(IP2_11_8, TCLK1_B, SEL_TMU1_1),
779 PINMUX_IPSR_DATA(IP2_11_8, CC5_OSCOUT), 778 PINMUX_IPSR_DATA(IP2_11_8, CC5_OSCOUT),
780 PINMUX_IPSR_MODSEL_DATA(IP2_15_12, HRTS0, SEL_HSCIF0_0), 779 PINMUX_IPSR_MSEL(IP2_15_12, HRTS0, SEL_HSCIF0_0),
781 PINMUX_IPSR_MODSEL_DATA(IP2_15_12, RTS1_TANS, SEL_SCIF1_0), 780 PINMUX_IPSR_MSEL(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
782 PINMUX_IPSR_DATA(IP2_15_12, MDATA), 781 PINMUX_IPSR_DATA(IP2_15_12, MDATA),
783 PINMUX_IPSR_DATA(IP2_15_12, TX0_C), 782 PINMUX_IPSR_DATA(IP2_15_12, TX0_C),
784 PINMUX_IPSR_DATA(IP2_15_12, SUB_TMS), 783 PINMUX_IPSR_DATA(IP2_15_12, SUB_TMS),
@@ -789,17 +788,17 @@ static const u16 pinmux_data[] = {
789 PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE33), 788 PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE33),
790 PINMUX_IPSR_DATA(IP2_18_16, DU0_DR0), 789 PINMUX_IPSR_DATA(IP2_18_16, DU0_DR0),
791 PINMUX_IPSR_DATA(IP2_18_16, LCDOUT0), 790 PINMUX_IPSR_DATA(IP2_18_16, LCDOUT0),
792 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ0, SEL_EXBUS0_0), 791 PINMUX_IPSR_MSEL(IP2_18_16, DREQ0, SEL_EXBUS0_0),
793 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, GPS_CLK_B, SEL_GPS_1), 792 PINMUX_IPSR_MSEL(IP2_18_16, GPS_CLK_B, SEL_GPS_1),
794 PINMUX_IPSR_DATA(IP2_18_16, AUDATA0), 793 PINMUX_IPSR_DATA(IP2_18_16, AUDATA0),
795 PINMUX_IPSR_DATA(IP2_18_16, TX5_C), 794 PINMUX_IPSR_DATA(IP2_18_16, TX5_C),
796 PINMUX_IPSR_DATA(IP2_21_19, DU0_DR1), 795 PINMUX_IPSR_DATA(IP2_21_19, DU0_DR1),
797 PINMUX_IPSR_DATA(IP2_21_19, LCDOUT1), 796 PINMUX_IPSR_DATA(IP2_21_19, LCDOUT1),
798 PINMUX_IPSR_DATA(IP2_21_19, DACK0), 797 PINMUX_IPSR_DATA(IP2_21_19, DACK0),
799 PINMUX_IPSR_DATA(IP2_21_19, DRACK0), 798 PINMUX_IPSR_DATA(IP2_21_19, DRACK0),
800 PINMUX_IPSR_MODSEL_DATA(IP2_21_19, GPS_SIGN_B, SEL_GPS_1), 799 PINMUX_IPSR_MSEL(IP2_21_19, GPS_SIGN_B, SEL_GPS_1),
801 PINMUX_IPSR_DATA(IP2_21_19, AUDATA1), 800 PINMUX_IPSR_DATA(IP2_21_19, AUDATA1),
802 PINMUX_IPSR_MODSEL_DATA(IP2_21_19, RX5_C, SEL_SCIF5_2), 801 PINMUX_IPSR_MSEL(IP2_21_19, RX5_C, SEL_SCIF5_2),
803 PINMUX_IPSR_DATA(IP2_22, DU0_DR2), 802 PINMUX_IPSR_DATA(IP2_22, DU0_DR2),
804 PINMUX_IPSR_DATA(IP2_22, LCDOUT2), 803 PINMUX_IPSR_DATA(IP2_22, LCDOUT2),
805 PINMUX_IPSR_DATA(IP2_23, DU0_DR3), 804 PINMUX_IPSR_DATA(IP2_23, DU0_DR3),
@@ -814,14 +813,14 @@ static const u16 pinmux_data[] = {
814 PINMUX_IPSR_DATA(IP2_27, LCDOUT7), 813 PINMUX_IPSR_DATA(IP2_27, LCDOUT7),
815 PINMUX_IPSR_DATA(IP2_30_28, DU0_DG0), 814 PINMUX_IPSR_DATA(IP2_30_28, DU0_DG0),
816 PINMUX_IPSR_DATA(IP2_30_28, LCDOUT8), 815 PINMUX_IPSR_DATA(IP2_30_28, LCDOUT8),
817 PINMUX_IPSR_MODSEL_DATA(IP2_30_28, DREQ1, SEL_EXBUS1_0), 816 PINMUX_IPSR_MSEL(IP2_30_28, DREQ1, SEL_EXBUS1_0),
818 PINMUX_IPSR_MODSEL_DATA(IP2_30_28, SCL2, SEL_I2C2_0), 817 PINMUX_IPSR_MSEL(IP2_30_28, SCL2, SEL_I2C2_0),
819 PINMUX_IPSR_DATA(IP2_30_28, AUDATA2), 818 PINMUX_IPSR_DATA(IP2_30_28, AUDATA2),
820 819
821 PINMUX_IPSR_DATA(IP3_2_0, DU0_DG1), 820 PINMUX_IPSR_DATA(IP3_2_0, DU0_DG1),
822 PINMUX_IPSR_DATA(IP3_2_0, LCDOUT9), 821 PINMUX_IPSR_DATA(IP3_2_0, LCDOUT9),
823 PINMUX_IPSR_DATA(IP3_2_0, DACK1), 822 PINMUX_IPSR_DATA(IP3_2_0, DACK1),
824 PINMUX_IPSR_MODSEL_DATA(IP3_2_0, SDA2, SEL_I2C2_0), 823 PINMUX_IPSR_MSEL(IP3_2_0, SDA2, SEL_I2C2_0),
825 PINMUX_IPSR_DATA(IP3_2_0, AUDATA3), 824 PINMUX_IPSR_DATA(IP3_2_0, AUDATA3),
826 PINMUX_IPSR_DATA(IP3_3, DU0_DG2), 825 PINMUX_IPSR_DATA(IP3_3, DU0_DG2),
827 PINMUX_IPSR_DATA(IP3_3, LCDOUT10), 826 PINMUX_IPSR_DATA(IP3_3, LCDOUT10),
@@ -838,16 +837,16 @@ static const u16 pinmux_data[] = {
838 PINMUX_IPSR_DATA(IP3_11_9, DU0_DB0), 837 PINMUX_IPSR_DATA(IP3_11_9, DU0_DB0),
839 PINMUX_IPSR_DATA(IP3_11_9, LCDOUT16), 838 PINMUX_IPSR_DATA(IP3_11_9, LCDOUT16),
840 PINMUX_IPSR_DATA(IP3_11_9, EX_WAIT1), 839 PINMUX_IPSR_DATA(IP3_11_9, EX_WAIT1),
841 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCL1, SEL_I2C1_0), 840 PINMUX_IPSR_MSEL(IP3_11_9, SCL1, SEL_I2C1_0),
842 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, TCLK1, SEL_TMU1_0), 841 PINMUX_IPSR_MSEL(IP3_11_9, TCLK1, SEL_TMU1_0),
843 PINMUX_IPSR_DATA(IP3_11_9, AUDATA4), 842 PINMUX_IPSR_DATA(IP3_11_9, AUDATA4),
844 PINMUX_IPSR_DATA(IP3_14_12, DU0_DB1), 843 PINMUX_IPSR_DATA(IP3_14_12, DU0_DB1),
845 PINMUX_IPSR_DATA(IP3_14_12, LCDOUT17), 844 PINMUX_IPSR_DATA(IP3_14_12, LCDOUT17),
846 PINMUX_IPSR_DATA(IP3_14_12, EX_WAIT2), 845 PINMUX_IPSR_DATA(IP3_14_12, EX_WAIT2),
847 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SDA1, SEL_I2C1_0), 846 PINMUX_IPSR_MSEL(IP3_14_12, SDA1, SEL_I2C1_0),
848 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, GPS_MAG_B, SEL_GPS_1), 847 PINMUX_IPSR_MSEL(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
849 PINMUX_IPSR_DATA(IP3_14_12, AUDATA5), 848 PINMUX_IPSR_DATA(IP3_14_12, AUDATA5),
850 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCK5_C, SEL_SCIF5_2), 849 PINMUX_IPSR_MSEL(IP3_14_12, SCK5_C, SEL_SCIF5_2),
851 PINMUX_IPSR_DATA(IP3_15, DU0_DB2), 850 PINMUX_IPSR_DATA(IP3_15, DU0_DB2),
852 PINMUX_IPSR_DATA(IP3_15, LCDOUT18), 851 PINMUX_IPSR_DATA(IP3_15, LCDOUT18),
853 PINMUX_IPSR_DATA(IP3_16, DU0_DB3), 852 PINMUX_IPSR_DATA(IP3_16, DU0_DB3),
@@ -863,14 +862,14 @@ static const u16 pinmux_data[] = {
863 PINMUX_IPSR_DATA(IP3_22_21, DU0_DOTCLKIN), 862 PINMUX_IPSR_DATA(IP3_22_21, DU0_DOTCLKIN),
864 PINMUX_IPSR_DATA(IP3_22_21, QSTVA_QVS), 863 PINMUX_IPSR_DATA(IP3_22_21, QSTVA_QVS),
865 PINMUX_IPSR_DATA(IP3_22_21, TX3_D_IRDA_TX_D), 864 PINMUX_IPSR_DATA(IP3_22_21, TX3_D_IRDA_TX_D),
866 PINMUX_IPSR_MODSEL_DATA(IP3_22_21, SCL3_B, SEL_I2C3_1), 865 PINMUX_IPSR_MSEL(IP3_22_21, SCL3_B, SEL_I2C3_1),
867 PINMUX_IPSR_DATA(IP3_23, DU0_DOTCLKOUT0), 866 PINMUX_IPSR_DATA(IP3_23, DU0_DOTCLKOUT0),
868 PINMUX_IPSR_DATA(IP3_23, QCLK), 867 PINMUX_IPSR_DATA(IP3_23, QCLK),
869 PINMUX_IPSR_DATA(IP3_26_24, DU0_DOTCLKOUT1), 868 PINMUX_IPSR_DATA(IP3_26_24, DU0_DOTCLKOUT1),
870 PINMUX_IPSR_DATA(IP3_26_24, QSTVB_QVE), 869 PINMUX_IPSR_DATA(IP3_26_24, QSTVB_QVE),
871 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3), 870 PINMUX_IPSR_MSEL(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
872 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA3_B, SEL_I2C3_1), 871 PINMUX_IPSR_MSEL(IP3_26_24, SDA3_B, SEL_I2C3_1),
873 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA2_C, SEL_I2C2_2), 872 PINMUX_IPSR_MSEL(IP3_26_24, SDA2_C, SEL_I2C2_2),
874 PINMUX_IPSR_DATA(IP3_26_24, DACK0_B), 873 PINMUX_IPSR_DATA(IP3_26_24, DACK0_B),
875 PINMUX_IPSR_DATA(IP3_26_24, DRACK0_B), 874 PINMUX_IPSR_DATA(IP3_26_24, DRACK0_B),
876 PINMUX_IPSR_DATA(IP3_27, DU0_EXHSYNC_DU0_HSYNC), 875 PINMUX_IPSR_DATA(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
@@ -881,34 +880,34 @@ static const u16 pinmux_data[] = {
881 PINMUX_IPSR_DATA(IP3_31_29, QCPV_QDE), 880 PINMUX_IPSR_DATA(IP3_31_29, QCPV_QDE),
882 PINMUX_IPSR_DATA(IP3_31_29, CAN1_TX), 881 PINMUX_IPSR_DATA(IP3_31_29, CAN1_TX),
883 PINMUX_IPSR_DATA(IP3_31_29, TX2_C), 882 PINMUX_IPSR_DATA(IP3_31_29, TX2_C),
884 PINMUX_IPSR_MODSEL_DATA(IP3_31_29, SCL2_C, SEL_I2C2_2), 883 PINMUX_IPSR_MSEL(IP3_31_29, SCL2_C, SEL_I2C2_2),
885 PINMUX_IPSR_DATA(IP3_31_29, REMOCON), 884 PINMUX_IPSR_DATA(IP3_31_29, REMOCON),
886 885
887 PINMUX_IPSR_DATA(IP4_1_0, DU0_DISP), 886 PINMUX_IPSR_DATA(IP4_1_0, DU0_DISP),
888 PINMUX_IPSR_DATA(IP4_1_0, QPOLA), 887 PINMUX_IPSR_DATA(IP4_1_0, QPOLA),
889 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2), 888 PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
890 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCK2_C, SEL_SCIF2_2), 889 PINMUX_IPSR_MSEL(IP4_1_0, SCK2_C, SEL_SCIF2_2),
891 PINMUX_IPSR_DATA(IP4_4_2, DU0_CDE), 890 PINMUX_IPSR_DATA(IP4_4_2, DU0_CDE),
892 PINMUX_IPSR_DATA(IP4_4_2, QPOLB), 891 PINMUX_IPSR_DATA(IP4_4_2, QPOLB),
893 PINMUX_IPSR_DATA(IP4_4_2, CAN1_RX), 892 PINMUX_IPSR_DATA(IP4_4_2, CAN1_RX),
894 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, RX2_C, SEL_SCIF2_2), 893 PINMUX_IPSR_MSEL(IP4_4_2, RX2_C, SEL_SCIF2_2),
895 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, DREQ0_B, SEL_EXBUS0_1), 894 PINMUX_IPSR_MSEL(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
896 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1), 895 PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
897 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCK0_B, SEL_SCIF0_1), 896 PINMUX_IPSR_MSEL(IP4_4_2, SCK0_B, SEL_SCIF0_1),
898 PINMUX_IPSR_DATA(IP4_7_5, DU1_DR0), 897 PINMUX_IPSR_DATA(IP4_7_5, DU1_DR0),
899 PINMUX_IPSR_DATA(IP4_7_5, VI2_DATA0_VI2_B0), 898 PINMUX_IPSR_DATA(IP4_7_5, VI2_DATA0_VI2_B0),
900 PINMUX_IPSR_DATA(IP4_7_5, PWM6), 899 PINMUX_IPSR_DATA(IP4_7_5, PWM6),
901 PINMUX_IPSR_DATA(IP4_7_5, SD3_CLK), 900 PINMUX_IPSR_DATA(IP4_7_5, SD3_CLK),
902 PINMUX_IPSR_DATA(IP4_7_5, TX3_E_IRDA_TX_E), 901 PINMUX_IPSR_DATA(IP4_7_5, TX3_E_IRDA_TX_E),
903 PINMUX_IPSR_DATA(IP4_7_5, AUDCK), 902 PINMUX_IPSR_DATA(IP4_7_5, AUDCK),
904 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1), 903 PINMUX_IPSR_MSEL(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
905 PINMUX_IPSR_DATA(IP4_10_8, DU1_DR1), 904 PINMUX_IPSR_DATA(IP4_10_8, DU1_DR1),
906 PINMUX_IPSR_DATA(IP4_10_8, VI2_DATA1_VI2_B1), 905 PINMUX_IPSR_DATA(IP4_10_8, VI2_DATA1_VI2_B1),
907 PINMUX_IPSR_DATA(IP4_10_8, PWM0), 906 PINMUX_IPSR_DATA(IP4_10_8, PWM0),
908 PINMUX_IPSR_DATA(IP4_10_8, SD3_CMD), 907 PINMUX_IPSR_DATA(IP4_10_8, SD3_CMD),
909 PINMUX_IPSR_MODSEL_DATA(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4), 908 PINMUX_IPSR_MSEL(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
910 PINMUX_IPSR_DATA(IP4_10_8, AUDSYNC), 909 PINMUX_IPSR_DATA(IP4_10_8, AUDSYNC),
911 PINMUX_IPSR_MODSEL_DATA(IP4_10_8, CTS0_D, SEL_SCIF0_3), 910 PINMUX_IPSR_MSEL(IP4_10_8, CTS0_D, SEL_SCIF0_3),
912 PINMUX_IPSR_DATA(IP4_11, DU1_DR2), 911 PINMUX_IPSR_DATA(IP4_11, DU1_DR2),
913 PINMUX_IPSR_DATA(IP4_11, VI2_G0), 912 PINMUX_IPSR_DATA(IP4_11, VI2_G0),
914 PINMUX_IPSR_DATA(IP4_12, DU1_DR3), 913 PINMUX_IPSR_DATA(IP4_12, DU1_DR3),
@@ -923,18 +922,18 @@ static const u16 pinmux_data[] = {
923 PINMUX_IPSR_DATA(IP4_16, VI2_G5), 922 PINMUX_IPSR_DATA(IP4_16, VI2_G5),
924 PINMUX_IPSR_DATA(IP4_19_17, DU1_DG0), 923 PINMUX_IPSR_DATA(IP4_19_17, DU1_DG0),
925 PINMUX_IPSR_DATA(IP4_19_17, VI2_DATA2_VI2_B2), 924 PINMUX_IPSR_DATA(IP4_19_17, VI2_DATA2_VI2_B2),
926 PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCL1_B, SEL_I2C1_1), 925 PINMUX_IPSR_MSEL(IP4_19_17, SCL1_B, SEL_I2C1_1),
927 PINMUX_IPSR_DATA(IP4_19_17, SD3_DAT2), 926 PINMUX_IPSR_DATA(IP4_19_17, SD3_DAT2),
928 PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCK3_E, SEL_SCIF3_4), 927 PINMUX_IPSR_MSEL(IP4_19_17, SCK3_E, SEL_SCIF3_4),
929 PINMUX_IPSR_DATA(IP4_19_17, AUDATA6), 928 PINMUX_IPSR_DATA(IP4_19_17, AUDATA6),
930 PINMUX_IPSR_DATA(IP4_19_17, TX0_D), 929 PINMUX_IPSR_DATA(IP4_19_17, TX0_D),
931 PINMUX_IPSR_DATA(IP4_22_20, DU1_DG1), 930 PINMUX_IPSR_DATA(IP4_22_20, DU1_DG1),
932 PINMUX_IPSR_DATA(IP4_22_20, VI2_DATA3_VI2_B3), 931 PINMUX_IPSR_DATA(IP4_22_20, VI2_DATA3_VI2_B3),
933 PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SDA1_B, SEL_I2C1_1), 932 PINMUX_IPSR_MSEL(IP4_22_20, SDA1_B, SEL_I2C1_1),
934 PINMUX_IPSR_DATA(IP4_22_20, SD3_DAT3), 933 PINMUX_IPSR_DATA(IP4_22_20, SD3_DAT3),
935 PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCK5, SEL_SCIF5_0), 934 PINMUX_IPSR_MSEL(IP4_22_20, SCK5, SEL_SCIF5_0),
936 PINMUX_IPSR_DATA(IP4_22_20, AUDATA7), 935 PINMUX_IPSR_DATA(IP4_22_20, AUDATA7),
937 PINMUX_IPSR_MODSEL_DATA(IP4_22_20, RX0_D, SEL_SCIF0_3), 936 PINMUX_IPSR_MSEL(IP4_22_20, RX0_D, SEL_SCIF0_3),
938 PINMUX_IPSR_DATA(IP4_23, DU1_DG2), 937 PINMUX_IPSR_DATA(IP4_23, DU1_DG2),
939 PINMUX_IPSR_DATA(IP4_23, VI2_G6), 938 PINMUX_IPSR_DATA(IP4_23, VI2_G6),
940 PINMUX_IPSR_DATA(IP4_24, DU1_DG3), 939 PINMUX_IPSR_DATA(IP4_24, DU1_DG3),
@@ -949,17 +948,17 @@ static const u16 pinmux_data[] = {
949 PINMUX_IPSR_DATA(IP4_28, VI2_R3), 948 PINMUX_IPSR_DATA(IP4_28, VI2_R3),
950 PINMUX_IPSR_DATA(IP4_31_29, DU1_DB0), 949 PINMUX_IPSR_DATA(IP4_31_29, DU1_DB0),
951 PINMUX_IPSR_DATA(IP4_31_29, VI2_DATA4_VI2_B4), 950 PINMUX_IPSR_DATA(IP4_31_29, VI2_DATA4_VI2_B4),
952 PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCL2_B, SEL_I2C2_1), 951 PINMUX_IPSR_MSEL(IP4_31_29, SCL2_B, SEL_I2C2_1),
953 PINMUX_IPSR_DATA(IP4_31_29, SD3_DAT0), 952 PINMUX_IPSR_DATA(IP4_31_29, SD3_DAT0),
954 PINMUX_IPSR_DATA(IP4_31_29, TX5), 953 PINMUX_IPSR_DATA(IP4_31_29, TX5),
955 PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCK0_D, SEL_SCIF0_3), 954 PINMUX_IPSR_MSEL(IP4_31_29, SCK0_D, SEL_SCIF0_3),
956 955
957 PINMUX_IPSR_DATA(IP5_2_0, DU1_DB1), 956 PINMUX_IPSR_DATA(IP5_2_0, DU1_DB1),
958 PINMUX_IPSR_DATA(IP5_2_0, VI2_DATA5_VI2_B5), 957 PINMUX_IPSR_DATA(IP5_2_0, VI2_DATA5_VI2_B5),
959 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, SDA2_B, SEL_I2C2_1), 958 PINMUX_IPSR_MSEL(IP5_2_0, SDA2_B, SEL_I2C2_1),
960 PINMUX_IPSR_DATA(IP5_2_0, SD3_DAT1), 959 PINMUX_IPSR_DATA(IP5_2_0, SD3_DAT1),
961 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RX5, SEL_SCIF5_0), 960 PINMUX_IPSR_MSEL(IP5_2_0, RX5, SEL_SCIF5_0),
962 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3), 961 PINMUX_IPSR_MSEL(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3),
963 PINMUX_IPSR_DATA(IP5_3, DU1_DB2), 962 PINMUX_IPSR_DATA(IP5_3, DU1_DB2),
964 PINMUX_IPSR_DATA(IP5_3, VI2_R4), 963 PINMUX_IPSR_DATA(IP5_3, VI2_R4),
965 PINMUX_IPSR_DATA(IP5_4, DU1_DB3), 964 PINMUX_IPSR_DATA(IP5_4, DU1_DB3),
@@ -969,16 +968,16 @@ static const u16 pinmux_data[] = {
969 PINMUX_IPSR_DATA(IP5_6, DU1_DB5), 968 PINMUX_IPSR_DATA(IP5_6, DU1_DB5),
970 PINMUX_IPSR_DATA(IP5_6, VI2_R7), 969 PINMUX_IPSR_DATA(IP5_6, VI2_R7),
971 PINMUX_IPSR_DATA(IP5_7, DU1_DB6), 970 PINMUX_IPSR_DATA(IP5_7, DU1_DB6),
972 PINMUX_IPSR_MODSEL_DATA(IP5_7, SCL2_D, SEL_I2C2_3), 971 PINMUX_IPSR_MSEL(IP5_7, SCL2_D, SEL_I2C2_3),
973 PINMUX_IPSR_DATA(IP5_8, DU1_DB7), 972 PINMUX_IPSR_DATA(IP5_8, DU1_DB7),
974 PINMUX_IPSR_MODSEL_DATA(IP5_8, SDA2_D, SEL_I2C2_3), 973 PINMUX_IPSR_MSEL(IP5_8, SDA2_D, SEL_I2C2_3),
975 PINMUX_IPSR_DATA(IP5_10_9, DU1_DOTCLKIN), 974 PINMUX_IPSR_DATA(IP5_10_9, DU1_DOTCLKIN),
976 PINMUX_IPSR_DATA(IP5_10_9, VI2_CLKENB), 975 PINMUX_IPSR_DATA(IP5_10_9, VI2_CLKENB),
977 PINMUX_IPSR_MODSEL_DATA(IP5_10_9, HSPI_CS1, SEL_HSPI1_0), 976 PINMUX_IPSR_MSEL(IP5_10_9, HSPI_CS1, SEL_HSPI1_0),
978 PINMUX_IPSR_MODSEL_DATA(IP5_10_9, SCL1_D, SEL_I2C1_3), 977 PINMUX_IPSR_MSEL(IP5_10_9, SCL1_D, SEL_I2C1_3),
979 PINMUX_IPSR_DATA(IP5_12_11, DU1_DOTCLKOUT), 978 PINMUX_IPSR_DATA(IP5_12_11, DU1_DOTCLKOUT),
980 PINMUX_IPSR_DATA(IP5_12_11, VI2_FIELD), 979 PINMUX_IPSR_DATA(IP5_12_11, VI2_FIELD),
981 PINMUX_IPSR_MODSEL_DATA(IP5_12_11, SDA1_D, SEL_I2C1_3), 980 PINMUX_IPSR_MSEL(IP5_12_11, SDA1_D, SEL_I2C1_3),
982 PINMUX_IPSR_DATA(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC), 981 PINMUX_IPSR_DATA(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC),
983 PINMUX_IPSR_DATA(IP5_14_13, VI2_HSYNC), 982 PINMUX_IPSR_DATA(IP5_14_13, VI2_HSYNC),
984 PINMUX_IPSR_DATA(IP5_14_13, VI3_HSYNC), 983 PINMUX_IPSR_DATA(IP5_14_13, VI3_HSYNC),
@@ -995,26 +994,26 @@ static const u16 pinmux_data[] = {
995 PINMUX_IPSR_DATA(IP5_20_17, AUDIO_CLKC), 994 PINMUX_IPSR_DATA(IP5_20_17, AUDIO_CLKC),
996 PINMUX_IPSR_DATA(IP5_20_17, TX2_D), 995 PINMUX_IPSR_DATA(IP5_20_17, TX2_D),
997 PINMUX_IPSR_DATA(IP5_20_17, SPEEDIN), 996 PINMUX_IPSR_DATA(IP5_20_17, SPEEDIN),
998 PINMUX_IPSR_MODSEL_DATA(IP5_20_17, GPS_SIGN_D, SEL_GPS_3), 997 PINMUX_IPSR_MSEL(IP5_20_17, GPS_SIGN_D, SEL_GPS_3),
999 PINMUX_IPSR_DATA(IP5_23_21, DU1_DISP), 998 PINMUX_IPSR_DATA(IP5_23_21, DU1_DISP),
1000 PINMUX_IPSR_DATA(IP5_23_21, VI2_DATA6_VI2_B6), 999 PINMUX_IPSR_DATA(IP5_23_21, VI2_DATA6_VI2_B6),
1001 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, TCLK0, SEL_TMU0_0), 1000 PINMUX_IPSR_MSEL(IP5_23_21, TCLK0, SEL_TMU0_0),
1002 PINMUX_IPSR_DATA(IP5_23_21, QSTVA_B_QVS_B), 1001 PINMUX_IPSR_DATA(IP5_23_21, QSTVA_B_QVS_B),
1003 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0), 1002 PINMUX_IPSR_MSEL(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0),
1004 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCK2_D, SEL_SCIF2_3), 1003 PINMUX_IPSR_MSEL(IP5_23_21, SCK2_D, SEL_SCIF2_3),
1005 PINMUX_IPSR_DATA(IP5_23_21, AUDIO_CLKOUT_B), 1004 PINMUX_IPSR_DATA(IP5_23_21, AUDIO_CLKOUT_B),
1006 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, GPS_MAG_D, SEL_GPS_3), 1005 PINMUX_IPSR_MSEL(IP5_23_21, GPS_MAG_D, SEL_GPS_3),
1007 PINMUX_IPSR_DATA(IP5_27_24, DU1_CDE), 1006 PINMUX_IPSR_DATA(IP5_27_24, DU1_CDE),
1008 PINMUX_IPSR_DATA(IP5_27_24, VI2_DATA7_VI2_B7), 1007 PINMUX_IPSR_DATA(IP5_27_24, VI2_DATA7_VI2_B7),
1009 PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1), 1008 PINMUX_IPSR_MSEL(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
1010 PINMUX_IPSR_DATA(IP5_27_24, SD3_WP), 1009 PINMUX_IPSR_DATA(IP5_27_24, SD3_WP),
1011 PINMUX_IPSR_MODSEL_DATA(IP5_27_24, HSPI_RX1, SEL_HSPI1_0), 1010 PINMUX_IPSR_MSEL(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
1012 PINMUX_IPSR_DATA(IP5_27_24, VI1_FIELD), 1011 PINMUX_IPSR_DATA(IP5_27_24, VI1_FIELD),
1013 PINMUX_IPSR_DATA(IP5_27_24, VI3_FIELD), 1012 PINMUX_IPSR_DATA(IP5_27_24, VI3_FIELD),
1014 PINMUX_IPSR_DATA(IP5_27_24, AUDIO_CLKOUT), 1013 PINMUX_IPSR_DATA(IP5_27_24, AUDIO_CLKOUT),
1015 PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX2_D, SEL_SCIF2_3), 1014 PINMUX_IPSR_MSEL(IP5_27_24, RX2_D, SEL_SCIF2_3),
1016 PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_C, SEL_GPS_2), 1015 PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_C, SEL_GPS_2),
1017 PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_D, SEL_GPS_3), 1016 PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_D, SEL_GPS_3),
1018 PINMUX_IPSR_DATA(IP5_28, AUDIO_CLKA), 1017 PINMUX_IPSR_DATA(IP5_28, AUDIO_CLKA),
1019 PINMUX_IPSR_DATA(IP5_28, CAN_TXCLK), 1018 PINMUX_IPSR_DATA(IP5_28, CAN_TXCLK),
1020 PINMUX_IPSR_DATA(IP5_30_29, AUDIO_CLKB), 1019 PINMUX_IPSR_DATA(IP5_30_29, AUDIO_CLKB),
@@ -1039,82 +1038,82 @@ static const u16 pinmux_data[] = {
1039 PINMUX_IPSR_DATA(IP6_11_9, SSI_SCK34), 1038 PINMUX_IPSR_DATA(IP6_11_9, SSI_SCK34),
1040 PINMUX_IPSR_DATA(IP6_11_9, CAN_DEBUGOUT6), 1039 PINMUX_IPSR_DATA(IP6_11_9, CAN_DEBUGOUT6),
1041 PINMUX_IPSR_DATA(IP6_11_9, CAN0_TX_B), 1040 PINMUX_IPSR_DATA(IP6_11_9, CAN0_TX_B),
1042 PINMUX_IPSR_MODSEL_DATA(IP6_11_9, IERX, SEL_IE_0), 1041 PINMUX_IPSR_MSEL(IP6_11_9, IERX, SEL_IE_0),
1043 PINMUX_IPSR_MODSEL_DATA(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2), 1042 PINMUX_IPSR_MSEL(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2),
1044 PINMUX_IPSR_DATA(IP6_14_12, SSI_WS34), 1043 PINMUX_IPSR_DATA(IP6_14_12, SSI_WS34),
1045 PINMUX_IPSR_DATA(IP6_14_12, CAN_DEBUGOUT7), 1044 PINMUX_IPSR_DATA(IP6_14_12, CAN_DEBUGOUT7),
1046 PINMUX_IPSR_MODSEL_DATA(IP6_14_12, CAN0_RX_B, SEL_CAN0_1), 1045 PINMUX_IPSR_MSEL(IP6_14_12, CAN0_RX_B, SEL_CAN0_1),
1047 PINMUX_IPSR_DATA(IP6_14_12, IETX), 1046 PINMUX_IPSR_DATA(IP6_14_12, IETX),
1048 PINMUX_IPSR_MODSEL_DATA(IP6_14_12, SSI_WS9_C, SEL_SSI9_2), 1047 PINMUX_IPSR_MSEL(IP6_14_12, SSI_WS9_C, SEL_SSI9_2),
1049 PINMUX_IPSR_DATA(IP6_17_15, SSI_SDATA3), 1048 PINMUX_IPSR_DATA(IP6_17_15, SSI_SDATA3),
1050 PINMUX_IPSR_DATA(IP6_17_15, PWM0_C), 1049 PINMUX_IPSR_DATA(IP6_17_15, PWM0_C),
1051 PINMUX_IPSR_DATA(IP6_17_15, CAN_DEBUGOUT8), 1050 PINMUX_IPSR_DATA(IP6_17_15, CAN_DEBUGOUT8),
1052 PINMUX_IPSR_MODSEL_DATA(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1), 1051 PINMUX_IPSR_MSEL(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1),
1053 PINMUX_IPSR_MODSEL_DATA(IP6_17_15, IECLK, SEL_IE_0), 1052 PINMUX_IPSR_MSEL(IP6_17_15, IECLK, SEL_IE_0),
1054 PINMUX_IPSR_MODSEL_DATA(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1), 1053 PINMUX_IPSR_MSEL(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1),
1055 PINMUX_IPSR_MODSEL_DATA(IP6_17_15, TCLK0_B, SEL_TMU0_1), 1054 PINMUX_IPSR_MSEL(IP6_17_15, TCLK0_B, SEL_TMU0_1),
1056 PINMUX_IPSR_DATA(IP6_19_18, SSI_SDATA4), 1055 PINMUX_IPSR_DATA(IP6_19_18, SSI_SDATA4),
1057 PINMUX_IPSR_DATA(IP6_19_18, CAN_DEBUGOUT9), 1056 PINMUX_IPSR_DATA(IP6_19_18, CAN_DEBUGOUT9),
1058 PINMUX_IPSR_MODSEL_DATA(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2), 1057 PINMUX_IPSR_MSEL(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2),
1059 PINMUX_IPSR_DATA(IP6_22_20, SSI_SCK5), 1058 PINMUX_IPSR_DATA(IP6_22_20, SSI_SCK5),
1060 PINMUX_IPSR_DATA(IP6_22_20, ADICLK), 1059 PINMUX_IPSR_DATA(IP6_22_20, ADICLK),
1061 PINMUX_IPSR_DATA(IP6_22_20, CAN_DEBUGOUT10), 1060 PINMUX_IPSR_DATA(IP6_22_20, CAN_DEBUGOUT10),
1062 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK3, SEL_SCIF3_0), 1061 PINMUX_IPSR_MSEL(IP6_22_20, SCK3, SEL_SCIF3_0),
1063 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TCLK0_D, SEL_TMU0_3), 1062 PINMUX_IPSR_MSEL(IP6_22_20, TCLK0_D, SEL_TMU0_3),
1064 PINMUX_IPSR_DATA(IP6_24_23, SSI_WS5), 1063 PINMUX_IPSR_DATA(IP6_24_23, SSI_WS5),
1065 PINMUX_IPSR_MODSEL_DATA(IP6_24_23, ADICS_SAMP, SEL_ADI_0), 1064 PINMUX_IPSR_MSEL(IP6_24_23, ADICS_SAMP, SEL_ADI_0),
1066 PINMUX_IPSR_DATA(IP6_24_23, CAN_DEBUGOUT11), 1065 PINMUX_IPSR_DATA(IP6_24_23, CAN_DEBUGOUT11),
1067 PINMUX_IPSR_DATA(IP6_24_23, TX3_IRDA_TX), 1066 PINMUX_IPSR_DATA(IP6_24_23, TX3_IRDA_TX),
1068 PINMUX_IPSR_DATA(IP6_26_25, SSI_SDATA5), 1067 PINMUX_IPSR_DATA(IP6_26_25, SSI_SDATA5),
1069 PINMUX_IPSR_MODSEL_DATA(IP6_26_25, ADIDATA, SEL_ADI_0), 1068 PINMUX_IPSR_MSEL(IP6_26_25, ADIDATA, SEL_ADI_0),
1070 PINMUX_IPSR_DATA(IP6_26_25, CAN_DEBUGOUT12), 1069 PINMUX_IPSR_DATA(IP6_26_25, CAN_DEBUGOUT12),
1071 PINMUX_IPSR_MODSEL_DATA(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0), 1070 PINMUX_IPSR_MSEL(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0),
1072 PINMUX_IPSR_DATA(IP6_30_29, SSI_SCK6), 1071 PINMUX_IPSR_DATA(IP6_30_29, SSI_SCK6),
1073 PINMUX_IPSR_DATA(IP6_30_29, ADICHS0), 1072 PINMUX_IPSR_DATA(IP6_30_29, ADICHS0),
1074 PINMUX_IPSR_DATA(IP6_30_29, CAN0_TX), 1073 PINMUX_IPSR_DATA(IP6_30_29, CAN0_TX),
1075 PINMUX_IPSR_MODSEL_DATA(IP6_30_29, IERX_B, SEL_IE_1), 1074 PINMUX_IPSR_MSEL(IP6_30_29, IERX_B, SEL_IE_1),
1076 1075
1077 PINMUX_IPSR_DATA(IP7_1_0, SSI_WS6), 1076 PINMUX_IPSR_DATA(IP7_1_0, SSI_WS6),
1078 PINMUX_IPSR_DATA(IP7_1_0, ADICHS1), 1077 PINMUX_IPSR_DATA(IP7_1_0, ADICHS1),
1079 PINMUX_IPSR_MODSEL_DATA(IP7_1_0, CAN0_RX, SEL_CAN0_0), 1078 PINMUX_IPSR_MSEL(IP7_1_0, CAN0_RX, SEL_CAN0_0),
1080 PINMUX_IPSR_DATA(IP7_1_0, IETX_B), 1079 PINMUX_IPSR_DATA(IP7_1_0, IETX_B),
1081 PINMUX_IPSR_DATA(IP7_3_2, SSI_SDATA6), 1080 PINMUX_IPSR_DATA(IP7_3_2, SSI_SDATA6),
1082 PINMUX_IPSR_DATA(IP7_3_2, ADICHS2), 1081 PINMUX_IPSR_DATA(IP7_3_2, ADICHS2),
1083 PINMUX_IPSR_MODSEL_DATA(IP7_3_2, CAN_CLK, SEL_CANCLK_0), 1082 PINMUX_IPSR_MSEL(IP7_3_2, CAN_CLK, SEL_CANCLK_0),
1084 PINMUX_IPSR_MODSEL_DATA(IP7_3_2, IECLK_B, SEL_IE_1), 1083 PINMUX_IPSR_MSEL(IP7_3_2, IECLK_B, SEL_IE_1),
1085 PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK78, SEL_SSI7_0), 1084 PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK78, SEL_SSI7_0),
1086 PINMUX_IPSR_DATA(IP7_6_4, CAN_DEBUGOUT13), 1085 PINMUX_IPSR_DATA(IP7_6_4, CAN_DEBUGOUT13),
1087 PINMUX_IPSR_MODSEL_DATA(IP7_6_4, IRQ0_B, SEL_INT0_1), 1086 PINMUX_IPSR_MSEL(IP7_6_4, IRQ0_B, SEL_INT0_1),
1088 PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1), 1087 PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1),
1089 PINMUX_IPSR_MODSEL_DATA(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2), 1088 PINMUX_IPSR_MSEL(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2),
1090 PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS78, SEL_SSI7_0), 1089 PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS78, SEL_SSI7_0),
1091 PINMUX_IPSR_DATA(IP7_9_7, CAN_DEBUGOUT14), 1090 PINMUX_IPSR_DATA(IP7_9_7, CAN_DEBUGOUT14),
1092 PINMUX_IPSR_MODSEL_DATA(IP7_9_7, IRQ1_B, SEL_INT1_1), 1091 PINMUX_IPSR_MSEL(IP7_9_7, IRQ1_B, SEL_INT1_1),
1093 PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS9_B, SEL_SSI9_1), 1092 PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS9_B, SEL_SSI9_1),
1094 PINMUX_IPSR_MODSEL_DATA(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2), 1093 PINMUX_IPSR_MSEL(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2),
1095 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, SSI_SDATA7, SEL_SSI7_0), 1094 PINMUX_IPSR_MSEL(IP7_12_10, SSI_SDATA7, SEL_SSI7_0),
1096 PINMUX_IPSR_DATA(IP7_12_10, CAN_DEBUGOUT15), 1095 PINMUX_IPSR_DATA(IP7_12_10, CAN_DEBUGOUT15),
1097 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, IRQ2_B, SEL_INT2_1), 1096 PINMUX_IPSR_MSEL(IP7_12_10, IRQ2_B, SEL_INT2_1),
1098 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TCLK1_C, SEL_TMU1_2), 1097 PINMUX_IPSR_MSEL(IP7_12_10, TCLK1_C, SEL_TMU1_2),
1099 PINMUX_IPSR_DATA(IP7_12_10, HSPI_TX1_C), 1098 PINMUX_IPSR_DATA(IP7_12_10, HSPI_TX1_C),
1100 PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA8, SEL_SSI8_0), 1099 PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA8, SEL_SSI8_0),
1101 PINMUX_IPSR_DATA(IP7_14_13, VSP), 1100 PINMUX_IPSR_DATA(IP7_14_13, VSP),
1102 PINMUX_IPSR_MODSEL_DATA(IP7_14_13, IRQ3_B, SEL_INT3_1), 1101 PINMUX_IPSR_MSEL(IP7_14_13, IRQ3_B, SEL_INT3_1),
1103 PINMUX_IPSR_MODSEL_DATA(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2), 1102 PINMUX_IPSR_MSEL(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2),
1104 PINMUX_IPSR_DATA(IP7_16_15, SD0_CLK), 1103 PINMUX_IPSR_DATA(IP7_16_15, SD0_CLK),
1105 PINMUX_IPSR_DATA(IP7_16_15, ATACS01), 1104 PINMUX_IPSR_DATA(IP7_16_15, ATACS01),
1106 PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SCK1_B, SEL_SCIF1_1), 1105 PINMUX_IPSR_MSEL(IP7_16_15, SCK1_B, SEL_SCIF1_1),
1107 PINMUX_IPSR_DATA(IP7_18_17, SD0_CMD), 1106 PINMUX_IPSR_DATA(IP7_18_17, SD0_CMD),
1108 PINMUX_IPSR_DATA(IP7_18_17, ATACS11), 1107 PINMUX_IPSR_DATA(IP7_18_17, ATACS11),
1109 PINMUX_IPSR_DATA(IP7_18_17, TX1_B), 1108 PINMUX_IPSR_DATA(IP7_18_17, TX1_B),
1110 PINMUX_IPSR_DATA(IP7_18_17, CC5_TDO), 1109 PINMUX_IPSR_DATA(IP7_18_17, CC5_TDO),
1111 PINMUX_IPSR_DATA(IP7_20_19, SD0_DAT0), 1110 PINMUX_IPSR_DATA(IP7_20_19, SD0_DAT0),
1112 PINMUX_IPSR_DATA(IP7_20_19, ATADIR1), 1111 PINMUX_IPSR_DATA(IP7_20_19, ATADIR1),
1113 PINMUX_IPSR_MODSEL_DATA(IP7_20_19, RX1_B, SEL_SCIF1_1), 1112 PINMUX_IPSR_MSEL(IP7_20_19, RX1_B, SEL_SCIF1_1),
1114 PINMUX_IPSR_DATA(IP7_20_19, CC5_TRST), 1113 PINMUX_IPSR_DATA(IP7_20_19, CC5_TRST),
1115 PINMUX_IPSR_DATA(IP7_22_21, SD0_DAT1), 1114 PINMUX_IPSR_DATA(IP7_22_21, SD0_DAT1),
1116 PINMUX_IPSR_DATA(IP7_22_21, ATAG1), 1115 PINMUX_IPSR_DATA(IP7_22_21, ATAG1),
1117 PINMUX_IPSR_MODSEL_DATA(IP7_22_21, SCK2_B, SEL_SCIF2_1), 1116 PINMUX_IPSR_MSEL(IP7_22_21, SCK2_B, SEL_SCIF2_1),
1118 PINMUX_IPSR_DATA(IP7_22_21, CC5_TMS), 1117 PINMUX_IPSR_DATA(IP7_22_21, CC5_TMS),
1119 PINMUX_IPSR_DATA(IP7_24_23, SD0_DAT2), 1118 PINMUX_IPSR_DATA(IP7_24_23, SD0_DAT2),
1120 PINMUX_IPSR_DATA(IP7_24_23, ATARD1), 1119 PINMUX_IPSR_DATA(IP7_24_23, ATARD1),
@@ -1122,17 +1121,17 @@ static const u16 pinmux_data[] = {
1122 PINMUX_IPSR_DATA(IP7_24_23, CC5_TCK), 1121 PINMUX_IPSR_DATA(IP7_24_23, CC5_TCK),
1123 PINMUX_IPSR_DATA(IP7_26_25, SD0_DAT3), 1122 PINMUX_IPSR_DATA(IP7_26_25, SD0_DAT3),
1124 PINMUX_IPSR_DATA(IP7_26_25, ATAWR1), 1123 PINMUX_IPSR_DATA(IP7_26_25, ATAWR1),
1125 PINMUX_IPSR_MODSEL_DATA(IP7_26_25, RX2_B, SEL_SCIF2_1), 1124 PINMUX_IPSR_MSEL(IP7_26_25, RX2_B, SEL_SCIF2_1),
1126 PINMUX_IPSR_DATA(IP7_26_25, CC5_TDI), 1125 PINMUX_IPSR_DATA(IP7_26_25, CC5_TDI),
1127 PINMUX_IPSR_DATA(IP7_28_27, SD0_CD), 1126 PINMUX_IPSR_DATA(IP7_28_27, SD0_CD),
1128 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, DREQ2, SEL_EXBUS2_0), 1127 PINMUX_IPSR_MSEL(IP7_28_27, DREQ2, SEL_EXBUS2_0),
1129 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1), 1128 PINMUX_IPSR_MSEL(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1),
1130 PINMUX_IPSR_DATA(IP7_30_29, SD0_WP), 1129 PINMUX_IPSR_DATA(IP7_30_29, SD0_WP),
1131 PINMUX_IPSR_DATA(IP7_30_29, DACK2), 1130 PINMUX_IPSR_DATA(IP7_30_29, DACK2),
1132 PINMUX_IPSR_MODSEL_DATA(IP7_30_29, CTS1_B, SEL_SCIF1_1), 1131 PINMUX_IPSR_MSEL(IP7_30_29, CTS1_B, SEL_SCIF1_1),
1133 1132
1134 PINMUX_IPSR_DATA(IP8_3_0, HSPI_CLK0), 1133 PINMUX_IPSR_DATA(IP8_3_0, HSPI_CLK0),
1135 PINMUX_IPSR_MODSEL_DATA(IP8_3_0, CTS0, SEL_SCIF0_0), 1134 PINMUX_IPSR_MSEL(IP8_3_0, CTS0, SEL_SCIF0_0),
1136 PINMUX_IPSR_DATA(IP8_3_0, USB_OVC0), 1135 PINMUX_IPSR_DATA(IP8_3_0, USB_OVC0),
1137 PINMUX_IPSR_DATA(IP8_3_0, AD_CLK), 1136 PINMUX_IPSR_DATA(IP8_3_0, AD_CLK),
1138 PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE4), 1137 PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE4),
@@ -1141,7 +1140,7 @@ static const u16 pinmux_data[] = {
1141 PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE28), 1140 PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE28),
1142 PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE36), 1141 PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE36),
1143 PINMUX_IPSR_DATA(IP8_7_4, HSPI_CS0), 1142 PINMUX_IPSR_DATA(IP8_7_4, HSPI_CS0),
1144 PINMUX_IPSR_MODSEL_DATA(IP8_7_4, RTS0_TANS, SEL_SCIF0_0), 1143 PINMUX_IPSR_MSEL(IP8_7_4, RTS0_TANS, SEL_SCIF0_0),
1145 PINMUX_IPSR_DATA(IP8_7_4, USB_OVC1), 1144 PINMUX_IPSR_DATA(IP8_7_4, USB_OVC1),
1146 PINMUX_IPSR_DATA(IP8_7_4, AD_DI), 1145 PINMUX_IPSR_DATA(IP8_7_4, AD_DI),
1147 PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE5), 1146 PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE5),
@@ -1159,7 +1158,7 @@ static const u16 pinmux_data[] = {
1159 PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE30), 1158 PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE30),
1160 PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE38), 1159 PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE38),
1161 PINMUX_IPSR_DATA(IP8_15_12, HSPI_RX0), 1160 PINMUX_IPSR_DATA(IP8_15_12, HSPI_RX0),
1162 PINMUX_IPSR_MODSEL_DATA(IP8_15_12, RX0, SEL_SCIF0_0), 1161 PINMUX_IPSR_MSEL(IP8_15_12, RX0, SEL_SCIF0_0),
1163 PINMUX_IPSR_DATA(IP8_15_12, CAN_STEP0), 1162 PINMUX_IPSR_DATA(IP8_15_12, CAN_STEP0),
1164 PINMUX_IPSR_DATA(IP8_15_12, AD_NCS), 1163 PINMUX_IPSR_DATA(IP8_15_12, AD_NCS),
1165 PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE7), 1164 PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE7),
@@ -1181,25 +1180,25 @@ static const u16 pinmux_data[] = {
1181 PINMUX_IPSR_DATA(IP8_22_21, HTX1_B), 1180 PINMUX_IPSR_DATA(IP8_22_21, HTX1_B),
1182 PINMUX_IPSR_DATA(IP8_22_21, MT1_SYNC), 1181 PINMUX_IPSR_DATA(IP8_22_21, MT1_SYNC),
1183 PINMUX_IPSR_DATA(IP8_24_23, VI0_FIELD), 1182 PINMUX_IPSR_DATA(IP8_24_23, VI0_FIELD),
1184 PINMUX_IPSR_MODSEL_DATA(IP8_24_23, RX1_C, SEL_SCIF1_2), 1183 PINMUX_IPSR_MSEL(IP8_24_23, RX1_C, SEL_SCIF1_2),
1185 PINMUX_IPSR_MODSEL_DATA(IP8_24_23, HRX1_B, SEL_HSCIF1_1), 1184 PINMUX_IPSR_MSEL(IP8_24_23, HRX1_B, SEL_HSCIF1_1),
1186 PINMUX_IPSR_DATA(IP8_27_25, VI0_HSYNC), 1185 PINMUX_IPSR_DATA(IP8_27_25, VI0_HSYNC),
1187 PINMUX_IPSR_MODSEL_DATA(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1), 1186 PINMUX_IPSR_MSEL(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1),
1188 PINMUX_IPSR_MODSEL_DATA(IP8_27_25, CTS1_C, SEL_SCIF1_2), 1187 PINMUX_IPSR_MSEL(IP8_27_25, CTS1_C, SEL_SCIF1_2),
1189 PINMUX_IPSR_DATA(IP8_27_25, TX4_D), 1188 PINMUX_IPSR_DATA(IP8_27_25, TX4_D),
1190 PINMUX_IPSR_DATA(IP8_27_25, MMC1_CMD), 1189 PINMUX_IPSR_DATA(IP8_27_25, MMC1_CMD),
1191 PINMUX_IPSR_MODSEL_DATA(IP8_27_25, HSCK1_B, SEL_HSCIF1_1), 1190 PINMUX_IPSR_MSEL(IP8_27_25, HSCK1_B, SEL_HSCIF1_1),
1192 PINMUX_IPSR_DATA(IP8_30_28, VI0_VSYNC), 1191 PINMUX_IPSR_DATA(IP8_30_28, VI0_VSYNC),
1193 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1), 1192 PINMUX_IPSR_MSEL(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1),
1194 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2), 1193 PINMUX_IPSR_MSEL(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2),
1195 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RX4_D, SEL_SCIF4_3), 1194 PINMUX_IPSR_MSEL(IP8_30_28, RX4_D, SEL_SCIF4_3),
1196 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2), 1195 PINMUX_IPSR_MSEL(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2),
1197 1196
1198 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0), 1197 PINMUX_IPSR_MSEL(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0),
1199 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, HRTS1_B, SEL_HSCIF1_1), 1198 PINMUX_IPSR_MSEL(IP9_1_0, HRTS1_B, SEL_HSCIF1_1),
1200 PINMUX_IPSR_DATA(IP9_1_0, MT1_VCXO), 1199 PINMUX_IPSR_DATA(IP9_1_0, MT1_VCXO),
1201 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0), 1200 PINMUX_IPSR_MSEL(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0),
1202 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, HCTS1_B, SEL_HSCIF1_1), 1201 PINMUX_IPSR_MSEL(IP9_3_2, HCTS1_B, SEL_HSCIF1_1),
1203 PINMUX_IPSR_DATA(IP9_3_2, MT1_PWM), 1202 PINMUX_IPSR_DATA(IP9_3_2, MT1_PWM),
1204 PINMUX_IPSR_DATA(IP9_4, VI0_DATA2_VI0_B2), 1203 PINMUX_IPSR_DATA(IP9_4, VI0_DATA2_VI0_B2),
1205 PINMUX_IPSR_DATA(IP9_4, MMC1_D0), 1204 PINMUX_IPSR_DATA(IP9_4, MMC1_D0),
@@ -1216,12 +1215,12 @@ static const u16 pinmux_data[] = {
1216 PINMUX_IPSR_DATA(IP9_11_10, MMC1_D5), 1215 PINMUX_IPSR_DATA(IP9_11_10, MMC1_D5),
1217 PINMUX_IPSR_DATA(IP9_11_10, ARM_TRACEDATA_1), 1216 PINMUX_IPSR_DATA(IP9_11_10, ARM_TRACEDATA_1),
1218 PINMUX_IPSR_DATA(IP9_13_12, VI0_G0), 1217 PINMUX_IPSR_DATA(IP9_13_12, VI0_G0),
1219 PINMUX_IPSR_MODSEL_DATA(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2), 1218 PINMUX_IPSR_MSEL(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2),
1220 PINMUX_IPSR_MODSEL_DATA(IP9_13_12, IRQ0, SEL_INT0_0), 1219 PINMUX_IPSR_MSEL(IP9_13_12, IRQ0, SEL_INT0_0),
1221 PINMUX_IPSR_DATA(IP9_13_12, ARM_TRACEDATA_2), 1220 PINMUX_IPSR_DATA(IP9_13_12, ARM_TRACEDATA_2),
1222 PINMUX_IPSR_DATA(IP9_15_14, VI0_G1), 1221 PINMUX_IPSR_DATA(IP9_15_14, VI0_G1),
1223 PINMUX_IPSR_MODSEL_DATA(IP9_15_14, SSI_WS78_C, SEL_SSI7_2), 1222 PINMUX_IPSR_MSEL(IP9_15_14, SSI_WS78_C, SEL_SSI7_2),
1224 PINMUX_IPSR_MODSEL_DATA(IP9_15_14, IRQ1, SEL_INT1_0), 1223 PINMUX_IPSR_MSEL(IP9_15_14, IRQ1, SEL_INT1_0),
1225 PINMUX_IPSR_DATA(IP9_15_14, ARM_TRACEDATA_3), 1224 PINMUX_IPSR_DATA(IP9_15_14, ARM_TRACEDATA_3),
1226 PINMUX_IPSR_DATA(IP9_18_16, VI0_G2), 1225 PINMUX_IPSR_DATA(IP9_18_16, VI0_G2),
1227 PINMUX_IPSR_DATA(IP9_18_16, ETH_TXD1), 1226 PINMUX_IPSR_DATA(IP9_18_16, ETH_TXD1),
@@ -1235,29 +1234,29 @@ static const u16 pinmux_data[] = {
1235 PINMUX_IPSR_DATA(IP9_21_19, TS_SDAT0), 1234 PINMUX_IPSR_DATA(IP9_21_19, TS_SDAT0),
1236 PINMUX_IPSR_DATA(IP9_23_22, VI0_G4), 1235 PINMUX_IPSR_DATA(IP9_23_22, VI0_G4),
1237 PINMUX_IPSR_DATA(IP9_23_22, ETH_TX_EN), 1236 PINMUX_IPSR_DATA(IP9_23_22, ETH_TX_EN),
1238 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SD2_DAT0_B, SEL_SD2_1), 1237 PINMUX_IPSR_MSEL(IP9_23_22, SD2_DAT0_B, SEL_SD2_1),
1239 PINMUX_IPSR_DATA(IP9_23_22, ARM_TRACEDATA_6), 1238 PINMUX_IPSR_DATA(IP9_23_22, ARM_TRACEDATA_6),
1240 PINMUX_IPSR_DATA(IP9_25_24, VI0_G5), 1239 PINMUX_IPSR_DATA(IP9_25_24, VI0_G5),
1241 PINMUX_IPSR_DATA(IP9_25_24, ETH_RX_ER), 1240 PINMUX_IPSR_DATA(IP9_25_24, ETH_RX_ER),
1242 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SD2_DAT1_B, SEL_SD2_1), 1241 PINMUX_IPSR_MSEL(IP9_25_24, SD2_DAT1_B, SEL_SD2_1),
1243 PINMUX_IPSR_DATA(IP9_25_24, ARM_TRACEDATA_7), 1242 PINMUX_IPSR_DATA(IP9_25_24, ARM_TRACEDATA_7),
1244 PINMUX_IPSR_DATA(IP9_27_26, VI0_G6), 1243 PINMUX_IPSR_DATA(IP9_27_26, VI0_G6),
1245 PINMUX_IPSR_DATA(IP9_27_26, ETH_RXD0), 1244 PINMUX_IPSR_DATA(IP9_27_26, ETH_RXD0),
1246 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SD2_DAT2_B, SEL_SD2_1), 1245 PINMUX_IPSR_MSEL(IP9_27_26, SD2_DAT2_B, SEL_SD2_1),
1247 PINMUX_IPSR_DATA(IP9_27_26, ARM_TRACEDATA_8), 1246 PINMUX_IPSR_DATA(IP9_27_26, ARM_TRACEDATA_8),
1248 PINMUX_IPSR_DATA(IP9_29_28, VI0_G7), 1247 PINMUX_IPSR_DATA(IP9_29_28, VI0_G7),
1249 PINMUX_IPSR_DATA(IP9_29_28, ETH_RXD1), 1248 PINMUX_IPSR_DATA(IP9_29_28, ETH_RXD1),
1250 PINMUX_IPSR_MODSEL_DATA(IP9_29_28, SD2_DAT3_B, SEL_SD2_1), 1249 PINMUX_IPSR_MSEL(IP9_29_28, SD2_DAT3_B, SEL_SD2_1),
1251 PINMUX_IPSR_DATA(IP9_29_28, ARM_TRACEDATA_9), 1250 PINMUX_IPSR_DATA(IP9_29_28, ARM_TRACEDATA_9),
1252 1251
1253 PINMUX_IPSR_DATA(IP10_2_0, VI0_R0), 1252 PINMUX_IPSR_DATA(IP10_2_0, VI0_R0),
1254 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2), 1253 PINMUX_IPSR_MSEL(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2),
1255 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCK1_C, SEL_SCIF1_2), 1254 PINMUX_IPSR_MSEL(IP10_2_0, SCK1_C, SEL_SCIF1_2),
1256 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ1_B, SEL_EXBUS1_0), 1255 PINMUX_IPSR_MSEL(IP10_2_0, DREQ1_B, SEL_EXBUS1_0),
1257 PINMUX_IPSR_DATA(IP10_2_0, ARM_TRACEDATA_10), 1256 PINMUX_IPSR_DATA(IP10_2_0, ARM_TRACEDATA_10),
1258 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ0_C, SEL_EXBUS0_2), 1257 PINMUX_IPSR_MSEL(IP10_2_0, DREQ0_C, SEL_EXBUS0_2),
1259 PINMUX_IPSR_DATA(IP10_5_3, VI0_R1), 1258 PINMUX_IPSR_DATA(IP10_5_3, VI0_R1),
1260 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2), 1259 PINMUX_IPSR_MSEL(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2),
1261 PINMUX_IPSR_DATA(IP10_5_3, DACK1_B), 1260 PINMUX_IPSR_DATA(IP10_5_3, DACK1_B),
1262 PINMUX_IPSR_DATA(IP10_5_3, ARM_TRACEDATA_11), 1261 PINMUX_IPSR_DATA(IP10_5_3, ARM_TRACEDATA_11),
1263 PINMUX_IPSR_DATA(IP10_5_3, DACK0_C), 1262 PINMUX_IPSR_DATA(IP10_5_3, DACK0_C),
@@ -1265,74 +1264,74 @@ static const u16 pinmux_data[] = {
1265 PINMUX_IPSR_DATA(IP10_8_6, VI0_R2), 1264 PINMUX_IPSR_DATA(IP10_8_6, VI0_R2),
1266 PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK), 1265 PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK),
1267 PINMUX_IPSR_DATA(IP10_8_6, SD2_CLK_B), 1266 PINMUX_IPSR_DATA(IP10_8_6, SD2_CLK_B),
1268 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IRQ2, SEL_INT2_0), 1267 PINMUX_IPSR_MSEL(IP10_8_6, IRQ2, SEL_INT2_0),
1269 PINMUX_IPSR_DATA(IP10_8_6, ARM_TRACEDATA_12), 1268 PINMUX_IPSR_DATA(IP10_8_6, ARM_TRACEDATA_12),
1270 PINMUX_IPSR_DATA(IP10_11_9, VI0_R3), 1269 PINMUX_IPSR_DATA(IP10_11_9, VI0_R3),
1271 PINMUX_IPSR_DATA(IP10_11_9, ETH_MAGIC), 1270 PINMUX_IPSR_DATA(IP10_11_9, ETH_MAGIC),
1272 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SD2_CMD_B, SEL_SD2_1), 1271 PINMUX_IPSR_MSEL(IP10_11_9, SD2_CMD_B, SEL_SD2_1),
1273 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IRQ3, SEL_INT3_0), 1272 PINMUX_IPSR_MSEL(IP10_11_9, IRQ3, SEL_INT3_0),
1274 PINMUX_IPSR_DATA(IP10_11_9, ARM_TRACEDATA_13), 1273 PINMUX_IPSR_DATA(IP10_11_9, ARM_TRACEDATA_13),
1275 PINMUX_IPSR_DATA(IP10_14_12, VI0_R4), 1274 PINMUX_IPSR_DATA(IP10_14_12, VI0_R4),
1276 PINMUX_IPSR_DATA(IP10_14_12, ETH_REFCLK), 1275 PINMUX_IPSR_DATA(IP10_14_12, ETH_REFCLK),
1277 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SD2_CD_B, SEL_SD2_1), 1276 PINMUX_IPSR_MSEL(IP10_14_12, SD2_CD_B, SEL_SD2_1),
1278 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1), 1277 PINMUX_IPSR_MSEL(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1),
1279 PINMUX_IPSR_DATA(IP10_14_12, ARM_TRACEDATA_14), 1278 PINMUX_IPSR_DATA(IP10_14_12, ARM_TRACEDATA_14),
1280 PINMUX_IPSR_DATA(IP10_14_12, MT1_CLK), 1279 PINMUX_IPSR_DATA(IP10_14_12, MT1_CLK),
1281 PINMUX_IPSR_DATA(IP10_14_12, TS_SCK0), 1280 PINMUX_IPSR_DATA(IP10_14_12, TS_SCK0),
1282 PINMUX_IPSR_DATA(IP10_17_15, VI0_R5), 1281 PINMUX_IPSR_DATA(IP10_17_15, VI0_R5),
1283 PINMUX_IPSR_DATA(IP10_17_15, ETH_TXD0), 1282 PINMUX_IPSR_DATA(IP10_17_15, ETH_TXD0),
1284 PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SD2_WP_B, SEL_SD2_1), 1283 PINMUX_IPSR_MSEL(IP10_17_15, SD2_WP_B, SEL_SD2_1),
1285 PINMUX_IPSR_MODSEL_DATA(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1), 1284 PINMUX_IPSR_MSEL(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1),
1286 PINMUX_IPSR_DATA(IP10_17_15, ARM_TRACEDATA_15), 1285 PINMUX_IPSR_DATA(IP10_17_15, ARM_TRACEDATA_15),
1287 PINMUX_IPSR_DATA(IP10_17_15, MT1_D), 1286 PINMUX_IPSR_DATA(IP10_17_15, MT1_D),
1288 PINMUX_IPSR_DATA(IP10_17_15, TS_SDEN0), 1287 PINMUX_IPSR_DATA(IP10_17_15, TS_SDEN0),
1289 PINMUX_IPSR_DATA(IP10_20_18, VI0_R6), 1288 PINMUX_IPSR_DATA(IP10_20_18, VI0_R6),
1290 PINMUX_IPSR_DATA(IP10_20_18, ETH_MDC), 1289 PINMUX_IPSR_DATA(IP10_20_18, ETH_MDC),
1291 PINMUX_IPSR_MODSEL_DATA(IP10_20_18, DREQ2_C, SEL_EXBUS2_2), 1290 PINMUX_IPSR_MSEL(IP10_20_18, DREQ2_C, SEL_EXBUS2_2),
1292 PINMUX_IPSR_DATA(IP10_20_18, HSPI_TX1_B), 1291 PINMUX_IPSR_DATA(IP10_20_18, HSPI_TX1_B),
1293 PINMUX_IPSR_DATA(IP10_20_18, TRACECLK), 1292 PINMUX_IPSR_DATA(IP10_20_18, TRACECLK),
1294 PINMUX_IPSR_DATA(IP10_20_18, MT1_BEN), 1293 PINMUX_IPSR_DATA(IP10_20_18, MT1_BEN),
1295 PINMUX_IPSR_MODSEL_DATA(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3), 1294 PINMUX_IPSR_MSEL(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3),
1296 PINMUX_IPSR_DATA(IP10_23_21, VI0_R7), 1295 PINMUX_IPSR_DATA(IP10_23_21, VI0_R7),
1297 PINMUX_IPSR_DATA(IP10_23_21, ETH_MDIO), 1296 PINMUX_IPSR_DATA(IP10_23_21, ETH_MDIO),
1298 PINMUX_IPSR_DATA(IP10_23_21, DACK2_C), 1297 PINMUX_IPSR_DATA(IP10_23_21, DACK2_C),
1299 PINMUX_IPSR_MODSEL_DATA(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1), 1298 PINMUX_IPSR_MSEL(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1),
1300 PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3), 1299 PINMUX_IPSR_MSEL(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3),
1301 PINMUX_IPSR_DATA(IP10_23_21, TRACECTL), 1300 PINMUX_IPSR_DATA(IP10_23_21, TRACECTL),
1302 PINMUX_IPSR_DATA(IP10_23_21, MT1_PEN), 1301 PINMUX_IPSR_DATA(IP10_23_21, MT1_PEN),
1303 PINMUX_IPSR_DATA(IP10_25_24, VI1_CLK), 1302 PINMUX_IPSR_DATA(IP10_25_24, VI1_CLK),
1304 PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SIM_D, SEL_SIM_0), 1303 PINMUX_IPSR_MSEL(IP10_25_24, SIM_D, SEL_SIM_0),
1305 PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SDA3, SEL_I2C3_0), 1304 PINMUX_IPSR_MSEL(IP10_25_24, SDA3, SEL_I2C3_0),
1306 PINMUX_IPSR_DATA(IP10_28_26, VI1_HSYNC), 1305 PINMUX_IPSR_DATA(IP10_28_26, VI1_HSYNC),
1307 PINMUX_IPSR_DATA(IP10_28_26, VI3_CLK), 1306 PINMUX_IPSR_DATA(IP10_28_26, VI3_CLK),
1308 PINMUX_IPSR_DATA(IP10_28_26, SSI_SCK4), 1307 PINMUX_IPSR_DATA(IP10_28_26, SSI_SCK4),
1309 PINMUX_IPSR_MODSEL_DATA(IP10_28_26, GPS_SIGN_C, SEL_GPS_2), 1308 PINMUX_IPSR_MSEL(IP10_28_26, GPS_SIGN_C, SEL_GPS_2),
1310 PINMUX_IPSR_MODSEL_DATA(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4), 1309 PINMUX_IPSR_MSEL(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4),
1311 PINMUX_IPSR_DATA(IP10_31_29, VI1_VSYNC), 1310 PINMUX_IPSR_DATA(IP10_31_29, VI1_VSYNC),
1312 PINMUX_IPSR_DATA(IP10_31_29, AUDIO_CLKOUT_C), 1311 PINMUX_IPSR_DATA(IP10_31_29, AUDIO_CLKOUT_C),
1313 PINMUX_IPSR_DATA(IP10_31_29, SSI_WS4), 1312 PINMUX_IPSR_DATA(IP10_31_29, SSI_WS4),
1314 PINMUX_IPSR_DATA(IP10_31_29, SIM_CLK), 1313 PINMUX_IPSR_DATA(IP10_31_29, SIM_CLK),
1315 PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GPS_MAG_C, SEL_GPS_2), 1314 PINMUX_IPSR_MSEL(IP10_31_29, GPS_MAG_C, SEL_GPS_2),
1316 PINMUX_IPSR_DATA(IP10_31_29, SPV_TRST), 1315 PINMUX_IPSR_DATA(IP10_31_29, SPV_TRST),
1317 PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL3, SEL_I2C3_0), 1316 PINMUX_IPSR_MSEL(IP10_31_29, SCL3, SEL_I2C3_0),
1318 1317
1319 PINMUX_IPSR_DATA(IP11_2_0, VI1_DATA0_VI1_B0), 1318 PINMUX_IPSR_DATA(IP11_2_0, VI1_DATA0_VI1_B0),
1320 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SD2_DAT0, SEL_SD2_0), 1319 PINMUX_IPSR_MSEL(IP11_2_0, SD2_DAT0, SEL_SD2_0),
1321 PINMUX_IPSR_DATA(IP11_2_0, SIM_RST), 1320 PINMUX_IPSR_DATA(IP11_2_0, SIM_RST),
1322 PINMUX_IPSR_DATA(IP11_2_0, SPV_TCK), 1321 PINMUX_IPSR_DATA(IP11_2_0, SPV_TCK),
1323 PINMUX_IPSR_DATA(IP11_2_0, ADICLK_B), 1322 PINMUX_IPSR_DATA(IP11_2_0, ADICLK_B),
1324 PINMUX_IPSR_DATA(IP11_5_3, VI1_DATA1_VI1_B1), 1323 PINMUX_IPSR_DATA(IP11_5_3, VI1_DATA1_VI1_B1),
1325 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SD2_DAT1, SEL_SD2_0), 1324 PINMUX_IPSR_MSEL(IP11_5_3, SD2_DAT1, SEL_SD2_0),
1326 PINMUX_IPSR_DATA(IP11_5_3, MT0_CLK), 1325 PINMUX_IPSR_DATA(IP11_5_3, MT0_CLK),
1327 PINMUX_IPSR_DATA(IP11_5_3, SPV_TMS), 1326 PINMUX_IPSR_DATA(IP11_5_3, SPV_TMS),
1328 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1), 1327 PINMUX_IPSR_MSEL(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1),
1329 PINMUX_IPSR_DATA(IP11_8_6, VI1_DATA2_VI1_B2), 1328 PINMUX_IPSR_DATA(IP11_8_6, VI1_DATA2_VI1_B2),
1330 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SD2_DAT2, SEL_SD2_0), 1329 PINMUX_IPSR_MSEL(IP11_8_6, SD2_DAT2, SEL_SD2_0),
1331 PINMUX_IPSR_DATA(IP11_8_6, MT0_D), 1330 PINMUX_IPSR_DATA(IP11_8_6, MT0_D),
1332 PINMUX_IPSR_DATA(IP11_8_6, SPVTDI), 1331 PINMUX_IPSR_DATA(IP11_8_6, SPVTDI),
1333 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, ADIDATA_B, SEL_ADI_1), 1332 PINMUX_IPSR_MSEL(IP11_8_6, ADIDATA_B, SEL_ADI_1),
1334 PINMUX_IPSR_DATA(IP11_11_9, VI1_DATA3_VI1_B3), 1333 PINMUX_IPSR_DATA(IP11_11_9, VI1_DATA3_VI1_B3),
1335 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SD2_DAT3, SEL_SD2_0), 1334 PINMUX_IPSR_MSEL(IP11_11_9, SD2_DAT3, SEL_SD2_0),
1336 PINMUX_IPSR_DATA(IP11_11_9, MT0_BEN), 1335 PINMUX_IPSR_DATA(IP11_11_9, MT0_BEN),
1337 PINMUX_IPSR_DATA(IP11_11_9, SPV_TDO), 1336 PINMUX_IPSR_DATA(IP11_11_9, SPV_TDO),
1338 PINMUX_IPSR_DATA(IP11_11_9, ADICHS0_B), 1337 PINMUX_IPSR_DATA(IP11_11_9, ADICHS0_B),
@@ -1340,74 +1339,74 @@ static const u16 pinmux_data[] = {
1340 PINMUX_IPSR_DATA(IP11_14_12, SD2_CLK), 1339 PINMUX_IPSR_DATA(IP11_14_12, SD2_CLK),
1341 PINMUX_IPSR_DATA(IP11_14_12, MT0_PEN), 1340 PINMUX_IPSR_DATA(IP11_14_12, MT0_PEN),
1342 PINMUX_IPSR_DATA(IP11_14_12, SPA_TRST), 1341 PINMUX_IPSR_DATA(IP11_14_12, SPA_TRST),
1343 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3), 1342 PINMUX_IPSR_MSEL(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3),
1344 PINMUX_IPSR_DATA(IP11_14_12, ADICHS1_B), 1343 PINMUX_IPSR_DATA(IP11_14_12, ADICHS1_B),
1345 PINMUX_IPSR_DATA(IP11_17_15, VI1_DATA5_VI1_B5), 1344 PINMUX_IPSR_DATA(IP11_17_15, VI1_DATA5_VI1_B5),
1346 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SD2_CMD, SEL_SD2_0), 1345 PINMUX_IPSR_MSEL(IP11_17_15, SD2_CMD, SEL_SD2_0),
1347 PINMUX_IPSR_DATA(IP11_17_15, MT0_SYNC), 1346 PINMUX_IPSR_DATA(IP11_17_15, MT0_SYNC),
1348 PINMUX_IPSR_DATA(IP11_17_15, SPA_TCK), 1347 PINMUX_IPSR_DATA(IP11_17_15, SPA_TCK),
1349 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3), 1348 PINMUX_IPSR_MSEL(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3),
1350 PINMUX_IPSR_DATA(IP11_17_15, ADICHS2_B), 1349 PINMUX_IPSR_DATA(IP11_17_15, ADICHS2_B),
1351 PINMUX_IPSR_DATA(IP11_20_18, VI1_DATA6_VI1_B6), 1350 PINMUX_IPSR_DATA(IP11_20_18, VI1_DATA6_VI1_B6),
1352 PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SD2_CD, SEL_SD2_0), 1351 PINMUX_IPSR_MSEL(IP11_20_18, SD2_CD, SEL_SD2_0),
1353 PINMUX_IPSR_DATA(IP11_20_18, MT0_VCXO), 1352 PINMUX_IPSR_DATA(IP11_20_18, MT0_VCXO),
1354 PINMUX_IPSR_DATA(IP11_20_18, SPA_TMS), 1353 PINMUX_IPSR_DATA(IP11_20_18, SPA_TMS),
1355 PINMUX_IPSR_DATA(IP11_20_18, HSPI_TX1_D), 1354 PINMUX_IPSR_DATA(IP11_20_18, HSPI_TX1_D),
1356 PINMUX_IPSR_DATA(IP11_23_21, VI1_DATA7_VI1_B7), 1355 PINMUX_IPSR_DATA(IP11_23_21, VI1_DATA7_VI1_B7),
1357 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SD2_WP, SEL_SD2_0), 1356 PINMUX_IPSR_MSEL(IP11_23_21, SD2_WP, SEL_SD2_0),
1358 PINMUX_IPSR_DATA(IP11_23_21, MT0_PWM), 1357 PINMUX_IPSR_DATA(IP11_23_21, MT0_PWM),
1359 PINMUX_IPSR_DATA(IP11_23_21, SPA_TDI), 1358 PINMUX_IPSR_DATA(IP11_23_21, SPA_TDI),
1360 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3), 1359 PINMUX_IPSR_MSEL(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
1361 PINMUX_IPSR_DATA(IP11_26_24, VI1_G0), 1360 PINMUX_IPSR_DATA(IP11_26_24, VI1_G0),
1362 PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0), 1361 PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0),
1363 PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1), 1362 PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1),
1364 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1), 1363 PINMUX_IPSR_MSEL(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
1365 PINMUX_IPSR_DATA(IP11_26_24, TX2), 1364 PINMUX_IPSR_DATA(IP11_26_24, TX2),
1366 PINMUX_IPSR_DATA(IP11_26_24, SPA_TDO), 1365 PINMUX_IPSR_DATA(IP11_26_24, SPA_TDO),
1367 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, HCTS0_B, SEL_HSCIF0_1), 1366 PINMUX_IPSR_MSEL(IP11_26_24, HCTS0_B, SEL_HSCIF0_1),
1368 PINMUX_IPSR_DATA(IP11_29_27, VI1_G1), 1367 PINMUX_IPSR_DATA(IP11_29_27, VI1_G1),
1369 PINMUX_IPSR_DATA(IP11_29_27, VI3_DATA1), 1368 PINMUX_IPSR_DATA(IP11_29_27, VI3_DATA1),
1370 PINMUX_IPSR_DATA(IP11_29_27, SSI_SCK1), 1369 PINMUX_IPSR_DATA(IP11_29_27, SSI_SCK1),
1371 PINMUX_IPSR_DATA(IP11_29_27, TS_SDEN1), 1370 PINMUX_IPSR_DATA(IP11_29_27, TS_SDEN1),
1372 PINMUX_IPSR_DATA(IP11_29_27, DACK2_B), 1371 PINMUX_IPSR_DATA(IP11_29_27, DACK2_B),
1373 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RX2, SEL_SCIF2_0), 1372 PINMUX_IPSR_MSEL(IP11_29_27, RX2, SEL_SCIF2_0),
1374 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, HRTS0_B, SEL_HSCIF0_1), 1373 PINMUX_IPSR_MSEL(IP11_29_27, HRTS0_B, SEL_HSCIF0_1),
1375 1374
1376 PINMUX_IPSR_DATA(IP12_2_0, VI1_G2), 1375 PINMUX_IPSR_DATA(IP12_2_0, VI1_G2),
1377 PINMUX_IPSR_DATA(IP12_2_0, VI3_DATA2), 1376 PINMUX_IPSR_DATA(IP12_2_0, VI3_DATA2),
1378 PINMUX_IPSR_DATA(IP12_2_0, SSI_WS1), 1377 PINMUX_IPSR_DATA(IP12_2_0, SSI_WS1),
1379 PINMUX_IPSR_DATA(IP12_2_0, TS_SPSYNC1), 1378 PINMUX_IPSR_DATA(IP12_2_0, TS_SPSYNC1),
1380 PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCK2, SEL_SCIF2_0), 1379 PINMUX_IPSR_MSEL(IP12_2_0, SCK2, SEL_SCIF2_0),
1381 PINMUX_IPSR_MODSEL_DATA(IP12_2_0, HSCK0_B, SEL_HSCIF0_1), 1380 PINMUX_IPSR_MSEL(IP12_2_0, HSCK0_B, SEL_HSCIF0_1),
1382 PINMUX_IPSR_DATA(IP12_5_3, VI1_G3), 1381 PINMUX_IPSR_DATA(IP12_5_3, VI1_G3),
1383 PINMUX_IPSR_DATA(IP12_5_3, VI3_DATA3), 1382 PINMUX_IPSR_DATA(IP12_5_3, VI3_DATA3),
1384 PINMUX_IPSR_DATA(IP12_5_3, SSI_SCK2), 1383 PINMUX_IPSR_DATA(IP12_5_3, SSI_SCK2),
1385 PINMUX_IPSR_DATA(IP12_5_3, TS_SDAT1), 1384 PINMUX_IPSR_DATA(IP12_5_3, TS_SDAT1),
1386 PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCL1_C, SEL_I2C1_2), 1385 PINMUX_IPSR_MSEL(IP12_5_3, SCL1_C, SEL_I2C1_2),
1387 PINMUX_IPSR_DATA(IP12_5_3, HTX0_B), 1386 PINMUX_IPSR_DATA(IP12_5_3, HTX0_B),
1388 PINMUX_IPSR_DATA(IP12_8_6, VI1_G4), 1387 PINMUX_IPSR_DATA(IP12_8_6, VI1_G4),
1389 PINMUX_IPSR_DATA(IP12_8_6, VI3_DATA4), 1388 PINMUX_IPSR_DATA(IP12_8_6, VI3_DATA4),
1390 PINMUX_IPSR_DATA(IP12_8_6, SSI_WS2), 1389 PINMUX_IPSR_DATA(IP12_8_6, SSI_WS2),
1391 PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SDA1_C, SEL_I2C1_2), 1390 PINMUX_IPSR_MSEL(IP12_8_6, SDA1_C, SEL_I2C1_2),
1392 PINMUX_IPSR_DATA(IP12_8_6, SIM_RST_B), 1391 PINMUX_IPSR_DATA(IP12_8_6, SIM_RST_B),
1393 PINMUX_IPSR_MODSEL_DATA(IP12_8_6, HRX0_B, SEL_HSCIF0_1), 1392 PINMUX_IPSR_MSEL(IP12_8_6, HRX0_B, SEL_HSCIF0_1),
1394 PINMUX_IPSR_DATA(IP12_11_9, VI1_G5), 1393 PINMUX_IPSR_DATA(IP12_11_9, VI1_G5),
1395 PINMUX_IPSR_DATA(IP12_11_9, VI3_DATA5), 1394 PINMUX_IPSR_DATA(IP12_11_9, VI3_DATA5),
1396 PINMUX_IPSR_MODSEL_DATA(IP12_11_9, GPS_CLK, SEL_GPS_0), 1395 PINMUX_IPSR_MSEL(IP12_11_9, GPS_CLK, SEL_GPS_0),
1397 PINMUX_IPSR_DATA(IP12_11_9, FSE), 1396 PINMUX_IPSR_DATA(IP12_11_9, FSE),
1398 PINMUX_IPSR_DATA(IP12_11_9, TX4_B), 1397 PINMUX_IPSR_DATA(IP12_11_9, TX4_B),
1399 PINMUX_IPSR_MODSEL_DATA(IP12_11_9, SIM_D_B, SEL_SIM_1), 1398 PINMUX_IPSR_MSEL(IP12_11_9, SIM_D_B, SEL_SIM_1),
1400 PINMUX_IPSR_DATA(IP12_14_12, VI1_G6), 1399 PINMUX_IPSR_DATA(IP12_14_12, VI1_G6),
1401 PINMUX_IPSR_DATA(IP12_14_12, VI3_DATA6), 1400 PINMUX_IPSR_DATA(IP12_14_12, VI3_DATA6),
1402 PINMUX_IPSR_MODSEL_DATA(IP12_14_12, GPS_SIGN, SEL_GPS_0), 1401 PINMUX_IPSR_MSEL(IP12_14_12, GPS_SIGN, SEL_GPS_0),
1403 PINMUX_IPSR_DATA(IP12_14_12, FRB), 1402 PINMUX_IPSR_DATA(IP12_14_12, FRB),
1404 PINMUX_IPSR_MODSEL_DATA(IP12_14_12, RX4_B, SEL_SCIF4_1), 1403 PINMUX_IPSR_MSEL(IP12_14_12, RX4_B, SEL_SCIF4_1),
1405 PINMUX_IPSR_DATA(IP12_14_12, SIM_CLK_B), 1404 PINMUX_IPSR_DATA(IP12_14_12, SIM_CLK_B),
1406 PINMUX_IPSR_DATA(IP12_17_15, VI1_G7), 1405 PINMUX_IPSR_DATA(IP12_17_15, VI1_G7),
1407 PINMUX_IPSR_DATA(IP12_17_15, VI3_DATA7), 1406 PINMUX_IPSR_DATA(IP12_17_15, VI3_DATA7),
1408 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, GPS_MAG, SEL_GPS_0), 1407 PINMUX_IPSR_MSEL(IP12_17_15, GPS_MAG, SEL_GPS_0),
1409 PINMUX_IPSR_DATA(IP12_17_15, FCE), 1408 PINMUX_IPSR_DATA(IP12_17_15, FCE),
1410 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1), 1409 PINMUX_IPSR_MSEL(IP12_17_15, SCK4_B, SEL_SCIF4_1),
1411}; 1410};
1412 1411
1413static const struct sh_pfc_pin pinmux_pins[] = { 1412static const struct sh_pfc_pin pinmux_pins[] = {
@@ -3868,6 +3867,6 @@ const struct sh_pfc_soc_info r8a7779_pinmux_info = {
3868 3867
3869 .cfg_regs = pinmux_config_regs, 3868 .cfg_regs = pinmux_config_regs,
3870 3869
3871 .gpio_data = pinmux_data, 3870 .pinmux_data = pinmux_data,
3872 .gpio_data_size = ARRAY_SIZE(pinmux_data), 3871 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3873}; 3872};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index fc344a7c2b53..d9924b0d53b7 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -22,7 +22,6 @@
22 */ 22 */
23 23
24#include <linux/kernel.h> 24#include <linux/kernel.h>
25#include <linux/platform_data/gpio-rcar.h>
26 25
27#include "core.h" 26#include "core.h"
28#include "sh_pfc.h" 27#include "sh_pfc.h"
@@ -818,103 +817,103 @@ static const u16 pinmux_data[] = {
818 PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2), 817 PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2),
819 818
820 PINMUX_IPSR_DATA(IP0_2_0, D0), 819 PINMUX_IPSR_DATA(IP0_2_0, D0),
821 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1), 820 PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
822 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0), 821 PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0),
823 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0), 822 PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0),
824 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1), 823 PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1),
825 PINMUX_IPSR_DATA(IP0_5_3, D1), 824 PINMUX_IPSR_DATA(IP0_5_3, D1),
826 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1), 825 PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
827 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0), 826 PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0),
828 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0), 827 PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0),
829 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1), 828 PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1),
830 PINMUX_IPSR_DATA(IP0_8_6, D2), 829 PINMUX_IPSR_DATA(IP0_8_6, D2),
831 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1), 830 PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
832 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0), 831 PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0),
833 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0), 832 PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6, SEL_VI0_0),
834 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1), 833 PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6_B, SEL_VI0_1),
835 PINMUX_IPSR_DATA(IP0_11_9, D3), 834 PINMUX_IPSR_DATA(IP0_11_9, D3),
836 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1), 835 PINMUX_IPSR_MSEL(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
837 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0), 836 PINMUX_IPSR_MSEL(IP0_11_9, VI3_DATA3, SEL_VI3_0),
838 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0), 837 PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7, SEL_VI0_0),
839 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1), 838 PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7_B, SEL_VI0_1),
840 PINMUX_IPSR_DATA(IP0_15_12, D4), 839 PINMUX_IPSR_DATA(IP0_15_12, D4),
841 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5), 840 PINMUX_IPSR_MSEL(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
842 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2), 841 PINMUX_IPSR_MSEL(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
843 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0), 842 PINMUX_IPSR_MSEL(IP0_15_12, VI3_DATA4, SEL_VI3_0),
844 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0), 843 PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0, SEL_VI0_0),
845 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1), 844 PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0_B, SEL_VI0_1),
846 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1), 845 PINMUX_IPSR_MSEL(IP0_15_12, RX0_B, SEL_SCIF0_1),
847 PINMUX_IPSR_DATA(IP0_19_16, D5), 846 PINMUX_IPSR_DATA(IP0_19_16, D5),
848 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5), 847 PINMUX_IPSR_MSEL(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
849 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2), 848 PINMUX_IPSR_MSEL(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
850 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0), 849 PINMUX_IPSR_MSEL(IP0_19_16, VI3_DATA5, SEL_VI3_0),
851 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0), 850 PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1, SEL_VI0_0),
852 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1), 851 PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1_B, SEL_VI0_1),
853 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1), 852 PINMUX_IPSR_MSEL(IP0_19_16, TX0_B, SEL_SCIF0_1),
854 PINMUX_IPSR_DATA(IP0_22_20, D6), 853 PINMUX_IPSR_DATA(IP0_22_20, D6),
855 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2), 854 PINMUX_IPSR_MSEL(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
856 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0), 855 PINMUX_IPSR_MSEL(IP0_22_20, VI3_DATA6, SEL_VI3_0),
857 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0), 856 PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2, SEL_VI0_0),
858 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1), 857 PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2_B, SEL_VI0_1),
859 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2), 858 PINMUX_IPSR_MSEL(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
860 PINMUX_IPSR_DATA(IP0_26_23, D7), 859 PINMUX_IPSR_DATA(IP0_26_23, D7),
861 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1), 860 PINMUX_IPSR_MSEL(IP0_26_23, AD_DI_B, SEL_ADI_1),
862 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2), 861 PINMUX_IPSR_MSEL(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
863 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0), 862 PINMUX_IPSR_MSEL(IP0_26_23, VI3_DATA7, SEL_VI3_0),
864 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0), 863 PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3, SEL_VI0_0),
865 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1), 864 PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3_B, SEL_VI0_1),
866 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2), 865 PINMUX_IPSR_MSEL(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
867 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, TCLK1, SEL_TMU1_0), 866 PINMUX_IPSR_MSEL(IP0_26_23, TCLK1, SEL_TMU1_0),
868 PINMUX_IPSR_DATA(IP0_30_27, D8), 867 PINMUX_IPSR_DATA(IP0_30_27, D8),
869 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), 868 PINMUX_IPSR_MSEL(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
870 PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0), 869 PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0),
871 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0), 870 PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0, SEL_VI0_0),
872 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1), 871 PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0_B, SEL_VI0_1),
873 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0), 872 PINMUX_IPSR_MSEL(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
874 873
875 PINMUX_IPSR_DATA(IP1_3_0, D9), 874 PINMUX_IPSR_DATA(IP1_3_0, D9),
876 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2), 875 PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
877 PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1), 876 PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1),
878 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0), 877 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0),
879 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1), 878 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1),
880 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0), 879 PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
881 PINMUX_IPSR_DATA(IP1_7_4, D10), 880 PINMUX_IPSR_DATA(IP1_7_4, D10),
882 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2), 881 PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
883 PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2), 882 PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2),
884 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0), 883 PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0),
885 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1), 884 PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1),
886 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0), 885 PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
887 PINMUX_IPSR_DATA(IP1_11_8, D11), 886 PINMUX_IPSR_DATA(IP1_11_8, D11),
888 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2), 887 PINMUX_IPSR_MSEL(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
889 PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3), 888 PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3),
890 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0), 889 PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3, SEL_VI0_0),
891 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1), 890 PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3_B, SEL_VI0_1),
892 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0), 891 PINMUX_IPSR_MSEL(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
893 PINMUX_IPSR_DATA(IP1_14_12, D12), 892 PINMUX_IPSR_DATA(IP1_14_12, D12),
894 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2), 893 PINMUX_IPSR_MSEL(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
895 PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4), 894 PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4),
896 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0), 895 PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
897 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1), 896 PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
898 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0), 897 PINMUX_IPSR_MSEL(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
899 PINMUX_IPSR_DATA(IP1_17_15, D13), 898 PINMUX_IPSR_DATA(IP1_17_15, D13),
900 PINMUX_IPSR_DATA(IP1_17_15, AVB_TXD5), 899 PINMUX_IPSR_DATA(IP1_17_15, AVB_TXD5),
901 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0), 900 PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
902 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1), 901 PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
903 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0), 902 PINMUX_IPSR_MSEL(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
904 PINMUX_IPSR_DATA(IP1_21_18, D14), 903 PINMUX_IPSR_DATA(IP1_21_18, D14),
905 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2), 904 PINMUX_IPSR_MSEL(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
906 PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6), 905 PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6),
907 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1), 906 PINMUX_IPSR_MSEL(IP1_21_18, RX1_B, SEL_SCIF1_1),
908 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0), 907 PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
909 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1), 908 PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
910 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0), 909 PINMUX_IPSR_MSEL(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
911 PINMUX_IPSR_DATA(IP1_25_22, D15), 910 PINMUX_IPSR_DATA(IP1_25_22, D15),
912 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2), 911 PINMUX_IPSR_MSEL(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
913 PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7), 912 PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7),
914 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1), 913 PINMUX_IPSR_MSEL(IP1_25_22, TX1_B, SEL_SCIF1_1),
915 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0), 914 PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD, SEL_VI0_0),
916 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1), 915 PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
917 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0), 916 PINMUX_IPSR_MSEL(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
918 PINMUX_IPSR_DATA(IP1_27_26, A0), 917 PINMUX_IPSR_DATA(IP1_27_26, A0),
919 PINMUX_IPSR_DATA(IP1_27_26, PWM3), 918 PINMUX_IPSR_DATA(IP1_27_26, PWM3),
920 PINMUX_IPSR_DATA(IP1_29_28, A1), 919 PINMUX_IPSR_DATA(IP1_29_28, A1),
@@ -922,512 +921,512 @@ static const u16 pinmux_data[] = {
922 921
923 PINMUX_IPSR_DATA(IP2_2_0, A2), 922 PINMUX_IPSR_DATA(IP2_2_0, A2),
924 PINMUX_IPSR_DATA(IP2_2_0, PWM5), 923 PINMUX_IPSR_DATA(IP2_2_0, PWM5),
925 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1), 924 PINMUX_IPSR_MSEL(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
926 PINMUX_IPSR_DATA(IP2_5_3, A3), 925 PINMUX_IPSR_DATA(IP2_5_3, A3),
927 PINMUX_IPSR_DATA(IP2_5_3, PWM6), 926 PINMUX_IPSR_DATA(IP2_5_3, PWM6),
928 PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1), 927 PINMUX_IPSR_MSEL(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
929 PINMUX_IPSR_DATA(IP2_8_6, A4), 928 PINMUX_IPSR_DATA(IP2_8_6, A4),
930 PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1), 929 PINMUX_IPSR_MSEL(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
931 PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0), 930 PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0),
932 PINMUX_IPSR_DATA(IP2_11_9, A5), 931 PINMUX_IPSR_DATA(IP2_11_9, A5),
933 PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1), 932 PINMUX_IPSR_MSEL(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
934 PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1), 933 PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1),
935 PINMUX_IPSR_DATA(IP2_14_12, A6), 934 PINMUX_IPSR_DATA(IP2_14_12, A6),
936 PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1), 935 PINMUX_IPSR_MSEL(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
937 PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2), 936 PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2),
938 PINMUX_IPSR_DATA(IP2_17_15, A7), 937 PINMUX_IPSR_DATA(IP2_17_15, A7),
939 PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1), 938 PINMUX_IPSR_MSEL(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
940 PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B), 939 PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B),
941 PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3), 940 PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3),
942 PINMUX_IPSR_DATA(IP2_21_18, A8), 941 PINMUX_IPSR_DATA(IP2_21_18, A8),
943 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1), 942 PINMUX_IPSR_MSEL(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
944 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1), 943 PINMUX_IPSR_MSEL(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
945 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0), 944 PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4, SEL_VI0_0),
946 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1), 945 PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4_B, SEL_VI0_1),
947 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2), 946 PINMUX_IPSR_MSEL(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
948 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, RX2_B, SEL_SCIF2_1), 947 PINMUX_IPSR_MSEL(IP2_21_18, RX2_B, SEL_SCIF2_1),
949 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1), 948 PINMUX_IPSR_MSEL(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
950 PINMUX_IPSR_DATA(IP2_25_22, A9), 949 PINMUX_IPSR_DATA(IP2_25_22, A9),
951 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1), 950 PINMUX_IPSR_MSEL(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
952 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1), 951 PINMUX_IPSR_MSEL(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
953 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0), 952 PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5, SEL_VI0_0),
954 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1), 953 PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5_B, SEL_VI0_1),
955 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2), 954 PINMUX_IPSR_MSEL(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
956 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, TX2_B, SEL_SCIF2_1), 955 PINMUX_IPSR_MSEL(IP2_25_22, TX2_B, SEL_SCIF2_1),
957 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1), 956 PINMUX_IPSR_MSEL(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
958 PINMUX_IPSR_DATA(IP2_28_26, A10), 957 PINMUX_IPSR_DATA(IP2_28_26, A10),
959 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1), 958 PINMUX_IPSR_MSEL(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
960 PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC), 959 PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC),
961 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0), 960 PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6, SEL_VI0_0),
962 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1), 961 PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6_B, SEL_VI0_1),
963 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1), 962 PINMUX_IPSR_MSEL(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
964 963
965 PINMUX_IPSR_DATA(IP3_3_0, A11), 964 PINMUX_IPSR_DATA(IP3_3_0, A11),
966 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1), 965 PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
967 PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK), 966 PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK),
968 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0), 967 PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0),
969 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1), 968 PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1),
970 PINMUX_IPSR_DATA(IP3_3_0, VI2_G0), 969 PINMUX_IPSR_DATA(IP3_3_0, VI2_G0),
971 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1), 970 PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
972 PINMUX_IPSR_DATA(IP3_7_4, A12), 971 PINMUX_IPSR_DATA(IP3_7_4, A12),
973 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1), 972 PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
974 PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD), 973 PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD),
975 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0), 974 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0),
976 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1), 975 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1),
977 PINMUX_IPSR_DATA(IP3_7_4, VI2_G1), 976 PINMUX_IPSR_DATA(IP3_7_4, VI2_G1),
978 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1), 977 PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
979 PINMUX_IPSR_DATA(IP3_11_8, A13), 978 PINMUX_IPSR_DATA(IP3_11_8, A13),
980 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1), 979 PINMUX_IPSR_MSEL(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
981 PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2), 980 PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2),
982 PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD), 981 PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD),
983 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0), 982 PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2, SEL_VI1_0),
984 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1), 983 PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2_B, SEL_VI1_1),
985 PINMUX_IPSR_DATA(IP3_11_8, VI2_G2), 984 PINMUX_IPSR_DATA(IP3_11_8, VI2_G2),
986 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1), 985 PINMUX_IPSR_MSEL(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
987 PINMUX_IPSR_DATA(IP3_14_12, A14), 986 PINMUX_IPSR_DATA(IP3_14_12, A14),
988 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1), 987 PINMUX_IPSR_MSEL(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
989 PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N), 988 PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N),
990 PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1), 989 PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1),
991 PINMUX_IPSR_DATA(IP3_17_15, A15), 990 PINMUX_IPSR_DATA(IP3_17_15, A15),
992 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1), 991 PINMUX_IPSR_MSEL(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
993 PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N), 992 PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N),
994 PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2), 993 PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2),
995 PINMUX_IPSR_DATA(IP3_19_18, A16), 994 PINMUX_IPSR_DATA(IP3_19_18, A16),
996 PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N), 995 PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N),
997 PINMUX_IPSR_DATA(IP3_22_20, A17), 996 PINMUX_IPSR_DATA(IP3_22_20, A17),
998 PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1), 997 PINMUX_IPSR_MSEL(IP3_22_20, AD_DO_B, SEL_ADI_1),
999 PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N), 998 PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N),
1000 PINMUX_IPSR_DATA(IP3_25_23, A18), 999 PINMUX_IPSR_DATA(IP3_25_23, A18),
1001 PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1), 1000 PINMUX_IPSR_MSEL(IP3_25_23, AD_CLK_B, SEL_ADI_1),
1002 PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N), 1001 PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N),
1003 PINMUX_IPSR_DATA(IP3_28_26, A19), 1002 PINMUX_IPSR_DATA(IP3_28_26, A19),
1004 PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1), 1003 PINMUX_IPSR_MSEL(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
1005 PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N), 1004 PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N),
1006 PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1), 1005 PINMUX_IPSR_MSEL(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
1007 PINMUX_IPSR_DATA(IP3_31_29, A20), 1006 PINMUX_IPSR_DATA(IP3_31_29, A20),
1008 PINMUX_IPSR_DATA(IP3_31_29, SPCLK), 1007 PINMUX_IPSR_DATA(IP3_31_29, SPCLK),
1009 PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0), 1008 PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3, SEL_VI1_0),
1010 PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1), 1009 PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3_B, SEL_VI1_1),
1011 PINMUX_IPSR_DATA(IP3_31_29, VI2_G4), 1010 PINMUX_IPSR_DATA(IP3_31_29, VI2_G4),
1012 1011
1013 PINMUX_IPSR_DATA(IP4_2_0, A21), 1012 PINMUX_IPSR_DATA(IP4_2_0, A21),
1014 PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0), 1013 PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0),
1015 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0), 1014 PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4, SEL_VI1_0),
1016 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1), 1015 PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4_B, SEL_VI1_1),
1017 PINMUX_IPSR_DATA(IP4_2_0, VI2_G5), 1016 PINMUX_IPSR_DATA(IP4_2_0, VI2_G5),
1018 PINMUX_IPSR_DATA(IP4_5_3, A22), 1017 PINMUX_IPSR_DATA(IP4_5_3, A22),
1019 PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1), 1018 PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1),
1020 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0), 1019 PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5, SEL_VI1_0),
1021 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1), 1020 PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5_B, SEL_VI1_1),
1022 PINMUX_IPSR_DATA(IP4_5_3, VI2_G6), 1021 PINMUX_IPSR_DATA(IP4_5_3, VI2_G6),
1023 PINMUX_IPSR_DATA(IP4_8_6, A23), 1022 PINMUX_IPSR_DATA(IP4_8_6, A23),
1024 PINMUX_IPSR_DATA(IP4_8_6, IO2), 1023 PINMUX_IPSR_DATA(IP4_8_6, IO2),
1025 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0), 1024 PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7, SEL_VI1_0),
1026 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1), 1025 PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7_B, SEL_VI1_1),
1027 PINMUX_IPSR_DATA(IP4_8_6, VI2_G7), 1026 PINMUX_IPSR_DATA(IP4_8_6, VI2_G7),
1028 PINMUX_IPSR_DATA(IP4_11_9, A24), 1027 PINMUX_IPSR_DATA(IP4_11_9, A24),
1029 PINMUX_IPSR_DATA(IP4_11_9, IO3), 1028 PINMUX_IPSR_DATA(IP4_11_9, IO3),
1030 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0), 1029 PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7, SEL_VI1_0),
1031 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1), 1030 PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7_B, SEL_VI1_1),
1032 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0), 1031 PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
1033 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1), 1032 PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
1034 PINMUX_IPSR_DATA(IP4_14_12, A25), 1033 PINMUX_IPSR_DATA(IP4_14_12, A25),
1035 PINMUX_IPSR_DATA(IP4_14_12, SSL), 1034 PINMUX_IPSR_DATA(IP4_14_12, SSL),
1036 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0), 1035 PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6, SEL_VI1_0),
1037 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1), 1036 PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6_B, SEL_VI1_1),
1038 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0), 1037 PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD, SEL_VI2_0),
1039 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1), 1038 PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
1040 PINMUX_IPSR_DATA(IP4_17_15, CS0_N), 1039 PINMUX_IPSR_DATA(IP4_17_15, CS0_N),
1041 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0), 1040 PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6, SEL_VI1_0),
1042 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1), 1041 PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6_B, SEL_VI1_1),
1043 PINMUX_IPSR_DATA(IP4_17_15, VI2_G3), 1042 PINMUX_IPSR_DATA(IP4_17_15, VI2_G3),
1044 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1), 1043 PINMUX_IPSR_MSEL(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
1045 PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26), 1044 PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26),
1046 PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN), 1045 PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN),
1047 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0), 1046 PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7, SEL_VI0_0),
1048 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1), 1047 PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7_B, SEL_VI0_1),
1049 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0), 1048 PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK, SEL_VI2_0),
1050 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1), 1049 PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
1051 PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N), 1050 PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N),
1052 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1), 1051 PINMUX_IPSR_MSEL(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
1053 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0), 1052 PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5, SEL_VI1_0),
1054 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1), 1053 PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5_B, SEL_VI1_1),
1055 PINMUX_IPSR_DATA(IP4_23_21, VI2_R0), 1054 PINMUX_IPSR_DATA(IP4_23_21, VI2_R0),
1056 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1), 1055 PINMUX_IPSR_MSEL(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
1057 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1), 1056 PINMUX_IPSR_MSEL(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
1058 PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N), 1057 PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N),
1059 PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK), 1058 PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK),
1060 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1), 1059 PINMUX_IPSR_MSEL(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
1061 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0), 1060 PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD, SEL_VI1_0),
1062 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1), 1061 PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
1063 PINMUX_IPSR_DATA(IP4_26_24, VI2_R1), 1062 PINMUX_IPSR_DATA(IP4_26_24, VI2_R1),
1064 PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N), 1063 PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N),
1065 PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN), 1064 PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN),
1066 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1), 1065 PINMUX_IPSR_MSEL(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
1067 PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB), 1066 PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB),
1068 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0), 1067 PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0, SEL_VI1_0),
1069 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1), 1068 PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0_B, SEL_VI1_1),
1070 PINMUX_IPSR_DATA(IP4_29_27, VI2_R2), 1069 PINMUX_IPSR_DATA(IP4_29_27, VI2_R2),
1071 1070
1072 PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N), 1071 PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N),
1073 PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG), 1072 PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG),
1074 PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD), 1073 PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD),
1075 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0), 1074 PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1, SEL_VI1_0),
1076 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1), 1075 PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1_B, SEL_VI1_1),
1077 PINMUX_IPSR_DATA(IP5_2_0, VI2_R3), 1076 PINMUX_IPSR_DATA(IP5_2_0, VI2_R3),
1078 PINMUX_IPSR_DATA(IP5_5_3, EX_CS4_N), 1077 PINMUX_IPSR_DATA(IP5_5_3, EX_CS4_N),
1079 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1), 1078 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
1080 PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N), 1079 PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N),
1081 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0), 1080 PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
1082 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, IIC1_SCL, SEL_IIC1_0), 1081 PINMUX_IPSR_MSEL(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
1083 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1), 1082 PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
1084 PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N), 1083 PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N),
1085 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, I2C1_SCL, SEL_I2C1_0), 1084 PINMUX_IPSR_MSEL(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
1086 PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N), 1085 PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N),
1087 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0), 1086 PINMUX_IPSR_MSEL(IP5_9_6, CAN0_RX, SEL_CAN0_0),
1088 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1), 1087 PINMUX_IPSR_MSEL(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
1089 PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N), 1088 PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N),
1090 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0), 1089 PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2, SEL_VI1_0),
1091 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1), 1090 PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2_B, SEL_VI1_1),
1092 PINMUX_IPSR_DATA(IP5_9_6, VI2_R4), 1091 PINMUX_IPSR_DATA(IP5_9_6, VI2_R4),
1093 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, IIC1_SDA, SEL_IIC1_0), 1092 PINMUX_IPSR_MSEL(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
1094 PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N), 1093 PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N),
1095 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, I2C1_SDA, SEL_I2C1_0), 1094 PINMUX_IPSR_MSEL(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
1096 PINMUX_IPSR_DATA(IP5_12_10, BS_N), 1095 PINMUX_IPSR_DATA(IP5_12_10, BS_N),
1097 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0), 1096 PINMUX_IPSR_MSEL(IP5_12_10, IETX, SEL_IEB_0),
1098 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1), 1097 PINMUX_IPSR_MSEL(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
1099 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0), 1098 PINMUX_IPSR_MSEL(IP5_12_10, CAN1_TX, SEL_CAN1_0),
1100 PINMUX_IPSR_DATA(IP5_12_10, DRACK0), 1099 PINMUX_IPSR_DATA(IP5_12_10, DRACK0),
1101 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2), 1100 PINMUX_IPSR_MSEL(IP5_12_10, IETX_C, SEL_IEB_2),
1102 PINMUX_IPSR_DATA(IP5_14_13, RD_N), 1101 PINMUX_IPSR_DATA(IP5_14_13, RD_N),
1103 PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0), 1102 PINMUX_IPSR_MSEL(IP5_14_13, CAN0_TX, SEL_CAN0_0),
1104 PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1), 1103 PINMUX_IPSR_MSEL(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
1105 PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N), 1104 PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N),
1106 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0), 1105 PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3, SEL_VI1_0),
1107 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1), 1106 PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1),
1108 PINMUX_IPSR_DATA(IP5_17_15, VI2_R5), 1107 PINMUX_IPSR_DATA(IP5_17_15, VI2_R5),
1109 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1), 1108 PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
1110 PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N), 1109 PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N),
1111 PINMUX_IPSR_DATA(IP5_20_18, WE0_N), 1110 PINMUX_IPSR_DATA(IP5_20_18, WE0_N),
1112 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0), 1111 PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0),
1113 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0), 1112 PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
1114 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0), 1113 PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
1115 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1), 1114 PINMUX_IPSR_MSEL(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
1116 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1), 1115 PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
1117 PINMUX_IPSR_DATA(IP5_23_21, WE1_N), 1116 PINMUX_IPSR_DATA(IP5_23_21, WE1_N),
1118 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0), 1117 PINMUX_IPSR_MSEL(IP5_23_21, IERX, SEL_IEB_0),
1119 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0), 1118 PINMUX_IPSR_MSEL(IP5_23_21, CAN1_RX, SEL_CAN1_0),
1120 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0), 1119 PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4, SEL_VI1_0),
1121 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1), 1120 PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4_B, SEL_VI1_1),
1122 PINMUX_IPSR_DATA(IP5_23_21, VI2_R6), 1121 PINMUX_IPSR_DATA(IP5_23_21, VI2_R6),
1123 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1), 1122 PINMUX_IPSR_MSEL(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
1124 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2), 1123 PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2),
1125 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, EX_WAIT0, SEL_LBS_0), 1124 PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0),
1126 PINMUX_IPSR_DATA(IP5_26_24, IRQ3), 1125 PINMUX_IPSR_DATA(IP5_26_24, IRQ3),
1127 PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N), 1126 PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N),
1128 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0), 1127 PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0),
1129 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1), 1128 PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
1130 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1), 1129 PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
1131 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1), 1130 PINMUX_IPSR_MSEL(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
1132 PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N), 1131 PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N),
1133 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0), 1132 PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
1134 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1), 1133 PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
1135 PINMUX_IPSR_DATA(IP5_29_27, VI2_R7), 1134 PINMUX_IPSR_DATA(IP5_29_27, VI2_R7),
1136 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2), 1135 PINMUX_IPSR_MSEL(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
1137 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1), 1136 PINMUX_IPSR_MSEL(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
1138 1137
1139 PINMUX_IPSR_DATA(IP6_2_0, DACK0), 1138 PINMUX_IPSR_DATA(IP6_2_0, DACK0),
1140 PINMUX_IPSR_DATA(IP6_2_0, IRQ0), 1139 PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
1141 PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N), 1140 PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
1142 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), 1141 PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
1143 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), 1142 PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
1144 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), 1143 PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
1145 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2), 1144 PINMUX_IPSR_MSEL(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
1146 PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N), 1145 PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
1147 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0), 1146 PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
1148 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1), 1147 PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
1149 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2), 1148 PINMUX_IPSR_MSEL(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
1150 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), 1149 PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
1151 PINMUX_IPSR_DATA(IP6_8_6, DACK1), 1150 PINMUX_IPSR_DATA(IP6_8_6, DACK1),
1152 PINMUX_IPSR_DATA(IP6_8_6, IRQ1), 1151 PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
1153 PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N), 1152 PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
1154 PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), 1153 PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
1155 PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), 1154 PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
1156 PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N), 1155 PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
1157 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1), 1156 PINMUX_IPSR_MSEL(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
1158 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1), 1157 PINMUX_IPSR_MSEL(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
1159 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), 1158 PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
1160 PINMUX_IPSR_DATA(IP6_13_11, DACK2), 1159 PINMUX_IPSR_DATA(IP6_13_11, DACK2),
1161 PINMUX_IPSR_DATA(IP6_13_11, IRQ2), 1160 PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
1162 PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N), 1161 PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
1163 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), 1162 PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
1164 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), 1163 PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
1165 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), 1164 PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
1166 PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV), 1165 PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
1167 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), 1166 PINMUX_IPSR_MSEL(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
1168 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), 1167 PINMUX_IPSR_MSEL(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
1169 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2), 1168 PINMUX_IPSR_MSEL(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
1170 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4), 1169 PINMUX_IPSR_MSEL(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
1171 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4), 1170 PINMUX_IPSR_MSEL(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
1172 PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER), 1171 PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
1173 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), 1172 PINMUX_IPSR_MSEL(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
1174 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), 1173 PINMUX_IPSR_MSEL(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
1175 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2), 1174 PINMUX_IPSR_MSEL(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
1176 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4), 1175 PINMUX_IPSR_MSEL(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
1177 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4), 1176 PINMUX_IPSR_MSEL(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
1178 PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0), 1177 PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
1179 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), 1178 PINMUX_IPSR_MSEL(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
1180 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), 1179 PINMUX_IPSR_MSEL(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
1181 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2), 1180 PINMUX_IPSR_MSEL(IP6_22_20, GLO_I0_C, SEL_GPS_2),
1182 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), 1181 PINMUX_IPSR_MSEL(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
1183 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4), 1182 PINMUX_IPSR_MSEL(IP6_22_20, SCK1_E, SEL_SCIF1_4),
1184 PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1), 1183 PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
1185 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4), 1184 PINMUX_IPSR_MSEL(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
1186 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), 1185 PINMUX_IPSR_MSEL(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
1187 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), 1186 PINMUX_IPSR_MSEL(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
1188 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2), 1187 PINMUX_IPSR_MSEL(IP6_25_23, GLO_I1_C, SEL_GPS_2),
1189 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), 1188 PINMUX_IPSR_MSEL(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
1190 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4), 1189 PINMUX_IPSR_MSEL(IP6_25_23, RX1_E, SEL_SCIF1_4),
1191 PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK), 1190 PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
1192 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4), 1191 PINMUX_IPSR_MSEL(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
1193 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), 1192 PINMUX_IPSR_MSEL(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
1194 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), 1193 PINMUX_IPSR_MSEL(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
1195 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4), 1194 PINMUX_IPSR_MSEL(IP6_28_26, TX1_E, SEL_SCIF1_4),
1196 PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK), 1195 PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
1197 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), 1196 PINMUX_IPSR_MSEL(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
1198 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), 1197 PINMUX_IPSR_MSEL(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
1199 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5), 1198 PINMUX_IPSR_MSEL(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
1200 1199
1201 PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO), 1200 PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
1202 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), 1201 PINMUX_IPSR_MSEL(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
1203 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2), 1202 PINMUX_IPSR_MSEL(IP7_2_0, SIM0_D_C, SEL_SIM_2),
1204 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), 1203 PINMUX_IPSR_MSEL(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
1205 PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1), 1204 PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
1206 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_5), 1205 PINMUX_IPSR_MSEL(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
1207 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_FM_6), 1206 PINMUX_IPSR_MSEL(IP7_5_3, BPFCLK_G, SEL_FM_6),
1208 PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN), 1207 PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
1209 PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), 1208 PINMUX_IPSR_MSEL(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
1210 PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), 1209 PINMUX_IPSR_MSEL(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
1211 PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC), 1210 PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
1212 PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2), 1211 PINMUX_IPSR_MSEL(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
1213 PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0), 1212 PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
1214 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), 1213 PINMUX_IPSR_MSEL(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
1215 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), 1214 PINMUX_IPSR_MSEL(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
1216 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), 1215 PINMUX_IPSR_MSEL(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
1217 PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC), 1216 PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
1218 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), 1217 PINMUX_IPSR_MSEL(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
1219 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), 1218 PINMUX_IPSR_MSEL(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
1220 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), 1219 PINMUX_IPSR_MSEL(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
1221 PINMUX_IPSR_DATA(IP7_18_16, PWM0), 1220 PINMUX_IPSR_DATA(IP7_18_16, PWM0),
1222 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2), 1221 PINMUX_IPSR_MSEL(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
1223 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1), 1222 PINMUX_IPSR_MSEL(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
1224 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2), 1223 PINMUX_IPSR_MSEL(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
1225 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2), 1224 PINMUX_IPSR_MSEL(IP7_18_16, GLO_SS_C, SEL_GPS_2),
1226 PINMUX_IPSR_DATA(IP7_21_19, PWM1), 1225 PINMUX_IPSR_DATA(IP7_21_19, PWM1),
1227 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2), 1226 PINMUX_IPSR_MSEL(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
1228 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1), 1227 PINMUX_IPSR_MSEL(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
1229 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2), 1228 PINMUX_IPSR_MSEL(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
1230 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2), 1229 PINMUX_IPSR_MSEL(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
1231 PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N), 1230 PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
1232 PINMUX_IPSR_DATA(IP7_24_22, PWM2), 1231 PINMUX_IPSR_DATA(IP7_24_22, PWM2),
1233 PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0), 1232 PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
1234 PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2), 1233 PINMUX_IPSR_MSEL(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
1235 PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N), 1234 PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
1236 PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2), 1235 PINMUX_IPSR_MSEL(IP7_24_22, IECLK_C, SEL_IEB_2),
1237 PINMUX_IPSR_DATA(IP7_26_25, DU_DOTCLKIN1), 1236 PINMUX_IPSR_DATA(IP7_26_25, DU_DOTCLKIN1),
1238 PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC), 1237 PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
1239 PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C), 1238 PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
1240 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0), 1239 PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0),
1241 PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N), 1240 PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
1242 PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1), 1241 PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
1243 PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), 1242 PINMUX_IPSR_MSEL(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
1244 PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N), 1243 PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
1245 PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2), 1244 PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
1246 1245
1247 PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0), 1246 PINMUX_IPSR_MSEL(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
1248 PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N), 1247 PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
1249 PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3), 1248 PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
1250 PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0), 1249 PINMUX_IPSR_MSEL(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
1251 PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N), 1250 PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
1252 PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4), 1251 PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
1253 PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0), 1252 PINMUX_IPSR_MSEL(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
1254 PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N), 1253 PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N),
1255 PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5), 1254 PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5),
1256 PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0), 1255 PINMUX_IPSR_MSEL(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
1257 PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N), 1256 PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N),
1258 PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6), 1257 PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6),
1259 PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0), 1258 PINMUX_IPSR_MSEL(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
1260 PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1), 1259 PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1),
1261 PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7), 1260 PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
1262 PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0), 1261 PINMUX_IPSR_MSEL(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
1263 PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER), 1262 PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
1264 PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0), 1263 PINMUX_IPSR_MSEL(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
1265 PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK), 1264 PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
1266 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0), 1265 PINMUX_IPSR_MSEL(IP8_15_14, VI1_CLK, SEL_VI1_0),
1267 PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV), 1266 PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
1268 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0), 1267 PINMUX_IPSR_MSEL(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
1269 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3), 1268 PINMUX_IPSR_MSEL(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
1270 PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS), 1269 PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
1271 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0), 1270 PINMUX_IPSR_MSEL(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
1272 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3), 1271 PINMUX_IPSR_MSEL(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
1273 PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC), 1272 PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
1274 PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0), 1273 PINMUX_IPSR_MSEL(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
1275 PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3), 1274 PINMUX_IPSR_MSEL(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
1276 PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO), 1275 PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
1277 PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0), 1276 PINMUX_IPSR_MSEL(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
1278 PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3), 1277 PINMUX_IPSR_MSEL(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
1279 PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK), 1278 PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
1280 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0), 1279 PINMUX_IPSR_MSEL(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
1281 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3), 1280 PINMUX_IPSR_MSEL(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
1282 PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC), 1281 PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
1283 PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0), 1282 PINMUX_IPSR_MSEL(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
1284 PINMUX_IPSR_DATA(IP8_26, AVB_PHY_INT), 1283 PINMUX_IPSR_DATA(IP8_26, AVB_PHY_INT),
1285 PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0), 1284 PINMUX_IPSR_MSEL(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
1286 PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK), 1285 PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
1287 PINMUX_IPSR_DATA(IP8_28, SD0_CLK), 1286 PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
1288 PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1), 1287 PINMUX_IPSR_MSEL(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
1289 PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD), 1288 PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD),
1290 PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1), 1289 PINMUX_IPSR_MSEL(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
1291 PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1), 1290 PINMUX_IPSR_MSEL(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
1292 1291
1293 PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0), 1292 PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0),
1294 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1), 1293 PINMUX_IPSR_MSEL(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
1295 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1), 1294 PINMUX_IPSR_MSEL(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
1296 PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1), 1295 PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1),
1297 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1), 1296 PINMUX_IPSR_MSEL(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
1298 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1), 1297 PINMUX_IPSR_MSEL(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
1299 PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2), 1298 PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2),
1300 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1), 1299 PINMUX_IPSR_MSEL(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
1301 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1), 1300 PINMUX_IPSR_MSEL(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
1302 PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3), 1301 PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3),
1303 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1), 1302 PINMUX_IPSR_MSEL(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
1304 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1), 1303 PINMUX_IPSR_MSEL(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
1305 PINMUX_IPSR_DATA(IP9_11_8, SD0_CD), 1304 PINMUX_IPSR_DATA(IP9_11_8, SD0_CD),
1306 PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6), 1305 PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6),
1307 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1), 1306 PINMUX_IPSR_MSEL(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
1308 PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP), 1307 PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
1309 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0), 1308 PINMUX_IPSR_MSEL(IP9_11_8, GLO_SCLK, SEL_GPS_0),
1310 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1), 1309 PINMUX_IPSR_MSEL(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
1311 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1), 1310 PINMUX_IPSR_MSEL(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
1312 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1), 1311 PINMUX_IPSR_MSEL(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
1313 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1), 1312 PINMUX_IPSR_MSEL(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
1314 PINMUX_IPSR_DATA(IP9_15_12, SD0_WP), 1313 PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
1315 PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7), 1314 PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
1316 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1), 1315 PINMUX_IPSR_MSEL(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
1317 PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN), 1316 PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
1318 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0), 1317 PINMUX_IPSR_MSEL(IP9_15_12, GLO_SDATA, SEL_GPS_0),
1319 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1), 1318 PINMUX_IPSR_MSEL(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
1320 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1), 1319 PINMUX_IPSR_MSEL(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
1321 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1), 1320 PINMUX_IPSR_MSEL(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
1322 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), 1321 PINMUX_IPSR_MSEL(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
1323 PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK), 1322 PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
1324 PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN), 1323 PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
1325 PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD), 1324 PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
1326 PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER), 1325 PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
1327 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1), 1326 PINMUX_IPSR_MSEL(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
1328 PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0), 1327 PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
1329 PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK), 1328 PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
1330 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1), 1329 PINMUX_IPSR_MSEL(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
1331 PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1), 1330 PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
1332 PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK), 1331 PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
1333 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1), 1332 PINMUX_IPSR_MSEL(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
1334 PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2), 1333 PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
1335 PINMUX_IPSR_DATA(IP9_25_24, AVB_COL), 1334 PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
1336 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1), 1335 PINMUX_IPSR_MSEL(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
1337 PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3), 1336 PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
1338 PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0), 1337 PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
1339 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1), 1338 PINMUX_IPSR_MSEL(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
1340 PINMUX_IPSR_DATA(IP9_31_28, SD1_CD), 1339 PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
1341 PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6), 1340 PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
1342 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0), 1341 PINMUX_IPSR_MSEL(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
1343 PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP), 1342 PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
1344 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0), 1343 PINMUX_IPSR_MSEL(IP9_31_28, GLO_SS, SEL_GPS_0),
1345 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1), 1344 PINMUX_IPSR_MSEL(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
1346 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3), 1345 PINMUX_IPSR_MSEL(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
1347 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3), 1346 PINMUX_IPSR_MSEL(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
1348 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1), 1347 PINMUX_IPSR_MSEL(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
1349 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1), 1348 PINMUX_IPSR_MSEL(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
1350 1349
1351 PINMUX_IPSR_DATA(IP10_3_0, SD1_WP), 1350 PINMUX_IPSR_DATA(IP10_3_0, SD1_WP),
1352 PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7), 1351 PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7),
1353 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0), 1352 PINMUX_IPSR_MSEL(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
1354 PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN), 1353 PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
1355 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0), 1354 PINMUX_IPSR_MSEL(IP10_3_0, GLO_RFON, SEL_GPS_0),
1356 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1), 1355 PINMUX_IPSR_MSEL(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
1357 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3), 1356 PINMUX_IPSR_MSEL(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
1358 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3), 1357 PINMUX_IPSR_MSEL(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
1359 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1), 1358 PINMUX_IPSR_MSEL(IP10_3_0, SIM0_D_B, SEL_SIM_1),
1360 PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK), 1359 PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
1361 PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK), 1360 PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
1362 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0), 1361 PINMUX_IPSR_MSEL(IP10_6_4, SIM0_CLK, SEL_SIM_0),
1363 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1), 1362 PINMUX_IPSR_MSEL(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
1364 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2), 1363 PINMUX_IPSR_MSEL(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
1365 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1), 1364 PINMUX_IPSR_MSEL(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
1366 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1), 1365 PINMUX_IPSR_MSEL(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
1367 PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD), 1366 PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD),
1368 PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD), 1367 PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD),
1369 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0), 1368 PINMUX_IPSR_MSEL(IP10_10_7, SIM0_D, SEL_SIM_0),
1370 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1), 1369 PINMUX_IPSR_MSEL(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
1371 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4), 1370 PINMUX_IPSR_MSEL(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
1372 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3), 1371 PINMUX_IPSR_MSEL(IP10_10_7, SCK1_D, SEL_SCIF1_3),
1373 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2), 1372 PINMUX_IPSR_MSEL(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
1374 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1), 1373 PINMUX_IPSR_MSEL(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
1375 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1), 1374 PINMUX_IPSR_MSEL(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
1376 PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0), 1375 PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0),
1377 PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0), 1376 PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0),
1378 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1), 1377 PINMUX_IPSR_MSEL(IP10_14_11, FMCLK_B, SEL_FM_1),
1379 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1), 1378 PINMUX_IPSR_MSEL(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
1380 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4), 1379 PINMUX_IPSR_MSEL(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
1381 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3), 1380 PINMUX_IPSR_MSEL(IP10_14_11, RX1_D, SEL_SCIF1_3),
1382 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2), 1381 PINMUX_IPSR_MSEL(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
1383 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1), 1382 PINMUX_IPSR_MSEL(IP10_14_11, GLO_SS_B, SEL_GPS_1),
1384 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1), 1383 PINMUX_IPSR_MSEL(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
1385 PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1), 1384 PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
1386 PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1), 1385 PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
1387 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1), 1386 PINMUX_IPSR_MSEL(IP10_18_15, FMIN_B, SEL_FM_1),
1388 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1), 1387 PINMUX_IPSR_MSEL(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
1389 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4), 1388 PINMUX_IPSR_MSEL(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
1390 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3), 1389 PINMUX_IPSR_MSEL(IP10_18_15, TX1_D, SEL_SCIF1_3),
1391 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2), 1390 PINMUX_IPSR_MSEL(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
1392 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1), 1391 PINMUX_IPSR_MSEL(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
1393 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1), 1392 PINMUX_IPSR_MSEL(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
1394 PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2), 1393 PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
1395 PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2), 1394 PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
1396 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1), 1395 PINMUX_IPSR_MSEL(IP10_22_19, BPFCLK_B, SEL_FM_1),
1397 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1), 1396 PINMUX_IPSR_MSEL(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
1398 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3), 1397 PINMUX_IPSR_MSEL(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
1399 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1), 1398 PINMUX_IPSR_MSEL(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
1400 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1), 1399 PINMUX_IPSR_MSEL(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
1401 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1), 1400 PINMUX_IPSR_MSEL(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
1402 PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3), 1401 PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3),
1403 PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3), 1402 PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3),
1404 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0), 1403 PINMUX_IPSR_MSEL(IP10_25_23, SIM0_RST, SEL_SIM_0),
1405 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1), 1404 PINMUX_IPSR_MSEL(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
1406 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3), 1405 PINMUX_IPSR_MSEL(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
1407 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1), 1406 PINMUX_IPSR_MSEL(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
1408 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1), 1407 PINMUX_IPSR_MSEL(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
1409 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1), 1408 PINMUX_IPSR_MSEL(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
1410 PINMUX_IPSR_DATA(IP10_29_26, SD2_CD), 1409 PINMUX_IPSR_DATA(IP10_29_26, SD2_CD),
1411 PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4), 1410 PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4),
1412 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1), 1411 PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
1413 PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP), 1412 PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP),
1414 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0), 1413 PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0, SEL_GPS_0),
1415 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1), 1414 PINMUX_IPSR_MSEL(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
1416 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3), 1415 PINMUX_IPSR_MSEL(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
1417 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1), 1416 PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
1418 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1), 1417 PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0_B, SEL_GPS_1),
1419 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1), 1418 PINMUX_IPSR_MSEL(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
1420 1419
1421 PINMUX_IPSR_DATA(IP11_3_0, SD2_WP), 1420 PINMUX_IPSR_DATA(IP11_3_0, SD2_WP),
1422 PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5), 1421 PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5),
1423 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1), 1422 PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
1424 PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN), 1423 PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN),
1425 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0), 1424 PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1, SEL_GPS_0),
1426 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1), 1425 PINMUX_IPSR_MSEL(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
1427 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3), 1426 PINMUX_IPSR_MSEL(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
1428 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1), 1427 PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
1429 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1), 1428 PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1_B, SEL_GPS_1),
1430 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1), 1429 PINMUX_IPSR_MSEL(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
1431 PINMUX_IPSR_DATA(IP11_4, SD3_CLK), 1430 PINMUX_IPSR_DATA(IP11_4, SD3_CLK),
1432 PINMUX_IPSR_DATA(IP11_4, MMC1_CLK), 1431 PINMUX_IPSR_DATA(IP11_4, MMC1_CLK),
1433 PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD), 1432 PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD),
@@ -1447,298 +1446,298 @@ static const u16 pinmux_data[] = {
1447 PINMUX_IPSR_DATA(IP11_14_13, SCKZ), 1446 PINMUX_IPSR_DATA(IP11_14_13, SCKZ),
1448 PINMUX_IPSR_DATA(IP11_17_15, SD3_CD), 1447 PINMUX_IPSR_DATA(IP11_17_15, SD3_CD),
1449 PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4), 1448 PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4),
1450 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0), 1449 PINMUX_IPSR_MSEL(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
1451 PINMUX_IPSR_DATA(IP11_17_15, VSP), 1450 PINMUX_IPSR_DATA(IP11_17_15, VSP),
1452 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0), 1451 PINMUX_IPSR_MSEL(IP11_17_15, GLO_Q0, SEL_GPS_0),
1453 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1), 1452 PINMUX_IPSR_MSEL(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
1454 PINMUX_IPSR_DATA(IP11_21_18, SD3_WP), 1453 PINMUX_IPSR_DATA(IP11_21_18, SD3_WP),
1455 PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5), 1454 PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5),
1456 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0), 1455 PINMUX_IPSR_MSEL(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
1457 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0), 1456 PINMUX_IPSR_MSEL(IP11_21_18, GLO_Q1, SEL_GPS_0),
1458 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2), 1457 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_C, SEL_FM_2),
1459 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4), 1458 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_E, SEL_FM_4),
1460 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5), 1459 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_F, SEL_FM_5),
1461 PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK), 1460 PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
1462 PINMUX_IPSR_MODSEL_DATA(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1), 1461 PINMUX_IPSR_MSEL(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
1463 PINMUX_IPSR_MODSEL_DATA(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1), 1462 PINMUX_IPSR_MSEL(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
1464 PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG), 1463 PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
1465 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3), 1464 PINMUX_IPSR_MSEL(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
1466 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2), 1465 PINMUX_IPSR_MSEL(IP11_26_24, RX1_C, SEL_SCIF1_2),
1467 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1), 1466 PINMUX_IPSR_MSEL(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
1468 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1), 1467 PINMUX_IPSR_MSEL(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
1469 PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT), 1468 PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
1470 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3), 1469 PINMUX_IPSR_MSEL(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
1471 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2), 1470 PINMUX_IPSR_MSEL(IP11_29_27, TX1_C, SEL_SCIF1_2),
1472 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2), 1471 PINMUX_IPSR_MSEL(IP11_29_27, BPFCLK_C, SEL_FM_2),
1473 PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129), 1472 PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
1474 PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1), 1473 PINMUX_IPSR_MSEL(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
1475 PINMUX_IPSR_DATA(IP11_31_30, MOUT0), 1474 PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
1476 1475
1477 PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129), 1476 PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129),
1478 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1), 1477 PINMUX_IPSR_MSEL(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
1479 PINMUX_IPSR_DATA(IP12_1_0, MOUT1), 1478 PINMUX_IPSR_DATA(IP12_1_0, MOUT1),
1480 PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0), 1479 PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0),
1481 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1), 1480 PINMUX_IPSR_MSEL(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
1482 PINMUX_IPSR_DATA(IP12_3_2, MOUT2), 1481 PINMUX_IPSR_DATA(IP12_3_2, MOUT2),
1483 PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1), 1482 PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1),
1484 PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1), 1483 PINMUX_IPSR_MSEL(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
1485 PINMUX_IPSR_DATA(IP12_5_4, MOUT5), 1484 PINMUX_IPSR_DATA(IP12_5_4, MOUT5),
1486 PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2), 1485 PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2),
1487 PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1), 1486 PINMUX_IPSR_MSEL(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
1488 PINMUX_IPSR_DATA(IP12_7_6, SSI_SCK1), 1487 PINMUX_IPSR_DATA(IP12_7_6, SSI_SCK1),
1489 PINMUX_IPSR_DATA(IP12_7_6, MOUT6), 1488 PINMUX_IPSR_DATA(IP12_7_6, MOUT6),
1490 PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34), 1489 PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34),
1491 PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0), 1490 PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0),
1492 PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0), 1491 PINMUX_IPSR_MSEL(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
1493 PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0), 1492 PINMUX_IPSR_MSEL(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
1494 PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER), 1493 PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
1495 PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34), 1494 PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34),
1496 PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0), 1495 PINMUX_IPSR_MSEL(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
1497 PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0), 1496 PINMUX_IPSR_MSEL(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
1498 PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC), 1497 PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC),
1499 PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0), 1498 PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0),
1500 PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3), 1499 PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3),
1501 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0), 1500 PINMUX_IPSR_MSEL(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
1502 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0), 1501 PINMUX_IPSR_MSEL(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
1503 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0), 1502 PINMUX_IPSR_MSEL(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
1504 PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK), 1503 PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK),
1505 PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4), 1504 PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4),
1506 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0), 1505 PINMUX_IPSR_MSEL(IP12_19_17, STP_ISD_0, SEL_SSP_0),
1507 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0), 1506 PINMUX_IPSR_MSEL(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
1508 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0), 1507 PINMUX_IPSR_MSEL(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
1509 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2), 1508 PINMUX_IPSR_MSEL(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
1510 PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0), 1509 PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0),
1511 PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4), 1510 PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4),
1512 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0), 1511 PINMUX_IPSR_MSEL(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
1513 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0), 1512 PINMUX_IPSR_MSEL(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
1514 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0), 1513 PINMUX_IPSR_MSEL(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
1515 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2), 1514 PINMUX_IPSR_MSEL(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
1516 PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1), 1515 PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1),
1517 PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4), 1516 PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4),
1518 PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0), 1517 PINMUX_IPSR_MSEL(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
1519 PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0), 1518 PINMUX_IPSR_MSEL(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
1520 PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2), 1519 PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2),
1521 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0), 1520 PINMUX_IPSR_MSEL(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
1522 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0), 1521 PINMUX_IPSR_MSEL(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
1523 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1), 1522 PINMUX_IPSR_MSEL(IP12_27_25, IERX_B, SEL_IEB_1),
1524 PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC), 1523 PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
1525 PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS), 1524 PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS),
1526 PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3), 1525 PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3),
1527 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0), 1526 PINMUX_IPSR_MSEL(IP12_30_28, SSI_WS5, SEL_SSI5_0),
1528 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0), 1527 PINMUX_IPSR_MSEL(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
1529 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1), 1528 PINMUX_IPSR_MSEL(IP12_30_28, IECLK_B, SEL_IEB_1),
1530 PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC), 1529 PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
1531 PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE), 1530 PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE),
1532 PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4), 1531 PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4),
1533 1532
1534 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0), 1533 PINMUX_IPSR_MSEL(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
1535 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0), 1534 PINMUX_IPSR_MSEL(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
1536 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1), 1535 PINMUX_IPSR_MSEL(IP13_2_0, IETX_B, SEL_IEB_1),
1537 PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2), 1536 PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2),
1538 PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2), 1537 PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2),
1539 PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5), 1538 PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5),
1540 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0), 1539 PINMUX_IPSR_MSEL(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
1541 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0), 1540 PINMUX_IPSR_MSEL(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
1542 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3), 1541 PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_D, SEL_FM_3),
1543 PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3), 1542 PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3),
1544 PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3), 1543 PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3),
1545 PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6), 1544 PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6),
1546 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5), 1545 PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_F, SEL_FM_5),
1547 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0), 1546 PINMUX_IPSR_MSEL(IP13_9_7, SSI_WS6, SEL_SSI6_0),
1548 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0), 1547 PINMUX_IPSR_MSEL(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
1549 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3), 1548 PINMUX_IPSR_MSEL(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
1550 PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4), 1549 PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4),
1551 PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4), 1550 PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4),
1552 PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7), 1551 PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7),
1553 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0), 1552 PINMUX_IPSR_MSEL(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
1554 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3), 1553 PINMUX_IPSR_MSEL(IP13_12_10, FMIN_D, SEL_FM_3),
1555 PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5), 1554 PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5),
1556 PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5), 1555 PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5),
1557 PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8), 1556 PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8),
1558 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0), 1557 PINMUX_IPSR_MSEL(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
1559 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0), 1558 PINMUX_IPSR_MSEL(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
1560 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0), 1559 PINMUX_IPSR_MSEL(IP13_15_13, SCK1, SEL_SCIF1_0),
1561 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0), 1560 PINMUX_IPSR_MSEL(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
1562 PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6), 1561 PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6),
1563 PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6), 1562 PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6),
1564 PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9), 1563 PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9),
1565 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0), 1564 PINMUX_IPSR_MSEL(IP13_18_16, SSI_WS78, SEL_SSI7_0),
1566 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0), 1565 PINMUX_IPSR_MSEL(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
1567 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0), 1566 PINMUX_IPSR_MSEL(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
1568 PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N), 1567 PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N),
1569 PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7), 1568 PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7),
1570 PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7), 1569 PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7),
1571 PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10), 1570 PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10),
1572 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0), 1571 PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
1573 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0), 1572 PINMUX_IPSR_MSEL(IP13_22_19, STP_ISD_1, SEL_SSP_0),
1574 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0), 1573 PINMUX_IPSR_MSEL(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
1575 PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N), 1574 PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N),
1576 PINMUX_IPSR_DATA(IP13_22_19, TCLK2), 1575 PINMUX_IPSR_DATA(IP13_22_19, TCLK2),
1577 PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS), 1576 PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS),
1578 PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11), 1577 PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11),
1579 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4), 1578 PINMUX_IPSR_MSEL(IP13_22_19, BPFCLK_E, SEL_FM_4),
1580 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1), 1579 PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
1581 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6), 1580 PINMUX_IPSR_MSEL(IP13_22_19, FMIN_G, SEL_FM_6),
1582 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0), 1581 PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
1583 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0), 1582 PINMUX_IPSR_MSEL(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
1584 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0), 1583 PINMUX_IPSR_MSEL(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
1585 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2), 1584 PINMUX_IPSR_MSEL(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
1586 PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12), 1585 PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12),
1587 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1), 1586 PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
1588 PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9), 1587 PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9),
1589 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0), 1588 PINMUX_IPSR_MSEL(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
1590 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0), 1589 PINMUX_IPSR_MSEL(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
1591 PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1), 1590 PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1),
1592 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2), 1591 PINMUX_IPSR_MSEL(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
1593 PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13), 1592 PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13),
1594 PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA), 1593 PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA),
1595 PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0), 1594 PINMUX_IPSR_MSEL(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
1596 PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14), 1595 PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14),
1597 1596
1598 PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB), 1597 PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB),
1599 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0), 1598 PINMUX_IPSR_MSEL(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
1600 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3), 1599 PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
1601 PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE), 1600 PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE),
1602 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2), 1601 PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
1603 PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15), 1602 PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15),
1604 PINMUX_IPSR_DATA(IP14_2_0, REMOCON), 1603 PINMUX_IPSR_DATA(IP14_2_0, REMOCON),
1605 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0), 1604 PINMUX_IPSR_MSEL(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
1606 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0), 1605 PINMUX_IPSR_MSEL(IP14_5_3, HSCK1, SEL_HSCIF1_0),
1607 PINMUX_IPSR_DATA(IP14_5_3, SCK0), 1606 PINMUX_IPSR_DATA(IP14_5_3, SCK0),
1608 PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2), 1607 PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2),
1609 PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2), 1608 PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2),
1610 PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10), 1609 PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10),
1611 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2), 1610 PINMUX_IPSR_MSEL(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
1612 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2), 1611 PINMUX_IPSR_MSEL(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
1613 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0), 1612 PINMUX_IPSR_MSEL(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
1614 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0), 1613 PINMUX_IPSR_MSEL(IP14_8_6, HRX1, SEL_HSCIF1_0),
1615 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0), 1614 PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0),
1616 PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0), 1615 PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0),
1617 PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0), 1616 PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0),
1618 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0), 1617 PINMUX_IPSR_MSEL(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
1619 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0), 1618 PINMUX_IPSR_MSEL(IP14_11_9, HTX1, SEL_HSCIF1_0),
1620 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0), 1619 PINMUX_IPSR_MSEL(IP14_11_9, TX0, SEL_SCIF0_0),
1621 PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1), 1620 PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1),
1622 PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1), 1621 PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1),
1623 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0), 1622 PINMUX_IPSR_MSEL(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
1624 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0), 1623 PINMUX_IPSR_MSEL(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
1625 PINMUX_IPSR_DATA(IP14_15_12, CTS0_N), 1624 PINMUX_IPSR_DATA(IP14_15_12, CTS0_N),
1626 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0), 1625 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
1627 PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3), 1626 PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3),
1628 PINMUX_IPSR_DATA(IP14_15_12, LCDOUT11), 1627 PINMUX_IPSR_DATA(IP14_15_12, LCDOUT11),
1629 PINMUX_IPSR_DATA(IP14_15_12, PWM0_B), 1628 PINMUX_IPSR_DATA(IP14_15_12, PWM0_B),
1630 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2), 1629 PINMUX_IPSR_MSEL(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
1631 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2), 1630 PINMUX_IPSR_MSEL(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
1632 PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0), 1631 PINMUX_IPSR_MSEL(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
1633 PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0), 1632 PINMUX_IPSR_MSEL(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
1634 PINMUX_IPSR_DATA(IP14_18_16, RTS0_N), 1633 PINMUX_IPSR_DATA(IP14_18_16, RTS0_N),
1635 PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1), 1634 PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1),
1636 PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0), 1635 PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0),
1637 PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8), 1636 PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8),
1638 PINMUX_IPSR_DATA(IP14_18_16, PWM1_B), 1637 PINMUX_IPSR_DATA(IP14_18_16, PWM1_B),
1639 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0), 1638 PINMUX_IPSR_MSEL(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
1640 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0), 1639 PINMUX_IPSR_MSEL(IP14_21_19, AD_DI, SEL_ADI_0),
1641 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0), 1640 PINMUX_IPSR_MSEL(IP14_21_19, RX1, SEL_SCIF1_0),
1642 PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE), 1641 PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
1643 PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE), 1642 PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE),
1644 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0), 1643 PINMUX_IPSR_MSEL(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
1645 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0), 1644 PINMUX_IPSR_MSEL(IP14_24_22, AD_DO, SEL_ADI_0),
1646 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0), 1645 PINMUX_IPSR_MSEL(IP14_24_22, TX1, SEL_SCIF1_0),
1647 PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1), 1646 PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1),
1648 PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9), 1647 PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9),
1649 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0), 1648 PINMUX_IPSR_MSEL(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
1650 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0), 1649 PINMUX_IPSR_MSEL(IP14_27_25, AD_CLK, SEL_ADI_0),
1651 PINMUX_IPSR_DATA(IP14_27_25, CTS1_N), 1650 PINMUX_IPSR_DATA(IP14_27_25, CTS1_N),
1652 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0), 1651 PINMUX_IPSR_MSEL(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
1653 PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT), 1652 PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT),
1654 PINMUX_IPSR_DATA(IP14_27_25, QCLK), 1653 PINMUX_IPSR_DATA(IP14_27_25, QCLK),
1655 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0), 1654 PINMUX_IPSR_MSEL(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
1656 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0), 1655 PINMUX_IPSR_MSEL(IP14_30_28, AD_NCS_N, SEL_ADI_0),
1657 PINMUX_IPSR_DATA(IP14_30_28, RTS1_N), 1656 PINMUX_IPSR_DATA(IP14_30_28, RTS1_N),
1658 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0), 1657 PINMUX_IPSR_MSEL(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
1659 PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT), 1658 PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT),
1660 PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE), 1659 PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE),
1661 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2), 1660 PINMUX_IPSR_MSEL(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
1662 1661
1663 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0), 1662 PINMUX_IPSR_MSEL(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
1664 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0), 1663 PINMUX_IPSR_MSEL(IP15_2_0, FMCLK, SEL_FM_0),
1665 PINMUX_IPSR_DATA(IP15_2_0, SCK2), 1664 PINMUX_IPSR_DATA(IP15_2_0, SCK2),
1666 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0), 1665 PINMUX_IPSR_MSEL(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
1667 PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7), 1666 PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7),
1668 PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15), 1667 PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15),
1669 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1), 1668 PINMUX_IPSR_MSEL(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
1670 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0), 1669 PINMUX_IPSR_MSEL(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1671 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0), 1670 PINMUX_IPSR_MSEL(IP15_5_3, FMIN, SEL_FM_0),
1672 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, TX2, SEL_SCIF2_0), 1671 PINMUX_IPSR_MSEL(IP15_5_3, TX2, SEL_SCIF2_0),
1673 PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0), 1672 PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0),
1674 PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16), 1673 PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16),
1675 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, IIC2_SCL, SEL_IIC2_0), 1674 PINMUX_IPSR_MSEL(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
1676 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, I2C2_SCL, SEL_I2C2_0), 1675 PINMUX_IPSR_MSEL(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
1677 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0), 1676 PINMUX_IPSR_MSEL(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
1678 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0), 1677 PINMUX_IPSR_MSEL(IP15_8_6, BPFCLK, SEL_FM_0),
1679 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, RX2, SEL_SCIF2_0), 1678 PINMUX_IPSR_MSEL(IP15_8_6, RX2, SEL_SCIF2_0),
1680 PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1), 1679 PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1),
1681 PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17), 1680 PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17),
1682 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, IIC2_SDA, SEL_IIC2_0), 1681 PINMUX_IPSR_MSEL(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
1683 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, I2C2_SDA, SEL_I2C2_0), 1682 PINMUX_IPSR_MSEL(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
1684 PINMUX_IPSR_DATA(IP15_11_9, HSCK0), 1683 PINMUX_IPSR_DATA(IP15_11_9, HSCK0),
1685 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0), 1684 PINMUX_IPSR_MSEL(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
1686 PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4), 1685 PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4),
1687 PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12), 1686 PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12),
1688 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2), 1687 PINMUX_IPSR_MSEL(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
1689 PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0), 1688 PINMUX_IPSR_MSEL(IP15_13_12, HRX0, SEL_HSCIF0_0),
1690 PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2), 1689 PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2),
1691 PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18), 1690 PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18),
1692 PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0), 1691 PINMUX_IPSR_MSEL(IP15_15_14, HTX0, SEL_HSCIF0_0),
1693 PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3), 1692 PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3),
1694 PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19), 1693 PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19),
1695 PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0), 1694 PINMUX_IPSR_MSEL(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
1696 PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9), 1695 PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9),
1697 PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4), 1696 PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4),
1698 PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20), 1697 PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20),
1699 PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0), 1698 PINMUX_IPSR_MSEL(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
1700 PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9), 1699 PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9),
1701 PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5), 1700 PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5),
1702 PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21), 1701 PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21),
1703 PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0), 1702 PINMUX_IPSR_MSEL(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
1704 PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0), 1703 PINMUX_IPSR_MSEL(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
1705 PINMUX_IPSR_DATA(IP15_22_20, ADICLK), 1704 PINMUX_IPSR_DATA(IP15_22_20, ADICLK),
1706 PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6), 1705 PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6),
1707 PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22), 1706 PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22),
1708 PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC), 1707 PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC),
1709 PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0), 1708 PINMUX_IPSR_MSEL(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
1710 PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2), 1709 PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2),
1711 PINMUX_IPSR_DATA(IP15_25_23, ADIDATA), 1710 PINMUX_IPSR_DATA(IP15_25_23, ADIDATA),
1712 PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7), 1711 PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7),
1713 PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23), 1712 PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23),
1714 PINMUX_IPSR_MODSEL_DATA(IP15_25_23, HRX0_C, SEL_SCIFA2_1), 1713 PINMUX_IPSR_MSEL(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
1715 PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0), 1714 PINMUX_IPSR_MSEL(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
1716 PINMUX_IPSR_DATA(IP15_27_26, ADICHS0), 1715 PINMUX_IPSR_DATA(IP15_27_26, ADICHS0),
1717 PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5), 1716 PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5),
1718 PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13), 1717 PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13),
1719 PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0), 1718 PINMUX_IPSR_MSEL(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
1720 PINMUX_IPSR_DATA(IP15_29_28, ADICHS1), 1719 PINMUX_IPSR_DATA(IP15_29_28, ADICHS1),
1721 PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6), 1720 PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6),
1722 PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14), 1721 PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14),
1723 1722
1724 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0), 1723 PINMUX_IPSR_MSEL(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
1725 PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT), 1724 PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT),
1726 PINMUX_IPSR_DATA(IP16_2_0, ADICHS2), 1725 PINMUX_IPSR_DATA(IP16_2_0, ADICHS2),
1727 PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP), 1726 PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP),
1728 PINMUX_IPSR_DATA(IP16_2_0, QPOLA), 1727 PINMUX_IPSR_DATA(IP16_2_0, QPOLA),
1729 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2), 1728 PINMUX_IPSR_MSEL(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
1730 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1), 1729 PINMUX_IPSR_MSEL(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
1731 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0), 1730 PINMUX_IPSR_MSEL(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
1732 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0), 1731 PINMUX_IPSR_MSEL(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
1733 PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2), 1732 PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2),
1734 PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP), 1733 PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP),
1735 PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE), 1734 PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE),
1736 PINMUX_IPSR_DATA(IP16_5_3, QPOLB), 1735 PINMUX_IPSR_DATA(IP16_5_3, QPOLB),
1737 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2), 1736 PINMUX_IPSR_MSEL(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
1738 PINMUX_IPSR_DATA(IP16_6, USB1_PWEN), 1737 PINMUX_IPSR_DATA(IP16_6, USB1_PWEN),
1739 PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D), 1738 PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
1740 PINMUX_IPSR_DATA(IP16_7, USB1_OVC), 1739 PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
1741 PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1), 1740 PINMUX_IPSR_MSEL(IP16_7, TCLK1_B, SEL_TMU1_1),
1742 1741
1743 PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0), 1742 PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0),
1744 PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0), 1743 PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0),
@@ -3624,25 +3623,6 @@ static const unsigned int usb2_pins[] = {
3624static const unsigned int usb2_mux[] = { 3623static const unsigned int usb2_mux[] = {
3625 USB2_PWEN_MARK, USB2_OVC_MARK, 3624 USB2_PWEN_MARK, USB2_OVC_MARK,
3626}; 3625};
3627
3628union vin_data {
3629 unsigned int data24[24];
3630 unsigned int data20[20];
3631 unsigned int data16[16];
3632 unsigned int data12[12];
3633 unsigned int data10[10];
3634 unsigned int data8[8];
3635 unsigned int data4[4];
3636};
3637
3638#define VIN_DATA_PIN_GROUP(n, s) \
3639 { \
3640 .name = #n#s, \
3641 .pins = n##_pins.data##s, \
3642 .mux = n##_mux.data##s, \
3643 .nr_pins = ARRAY_SIZE(n##_pins.data##s), \
3644 }
3645
3646/* - VIN0 ------------------------------------------------------------------- */ 3626/* - VIN0 ------------------------------------------------------------------- */
3647static const union vin_data vin0_data_pins = { 3627static const union vin_data vin0_data_pins = {
3648 .data24 = { 3628 .data24 = {
@@ -5719,6 +5699,6 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = {
5719 5699
5720 .cfg_regs = pinmux_config_regs, 5700 .cfg_regs = pinmux_config_regs,
5721 5701
5722 .gpio_data = pinmux_data, 5702 .pinmux_data = pinmux_data,
5723 .gpio_data_size = ARRAY_SIZE(pinmux_data), 5703 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5724}; 5704};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index 25e8117f5a1a..87a4f44147c1 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -9,7 +9,6 @@
9 */ 9 */
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/platform_data/gpio-rcar.h>
13 12
14#include "core.h" 13#include "core.h"
15#include "sh_pfc.h" 14#include "sh_pfc.h"
@@ -824,459 +823,459 @@ static const u16 pinmux_data[] = {
824 PINMUX_IPSR_DATA(IP0_14, D14), 823 PINMUX_IPSR_DATA(IP0_14, D14),
825 PINMUX_IPSR_DATA(IP0_15, D15), 824 PINMUX_IPSR_DATA(IP0_15, D15),
826 PINMUX_IPSR_DATA(IP0_18_16, A0), 825 PINMUX_IPSR_DATA(IP0_18_16, A0),
827 PINMUX_IPSR_MODSEL_DATA(IP0_18_16, ATAWR0_N_C, SEL_LBS_2), 826 PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
828 PINMUX_IPSR_MODSEL_DATA(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1), 827 PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
829 PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SCL0_C, SEL_IIC0_2), 828 PINMUX_IPSR_MSEL(IP0_18_16, SCL0_C, SEL_IIC0_2),
830 PINMUX_IPSR_DATA(IP0_18_16, PWM2_B), 829 PINMUX_IPSR_DATA(IP0_18_16, PWM2_B),
831 PINMUX_IPSR_DATA(IP0_20_19, A1), 830 PINMUX_IPSR_DATA(IP0_20_19, A1),
832 PINMUX_IPSR_MODSEL_DATA(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1), 831 PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
833 PINMUX_IPSR_DATA(IP0_22_21, A2), 832 PINMUX_IPSR_DATA(IP0_22_21, A2),
834 PINMUX_IPSR_MODSEL_DATA(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1), 833 PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
835 PINMUX_IPSR_DATA(IP0_24_23, A3), 834 PINMUX_IPSR_DATA(IP0_24_23, A3),
836 PINMUX_IPSR_MODSEL_DATA(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1), 835 PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
837 PINMUX_IPSR_DATA(IP0_26_25, A4), 836 PINMUX_IPSR_DATA(IP0_26_25, A4),
838 PINMUX_IPSR_MODSEL_DATA(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1), 837 PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
839 PINMUX_IPSR_DATA(IP0_28_27, A5), 838 PINMUX_IPSR_DATA(IP0_28_27, A5),
840 PINMUX_IPSR_MODSEL_DATA(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1), 839 PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
841 PINMUX_IPSR_DATA(IP0_30_29, A6), 840 PINMUX_IPSR_DATA(IP0_30_29, A6),
842 PINMUX_IPSR_MODSEL_DATA(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0), 841 PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
843 842
844 /* IPSR1 */ 843 /* IPSR1 */
845 PINMUX_IPSR_DATA(IP1_1_0, A7), 844 PINMUX_IPSR_DATA(IP1_1_0, A7),
846 PINMUX_IPSR_MODSEL_DATA(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0), 845 PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
847 PINMUX_IPSR_DATA(IP1_3_2, A8), 846 PINMUX_IPSR_DATA(IP1_3_2, A8),
848 PINMUX_IPSR_MODSEL_DATA(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0), 847 PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
849 PINMUX_IPSR_MODSEL_DATA(IP1_3_2, SCL0, SEL_IIC0_0), 848 PINMUX_IPSR_MSEL(IP1_3_2, SCL0, SEL_IIC0_0),
850 PINMUX_IPSR_DATA(IP1_5_4, A9), 849 PINMUX_IPSR_DATA(IP1_5_4, A9),
851 PINMUX_IPSR_MODSEL_DATA(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0), 850 PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
852 PINMUX_IPSR_MODSEL_DATA(IP1_5_4, SDA0, SEL_IIC0_0), 851 PINMUX_IPSR_MSEL(IP1_5_4, SDA0, SEL_IIC0_0),
853 PINMUX_IPSR_DATA(IP1_7_6, A10), 852 PINMUX_IPSR_DATA(IP1_7_6, A10),
854 PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0), 853 PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
855 PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3), 854 PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
856 PINMUX_IPSR_DATA(IP1_10_8, A11), 855 PINMUX_IPSR_DATA(IP1_10_8, A11),
857 PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0), 856 PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
858 PINMUX_IPSR_MODSEL_DATA(IP1_10_8, SCL3_D, SEL_IIC3_3), 857 PINMUX_IPSR_MSEL(IP1_10_8, SCL3_D, SEL_IIC3_3),
859 PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3), 858 PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
860 PINMUX_IPSR_DATA(IP1_13_11, A12), 859 PINMUX_IPSR_DATA(IP1_13_11, A12),
861 PINMUX_IPSR_MODSEL_DATA(IP1_13_11, FMCLK, SEL_FM_0), 860 PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0),
862 PINMUX_IPSR_MODSEL_DATA(IP1_13_11, SDA3_D, SEL_IIC3_3), 861 PINMUX_IPSR_MSEL(IP1_13_11, SDA3_D, SEL_IIC3_3),
863 PINMUX_IPSR_MODSEL_DATA(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3), 862 PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
864 PINMUX_IPSR_DATA(IP1_16_14, A13), 863 PINMUX_IPSR_DATA(IP1_16_14, A13),
865 PINMUX_IPSR_MODSEL_DATA(IP1_16_14, ATAG0_N_C, SEL_LBS_2), 864 PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
866 PINMUX_IPSR_MODSEL_DATA(IP1_16_14, BPFCLK, SEL_FM_0), 865 PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0),
867 PINMUX_IPSR_MODSEL_DATA(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3), 866 PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
868 PINMUX_IPSR_DATA(IP1_19_17, A14), 867 PINMUX_IPSR_DATA(IP1_19_17, A14),
869 PINMUX_IPSR_MODSEL_DATA(IP1_19_17, ATADIR0_N_C, SEL_LBS_2), 868 PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
870 PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN, SEL_FM_0), 869 PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0),
871 PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN_C, SEL_FM_2), 870 PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2),
872 PINMUX_IPSR_MODSEL_DATA(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3), 871 PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
873 PINMUX_IPSR_DATA(IP1_22_20, A15), 872 PINMUX_IPSR_DATA(IP1_22_20, A15),
874 PINMUX_IPSR_MODSEL_DATA(IP1_22_20, BPFCLK_C, SEL_FM_2), 873 PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2),
875 PINMUX_IPSR_DATA(IP1_25_23, A16), 874 PINMUX_IPSR_DATA(IP1_25_23, A16),
876 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, DREQ2_B, SEL_LBS_1), 875 PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1),
877 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, FMCLK_C, SEL_FM_2), 876 PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2),
878 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1), 877 PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
879 PINMUX_IPSR_DATA(IP1_28_26, A17), 878 PINMUX_IPSR_DATA(IP1_28_26, A17),
880 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, DACK2_B, SEL_LBS_1), 879 PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1),
881 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, SDA0_C, SEL_IIC0_2), 880 PINMUX_IPSR_MSEL(IP1_28_26, SDA0_C, SEL_IIC0_2),
882 PINMUX_IPSR_DATA(IP1_31_29, A18), 881 PINMUX_IPSR_DATA(IP1_31_29, A18),
883 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, DREQ1, SEL_LBS_0), 882 PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0),
884 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2), 883 PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
885 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2), 884 PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
886 885
887 /* IPSR2 */ 886 /* IPSR2 */
888 PINMUX_IPSR_DATA(IP2_2_0, A19), 887 PINMUX_IPSR_DATA(IP2_2_0, A19),
889 PINMUX_IPSR_DATA(IP2_2_0, DACK1), 888 PINMUX_IPSR_DATA(IP2_2_0, DACK1),
890 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2), 889 PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
891 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2), 890 PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
892 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_0), 891 PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1),
893 PINMUX_IPSR_DATA(IP2_2_0, A20), 892 PINMUX_IPSR_DATA(IP2_2_0, A20),
894 PINMUX_IPSR_MODSEL_DATA(IP2_4_3, SPCLK, SEL_QSP_0), 893 PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0),
895 PINMUX_IPSR_DATA(IP2_6_5, A21), 894 PINMUX_IPSR_DATA(IP2_6_5, A21),
896 PINMUX_IPSR_MODSEL_DATA(IP2_6_5, ATAWR0_N_B, SEL_LBS_1), 895 PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
897 PINMUX_IPSR_MODSEL_DATA(IP2_6_5, MOSI_IO0, SEL_QSP_0), 896 PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0),
898 PINMUX_IPSR_DATA(IP2_9_7, A22), 897 PINMUX_IPSR_DATA(IP2_9_7, A22),
899 PINMUX_IPSR_MODSEL_DATA(IP2_9_7, MISO_IO1, SEL_QSP_0), 898 PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0),
900 PINMUX_IPSR_MODSEL_DATA(IP2_9_7, FMCLK_B, SEL_FM_1), 899 PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1),
901 PINMUX_IPSR_MODSEL_DATA(IP2_9_7, TX0, SEL_SCIF0_0), 900 PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0),
902 PINMUX_IPSR_MODSEL_DATA(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0), 901 PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
903 PINMUX_IPSR_DATA(IP2_12_10, A23), 902 PINMUX_IPSR_DATA(IP2_12_10, A23),
904 PINMUX_IPSR_MODSEL_DATA(IP2_12_10, IO2, SEL_QSP_0), 903 PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0),
905 PINMUX_IPSR_MODSEL_DATA(IP2_12_10, BPFCLK_B, SEL_FM_1), 904 PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1),
906 PINMUX_IPSR_MODSEL_DATA(IP2_12_10, RX0, SEL_SCIF0_0), 905 PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
907 PINMUX_IPSR_MODSEL_DATA(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0), 906 PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
908 PINMUX_IPSR_DATA(IP2_15_13, A24), 907 PINMUX_IPSR_DATA(IP2_15_13, A24),
909 PINMUX_IPSR_MODSEL_DATA(IP2_15_13, DREQ2, SEL_LBS_0), 908 PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0),
910 PINMUX_IPSR_MODSEL_DATA(IP2_15_13, IO3, SEL_QSP_0), 909 PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0),
911 PINMUX_IPSR_MODSEL_DATA(IP2_15_13, TX1, SEL_SCIF1_0), 910 PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0),
912 PINMUX_IPSR_MODSEL_DATA(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0), 911 PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
913 PINMUX_IPSR_DATA(IP2_18_16, A25), 912 PINMUX_IPSR_DATA(IP2_18_16, A25),
914 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DACK2, SEL_LBS_0), 913 PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0),
915 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SSL, SEL_QSP_0), 914 PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0),
916 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ1_C, SEL_LBS_2), 915 PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2),
917 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, RX1, SEL_SCIF1_0), 916 PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0),
918 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0), 917 PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
919 PINMUX_IPSR_DATA(IP2_20_19, CS0_N), 918 PINMUX_IPSR_DATA(IP2_20_19, CS0_N),
920 PINMUX_IPSR_MODSEL_DATA(IP2_20_19, ATAG0_N_B, SEL_LBS_1), 919 PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
921 PINMUX_IPSR_MODSEL_DATA(IP2_20_19, SCL1, SEL_IIC1_0), 920 PINMUX_IPSR_MSEL(IP2_20_19, SCL1, SEL_IIC1_0),
922 PINMUX_IPSR_DATA(IP2_22_21, CS1_N_A26), 921 PINMUX_IPSR_DATA(IP2_22_21, CS1_N_A26),
923 PINMUX_IPSR_MODSEL_DATA(IP2_22_21, ATADIR0_N_B, SEL_LBS_1), 922 PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
924 PINMUX_IPSR_MODSEL_DATA(IP2_22_21, SDA1, SEL_IIC1_0), 923 PINMUX_IPSR_MSEL(IP2_22_21, SDA1, SEL_IIC1_0),
925 PINMUX_IPSR_DATA(IP2_24_23, EX_CS1_N), 924 PINMUX_IPSR_DATA(IP2_24_23, EX_CS1_N),
926 PINMUX_IPSR_MODSEL_DATA(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0), 925 PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
927 PINMUX_IPSR_DATA(IP2_26_25, EX_CS2_N), 926 PINMUX_IPSR_DATA(IP2_26_25, EX_CS2_N),
928 PINMUX_IPSR_MODSEL_DATA(IP2_26_25, ATAWR0_N, SEL_LBS_0), 927 PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0),
929 PINMUX_IPSR_MODSEL_DATA(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0), 928 PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
930 PINMUX_IPSR_DATA(IP2_29_27, EX_CS3_N), 929 PINMUX_IPSR_DATA(IP2_29_27, EX_CS3_N),
931 PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATADIR0_N, SEL_LBS_0), 930 PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0),
932 PINMUX_IPSR_MODSEL_DATA(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0), 931 PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
933 PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATAG0_N, SEL_LBS_0), 932 PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0),
934 PINMUX_IPSR_DATA(IP2_29_27, EX_WAIT1), 933 PINMUX_IPSR_DATA(IP2_29_27, EX_WAIT1),
935 934
936 /* IPSR3 */ 935 /* IPSR3 */
937 PINMUX_IPSR_DATA(IP3_2_0, EX_CS4_N), 936 PINMUX_IPSR_DATA(IP3_2_0, EX_CS4_N),
938 PINMUX_IPSR_MODSEL_DATA(IP3_2_0, ATARD0_N, SEL_LBS_0), 937 PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0),
939 PINMUX_IPSR_MODSEL_DATA(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0), 938 PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
940 PINMUX_IPSR_DATA(IP3_2_0, EX_WAIT2), 939 PINMUX_IPSR_DATA(IP3_2_0, EX_WAIT2),
941 PINMUX_IPSR_DATA(IP3_5_3, EX_CS5_N), 940 PINMUX_IPSR_DATA(IP3_5_3, EX_CS5_N),
942 PINMUX_IPSR_DATA(IP3_5_3, ATACS00_N), 941 PINMUX_IPSR_DATA(IP3_5_3, ATACS00_N),
943 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0), 942 PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
944 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, HRX1_B, SEL_HSCIF1_1), 943 PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
945 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1), 944 PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
946 PINMUX_IPSR_DATA(IP3_5_3, PWM1), 945 PINMUX_IPSR_DATA(IP3_5_3, PWM1),
947 PINMUX_IPSR_DATA(IP3_5_3, TPU_TO1), 946 PINMUX_IPSR_DATA(IP3_5_3, TPU_TO1),
948 PINMUX_IPSR_DATA(IP3_8_6, BS_N), 947 PINMUX_IPSR_DATA(IP3_8_6, BS_N),
949 PINMUX_IPSR_DATA(IP3_8_6, ATACS10_N), 948 PINMUX_IPSR_DATA(IP3_8_6, ATACS10_N),
950 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0), 949 PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
951 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, HTX1_B, SEL_HSCIF1_1), 950 PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
952 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1), 951 PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
953 PINMUX_IPSR_DATA(IP3_8_6, PWM2), 952 PINMUX_IPSR_DATA(IP3_8_6, PWM2),
954 PINMUX_IPSR_DATA(IP3_8_6, TPU_TO2), 953 PINMUX_IPSR_DATA(IP3_8_6, TPU_TO2),
955 PINMUX_IPSR_DATA(IP3_11_9, RD_WR_N), 954 PINMUX_IPSR_DATA(IP3_11_9, RD_WR_N),
956 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, HRX2_B, SEL_HSCIF2_1), 955 PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
957 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, FMIN_B, SEL_FM_1), 956 PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1),
958 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1), 957 PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
959 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, DREQ1_D, SEL_LBS_1), 958 PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1),
960 PINMUX_IPSR_DATA(IP3_13_12, WE0_N), 959 PINMUX_IPSR_DATA(IP3_13_12, WE0_N),
961 PINMUX_IPSR_MODSEL_DATA(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1), 960 PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
962 PINMUX_IPSR_MODSEL_DATA(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1), 961 PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
963 PINMUX_IPSR_DATA(IP3_15_14, WE1_N), 962 PINMUX_IPSR_DATA(IP3_15_14, WE1_N),
964 PINMUX_IPSR_MODSEL_DATA(IP3_15_14, ATARD0_N_B, SEL_LBS_1), 963 PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
965 PINMUX_IPSR_MODSEL_DATA(IP3_15_14, HTX2_B, SEL_HSCIF2_1), 964 PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
966 PINMUX_IPSR_MODSEL_DATA(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1), 965 PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
967 PINMUX_IPSR_DATA(IP3_17_16, EX_WAIT0), 966 PINMUX_IPSR_DATA(IP3_17_16, EX_WAIT0),
968 PINMUX_IPSR_MODSEL_DATA(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1), 967 PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
969 PINMUX_IPSR_MODSEL_DATA(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1), 968 PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
970 PINMUX_IPSR_DATA(IP3_19_18, DREQ0), 969 PINMUX_IPSR_DATA(IP3_19_18, DREQ0),
971 PINMUX_IPSR_DATA(IP3_19_18, PWM3), 970 PINMUX_IPSR_DATA(IP3_19_18, PWM3),
972 PINMUX_IPSR_DATA(IP3_19_18, TPU_TO3), 971 PINMUX_IPSR_DATA(IP3_19_18, TPU_TO3),
973 PINMUX_IPSR_DATA(IP3_21_20, DACK0), 972 PINMUX_IPSR_DATA(IP3_21_20, DACK0),
974 PINMUX_IPSR_DATA(IP3_21_20, DRACK0), 973 PINMUX_IPSR_DATA(IP3_21_20, DRACK0),
975 PINMUX_IPSR_MODSEL_DATA(IP3_21_20, REMOCON, SEL_RCN_0), 974 PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0),
976 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SPEEDIN, SEL_RSP_0), 975 PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0),
977 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK0_C, SEL_HSCIF0_2), 976 PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
978 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK2_C, SEL_HSCIF2_2), 977 PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
979 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1), 978 PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
980 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1), 979 PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
981 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, DREQ2_C, SEL_LBS_2), 980 PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2),
982 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2), 981 PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
983 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SSI_SCK0129, SEL_SSI0_0), 982 PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
984 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX0_C, SEL_HSCIF0_2), 983 PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
985 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX2_C, SEL_HSCIF2_2), 984 PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
986 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2), 985 PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
987 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2), 986 PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
988 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SSI_WS0129, SEL_SSI0_0), 987 PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
989 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX0_C, SEL_HSCIF0_2), 988 PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
990 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2), 989 PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
991 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2), 990 PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
992 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2), 991 PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
993 992
994 /* IPSR4 */ 993 /* IPSR4 */
995 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SSI_SDATA0, SEL_SSI0_0), 994 PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
996 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL0_B, SEL_IIC0_1), 995 PINMUX_IPSR_MSEL(IP4_1_0, SCL0_B, SEL_IIC0_1),
997 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL7_B, SEL_IIC7_1), 996 PINMUX_IPSR_MSEL(IP4_1_0, SCL7_B, SEL_IIC7_1),
998 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2), 997 PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
999 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK1, SEL_SSI1_0), 998 PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
1000 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA0_B, SEL_IIC0_1), 999 PINMUX_IPSR_MSEL(IP4_4_2, SDA0_B, SEL_IIC0_1),
1001 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA7_B, SEL_IIC7_1), 1000 PINMUX_IPSR_MSEL(IP4_4_2, SDA7_B, SEL_IIC7_1),
1002 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2), 1001 PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
1003 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, GLO_I0_D, SEL_GPS_3), 1002 PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3),
1004 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SSI_WS1, SEL_SSI1_0), 1003 PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0),
1005 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL1_B, SEL_IIC1_1), 1004 PINMUX_IPSR_MSEL(IP4_7_5, SCL1_B, SEL_IIC1_1),
1006 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL8_B, SEL_IIC8_1), 1005 PINMUX_IPSR_MSEL(IP4_7_5, SCL8_B, SEL_IIC8_1),
1007 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2), 1006 PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
1008 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, GLO_I1_D, SEL_GPS_3), 1007 PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3),
1009 PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SSI_SDATA1, SEL_SSI1_0), 1008 PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
1010 PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA1_B, SEL_IIC1_1), 1009 PINMUX_IPSR_MSEL(IP4_9_8, SDA1_B, SEL_IIC1_1),
1011 PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA8_B, SEL_IIC8_1), 1010 PINMUX_IPSR_MSEL(IP4_9_8, SDA8_B, SEL_IIC8_1),
1012 PINMUX_IPSR_MODSEL_DATA(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2), 1011 PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
1013 PINMUX_IPSR_DATA(IP4_12_10, SSI_SCK2), 1012 PINMUX_IPSR_DATA(IP4_12_10, SSI_SCK2),
1014 PINMUX_IPSR_MODSEL_DATA(IP4_12_10, SCL2, SEL_IIC2_0), 1013 PINMUX_IPSR_MSEL(IP4_12_10, SCL2, SEL_IIC2_0),
1015 PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GPS_CLK_B, SEL_GPS_1), 1014 PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
1016 PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GLO_Q0_D, SEL_GPS_3), 1015 PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
1017 PINMUX_IPSR_DATA(IP4_15_13, SSI_WS2), 1016 PINMUX_IPSR_DATA(IP4_15_13, SSI_WS2),
1018 PINMUX_IPSR_MODSEL_DATA(IP4_15_13, SDA2, SEL_IIC2_0), 1017 PINMUX_IPSR_MSEL(IP4_15_13, SDA2, SEL_IIC2_0),
1019 PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GPS_SIGN_B, SEL_GPS_1), 1018 PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
1020 PINMUX_IPSR_MODSEL_DATA(IP4_15_13, RX2_E, SEL_SCIF2_4), 1019 PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
1021 PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GLO_Q1_D, SEL_GPS_3), 1020 PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
1022 PINMUX_IPSR_DATA(IP4_18_16, SSI_SDATA2), 1021 PINMUX_IPSR_DATA(IP4_18_16, SSI_SDATA2),
1023 PINMUX_IPSR_MODSEL_DATA(IP4_18_16, GPS_MAG_B, SEL_GPS_1), 1022 PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
1024 PINMUX_IPSR_MODSEL_DATA(IP4_18_16, TX2_E, SEL_SCIF2_4), 1023 PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
1025 PINMUX_IPSR_DATA(IP4_19, SSI_SCK34), 1024 PINMUX_IPSR_DATA(IP4_19, SSI_SCK34),
1026 PINMUX_IPSR_DATA(IP4_20, SSI_WS34), 1025 PINMUX_IPSR_DATA(IP4_20, SSI_WS34),
1027 PINMUX_IPSR_DATA(IP4_21, SSI_SDATA3), 1026 PINMUX_IPSR_DATA(IP4_21, SSI_SDATA3),
1028 PINMUX_IPSR_DATA(IP4_23_22, SSI_SCK4), 1027 PINMUX_IPSR_DATA(IP4_23_22, SSI_SCK4),
1029 PINMUX_IPSR_MODSEL_DATA(IP4_23_22, GLO_SS_D, SEL_GPS_3), 1028 PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3),
1030 PINMUX_IPSR_DATA(IP4_25_24, SSI_WS4), 1029 PINMUX_IPSR_DATA(IP4_25_24, SSI_WS4),
1031 PINMUX_IPSR_MODSEL_DATA(IP4_25_24, GLO_RFON_D, SEL_GPS_3), 1030 PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
1032 PINMUX_IPSR_DATA(IP4_27_26, SSI_SDATA4), 1031 PINMUX_IPSR_DATA(IP4_27_26, SSI_SDATA4),
1033 PINMUX_IPSR_MODSEL_DATA(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3), 1032 PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
1034 PINMUX_IPSR_DATA(IP4_30_28, SSI_SCK5), 1033 PINMUX_IPSR_DATA(IP4_30_28, SSI_SCK5),
1035 PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2), 1034 PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
1036 PINMUX_IPSR_MODSEL_DATA(IP4_30_28, TS_SDATA0, SEL_TSIF0_0), 1035 PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
1037 PINMUX_IPSR_MODSEL_DATA(IP4_30_28, GLO_I0, SEL_GPS_0), 1036 PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0),
1038 PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3), 1037 PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
1039 PINMUX_IPSR_DATA(IP4_30_28, VI1_R2_B), 1038 PINMUX_IPSR_DATA(IP4_30_28, VI1_R2_B),
1040 1039
1041 /* IPSR5 */ 1040 /* IPSR5 */
1042 PINMUX_IPSR_DATA(IP5_2_0, SSI_WS5), 1041 PINMUX_IPSR_DATA(IP5_2_0, SSI_WS5),
1043 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2), 1042 PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
1044 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, TS_SCK0, SEL_TSIF0_0), 1043 PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
1045 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, GLO_I1, SEL_GPS_0), 1044 PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0),
1046 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3), 1045 PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
1047 PINMUX_IPSR_DATA(IP5_2_0, VI1_R3_B), 1046 PINMUX_IPSR_DATA(IP5_2_0, VI1_R3_B),
1048 PINMUX_IPSR_DATA(IP5_5_3, SSI_SDATA5), 1047 PINMUX_IPSR_DATA(IP5_5_3, SSI_SDATA5),
1049 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2), 1048 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
1050 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, TS_SDEN0, SEL_TSIF0_0), 1049 PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
1051 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, GLO_Q0, SEL_GPS_0), 1050 PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0),
1052 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3), 1051 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
1053 PINMUX_IPSR_DATA(IP5_5_3, VI1_R4_B), 1052 PINMUX_IPSR_DATA(IP5_5_3, VI1_R4_B),
1054 PINMUX_IPSR_DATA(IP5_8_6, SSI_SCK6), 1053 PINMUX_IPSR_DATA(IP5_8_6, SSI_SCK6),
1055 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2), 1054 PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
1056 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0), 1055 PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
1057 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, GLO_Q1, SEL_GPS_0), 1056 PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0),
1058 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3), 1057 PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
1059 PINMUX_IPSR_DATA(IP5_8_6, VI1_R5_B), 1058 PINMUX_IPSR_DATA(IP5_8_6, VI1_R5_B),
1060 PINMUX_IPSR_DATA(IP5_11_9, SSI_WS6), 1059 PINMUX_IPSR_DATA(IP5_11_9, SSI_WS6),
1061 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, GLO_SCLK, SEL_GPS_0), 1060 PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0),
1062 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3), 1061 PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
1063 PINMUX_IPSR_DATA(IP5_11_9, VI1_R6_B), 1062 PINMUX_IPSR_DATA(IP5_11_9, VI1_R6_B),
1064 PINMUX_IPSR_DATA(IP5_14_12, SSI_SDATA6), 1063 PINMUX_IPSR_DATA(IP5_14_12, SSI_SDATA6),
1065 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1), 1064 PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
1066 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, GLO_SDATA, SEL_GPS_0), 1065 PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0),
1067 PINMUX_IPSR_DATA(IP5_14_12, VI1_R7_B), 1066 PINMUX_IPSR_DATA(IP5_14_12, VI1_R7_B),
1068 PINMUX_IPSR_MODSEL_DATA(IP5_16_15, SSI_SCK78, SEL_SSI7_0), 1067 PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
1069 PINMUX_IPSR_MODSEL_DATA(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1), 1068 PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
1070 PINMUX_IPSR_MODSEL_DATA(IP5_16_15, GLO_SS, SEL_GPS_0), 1069 PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0),
1071 PINMUX_IPSR_MODSEL_DATA(IP5_19_17, SSI_WS78, SEL_SSI7_0), 1070 PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0),
1072 PINMUX_IPSR_MODSEL_DATA(IP5_19_17, TX0_D, SEL_SCIF0_3), 1071 PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3),
1073 PINMUX_IPSR_MODSEL_DATA(IP5_19_17, STP_ISD_0_B, SEL_SSP_1), 1072 PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
1074 PINMUX_IPSR_MODSEL_DATA(IP5_19_17, GLO_RFON, SEL_GPS_0), 1073 PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0),
1075 PINMUX_IPSR_MODSEL_DATA(IP5_21_20, SSI_SDATA7, SEL_SSI7_0), 1074 PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
1076 PINMUX_IPSR_MODSEL_DATA(IP5_21_20, RX0_D, SEL_SCIF0_3), 1075 PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3),
1077 PINMUX_IPSR_MODSEL_DATA(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1), 1076 PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
1078 PINMUX_IPSR_MODSEL_DATA(IP5_23_22, SSI_SDATA8, SEL_SSI8_0), 1077 PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
1079 PINMUX_IPSR_MODSEL_DATA(IP5_23_22, TX1_D, SEL_SCIF1_3), 1078 PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3),
1080 PINMUX_IPSR_MODSEL_DATA(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1), 1079 PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
1081 PINMUX_IPSR_MODSEL_DATA(IP5_25_24, SSI_SCK9, SEL_SSI9_0), 1080 PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
1082 PINMUX_IPSR_MODSEL_DATA(IP5_25_24, RX1_D, SEL_SCIF1_3), 1081 PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3),
1083 PINMUX_IPSR_MODSEL_DATA(IP5_25_24, GLO_SCLK_D, SEL_GPS_3), 1082 PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
1084 PINMUX_IPSR_MODSEL_DATA(IP5_28_26, SSI_WS9, SEL_SSI9_0), 1083 PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0),
1085 PINMUX_IPSR_MODSEL_DATA(IP5_28_26, TX3_D, SEL_SCIF3_3), 1084 PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3),
1086 PINMUX_IPSR_MODSEL_DATA(IP5_28_26, CAN0_TX_D, SEL_CAN0_3), 1085 PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
1087 PINMUX_IPSR_MODSEL_DATA(IP5_28_26, GLO_SDATA_D, SEL_GPS_3), 1086 PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
1088 PINMUX_IPSR_MODSEL_DATA(IP5_31_29, SSI_SDATA9, SEL_SSI9_0), 1087 PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
1089 PINMUX_IPSR_MODSEL_DATA(IP5_31_29, RX3_D, SEL_SCIF3_3), 1088 PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3),
1090 PINMUX_IPSR_MODSEL_DATA(IP5_31_29, CAN0_RX_D, SEL_CAN0_3), 1089 PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
1091 1090
1092 /* IPSR6 */ 1091 /* IPSR6 */
1093 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, AUDIO_CLKB, SEL_ADG_0), 1092 PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
1094 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1), 1093 PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
1095 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1), 1094 PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
1096 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK, SEL_SCIF_0), 1095 PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
1097 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, BPFCLK_E, SEL_FM_4), 1096 PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
1098 PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC), 1097 PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC),
1099 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2), 1098 PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
1100 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1), 1099 PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
1101 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, RX2, SEL_SCIF2_0), 1100 PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0),
1102 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0), 1101 PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1103 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, FMIN_E, SEL_FM_4), 1102 PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
1104 PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT), 1103 PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT),
1105 PINMUX_IPSR_MODSEL_DATA(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1), 1104 PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
1106 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TX2, SEL_SCIF2_0), 1105 PINMUX_IPSR_MSEL(IP6_5_3, TX2, SEL_SCIF2_0),
1107 PINMUX_IPSR_MODSEL_DATA(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0), 1106 PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
1108 PINMUX_IPSR_DATA(IP6_9_8, IRQ0), 1107 PINMUX_IPSR_DATA(IP6_9_8, IRQ0),
1109 PINMUX_IPSR_MODSEL_DATA(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3), 1108 PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
1110 PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N), 1109 PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N),
1111 PINMUX_IPSR_DATA(IP6_11_10, IRQ1), 1110 PINMUX_IPSR_DATA(IP6_11_10, IRQ1),
1112 PINMUX_IPSR_MODSEL_DATA(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2), 1111 PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
1113 PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N), 1112 PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N),
1114 PINMUX_IPSR_DATA(IP6_13_12, IRQ2), 1113 PINMUX_IPSR_DATA(IP6_13_12, IRQ2),
1115 PINMUX_IPSR_MODSEL_DATA(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3), 1114 PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
1116 PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N), 1115 PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N),
1117 PINMUX_IPSR_DATA(IP6_15_14, IRQ3), 1116 PINMUX_IPSR_DATA(IP6_15_14, IRQ3),
1118 PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCL4_C, SEL_IIC4_2), 1117 PINMUX_IPSR_MSEL(IP6_15_14, SCL4_C, SEL_IIC4_2),
1119 PINMUX_IPSR_MODSEL_DATA(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4), 1118 PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
1120 PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N), 1119 PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N),
1121 PINMUX_IPSR_DATA(IP6_18_16, IRQ4), 1120 PINMUX_IPSR_DATA(IP6_18_16, IRQ4),
1122 PINMUX_IPSR_MODSEL_DATA(IP6_18_16, HRX1_C, SEL_HSCIF1_2), 1121 PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
1123 PINMUX_IPSR_MODSEL_DATA(IP6_18_16, SDA4_C, SEL_IIC4_2), 1122 PINMUX_IPSR_MSEL(IP6_18_16, SDA4_C, SEL_IIC4_2),
1124 PINMUX_IPSR_MODSEL_DATA(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4), 1123 PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
1125 PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N), 1124 PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N),
1126 PINMUX_IPSR_DATA(IP6_20_19, IRQ5), 1125 PINMUX_IPSR_DATA(IP6_20_19, IRQ5),
1127 PINMUX_IPSR_MODSEL_DATA(IP6_20_19, HTX1_C, SEL_HSCIF1_2), 1126 PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
1128 PINMUX_IPSR_MODSEL_DATA(IP6_20_19, SCL1_E, SEL_IIC1_4), 1127 PINMUX_IPSR_MSEL(IP6_20_19, SCL1_E, SEL_IIC1_4),
1129 PINMUX_IPSR_MODSEL_DATA(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4), 1128 PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
1130 PINMUX_IPSR_DATA(IP6_23_21, IRQ6), 1129 PINMUX_IPSR_DATA(IP6_23_21, IRQ6),
1131 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HSCK1_C, SEL_HSCIF1_2), 1130 PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
1132 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1), 1131 PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
1133 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, SDA1_E, SEL_IIC1_4), 1132 PINMUX_IPSR_MSEL(IP6_23_21, SDA1_E, SEL_IIC1_4),
1134 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4), 1133 PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
1135 PINMUX_IPSR_DATA(IP6_26_24, IRQ7), 1134 PINMUX_IPSR_DATA(IP6_26_24, IRQ7),
1136 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2), 1135 PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
1137 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1), 1136 PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
1138 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_C, SEL_GPS_2), 1137 PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
1139 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_D, SEL_GPS_3), 1138 PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
1140 PINMUX_IPSR_DATA(IP6_29_27, IRQ8), 1139 PINMUX_IPSR_DATA(IP6_29_27, IRQ8),
1141 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2), 1140 PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
1142 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1), 1141 PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
1143 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_C, SEL_GPS_2), 1142 PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
1144 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_D, SEL_GPS_3), 1143 PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
1145 1144
1146 /* IPSR7 */ 1145 /* IPSR7 */
1147 PINMUX_IPSR_DATA(IP7_2_0, IRQ9), 1146 PINMUX_IPSR_DATA(IP7_2_0, IRQ9),
1148 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1), 1147 PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
1149 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3), 1148 PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
1150 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_C, SEL_GPS_2), 1149 PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
1151 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1), 1150 PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
1152 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_D, SEL_GPS_3), 1151 PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
1153 PINMUX_IPSR_DATA(IP7_5_3, DU1_DR0), 1152 PINMUX_IPSR_DATA(IP7_5_3, DU1_DR0),
1154 PINMUX_IPSR_DATA(IP7_5_3, LCDOUT0), 1153 PINMUX_IPSR_DATA(IP7_5_3, LCDOUT0),
1155 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, VI1_DATA0_B, SEL_VI1_1), 1154 PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
1156 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, TX0_B, SEL_SCIF0_1), 1155 PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1),
1157 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1), 1156 PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
1158 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1), 1157 PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
1159 PINMUX_IPSR_DATA(IP7_8_6, DU1_DR1), 1158 PINMUX_IPSR_DATA(IP7_8_6, DU1_DR1),
1160 PINMUX_IPSR_DATA(IP7_8_6, LCDOUT1), 1159 PINMUX_IPSR_DATA(IP7_8_6, LCDOUT1),
1161 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, VI1_DATA1_B, SEL_VI1_1), 1160 PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
1162 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RX0_B, SEL_SCIF0_1), 1161 PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1),
1163 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1), 1162 PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
1164 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1), 1163 PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
1165 PINMUX_IPSR_DATA(IP7_10_9, DU1_DR2), 1164 PINMUX_IPSR_DATA(IP7_10_9, DU1_DR2),
1166 PINMUX_IPSR_DATA(IP7_10_9, LCDOUT2), 1165 PINMUX_IPSR_DATA(IP7_10_9, LCDOUT2),
1167 PINMUX_IPSR_MODSEL_DATA(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1), 1166 PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
1168 PINMUX_IPSR_DATA(IP7_12_11, DU1_DR3), 1167 PINMUX_IPSR_DATA(IP7_12_11, DU1_DR3),
1169 PINMUX_IPSR_DATA(IP7_12_11, LCDOUT3), 1168 PINMUX_IPSR_DATA(IP7_12_11, LCDOUT3),
1170 PINMUX_IPSR_MODSEL_DATA(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1), 1169 PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
1171 PINMUX_IPSR_DATA(IP7_14_13, DU1_DR4), 1170 PINMUX_IPSR_DATA(IP7_14_13, DU1_DR4),
1172 PINMUX_IPSR_DATA(IP7_14_13, LCDOUT4), 1171 PINMUX_IPSR_DATA(IP7_14_13, LCDOUT4),
1173 PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1), 1172 PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
1174 PINMUX_IPSR_DATA(IP7_16_15, DU1_DR5), 1173 PINMUX_IPSR_DATA(IP7_16_15, DU1_DR5),
1175 PINMUX_IPSR_DATA(IP7_16_15, LCDOUT5), 1174 PINMUX_IPSR_DATA(IP7_16_15, LCDOUT5),
1176 PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1), 1175 PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
1177 PINMUX_IPSR_DATA(IP7_18_17, DU1_DR6), 1176 PINMUX_IPSR_DATA(IP7_18_17, DU1_DR6),
1178 PINMUX_IPSR_DATA(IP7_18_17, LCDOUT6), 1177 PINMUX_IPSR_DATA(IP7_18_17, LCDOUT6),
1179 PINMUX_IPSR_MODSEL_DATA(IP7_18_17, SSI_WS1_B, SEL_SSI1_1), 1178 PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
1180 PINMUX_IPSR_DATA(IP7_20_19, DU1_DR7), 1179 PINMUX_IPSR_DATA(IP7_20_19, DU1_DR7),
1181 PINMUX_IPSR_DATA(IP7_20_19, LCDOUT7), 1180 PINMUX_IPSR_DATA(IP7_20_19, LCDOUT7),
1182 PINMUX_IPSR_MODSEL_DATA(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1), 1181 PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
1183 PINMUX_IPSR_DATA(IP7_23_21, DU1_DG0), 1182 PINMUX_IPSR_DATA(IP7_23_21, DU1_DG0),
1184 PINMUX_IPSR_DATA(IP7_23_21, LCDOUT8), 1183 PINMUX_IPSR_DATA(IP7_23_21, LCDOUT8),
1185 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, VI1_DATA2_B, SEL_VI1_1), 1184 PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
1186 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TX1_B, SEL_SCIF1_1), 1185 PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1),
1187 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1), 1186 PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
1188 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1), 1187 PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
1189 PINMUX_IPSR_DATA(IP7_26_24, DU1_DG1), 1188 PINMUX_IPSR_DATA(IP7_26_24, DU1_DG1),
1190 PINMUX_IPSR_DATA(IP7_26_24, LCDOUT9), 1189 PINMUX_IPSR_DATA(IP7_26_24, LCDOUT9),
1191 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, VI1_DATA3_B, SEL_VI1_1), 1190 PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
1192 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RX1_B, SEL_SCIF1_1), 1191 PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1),
1193 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1), 1192 PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
1194 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1), 1193 PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
1195 PINMUX_IPSR_DATA(IP7_29_27, DU1_DG2), 1194 PINMUX_IPSR_DATA(IP7_29_27, DU1_DG2),
1196 PINMUX_IPSR_DATA(IP7_29_27, LCDOUT10), 1195 PINMUX_IPSR_DATA(IP7_29_27, LCDOUT10),
1197 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, VI1_DATA4_B, SEL_VI1_1), 1196 PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
1198 PINMUX_IPSR_DATA(IP7_29_27, SCIF1_SCK_B), 1197 PINMUX_IPSR_DATA(IP7_29_27, SCIF1_SCK_B),
1199 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0), 1198 PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
1200 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1), 1199 PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
1201 1200
1202 /* IPSR8 */ 1201 /* IPSR8 */
1203 PINMUX_IPSR_DATA(IP8_2_0, DU1_DG3), 1202 PINMUX_IPSR_DATA(IP8_2_0, DU1_DG3),
1204 PINMUX_IPSR_DATA(IP8_2_0, LCDOUT11), 1203 PINMUX_IPSR_DATA(IP8_2_0, LCDOUT11),
1205 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, VI1_DATA5_B, SEL_VI1_1), 1204 PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
1206 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_WS78_B, SEL_SSI7_1), 1205 PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
1207 PINMUX_IPSR_DATA(IP8_5_3, DU1_DG4), 1206 PINMUX_IPSR_DATA(IP8_5_3, DU1_DG4),
1208 PINMUX_IPSR_DATA(IP8_5_3, LCDOUT12), 1207 PINMUX_IPSR_DATA(IP8_5_3, LCDOUT12),
1209 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, VI1_DATA6_B, SEL_VI1_1), 1208 PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
1210 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HRX0_B, SEL_HSCIF0_1), 1209 PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
1211 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1), 1210 PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
1212 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1), 1211 PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
1213 PINMUX_IPSR_DATA(IP8_8_6, DU1_DG5), 1212 PINMUX_IPSR_DATA(IP8_8_6, DU1_DG5),
1214 PINMUX_IPSR_DATA(IP8_8_6, LCDOUT13), 1213 PINMUX_IPSR_DATA(IP8_8_6, LCDOUT13),
1215 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, VI1_DATA7_B, SEL_VI1_1), 1214 PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
1216 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1), 1215 PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
1217 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1), 1216 PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
1218 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1), 1217 PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
1219 PINMUX_IPSR_DATA(IP8_11_9, DU1_DG6), 1218 PINMUX_IPSR_DATA(IP8_11_9, DU1_DG6),
1220 PINMUX_IPSR_DATA(IP8_11_9, LCDOUT14), 1219 PINMUX_IPSR_DATA(IP8_11_9, LCDOUT14),
1221 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1), 1220 PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
1222 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1), 1221 PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1223 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1), 1222 PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
1224 PINMUX_IPSR_DATA(IP8_14_12, DU1_DG7), 1223 PINMUX_IPSR_DATA(IP8_14_12, DU1_DG7),
1225 PINMUX_IPSR_DATA(IP8_14_12, LCDOUT15), 1224 PINMUX_IPSR_DATA(IP8_14_12, LCDOUT15),
1226 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, HTX0_B, SEL_HSCIF0_1), 1225 PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
1227 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1), 1226 PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1228 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_WS9_B, SEL_SSI9_1), 1227 PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
1229 PINMUX_IPSR_DATA(IP8_17_15, DU1_DB0), 1228 PINMUX_IPSR_DATA(IP8_17_15, DU1_DB0),
1230 PINMUX_IPSR_DATA(IP8_17_15, LCDOUT16), 1229 PINMUX_IPSR_DATA(IP8_17_15, LCDOUT16),
1231 PINMUX_IPSR_MODSEL_DATA(IP8_17_15, VI1_CLK_B, SEL_VI1_1), 1230 PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
1232 PINMUX_IPSR_MODSEL_DATA(IP8_17_15, TX2_B, SEL_SCIF2_1), 1231 PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1),
1233 PINMUX_IPSR_MODSEL_DATA(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1), 1232 PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
1234 PINMUX_IPSR_MODSEL_DATA(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1), 1233 PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
1235 PINMUX_IPSR_DATA(IP8_20_18, DU1_DB1), 1234 PINMUX_IPSR_DATA(IP8_20_18, DU1_DB1),
1236 PINMUX_IPSR_DATA(IP8_20_18, LCDOUT17), 1235 PINMUX_IPSR_DATA(IP8_20_18, LCDOUT17),
1237 PINMUX_IPSR_MODSEL_DATA(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1), 1236 PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
1238 PINMUX_IPSR_MODSEL_DATA(IP8_20_18, RX2_B, SEL_SCIF2_1), 1237 PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1),
1239 PINMUX_IPSR_MODSEL_DATA(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1), 1238 PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
1240 PINMUX_IPSR_MODSEL_DATA(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1), 1239 PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
1241 PINMUX_IPSR_DATA(IP8_23_21, DU1_DB2), 1240 PINMUX_IPSR_DATA(IP8_23_21, DU1_DB2),
1242 PINMUX_IPSR_DATA(IP8_23_21, LCDOUT18), 1241 PINMUX_IPSR_DATA(IP8_23_21, LCDOUT18),
1243 PINMUX_IPSR_MODSEL_DATA(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1), 1242 PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
1244 PINMUX_IPSR_DATA(IP8_23_21, SCIF2_SCK_B), 1243 PINMUX_IPSR_DATA(IP8_23_21, SCIF2_SCK_B),
1245 PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1), 1244 PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
1246 PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1), 1245 PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
1247 PINMUX_IPSR_DATA(IP8_25_24, DU1_DB3), 1246 PINMUX_IPSR_DATA(IP8_25_24, DU1_DB3),
1248 PINMUX_IPSR_DATA(IP8_25_24, LCDOUT19), 1247 PINMUX_IPSR_DATA(IP8_25_24, LCDOUT19),
1249 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1), 1248 PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
1250 PINMUX_IPSR_DATA(IP8_27_26, DU1_DB4), 1249 PINMUX_IPSR_DATA(IP8_27_26, DU1_DB4),
1251 PINMUX_IPSR_DATA(IP8_27_26, LCDOUT20), 1250 PINMUX_IPSR_DATA(IP8_27_26, LCDOUT20),
1252 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, VI1_FIELD_B, SEL_VI1_1), 1251 PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
1253 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, CAN1_RX, SEL_CAN1_0), 1252 PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0),
1254 PINMUX_IPSR_DATA(IP8_30_28, DU1_DB5), 1253 PINMUX_IPSR_DATA(IP8_30_28, DU1_DB5),
1255 PINMUX_IPSR_DATA(IP8_30_28, LCDOUT21), 1254 PINMUX_IPSR_DATA(IP8_30_28, LCDOUT21),
1256 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, TX3, SEL_SCIF3_0), 1255 PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0),
1257 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0), 1256 PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
1258 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, CAN1_TX, SEL_CAN1_0), 1257 PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0),
1259 1258
1260 /* IPSR9 */ 1259 /* IPSR9 */
1261 PINMUX_IPSR_DATA(IP9_2_0, DU1_DB6), 1260 PINMUX_IPSR_DATA(IP9_2_0, DU1_DB6),
1262 PINMUX_IPSR_DATA(IP9_2_0, LCDOUT22), 1261 PINMUX_IPSR_DATA(IP9_2_0, LCDOUT22),
1263 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCL3_C, SEL_IIC3_2), 1262 PINMUX_IPSR_MSEL(IP9_2_0, SCL3_C, SEL_IIC3_2),
1264 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RX3, SEL_SCIF3_0), 1263 PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0),
1265 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0), 1264 PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1266 PINMUX_IPSR_DATA(IP9_5_3, DU1_DB7), 1265 PINMUX_IPSR_DATA(IP9_5_3, DU1_DB7),
1267 PINMUX_IPSR_DATA(IP9_5_3, LCDOUT23), 1266 PINMUX_IPSR_DATA(IP9_5_3, LCDOUT23),
1268 PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SDA3_C, SEL_IIC3_2), 1267 PINMUX_IPSR_MSEL(IP9_5_3, SDA3_C, SEL_IIC3_2),
1269 PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0), 1268 PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
1270 PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0), 1269 PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
1271 PINMUX_IPSR_MODSEL_DATA(IP9_6, DU1_DOTCLKIN, SEL_DIS_0), 1270 PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
1272 PINMUX_IPSR_DATA(IP9_6, QSTVA_QVS), 1271 PINMUX_IPSR_DATA(IP9_6, QSTVA_QVS),
1273 PINMUX_IPSR_DATA(IP9_7, DU1_DOTCLKOUT0), 1272 PINMUX_IPSR_DATA(IP9_7, DU1_DOTCLKOUT0),
1274 PINMUX_IPSR_DATA(IP9_7, QCLK), 1273 PINMUX_IPSR_DATA(IP9_7, QCLK),
1275 PINMUX_IPSR_DATA(IP9_10_8, DU1_DOTCLKOUT1), 1274 PINMUX_IPSR_DATA(IP9_10_8, DU1_DOTCLKOUT1),
1276 PINMUX_IPSR_DATA(IP9_10_8, QSTVB_QVE), 1275 PINMUX_IPSR_DATA(IP9_10_8, QSTVB_QVE),
1277 PINMUX_IPSR_MODSEL_DATA(IP9_10_8, CAN0_TX, SEL_CAN0_0), 1276 PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0),
1278 PINMUX_IPSR_MODSEL_DATA(IP9_10_8, TX3_B, SEL_SCIF3_1), 1277 PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1),
1279 PINMUX_IPSR_MODSEL_DATA(IP9_10_8, SCL2_B, SEL_IIC2_1), 1278 PINMUX_IPSR_MSEL(IP9_10_8, SCL2_B, SEL_IIC2_1),
1280 PINMUX_IPSR_DATA(IP9_10_8, PWM4), 1279 PINMUX_IPSR_DATA(IP9_10_8, PWM4),
1281 PINMUX_IPSR_DATA(IP9_11, DU1_EXHSYNC_DU1_HSYNC), 1280 PINMUX_IPSR_DATA(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
1282 PINMUX_IPSR_DATA(IP9_11, QSTH_QHS), 1281 PINMUX_IPSR_DATA(IP9_11, QSTH_QHS),
@@ -1284,280 +1283,280 @@ static const u16 pinmux_data[] = {
1284 PINMUX_IPSR_DATA(IP9_12, QSTB_QHE), 1283 PINMUX_IPSR_DATA(IP9_12, QSTB_QHE),
1285 PINMUX_IPSR_DATA(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE), 1284 PINMUX_IPSR_DATA(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1286 PINMUX_IPSR_DATA(IP9_15_13, QCPV_QDE), 1285 PINMUX_IPSR_DATA(IP9_15_13, QCPV_QDE),
1287 PINMUX_IPSR_MODSEL_DATA(IP9_15_13, CAN0_RX, SEL_CAN0_0), 1286 PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0),
1288 PINMUX_IPSR_MODSEL_DATA(IP9_15_13, RX3_B, SEL_SCIF3_1), 1287 PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1),
1289 PINMUX_IPSR_MODSEL_DATA(IP9_15_13, SDA2_B, SEL_IIC2_1), 1288 PINMUX_IPSR_MSEL(IP9_15_13, SDA2_B, SEL_IIC2_1),
1290 PINMUX_IPSR_DATA(IP9_16, DU1_DISP), 1289 PINMUX_IPSR_DATA(IP9_16, DU1_DISP),
1291 PINMUX_IPSR_DATA(IP9_16, QPOLA), 1290 PINMUX_IPSR_DATA(IP9_16, QPOLA),
1292 PINMUX_IPSR_DATA(IP9_18_17, DU1_CDE), 1291 PINMUX_IPSR_DATA(IP9_18_17, DU1_CDE),
1293 PINMUX_IPSR_DATA(IP9_18_17, QPOLB), 1292 PINMUX_IPSR_DATA(IP9_18_17, QPOLB),
1294 PINMUX_IPSR_DATA(IP9_18_17, PWM4_B), 1293 PINMUX_IPSR_DATA(IP9_18_17, PWM4_B),
1295 PINMUX_IPSR_DATA(IP9_20_19, VI0_CLKENB), 1294 PINMUX_IPSR_DATA(IP9_20_19, VI0_CLKENB),
1296 PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TX4, SEL_SCIF4_0), 1295 PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0),
1297 PINMUX_IPSR_MODSEL_DATA(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0), 1296 PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
1298 PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3), 1297 PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
1299 PINMUX_IPSR_DATA(IP9_22_21, VI0_FIELD), 1298 PINMUX_IPSR_DATA(IP9_22_21, VI0_FIELD),
1300 PINMUX_IPSR_MODSEL_DATA(IP9_22_21, RX4, SEL_SCIF4_0), 1299 PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0),
1301 PINMUX_IPSR_MODSEL_DATA(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0), 1300 PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
1302 PINMUX_IPSR_MODSEL_DATA(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3), 1301 PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
1303 PINMUX_IPSR_DATA(IP9_24_23, VI0_HSYNC_N), 1302 PINMUX_IPSR_DATA(IP9_24_23, VI0_HSYNC_N),
1304 PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TX5, SEL_SCIF5_0), 1303 PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0),
1305 PINMUX_IPSR_MODSEL_DATA(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0), 1304 PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
1306 PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3), 1305 PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
1307 PINMUX_IPSR_DATA(IP9_26_25, VI0_VSYNC_N), 1306 PINMUX_IPSR_DATA(IP9_26_25, VI0_VSYNC_N),
1308 PINMUX_IPSR_MODSEL_DATA(IP9_26_25, RX5, SEL_SCIF5_0), 1307 PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0),
1309 PINMUX_IPSR_MODSEL_DATA(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0), 1308 PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
1310 PINMUX_IPSR_MODSEL_DATA(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3), 1309 PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
1311 PINMUX_IPSR_DATA(IP9_28_27, VI0_DATA3_VI0_B3), 1310 PINMUX_IPSR_DATA(IP9_28_27, VI0_DATA3_VI0_B3),
1312 PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1), 1311 PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
1313 PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1), 1312 PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
1314 PINMUX_IPSR_DATA(IP9_31_29, VI0_G0), 1313 PINMUX_IPSR_DATA(IP9_31_29, VI0_G0),
1315 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL8, SEL_IIC8_0), 1314 PINMUX_IPSR_MSEL(IP9_31_29, SCL8, SEL_IIC8_0),
1316 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2), 1315 PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
1317 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL4, SEL_IIC4_0), 1316 PINMUX_IPSR_MSEL(IP9_31_29, SCL4, SEL_IIC4_0),
1318 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, HCTS2_N, SEL_HSCIF2_0), 1317 PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
1319 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0), 1318 PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
1320 PINMUX_IPSR_DATA(IP9_31_29, ATAWR1_N), 1319 PINMUX_IPSR_DATA(IP9_31_29, ATAWR1_N),
1321 1320
1322 /* IPSR10 */ 1321 /* IPSR10 */
1323 PINMUX_IPSR_DATA(IP10_2_0, VI0_G1), 1322 PINMUX_IPSR_DATA(IP10_2_0, VI0_G1),
1324 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA8, SEL_IIC8_0), 1323 PINMUX_IPSR_MSEL(IP10_2_0, SDA8, SEL_IIC8_0),
1325 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2), 1324 PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
1326 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA4, SEL_IIC4_0), 1325 PINMUX_IPSR_MSEL(IP10_2_0, SDA4, SEL_IIC4_0),
1327 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, HRTS2_N, SEL_HSCIF2_0), 1326 PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
1328 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0), 1327 PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
1329 PINMUX_IPSR_DATA(IP10_2_0, ATADIR1_N), 1328 PINMUX_IPSR_DATA(IP10_2_0, ATADIR1_N),
1330 PINMUX_IPSR_DATA(IP10_5_3, VI0_G2), 1329 PINMUX_IPSR_DATA(IP10_5_3, VI0_G2),
1331 PINMUX_IPSR_DATA(IP10_5_3, VI2_HSYNC_N), 1330 PINMUX_IPSR_DATA(IP10_5_3, VI2_HSYNC_N),
1332 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, STP_ISD_0_C, SEL_SSP_2), 1331 PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
1333 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCL3_B, SEL_IIC3_1), 1332 PINMUX_IPSR_MSEL(IP10_5_3, SCL3_B, SEL_IIC3_1),
1334 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, HSCK2, SEL_HSCIF2_0), 1333 PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0),
1335 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0), 1334 PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
1336 PINMUX_IPSR_DATA(IP10_5_3, ATARD1_N), 1335 PINMUX_IPSR_DATA(IP10_5_3, ATARD1_N),
1337 PINMUX_IPSR_DATA(IP10_8_6, VI0_G3), 1336 PINMUX_IPSR_DATA(IP10_8_6, VI0_G3),
1338 PINMUX_IPSR_DATA(IP10_8_6, VI2_VSYNC_N), 1337 PINMUX_IPSR_DATA(IP10_8_6, VI2_VSYNC_N),
1339 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2), 1338 PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
1340 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SDA3_B, SEL_IIC3_1), 1339 PINMUX_IPSR_MSEL(IP10_8_6, SDA3_B, SEL_IIC3_1),
1341 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, HRX2, SEL_HSCIF2_0), 1340 PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0),
1342 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0), 1341 PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
1343 PINMUX_IPSR_DATA(IP10_8_6, ATACS01_N), 1342 PINMUX_IPSR_DATA(IP10_8_6, ATACS01_N),
1344 PINMUX_IPSR_DATA(IP10_11_9, VI0_G4), 1343 PINMUX_IPSR_DATA(IP10_11_9, VI0_G4),
1345 PINMUX_IPSR_DATA(IP10_11_9, VI2_CLKENB), 1344 PINMUX_IPSR_DATA(IP10_11_9, VI2_CLKENB),
1346 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2), 1345 PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
1347 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, HTX2, SEL_HSCIF2_0), 1346 PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0),
1348 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0), 1347 PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
1349 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3), 1348 PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
1350 PINMUX_IPSR_DATA(IP10_14_12, VI0_G5), 1349 PINMUX_IPSR_DATA(IP10_14_12, VI0_G5),
1351 PINMUX_IPSR_DATA(IP10_14_12, VI2_FIELD), 1350 PINMUX_IPSR_DATA(IP10_14_12, VI2_FIELD),
1352 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2), 1351 PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
1353 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, FMCLK_D, SEL_FM_3), 1352 PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3),
1354 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, CAN0_TX_E, SEL_CAN0_4), 1353 PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
1355 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HTX1_D, SEL_HSCIF1_3), 1354 PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
1356 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3), 1355 PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
1357 PINMUX_IPSR_DATA(IP10_16_15, VI0_G6), 1356 PINMUX_IPSR_DATA(IP10_16_15, VI0_G6),
1358 PINMUX_IPSR_DATA(IP10_16_15, VI2_CLK), 1357 PINMUX_IPSR_DATA(IP10_16_15, VI2_CLK),
1359 PINMUX_IPSR_MODSEL_DATA(IP10_16_15, BPFCLK_D, SEL_FM_3), 1358 PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3),
1360 PINMUX_IPSR_DATA(IP10_18_17, VI0_G7), 1359 PINMUX_IPSR_DATA(IP10_18_17, VI0_G7),
1361 PINMUX_IPSR_DATA(IP10_18_17, VI2_DATA0), 1360 PINMUX_IPSR_DATA(IP10_18_17, VI2_DATA0),
1362 PINMUX_IPSR_MODSEL_DATA(IP10_18_17, FMIN_D, SEL_FM_3), 1361 PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3),
1363 PINMUX_IPSR_DATA(IP10_21_19, VI0_R0), 1362 PINMUX_IPSR_DATA(IP10_21_19, VI0_R0),
1364 PINMUX_IPSR_DATA(IP10_21_19, VI2_DATA1), 1363 PINMUX_IPSR_DATA(IP10_21_19, VI2_DATA1),
1365 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, GLO_I0_B, SEL_GPS_1), 1364 PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1),
1366 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2), 1365 PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
1367 PINMUX_IPSR_DATA(IP10_21_19, ATACS11_N), 1366 PINMUX_IPSR_DATA(IP10_21_19, ATACS11_N),
1368 PINMUX_IPSR_DATA(IP10_24_22, VI0_R1), 1367 PINMUX_IPSR_DATA(IP10_24_22, VI0_R1),
1369 PINMUX_IPSR_DATA(IP10_24_22, VI2_DATA2), 1368 PINMUX_IPSR_DATA(IP10_24_22, VI2_DATA2),
1370 PINMUX_IPSR_MODSEL_DATA(IP10_24_22, GLO_I1_B, SEL_GPS_1), 1369 PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1),
1371 PINMUX_IPSR_MODSEL_DATA(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2), 1370 PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
1372 PINMUX_IPSR_DATA(IP10_24_22, ATAG1_N), 1371 PINMUX_IPSR_DATA(IP10_24_22, ATAG1_N),
1373 PINMUX_IPSR_DATA(IP10_26_25, VI0_R2), 1372 PINMUX_IPSR_DATA(IP10_26_25, VI0_R2),
1374 PINMUX_IPSR_DATA(IP10_26_25, VI2_DATA3), 1373 PINMUX_IPSR_DATA(IP10_26_25, VI2_DATA3),
1375 PINMUX_IPSR_MODSEL_DATA(IP10_26_25, GLO_Q0_B, SEL_GPS_1), 1374 PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
1376 PINMUX_IPSR_MODSEL_DATA(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2), 1375 PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
1377 PINMUX_IPSR_DATA(IP10_28_27, VI0_R3), 1376 PINMUX_IPSR_DATA(IP10_28_27, VI0_R3),
1378 PINMUX_IPSR_DATA(IP10_28_27, VI2_DATA4), 1377 PINMUX_IPSR_DATA(IP10_28_27, VI2_DATA4),
1379 PINMUX_IPSR_MODSEL_DATA(IP10_28_27, GLO_Q1_B, SEL_GPS_1), 1378 PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
1380 PINMUX_IPSR_MODSEL_DATA(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2), 1379 PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
1381 PINMUX_IPSR_DATA(IP10_31_29, VI0_R4), 1380 PINMUX_IPSR_DATA(IP10_31_29, VI0_R4),
1382 PINMUX_IPSR_DATA(IP10_31_29, VI2_DATA5), 1381 PINMUX_IPSR_DATA(IP10_31_29, VI2_DATA5),
1383 PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GLO_SCLK_B, SEL_GPS_1), 1382 PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
1384 PINMUX_IPSR_MODSEL_DATA(IP10_31_29, TX0_C, SEL_SCIF0_2), 1383 PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2),
1385 PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL1_D, SEL_IIC1_3), 1384 PINMUX_IPSR_MSEL(IP10_31_29, SCL1_D, SEL_IIC1_3),
1386 1385
1387 /* IPSR11 */ 1386 /* IPSR11 */
1388 PINMUX_IPSR_DATA(IP11_2_0, VI0_R5), 1387 PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
1389 PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6), 1388 PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
1390 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1), 1389 PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
1391 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2), 1390 PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2),
1392 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3), 1391 PINMUX_IPSR_MSEL(IP11_2_0, SDA1_D, SEL_IIC1_3),
1393 PINMUX_IPSR_DATA(IP11_5_3, VI0_R6), 1392 PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
1394 PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7), 1393 PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
1395 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1), 1394 PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1),
1396 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2), 1395 PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2),
1397 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1), 1396 PINMUX_IPSR_MSEL(IP11_5_3, SCL4_B, SEL_IIC4_1),
1398 PINMUX_IPSR_DATA(IP11_8_6, VI0_R7), 1397 PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
1399 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1), 1398 PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
1400 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2), 1399 PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2),
1401 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4), 1400 PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
1402 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1), 1401 PINMUX_IPSR_MSEL(IP11_8_6, SDA4_B, SEL_IIC4_1),
1403 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3), 1402 PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
1404 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3), 1403 PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
1405 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0), 1404 PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
1406 PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0), 1405 PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
1407 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1), 1406 PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
1408 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1), 1407 PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1),
1409 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1), 1408 PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
1410 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0), 1409 PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
1411 PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1), 1410 PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
1412 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1), 1411 PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
1413 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1), 1412 PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1),
1414 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1), 1413 PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
1415 PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0), 1414 PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
1416 PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2), 1415 PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
1417 PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1), 1416 PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
1418 PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0), 1417 PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0),
1419 PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3), 1418 PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
1420 PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1), 1419 PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
1421 PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0), 1420 PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0),
1422 PINMUX_IPSR_DATA(IP11_19, AVB_RXD4), 1421 PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
1423 PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0), 1422 PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0),
1424 PINMUX_IPSR_DATA(IP11_20, AVB_RXD5), 1423 PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
1425 PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0), 1424 PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0),
1426 PINMUX_IPSR_DATA(IP11_21, AVB_RXD6), 1425 PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
1427 PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0), 1426 PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0),
1428 PINMUX_IPSR_DATA(IP11_22, AVB_RXD7), 1427 PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
1429 PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0), 1428 PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0),
1430 PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER), 1429 PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
1431 PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0), 1430 PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0),
1432 PINMUX_IPSR_DATA(IP11_24, AVB_MDIO), 1431 PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
1433 PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0), 1432 PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0),
1434 PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV), 1433 PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
1435 PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0), 1434 PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0),
1436 PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC), 1435 PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
1437 PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0), 1436 PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0),
1438 PINMUX_IPSR_DATA(IP11_27, AVB_MDC), 1437 PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
1439 PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO), 1438 PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
1440 PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK), 1439 PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
1441 PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2), 1440 PINMUX_IPSR_MSEL(IP11_29_28, SCL2_C, SEL_IIC2_2),
1442 PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV), 1441 PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
1443 PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK), 1442 PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
1444 PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2), 1443 PINMUX_IPSR_MSEL(IP11_31_30, SDA2_C, SEL_IIC2_2),
1445 1444
1446 /* IPSR12 */ 1445 /* IPSR12 */
1447 PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER), 1446 PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
1448 PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS), 1447 PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
1449 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0), 1448 PINMUX_IPSR_MSEL(IP12_1_0, SCL3, SEL_IIC3_0),
1450 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0), 1449 PINMUX_IPSR_MSEL(IP12_1_0, SCL7, SEL_IIC7_0),
1451 PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0), 1450 PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
1452 PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT), 1451 PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
1453 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0), 1452 PINMUX_IPSR_MSEL(IP12_3_2, SDA3, SEL_IIC3_0),
1454 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0), 1453 PINMUX_IPSR_MSEL(IP12_3_2, SDA7, SEL_IIC7_0),
1455 PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1), 1454 PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
1456 PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK), 1455 PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
1457 PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2), 1456 PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
1458 PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3), 1457 PINMUX_IPSR_MSEL(IP12_6_4, SCL2_D, SEL_IIC2_3),
1459 PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4), 1458 PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
1460 PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK), 1459 PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
1461 PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0), 1460 PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
1462 PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2), 1461 PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
1463 PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3), 1462 PINMUX_IPSR_MSEL(IP12_9_7, SDA2_D, SEL_IIC2_3),
1464 PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4), 1463 PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
1465 PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK), 1464 PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
1466 PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1), 1465 PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
1467 PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1), 1466 PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
1468 PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2), 1467 PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
1469 PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4), 1468 PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
1470 PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1), 1469 PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
1471 PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2), 1470 PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
1472 PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1), 1471 PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
1473 PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2), 1472 PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
1474 PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4), 1473 PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
1475 PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN), 1474 PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
1476 PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3), 1475 PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
1477 PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0), 1476 PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0),
1478 PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1), 1477 PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
1479 PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC), 1478 PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
1480 PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4), 1479 PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
1481 PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2), 1480 PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2),
1482 PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0), 1481 PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
1483 PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5), 1482 PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
1484 PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2), 1483 PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2),
1485 PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC), 1484 PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
1486 PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6), 1485 PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
1487 PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2), 1486 PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2),
1488 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0), 1487 PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
1489 PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7), 1488 PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
1490 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3), 1489 PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
1491 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1), 1490 PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1),
1492 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2), 1491 PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
1493 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0), 1492 PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
1494 PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN), 1493 PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
1495 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3), 1494 PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
1496 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1), 1495 PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
1497 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2), 1496 PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
1498 1497
1499 /* IPSR13 */ 1498 /* IPSR13 */
1500 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, STP_ISD_0, SEL_SSP_0), 1499 PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0),
1501 PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER), 1500 PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER),
1502 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2), 1501 PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
1503 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ADICLK_B, SEL_RAD_1), 1502 PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1),
1504 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2), 1503 PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
1505 PINMUX_IPSR_MODSEL_DATA(IP13_4_3, STP_ISEN_0, SEL_SSP_0), 1504 PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
1506 PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK), 1505 PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK),
1507 PINMUX_IPSR_MODSEL_DATA(IP13_4_3, ADICHS0_B, SEL_RAD_1), 1506 PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1),
1508 PINMUX_IPSR_MODSEL_DATA(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2), 1507 PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
1509 PINMUX_IPSR_MODSEL_DATA(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0), 1508 PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
1510 PINMUX_IPSR_DATA(IP13_6_5, AVB_COL), 1509 PINMUX_IPSR_DATA(IP13_6_5, AVB_COL),
1511 PINMUX_IPSR_MODSEL_DATA(IP13_6_5, ADICHS1_B, SEL_RAD_1), 1510 PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1),
1512 PINMUX_IPSR_MODSEL_DATA(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2), 1511 PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
1513 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, STP_OPWM_0, SEL_SSP_0), 1512 PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
1514 PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK), 1513 PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK),
1515 PINMUX_IPSR_DATA(IP13_9_7, PWM0_B), 1514 PINMUX_IPSR_DATA(IP13_9_7, PWM0_B),
1516 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, ADICHS2_B, SEL_RAD_1), 1515 PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1),
1517 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2), 1516 PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
1518 PINMUX_IPSR_DATA(IP13_10, SD0_CLK), 1517 PINMUX_IPSR_DATA(IP13_10, SD0_CLK),
1519 PINMUX_IPSR_MODSEL_DATA(IP13_10, SPCLK_B, SEL_QSP_1), 1518 PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1),
1520 PINMUX_IPSR_DATA(IP13_11, SD0_CMD), 1519 PINMUX_IPSR_DATA(IP13_11, SD0_CMD),
1521 PINMUX_IPSR_MODSEL_DATA(IP13_11, MOSI_IO0_B, SEL_QSP_1), 1520 PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1),
1522 PINMUX_IPSR_DATA(IP13_12, SD0_DATA0), 1521 PINMUX_IPSR_DATA(IP13_12, SD0_DATA0),
1523 PINMUX_IPSR_MODSEL_DATA(IP13_12, MISO_IO1_B, SEL_QSP_1), 1522 PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1),
1524 PINMUX_IPSR_DATA(IP13_13, SD0_DATA1), 1523 PINMUX_IPSR_DATA(IP13_13, SD0_DATA1),
1525 PINMUX_IPSR_MODSEL_DATA(IP13_13, IO2_B, SEL_QSP_1), 1524 PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1),
1526 PINMUX_IPSR_DATA(IP13_14, SD0_DATA2), 1525 PINMUX_IPSR_DATA(IP13_14, SD0_DATA2),
1527 PINMUX_IPSR_MODSEL_DATA(IP13_14, IO3_B, SEL_QSP_1), 1526 PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1),
1528 PINMUX_IPSR_DATA(IP13_15, SD0_DATA3), 1527 PINMUX_IPSR_DATA(IP13_15, SD0_DATA3),
1529 PINMUX_IPSR_MODSEL_DATA(IP13_15, SSL_B, SEL_QSP_1), 1528 PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1),
1530 PINMUX_IPSR_DATA(IP13_18_16, SD0_CD), 1529 PINMUX_IPSR_DATA(IP13_18_16, SD0_CD),
1531 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, MMC_D6_B, SEL_MMC_1), 1530 PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1),
1532 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SIM0_RST_B, SEL_SIM_1), 1531 PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
1533 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, CAN0_RX_F, SEL_CAN0_5), 1532 PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
1534 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1), 1533 PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
1535 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, TX3_C, SEL_SCIF3_2), 1534 PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2),
1536 PINMUX_IPSR_DATA(IP13_21_19, SD0_WP), 1535 PINMUX_IPSR_DATA(IP13_21_19, SD0_WP),
1537 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, MMC_D7_B, SEL_MMC_1), 1536 PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1),
1538 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SIM0_D_B, SEL_SIM_1), 1537 PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1),
1539 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, CAN0_TX_F, SEL_CAN0_5), 1538 PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
1540 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1), 1539 PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
1541 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, RX3_C, SEL_SCIF3_2), 1540 PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2),
1542 PINMUX_IPSR_DATA(IP13_22, SD1_CMD), 1541 PINMUX_IPSR_DATA(IP13_22, SD1_CMD),
1543 PINMUX_IPSR_MODSEL_DATA(IP13_22, REMOCON_B, SEL_RCN_1), 1542 PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1),
1544 PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0), 1543 PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0),
1545 PINMUX_IPSR_MODSEL_DATA(IP13_24_23, SPEEDIN_B, SEL_RSP_1), 1544 PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
1546 PINMUX_IPSR_DATA(IP13_25, SD1_DATA1), 1545 PINMUX_IPSR_DATA(IP13_25, SD1_DATA1),
1547 PINMUX_IPSR_MODSEL_DATA(IP13_25, IETX_B, SEL_IEB_1), 1546 PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1),
1548 PINMUX_IPSR_DATA(IP13_26, SD1_DATA2), 1547 PINMUX_IPSR_DATA(IP13_26, SD1_DATA2),
1549 PINMUX_IPSR_MODSEL_DATA(IP13_26, IECLK_B, SEL_IEB_1), 1548 PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1),
1550 PINMUX_IPSR_DATA(IP13_27, SD1_DATA3), 1549 PINMUX_IPSR_DATA(IP13_27, SD1_DATA3),
1551 PINMUX_IPSR_MODSEL_DATA(IP13_27, IERX_B, SEL_IEB_1), 1550 PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1),
1552 PINMUX_IPSR_DATA(IP13_30_28, SD1_CD), 1551 PINMUX_IPSR_DATA(IP13_30_28, SD1_CD),
1553 PINMUX_IPSR_DATA(IP13_30_28, PWM0), 1552 PINMUX_IPSR_DATA(IP13_30_28, PWM0),
1554 PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0), 1553 PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0),
1555 PINMUX_IPSR_MODSEL_DATA(IP13_30_28, SCL1_C, SEL_IIC1_2), 1554 PINMUX_IPSR_MSEL(IP13_30_28, SCL1_C, SEL_IIC1_2),
1556 1555
1557 /* IPSR14 */ 1556 /* IPSR14 */
1558 PINMUX_IPSR_DATA(IP14_1_0, SD1_WP), 1557 PINMUX_IPSR_DATA(IP14_1_0, SD1_WP),
1559 PINMUX_IPSR_DATA(IP14_1_0, PWM1_B), 1558 PINMUX_IPSR_DATA(IP14_1_0, PWM1_B),
1560 PINMUX_IPSR_MODSEL_DATA(IP14_1_0, SDA1_C, SEL_IIC1_2), 1559 PINMUX_IPSR_MSEL(IP14_1_0, SDA1_C, SEL_IIC1_2),
1561 PINMUX_IPSR_DATA(IP14_2, SD2_CLK), 1560 PINMUX_IPSR_DATA(IP14_2, SD2_CLK),
1562 PINMUX_IPSR_DATA(IP14_2, MMC_CLK), 1561 PINMUX_IPSR_DATA(IP14_2, MMC_CLK),
1563 PINMUX_IPSR_DATA(IP14_3, SD2_CMD), 1562 PINMUX_IPSR_DATA(IP14_3, SD2_CMD),
@@ -1572,123 +1571,123 @@ static const u16 pinmux_data[] = {
1572 PINMUX_IPSR_DATA(IP14_7, MMC_D3), 1571 PINMUX_IPSR_DATA(IP14_7, MMC_D3),
1573 PINMUX_IPSR_DATA(IP14_10_8, SD2_CD), 1572 PINMUX_IPSR_DATA(IP14_10_8, SD2_CD),
1574 PINMUX_IPSR_DATA(IP14_10_8, MMC_D4), 1573 PINMUX_IPSR_DATA(IP14_10_8, MMC_D4),
1575 PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCL8_C, SEL_IIC8_2), 1574 PINMUX_IPSR_MSEL(IP14_10_8, SCL8_C, SEL_IIC8_2),
1576 PINMUX_IPSR_MODSEL_DATA(IP14_10_8, TX5_B, SEL_SCIF5_1), 1575 PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1),
1577 PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2), 1576 PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
1578 PINMUX_IPSR_DATA(IP14_13_11, SD2_WP), 1577 PINMUX_IPSR_DATA(IP14_13_11, SD2_WP),
1579 PINMUX_IPSR_DATA(IP14_13_11, MMC_D5), 1578 PINMUX_IPSR_DATA(IP14_13_11, MMC_D5),
1580 PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SDA8_C, SEL_IIC8_2), 1579 PINMUX_IPSR_MSEL(IP14_13_11, SDA8_C, SEL_IIC8_2),
1581 PINMUX_IPSR_MODSEL_DATA(IP14_13_11, RX5_B, SEL_SCIF5_1), 1580 PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1),
1582 PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2), 1581 PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
1583 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0), 1582 PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
1584 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, RX2_C, SEL_SCIF2_2), 1583 PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2),
1585 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, ADIDATA, SEL_RAD_0), 1584 PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0),
1586 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, VI1_CLK_C, SEL_VI1_2), 1585 PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
1587 PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B), 1586 PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B),
1588 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0), 1587 PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
1589 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, TX2_C, SEL_SCIF2_2), 1588 PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2),
1590 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, ADICS_SAMP, SEL_RAD_0), 1589 PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
1591 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2), 1590 PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
1592 PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B), 1591 PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B),
1593 PINMUX_IPSR_MODSEL_DATA(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0), 1592 PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
1594 PINMUX_IPSR_MODSEL_DATA(IP14_22_20, ADICLK, SEL_RAD_0), 1593 PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0),
1595 PINMUX_IPSR_MODSEL_DATA(IP14_22_20, VI1_FIELD_C, SEL_VI1_2), 1594 PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
1596 PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B), 1595 PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B),
1597 PINMUX_IPSR_MODSEL_DATA(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0), 1596 PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
1598 PINMUX_IPSR_MODSEL_DATA(IP14_25_23, ADICHS0, SEL_RAD_0), 1597 PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0),
1599 PINMUX_IPSR_MODSEL_DATA(IP14_25_23, VI1_DATA0_C, SEL_VI1_2), 1598 PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
1600 PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B), 1599 PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B),
1601 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0), 1600 PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
1602 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MMC_D6, SEL_MMC_0), 1601 PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0),
1603 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, ADICHS1, SEL_RAD_0), 1602 PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0),
1604 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, TX0_E, SEL_SCIF0_4), 1603 PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4),
1605 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2), 1604 PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
1606 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, SCL7_C, SEL_IIC7_2), 1605 PINMUX_IPSR_MSEL(IP14_28_26, SCL7_C, SEL_IIC7_2),
1607 PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B), 1606 PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B),
1608 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0), 1607 PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
1609 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MMC_D7, SEL_MMC_0), 1608 PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0),
1610 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, ADICHS2, SEL_RAD_0), 1609 PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0),
1611 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, RX0_E, SEL_SCIF0_4), 1610 PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4),
1612 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2), 1611 PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
1613 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, SDA7_C, SEL_IIC7_2), 1612 PINMUX_IPSR_MSEL(IP14_31_29, SDA7_C, SEL_IIC7_2),
1614 PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B), 1613 PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B),
1615 1614
1616 /* IPSR15 */ 1615 /* IPSR15 */
1617 PINMUX_IPSR_MODSEL_DATA(IP15_1_0, SIM0_RST, SEL_SIM_0), 1616 PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0),
1618 PINMUX_IPSR_MODSEL_DATA(IP15_1_0, IETX, SEL_IEB_0), 1617 PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0),
1619 PINMUX_IPSR_MODSEL_DATA(IP15_1_0, CAN1_TX_D, SEL_CAN1_3), 1618 PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
1620 PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK), 1619 PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK),
1621 PINMUX_IPSR_MODSEL_DATA(IP15_3_2, IECLK, SEL_IEB_0), 1620 PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0),
1622 PINMUX_IPSR_MODSEL_DATA(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2), 1621 PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
1623 PINMUX_IPSR_MODSEL_DATA(IP15_5_4, SIM0_D, SEL_SIM_0), 1622 PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0),
1624 PINMUX_IPSR_MODSEL_DATA(IP15_5_4, IERX, SEL_IEB_0), 1623 PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0),
1625 PINMUX_IPSR_MODSEL_DATA(IP15_5_4, CAN1_RX_D, SEL_CAN1_3), 1624 PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
1626 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, GPS_CLK, SEL_GPS_0), 1625 PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0),
1627 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2), 1626 PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
1628 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1), 1627 PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1629 PINMUX_IPSR_DATA(IP15_8_6, PWM5_B), 1628 PINMUX_IPSR_DATA(IP15_8_6, PWM5_B),
1630 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2), 1629 PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
1631 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, GPS_SIGN, SEL_GPS_0), 1630 PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0),
1632 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TX4_C, SEL_SCIF4_2), 1631 PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2),
1633 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), 1632 PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
1634 PINMUX_IPSR_DATA(IP15_11_9, PWM5), 1633 PINMUX_IPSR_DATA(IP15_11_9, PWM5),
1635 PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B), 1634 PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B),
1636 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2), 1635 PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
1637 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, GPS_MAG, SEL_GPS_0), 1636 PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0),
1638 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, RX4_C, SEL_SCIF4_2), 1637 PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2),
1639 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2), 1638 PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
1640 PINMUX_IPSR_DATA(IP15_14_12, PWM6), 1639 PINMUX_IPSR_DATA(IP15_14_12, PWM6),
1641 PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B), 1640 PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B),
1642 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2), 1641 PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
1643 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, HCTS0_N, SEL_HSCIF0_0), 1642 PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
1644 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0), 1643 PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
1645 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, GLO_I0_C, SEL_GPS_2), 1644 PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2),
1646 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, TCLK1, SEL_TMU1_0), 1645 PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0),
1647 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, VI1_DATA1_C, SEL_VI1_2), 1646 PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
1648 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, HRTS0_N, SEL_HSCIF0_0), 1647 PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
1649 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0), 1648 PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
1650 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, GLO_I1_C, SEL_GPS_2), 1649 PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2),
1651 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, VI1_DATA2_C, SEL_VI1_2), 1650 PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
1652 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, HSCK0, SEL_HSCIF0_0), 1651 PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0),
1653 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0), 1652 PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
1654 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, GLO_Q0_C, SEL_GPS_2), 1653 PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
1655 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, CAN_CLK, SEL_CANCLK_0), 1654 PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
1656 PINMUX_IPSR_DATA(IP15_23_21, TCLK2), 1655 PINMUX_IPSR_DATA(IP15_23_21, TCLK2),
1657 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, VI1_DATA3_C, SEL_VI1_2), 1656 PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
1658 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, HRX0, SEL_HSCIF0_0), 1657 PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0),
1659 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0), 1658 PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
1660 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, GLO_Q1_C, SEL_GPS_2), 1659 PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
1661 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, CAN0_RX_B, SEL_CAN0_1), 1660 PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
1662 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, VI1_DATA4_C, SEL_VI1_2), 1661 PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
1663 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, HTX0, SEL_HSCIF0_0), 1662 PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0),
1664 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0), 1663 PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
1665 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, GLO_SCLK_C, SEL_GPS_2), 1664 PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
1666 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, CAN0_TX_B, SEL_CAN0_1), 1665 PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
1667 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, VI1_DATA5_C, SEL_VI1_2), 1666 PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
1668 1667
1669 /* IPSR16 */ 1668 /* IPSR16 */
1670 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HRX1, SEL_HSCIF1_0), 1669 PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0),
1671 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0), 1670 PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
1672 PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B), 1671 PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B),
1673 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, GLO_SDATA_C, SEL_GPS_2), 1672 PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
1674 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, VI1_DATA6_C, SEL_VI1_2), 1673 PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
1675 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HTX1, SEL_HSCIF1_0), 1674 PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0),
1676 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0), 1675 PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
1677 PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B), 1676 PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B),
1678 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, GLO_SS_C, SEL_GPS_2), 1677 PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2),
1679 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, VI1_DATA7_C, SEL_VI1_2), 1678 PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
1680 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, HSCK1, SEL_HSCIF1_0), 1679 PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0),
1681 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0), 1680 PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
1682 PINMUX_IPSR_DATA(IP16_7_6, MLB_CLK), 1681 PINMUX_IPSR_DATA(IP16_7_6, MLB_CLK),
1683 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, GLO_RFON_C, SEL_GPS_2), 1682 PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
1684 PINMUX_IPSR_MODSEL_DATA(IP16_9_8, HCTS1_N, SEL_HSCIF1_0), 1683 PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
1685 PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N), 1684 PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N),
1686 PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG), 1685 PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG),
1687 PINMUX_IPSR_MODSEL_DATA(IP16_9_8, CAN1_TX_B, SEL_CAN1_1), 1686 PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
1688 PINMUX_IPSR_MODSEL_DATA(IP16_11_10, HRTS1_N, SEL_HSCIF1_0), 1687 PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
1689 PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N), 1688 PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N),
1690 PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT), 1689 PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT),
1691 PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1), 1690 PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1692}; 1691};
1693 1692
1694static const struct sh_pfc_pin pinmux_pins[] = { 1693static const struct sh_pfc_pin pinmux_pins[] = {
@@ -3986,24 +3985,6 @@ static const unsigned int usb1_mux[] = {
3986 USB1_PWEN_MARK, 3985 USB1_PWEN_MARK,
3987 USB1_OVC_MARK, 3986 USB1_OVC_MARK,
3988}; 3987};
3989
3990union vin_data {
3991 unsigned int data24[24];
3992 unsigned int data20[20];
3993 unsigned int data16[16];
3994 unsigned int data12[12];
3995 unsigned int data10[10];
3996 unsigned int data8[8];
3997};
3998
3999#define VIN_DATA_PIN_GROUP(n, s) \
4000 { \
4001 .name = #n#s, \
4002 .pins = n##_pins.data##s, \
4003 .mux = n##_mux.data##s, \
4004 .nr_pins = ARRAY_SIZE(n##_pins.data##s), \
4005 }
4006
4007/* - VIN0 ------------------------------------------------------------------- */ 3988/* - VIN0 ------------------------------------------------------------------- */
4008static const union vin_data vin0_data_pins = { 3989static const union vin_data vin0_data_pins = {
4009 .data24 = { 3990 .data24 = {
@@ -6337,8 +6318,8 @@ const struct sh_pfc_soc_info r8a7791_pinmux_info = {
6337 6318
6338 .cfg_regs = pinmux_config_regs, 6319 .cfg_regs = pinmux_config_regs,
6339 6320
6340 .gpio_data = pinmux_data, 6321 .pinmux_data = pinmux_data,
6341 .gpio_data_size = ARRAY_SIZE(pinmux_data), 6322 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6342}; 6323};
6343#endif 6324#endif
6344 6325
@@ -6358,7 +6339,7 @@ const struct sh_pfc_soc_info r8a7793_pinmux_info = {
6358 6339
6359 .cfg_regs = pinmux_config_regs, 6340 .cfg_regs = pinmux_config_regs,
6360 6341
6361 .gpio_data = pinmux_data, 6342 .pinmux_data = pinmux_data,
6362 .gpio_data_size = ARRAY_SIZE(pinmux_data), 6343 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6363}; 6344};
6364#endif 6345#endif
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
index 5248685dbb4e..086f6798b129 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
@@ -11,7 +11,6 @@
11 */ 11 */
12 12
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/platform_data/gpio-rcar.h>
15 14
16#include "core.h" 15#include "core.h"
17#include "sh_pfc.h" 16#include "sh_pfc.h"
@@ -644,10 +643,10 @@ static const u16 pinmux_data[] = {
644 643
645 /* IPSR0 */ 644 /* IPSR0 */
646 PINMUX_IPSR_DATA(IP0_0, SD1_CD), 645 PINMUX_IPSR_DATA(IP0_0, SD1_CD),
647 PINMUX_IPSR_MODSEL_DATA(IP0_0, CAN0_RX, SEL_CAN0_0), 646 PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0),
648 PINMUX_IPSR_DATA(IP0_9_8, SD1_WP), 647 PINMUX_IPSR_DATA(IP0_9_8, SD1_WP),
649 PINMUX_IPSR_DATA(IP0_9_8, IRQ7), 648 PINMUX_IPSR_DATA(IP0_9_8, IRQ7),
650 PINMUX_IPSR_MODSEL_DATA(IP0_9_8, CAN0_TX, SEL_CAN0_0), 649 PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0),
651 PINMUX_IPSR_DATA(IP0_10, MMC_CLK), 650 PINMUX_IPSR_DATA(IP0_10, MMC_CLK),
652 PINMUX_IPSR_DATA(IP0_10, SD2_CLK), 651 PINMUX_IPSR_DATA(IP0_10, SD2_CLK),
653 PINMUX_IPSR_DATA(IP0_11, MMC_CMD), 652 PINMUX_IPSR_DATA(IP0_11, MMC_CMD),
@@ -665,68 +664,68 @@ static const u16 pinmux_data[] = {
665 PINMUX_IPSR_DATA(IP0_17, MMC_D5), 664 PINMUX_IPSR_DATA(IP0_17, MMC_D5),
666 PINMUX_IPSR_DATA(IP0_17, SD2_WP), 665 PINMUX_IPSR_DATA(IP0_17, SD2_WP),
667 PINMUX_IPSR_DATA(IP0_19_18, MMC_D6), 666 PINMUX_IPSR_DATA(IP0_19_18, MMC_D6),
668 PINMUX_IPSR_MODSEL_DATA(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0), 667 PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
669 PINMUX_IPSR_MODSEL_DATA(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1), 668 PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
670 PINMUX_IPSR_MODSEL_DATA(IP0_19_18, CAN1_RX, SEL_CAN1_0), 669 PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0),
671 PINMUX_IPSR_DATA(IP0_21_20, MMC_D7), 670 PINMUX_IPSR_DATA(IP0_21_20, MMC_D7),
672 PINMUX_IPSR_MODSEL_DATA(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0), 671 PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
673 PINMUX_IPSR_MODSEL_DATA(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1), 672 PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
674 PINMUX_IPSR_MODSEL_DATA(IP0_21_20, CAN1_TX, SEL_CAN1_0), 673 PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0),
675 PINMUX_IPSR_DATA(IP0_23_22, D0), 674 PINMUX_IPSR_DATA(IP0_23_22, D0),
676 PINMUX_IPSR_MODSEL_DATA(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1), 675 PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
677 PINMUX_IPSR_DATA(IP0_23_22, IRQ4), 676 PINMUX_IPSR_DATA(IP0_23_22, IRQ4),
678 PINMUX_IPSR_DATA(IP0_24, D1), 677 PINMUX_IPSR_DATA(IP0_24, D1),
679 PINMUX_IPSR_MODSEL_DATA(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1), 678 PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
680 PINMUX_IPSR_DATA(IP0_25, D2), 679 PINMUX_IPSR_DATA(IP0_25, D2),
681 PINMUX_IPSR_MODSEL_DATA(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1), 680 PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
682 PINMUX_IPSR_DATA(IP0_27_26, D3), 681 PINMUX_IPSR_DATA(IP0_27_26, D3),
683 PINMUX_IPSR_MODSEL_DATA(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1), 682 PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
684 PINMUX_IPSR_MODSEL_DATA(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1), 683 PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
685 PINMUX_IPSR_DATA(IP0_29_28, D4), 684 PINMUX_IPSR_DATA(IP0_29_28, D4),
686 PINMUX_IPSR_MODSEL_DATA(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1), 685 PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
687 PINMUX_IPSR_MODSEL_DATA(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1), 686 PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
688 PINMUX_IPSR_DATA(IP0_31_30, D5), 687 PINMUX_IPSR_DATA(IP0_31_30, D5),
689 PINMUX_IPSR_MODSEL_DATA(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1), 688 PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
690 PINMUX_IPSR_MODSEL_DATA(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3), 689 PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
691 690
692 /* IPSR1 */ 691 /* IPSR1 */
693 PINMUX_IPSR_DATA(IP1_1_0, D6), 692 PINMUX_IPSR_DATA(IP1_1_0, D6),
694 PINMUX_IPSR_MODSEL_DATA(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1), 693 PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1),
695 PINMUX_IPSR_MODSEL_DATA(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3), 694 PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3),
696 PINMUX_IPSR_DATA(IP1_3_2, D7), 695 PINMUX_IPSR_DATA(IP1_3_2, D7),
697 PINMUX_IPSR_DATA(IP1_3_2, IRQ3), 696 PINMUX_IPSR_DATA(IP1_3_2, IRQ3),
698 PINMUX_IPSR_MODSEL_DATA(IP1_3_2, TCLK1, SEL_TMU_0), 697 PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0),
699 PINMUX_IPSR_DATA(IP1_3_2, PWM6_B), 698 PINMUX_IPSR_DATA(IP1_3_2, PWM6_B),
700 PINMUX_IPSR_DATA(IP1_5_4, D8), 699 PINMUX_IPSR_DATA(IP1_5_4, D8),
701 PINMUX_IPSR_DATA(IP1_5_4, HSCIF2_HRX), 700 PINMUX_IPSR_DATA(IP1_5_4, HSCIF2_HRX),
702 PINMUX_IPSR_MODSEL_DATA(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1), 701 PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1),
703 PINMUX_IPSR_DATA(IP1_7_6, D9), 702 PINMUX_IPSR_DATA(IP1_7_6, D9),
704 PINMUX_IPSR_DATA(IP1_7_6, HSCIF2_HTX), 703 PINMUX_IPSR_DATA(IP1_7_6, HSCIF2_HTX),
705 PINMUX_IPSR_MODSEL_DATA(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1), 704 PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1),
706 PINMUX_IPSR_DATA(IP1_10_8, D10), 705 PINMUX_IPSR_DATA(IP1_10_8, D10),
707 PINMUX_IPSR_DATA(IP1_10_8, HSCIF2_HSCK), 706 PINMUX_IPSR_DATA(IP1_10_8, HSCIF2_HSCK),
708 PINMUX_IPSR_MODSEL_DATA(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2), 707 PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2),
709 PINMUX_IPSR_DATA(IP1_10_8, IRQ6), 708 PINMUX_IPSR_DATA(IP1_10_8, IRQ6),
710 PINMUX_IPSR_DATA(IP1_10_8, PWM5_C), 709 PINMUX_IPSR_DATA(IP1_10_8, PWM5_C),
711 PINMUX_IPSR_DATA(IP1_12_11, D11), 710 PINMUX_IPSR_DATA(IP1_12_11, D11),
712 PINMUX_IPSR_DATA(IP1_12_11, HSCIF2_HCTS_N), 711 PINMUX_IPSR_DATA(IP1_12_11, HSCIF2_HCTS_N),
713 PINMUX_IPSR_MODSEL_DATA(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2), 712 PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2),
714 PINMUX_IPSR_MODSEL_DATA(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3), 713 PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3),
715 PINMUX_IPSR_DATA(IP1_14_13, D12), 714 PINMUX_IPSR_DATA(IP1_14_13, D12),
716 PINMUX_IPSR_DATA(IP1_14_13, HSCIF2_HRTS_N), 715 PINMUX_IPSR_DATA(IP1_14_13, HSCIF2_HRTS_N),
717 PINMUX_IPSR_MODSEL_DATA(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2), 716 PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2),
718 PINMUX_IPSR_MODSEL_DATA(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3), 717 PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
719 PINMUX_IPSR_DATA(IP1_17_15, D13), 718 PINMUX_IPSR_DATA(IP1_17_15, D13),
720 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0), 719 PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
721 PINMUX_IPSR_DATA(IP1_17_15, TANS1), 720 PINMUX_IPSR_DATA(IP1_17_15, TANS1),
722 PINMUX_IPSR_DATA(IP1_17_15, PWM2_C), 721 PINMUX_IPSR_DATA(IP1_17_15, PWM2_C),
723 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, TCLK2_B, SEL_TMU_1), 722 PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
724 PINMUX_IPSR_DATA(IP1_19_18, D14), 723 PINMUX_IPSR_DATA(IP1_19_18, D14),
725 PINMUX_IPSR_MODSEL_DATA(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0), 724 PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0),
726 PINMUX_IPSR_MODSEL_DATA(IP1_19_18, IIC0_SCL_B, SEL_IIC00_1), 725 PINMUX_IPSR_MSEL(IP1_19_18, IIC0_SCL_B, SEL_IIC00_1),
727 PINMUX_IPSR_DATA(IP1_21_20, D15), 726 PINMUX_IPSR_DATA(IP1_21_20, D15),
728 PINMUX_IPSR_MODSEL_DATA(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0), 727 PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0),
729 PINMUX_IPSR_MODSEL_DATA(IP1_21_20, IIC0_SDA_B, SEL_IIC00_1), 728 PINMUX_IPSR_MSEL(IP1_21_20, IIC0_SDA_B, SEL_IIC00_1),
730 PINMUX_IPSR_DATA(IP1_23_22, A0), 729 PINMUX_IPSR_DATA(IP1_23_22, A0),
731 PINMUX_IPSR_DATA(IP1_23_22, SCIFB1_SCK), 730 PINMUX_IPSR_DATA(IP1_23_22, SCIFB1_SCK),
732 PINMUX_IPSR_DATA(IP1_23_22, PWM3_B), 731 PINMUX_IPSR_DATA(IP1_23_22, PWM3_B),
@@ -742,58 +741,58 @@ static const u16 pinmux_data[] = {
742 PINMUX_IPSR_DATA(IP1_29_28, TPUTO3_C), 741 PINMUX_IPSR_DATA(IP1_29_28, TPUTO3_C),
743 PINMUX_IPSR_DATA(IP1_31_30, A6), 742 PINMUX_IPSR_DATA(IP1_31_30, A6),
744 PINMUX_IPSR_DATA(IP1_31_30, SCIFB0_CTS_N), 743 PINMUX_IPSR_DATA(IP1_31_30, SCIFB0_CTS_N),
745 PINMUX_IPSR_MODSEL_DATA(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1), 744 PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1),
746 PINMUX_IPSR_DATA(IP1_31_30, TPUTO2_C), 745 PINMUX_IPSR_DATA(IP1_31_30, TPUTO2_C),
747 746
748 /* IPSR2 */ 747 /* IPSR2 */
749 PINMUX_IPSR_DATA(IP2_1_0, A7), 748 PINMUX_IPSR_DATA(IP2_1_0, A7),
750 PINMUX_IPSR_DATA(IP2_1_0, SCIFB0_RTS_N), 749 PINMUX_IPSR_DATA(IP2_1_0, SCIFB0_RTS_N),
751 PINMUX_IPSR_MODSEL_DATA(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1), 750 PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1),
752 PINMUX_IPSR_DATA(IP2_3_2, A8), 751 PINMUX_IPSR_DATA(IP2_3_2, A8),
753 PINMUX_IPSR_MODSEL_DATA(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0), 752 PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0),
754 PINMUX_IPSR_MODSEL_DATA(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1), 753 PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1),
755 PINMUX_IPSR_DATA(IP2_5_4, A9), 754 PINMUX_IPSR_DATA(IP2_5_4, A9),
756 PINMUX_IPSR_MODSEL_DATA(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0), 755 PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0),
757 PINMUX_IPSR_MODSEL_DATA(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1), 756 PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1),
758 PINMUX_IPSR_DATA(IP2_7_6, A10), 757 PINMUX_IPSR_DATA(IP2_7_6, A10),
759 PINMUX_IPSR_MODSEL_DATA(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0), 758 PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0),
760 PINMUX_IPSR_MODSEL_DATA(IP2_7_6, IIC1_SCL_B, SEL_IIC01_1), 759 PINMUX_IPSR_MSEL(IP2_7_6, IIC1_SCL_B, SEL_IIC01_1),
761 PINMUX_IPSR_DATA(IP2_9_8, A11), 760 PINMUX_IPSR_DATA(IP2_9_8, A11),
762 PINMUX_IPSR_MODSEL_DATA(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0), 761 PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0),
763 PINMUX_IPSR_MODSEL_DATA(IP2_9_8, IIC1_SDA_B, SEL_IIC01_1), 762 PINMUX_IPSR_MSEL(IP2_9_8, IIC1_SDA_B, SEL_IIC01_1),
764 PINMUX_IPSR_DATA(IP2_11_10, A12), 763 PINMUX_IPSR_DATA(IP2_11_10, A12),
765 PINMUX_IPSR_MODSEL_DATA(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0), 764 PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0),
766 PINMUX_IPSR_MODSEL_DATA(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1), 765 PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1),
767 PINMUX_IPSR_DATA(IP2_13_12, A13), 766 PINMUX_IPSR_DATA(IP2_13_12, A13),
768 PINMUX_IPSR_MODSEL_DATA(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0), 767 PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0),
769 PINMUX_IPSR_MODSEL_DATA(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1), 768 PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1),
770 PINMUX_IPSR_DATA(IP2_15_14, A14), 769 PINMUX_IPSR_DATA(IP2_15_14, A14),
771 PINMUX_IPSR_MODSEL_DATA(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0), 770 PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0),
772 PINMUX_IPSR_MODSEL_DATA(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1), 771 PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1),
773 PINMUX_IPSR_MODSEL_DATA(IP2_15_14, DREQ1_N, SEL_LBS_0), 772 PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0),
774 PINMUX_IPSR_DATA(IP2_17_16, A15), 773 PINMUX_IPSR_DATA(IP2_17_16, A15),
775 PINMUX_IPSR_MODSEL_DATA(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0), 774 PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0),
776 PINMUX_IPSR_MODSEL_DATA(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1), 775 PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1),
777 PINMUX_IPSR_MODSEL_DATA(IP2_17_16, DACK1, SEL_LBS_0), 776 PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0),
778 PINMUX_IPSR_DATA(IP2_20_18, A16), 777 PINMUX_IPSR_DATA(IP2_20_18, A16),
779 PINMUX_IPSR_MODSEL_DATA(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0), 778 PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
780 PINMUX_IPSR_MODSEL_DATA(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1), 779 PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
781 PINMUX_IPSR_MODSEL_DATA(IP2_20_18, SPEEDIN, SEL_RSP_0), 780 PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
782 PINMUX_IPSR_MODSEL_DATA(IP2_20_18, VSP, SEL_SPDM_0), 781 PINMUX_IPSR_MSEL(IP2_20_18, VSP, SEL_SPDM_0),
783 PINMUX_IPSR_MODSEL_DATA(IP2_20_18, CAN_CLK_C, SEL_CAN_2), 782 PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
784 PINMUX_IPSR_DATA(IP2_20_18, TPUTO2_B), 783 PINMUX_IPSR_DATA(IP2_20_18, TPUTO2_B),
785 PINMUX_IPSR_DATA(IP2_23_21, A17), 784 PINMUX_IPSR_DATA(IP2_23_21, A17),
786 PINMUX_IPSR_MODSEL_DATA(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0), 785 PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
787 PINMUX_IPSR_MODSEL_DATA(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4), 786 PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
788 PINMUX_IPSR_MODSEL_DATA(IP2_23_21, CAN1_RX_B, SEL_CAN1_1), 787 PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
789 PINMUX_IPSR_MODSEL_DATA(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1), 788 PINMUX_IPSR_MSEL(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
790 PINMUX_IPSR_DATA(IP2_26_24, A18), 789 PINMUX_IPSR_DATA(IP2_26_24, A18),
791 PINMUX_IPSR_MODSEL_DATA(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0), 790 PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
792 PINMUX_IPSR_MODSEL_DATA(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4), 791 PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
793 PINMUX_IPSR_MODSEL_DATA(IP2_26_24, CAN1_TX_B, SEL_CAN1_1), 792 PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
794 PINMUX_IPSR_MODSEL_DATA(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1), 793 PINMUX_IPSR_MSEL(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1),
795 PINMUX_IPSR_DATA(IP2_29_27, A19), 794 PINMUX_IPSR_DATA(IP2_29_27, A19),
796 PINMUX_IPSR_MODSEL_DATA(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0), 795 PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
797 PINMUX_IPSR_DATA(IP2_29_27, PWM4), 796 PINMUX_IPSR_DATA(IP2_29_27, PWM4),
798 PINMUX_IPSR_DATA(IP2_29_27, TPUTO2), 797 PINMUX_IPSR_DATA(IP2_29_27, TPUTO2),
799 PINMUX_IPSR_DATA(IP2_29_27, MOUT0), 798 PINMUX_IPSR_DATA(IP2_29_27, MOUT0),
@@ -831,42 +830,42 @@ static const u16 pinmux_data[] = {
831 PINMUX_IPSR_DATA(IP3_14_13, VI1_DATA11), 830 PINMUX_IPSR_DATA(IP3_14_13, VI1_DATA11),
832 PINMUX_IPSR_DATA(IP3_17_15, EX_CS2_N), 831 PINMUX_IPSR_DATA(IP3_17_15, EX_CS2_N),
833 PINMUX_IPSR_DATA(IP3_17_15, PWM0), 832 PINMUX_IPSR_DATA(IP3_17_15, PWM0),
834 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2), 833 PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
835 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1), 834 PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
836 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, RIF0_SYNC, SEL_DR0_0), 835 PINMUX_IPSR_MSEL(IP3_17_15, RIF0_SYNC, SEL_DR0_0),
837 PINMUX_IPSR_DATA(IP3_17_15, TPUTO3), 836 PINMUX_IPSR_DATA(IP3_17_15, TPUTO3),
838 PINMUX_IPSR_DATA(IP3_17_15, SCIFB2_TXD), 837 PINMUX_IPSR_DATA(IP3_17_15, SCIFB2_TXD),
839 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SDATA_B, SEL_FSN_1), 838 PINMUX_IPSR_MSEL(IP3_17_15, SDATA_B, SEL_FSN_1),
840 PINMUX_IPSR_DATA(IP3_20_18, EX_CS3_N), 839 PINMUX_IPSR_DATA(IP3_20_18, EX_CS3_N),
841 PINMUX_IPSR_MODSEL_DATA(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0), 840 PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
842 PINMUX_IPSR_MODSEL_DATA(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2), 841 PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
843 PINMUX_IPSR_MODSEL_DATA(IP3_20_18, TS_SCK_B, SEL_TSIF0_1), 842 PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
844 PINMUX_IPSR_MODSEL_DATA(IP3_20_18, RIF0_CLK, SEL_DR0_0), 843 PINMUX_IPSR_MSEL(IP3_20_18, RIF0_CLK, SEL_DR0_0),
845 PINMUX_IPSR_MODSEL_DATA(IP3_20_18, BPFCLK, SEL_DARC_0), 844 PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
846 PINMUX_IPSR_DATA(IP3_20_18, SCIFB2_SCK), 845 PINMUX_IPSR_DATA(IP3_20_18, SCIFB2_SCK),
847 PINMUX_IPSR_MODSEL_DATA(IP3_20_18, MDATA_B, SEL_FSN_1), 846 PINMUX_IPSR_MSEL(IP3_20_18, MDATA_B, SEL_FSN_1),
848 PINMUX_IPSR_DATA(IP3_23_21, EX_CS4_N), 847 PINMUX_IPSR_DATA(IP3_23_21, EX_CS4_N),
849 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0), 848 PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
850 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4), 849 PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
851 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1), 850 PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
852 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, RIF0_D0, SEL_DR0_0), 851 PINMUX_IPSR_MSEL(IP3_23_21, RIF0_D0, SEL_DR0_0),
853 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, FMCLK, SEL_DARC_0), 852 PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
854 PINMUX_IPSR_DATA(IP3_23_21, SCIFB2_CTS_N), 853 PINMUX_IPSR_DATA(IP3_23_21, SCIFB2_CTS_N),
855 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SCKZ_B, SEL_FSN_1), 854 PINMUX_IPSR_MSEL(IP3_23_21, SCKZ_B, SEL_FSN_1),
856 PINMUX_IPSR_DATA(IP3_26_24, EX_CS5_N), 855 PINMUX_IPSR_DATA(IP3_26_24, EX_CS5_N),
857 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0), 856 PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
858 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4), 857 PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
859 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1), 858 PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
860 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RIF0_D1, SEL_DR1_0), 859 PINMUX_IPSR_MSEL(IP3_26_24, RIF0_D1, SEL_DR1_0),
861 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, FMIN, SEL_DARC_0), 860 PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
862 PINMUX_IPSR_DATA(IP3_26_24, SCIFB2_RTS_N), 861 PINMUX_IPSR_DATA(IP3_26_24, SCIFB2_RTS_N),
863 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, STM_N_B, SEL_FSN_1), 862 PINMUX_IPSR_MSEL(IP3_26_24, STM_N_B, SEL_FSN_1),
864 PINMUX_IPSR_DATA(IP3_29_27, BS_N), 863 PINMUX_IPSR_DATA(IP3_29_27, BS_N),
865 PINMUX_IPSR_DATA(IP3_29_27, DRACK0), 864 PINMUX_IPSR_DATA(IP3_29_27, DRACK0),
866 PINMUX_IPSR_DATA(IP3_29_27, PWM1_C), 865 PINMUX_IPSR_DATA(IP3_29_27, PWM1_C),
867 PINMUX_IPSR_DATA(IP3_29_27, TPUTO0_C), 866 PINMUX_IPSR_DATA(IP3_29_27, TPUTO0_C),
868 PINMUX_IPSR_DATA(IP3_29_27, ATACS01_N), 867 PINMUX_IPSR_DATA(IP3_29_27, ATACS01_N),
869 PINMUX_IPSR_MODSEL_DATA(IP3_29_27, MTS_N_B, SEL_FSN_1), 868 PINMUX_IPSR_MSEL(IP3_29_27, MTS_N_B, SEL_FSN_1),
870 PINMUX_IPSR_DATA(IP3_30, RD_N), 869 PINMUX_IPSR_DATA(IP3_30, RD_N),
871 PINMUX_IPSR_DATA(IP3_30, ATACS11_N), 870 PINMUX_IPSR_DATA(IP3_30, ATACS11_N),
872 PINMUX_IPSR_DATA(IP3_31, RD_WR_N), 871 PINMUX_IPSR_DATA(IP3_31, RD_WR_N),
@@ -874,18 +873,18 @@ static const u16 pinmux_data[] = {
874 873
875 /* IPSR4 */ 874 /* IPSR4 */
876 PINMUX_IPSR_DATA(IP4_1_0, EX_WAIT0), 875 PINMUX_IPSR_DATA(IP4_1_0, EX_WAIT0),
877 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_B, SEL_CAN_1), 876 PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
878 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCIF_CLK, SEL_SCIF0_0), 877 PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
879 PINMUX_IPSR_DATA(IP4_1_0, PWMFSW0), 878 PINMUX_IPSR_DATA(IP4_1_0, PWMFSW0),
880 PINMUX_IPSR_DATA(IP4_4_2, DU0_DR0), 879 PINMUX_IPSR_DATA(IP4_4_2, DU0_DR0),
881 PINMUX_IPSR_DATA(IP4_4_2, LCDOUT16), 880 PINMUX_IPSR_DATA(IP4_4_2, LCDOUT16),
882 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2), 881 PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
883 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3), 882 PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
884 PINMUX_IPSR_DATA(IP4_4_2, CC50_STATE0), 883 PINMUX_IPSR_DATA(IP4_4_2, CC50_STATE0),
885 PINMUX_IPSR_DATA(IP4_7_5, DU0_DR1), 884 PINMUX_IPSR_DATA(IP4_7_5, DU0_DR1),
886 PINMUX_IPSR_DATA(IP4_7_5, LCDOUT17), 885 PINMUX_IPSR_DATA(IP4_7_5, LCDOUT17),
887 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2), 886 PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
888 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3), 887 PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
889 PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE1), 888 PINMUX_IPSR_DATA(IP4_9_8, CC50_STATE1),
890 PINMUX_IPSR_DATA(IP4_9_8, DU0_DR2), 889 PINMUX_IPSR_DATA(IP4_9_8, DU0_DR2),
891 PINMUX_IPSR_DATA(IP4_9_8, LCDOUT18), 890 PINMUX_IPSR_DATA(IP4_9_8, LCDOUT18),
@@ -907,13 +906,13 @@ static const u16 pinmux_data[] = {
907 PINMUX_IPSR_DATA(IP4_19_18, CC50_STATE7), 906 PINMUX_IPSR_DATA(IP4_19_18, CC50_STATE7),
908 PINMUX_IPSR_DATA(IP4_22_20, DU0_DG0), 907 PINMUX_IPSR_DATA(IP4_22_20, DU0_DG0),
909 PINMUX_IPSR_DATA(IP4_22_20, LCDOUT8), 908 PINMUX_IPSR_DATA(IP4_22_20, LCDOUT8),
910 PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2), 909 PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
911 PINMUX_IPSR_MODSEL_DATA(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3), 910 PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
912 PINMUX_IPSR_DATA(IP4_22_20, CC50_STATE8), 911 PINMUX_IPSR_DATA(IP4_22_20, CC50_STATE8),
913 PINMUX_IPSR_DATA(IP4_25_23, DU0_DG1), 912 PINMUX_IPSR_DATA(IP4_25_23, DU0_DG1),
914 PINMUX_IPSR_DATA(IP4_25_23, LCDOUT9), 913 PINMUX_IPSR_DATA(IP4_25_23, LCDOUT9),
915 PINMUX_IPSR_MODSEL_DATA(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2), 914 PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
916 PINMUX_IPSR_MODSEL_DATA(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3), 915 PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
917 PINMUX_IPSR_DATA(IP4_25_23, CC50_STATE9), 916 PINMUX_IPSR_DATA(IP4_25_23, CC50_STATE9),
918 PINMUX_IPSR_DATA(IP4_27_26, DU0_DG2), 917 PINMUX_IPSR_DATA(IP4_27_26, DU0_DG2),
919 PINMUX_IPSR_DATA(IP4_27_26, LCDOUT10), 918 PINMUX_IPSR_DATA(IP4_27_26, LCDOUT10),
@@ -937,15 +936,15 @@ static const u16 pinmux_data[] = {
937 PINMUX_IPSR_DATA(IP5_5_4, CC50_STATE15), 936 PINMUX_IPSR_DATA(IP5_5_4, CC50_STATE15),
938 PINMUX_IPSR_DATA(IP5_8_6, DU0_DB0), 937 PINMUX_IPSR_DATA(IP5_8_6, DU0_DB0),
939 PINMUX_IPSR_DATA(IP5_8_6, LCDOUT0), 938 PINMUX_IPSR_DATA(IP5_8_6, LCDOUT0),
940 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2), 939 PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
941 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3), 940 PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
942 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_RX_C, SEL_CAN0_2), 941 PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
943 PINMUX_IPSR_DATA(IP5_8_6, CC50_STATE16), 942 PINMUX_IPSR_DATA(IP5_8_6, CC50_STATE16),
944 PINMUX_IPSR_DATA(IP5_11_9, DU0_DB1), 943 PINMUX_IPSR_DATA(IP5_11_9, DU0_DB1),
945 PINMUX_IPSR_DATA(IP5_11_9, LCDOUT1), 944 PINMUX_IPSR_DATA(IP5_11_9, LCDOUT1),
946 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), 945 PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
947 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3), 946 PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
948 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, CAN0_TX_C, SEL_CAN0_2), 947 PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
949 PINMUX_IPSR_DATA(IP5_11_9, CC50_STATE17), 948 PINMUX_IPSR_DATA(IP5_11_9, CC50_STATE17),
950 PINMUX_IPSR_DATA(IP5_13_12, DU0_DB2), 949 PINMUX_IPSR_DATA(IP5_13_12, DU0_DB2),
951 PINMUX_IPSR_DATA(IP5_13_12, LCDOUT2), 950 PINMUX_IPSR_DATA(IP5_13_12, LCDOUT2),
@@ -1010,501 +1009,501 @@ static const u16 pinmux_data[] = {
1010 PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7), 1009 PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7),
1011 PINMUX_IPSR_DATA(IP6_16, AVB_RXD6), 1010 PINMUX_IPSR_DATA(IP6_16, AVB_RXD6),
1012 PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB), 1011 PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB),
1013 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C3_SCL, SEL_I2C03_0), 1012 PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
1014 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2), 1013 PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
1015 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IETX_C, SEL_IEB_2), 1014 PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2),
1016 PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7), 1015 PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7),
1017 PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD), 1016 PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD),
1018 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, I2C3_SDA, SEL_I2C03_0), 1017 PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
1019 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2), 1018 PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
1020 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, IECLK_C, SEL_IEB_2), 1019 PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2),
1021 PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER), 1020 PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER),
1022 PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N), 1021 PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N),
1023 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1), 1022 PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
1024 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2), 1023 PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
1025 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, IERX_C, SEL_IEB_2), 1024 PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2),
1026 PINMUX_IPSR_DATA(IP6_25_23, AVB_COL), 1025 PINMUX_IPSR_DATA(IP6_25_23, AVB_COL),
1027 PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N), 1026 PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N),
1028 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1), 1027 PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
1029 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2), 1028 PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
1030 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1), 1029 PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
1031 PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN), 1030 PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN),
1032 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ETH_MDIO, SEL_ETH_0), 1031 PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0),
1033 PINMUX_IPSR_DATA(IP6_31_29, VI0_G0), 1032 PINMUX_IPSR_DATA(IP6_31_29, VI0_G0),
1034 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1), 1033 PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
1035 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3), 1034 PINMUX_IPSR_MSEL(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3),
1036 PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK), 1035 PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK),
1037 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ADIDATA, SEL_RAD_0), 1036 PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
1038 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, AD_DI, SEL_ADI_0), 1037 PINMUX_IPSR_MSEL(IP6_31_29, AD_DI, SEL_ADI_0),
1039 1038
1040 /* IPSR7 */ 1039 /* IPSR7 */
1041 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ETH_CRS_DV, SEL_ETH_0), 1040 PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
1042 PINMUX_IPSR_DATA(IP7_2_0, VI0_G1), 1041 PINMUX_IPSR_DATA(IP7_2_0, VI0_G1),
1043 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1), 1042 PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
1044 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3), 1043 PINMUX_IPSR_MSEL(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3),
1045 PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0), 1044 PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0),
1046 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ADICS_SAMP, SEL_RAD_0), 1045 PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
1047 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, AD_DO, SEL_ADI_0), 1046 PINMUX_IPSR_MSEL(IP7_2_0, AD_DO, SEL_ADI_0),
1048 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ETH_RX_ER, SEL_ETH_0), 1047 PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
1049 PINMUX_IPSR_DATA(IP7_5_3, VI0_G2), 1048 PINMUX_IPSR_DATA(IP7_5_3, VI0_G2),
1050 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1), 1049 PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
1051 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, CAN0_RX_B, SEL_CAN0_1), 1050 PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
1052 PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1), 1051 PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1),
1053 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ADICLK, SEL_RAD_0), 1052 PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
1054 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, AD_CLK, SEL_ADI_0), 1053 PINMUX_IPSR_MSEL(IP7_5_3, AD_CLK, SEL_ADI_0),
1055 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ETH_RXD0, SEL_ETH_0), 1054 PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
1056 PINMUX_IPSR_DATA(IP7_8_6, VI0_G3), 1055 PINMUX_IPSR_DATA(IP7_8_6, VI0_G3),
1057 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1), 1056 PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
1058 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_TX_B, SEL_CAN0_1), 1057 PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
1059 PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2), 1058 PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2),
1060 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ADICHS0, SEL_RAD_0), 1059 PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
1061 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, AD_NCS_N, SEL_ADI_0), 1060 PINMUX_IPSR_MSEL(IP7_8_6, AD_NCS_N, SEL_ADI_0),
1062 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ETH_RXD1, SEL_ETH_0), 1061 PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
1063 PINMUX_IPSR_DATA(IP7_11_9, VI0_G4), 1062 PINMUX_IPSR_DATA(IP7_11_9, VI0_G4),
1064 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1), 1063 PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
1065 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3), 1064 PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
1066 PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3), 1065 PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3),
1067 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ADICHS1, SEL_RAD_0), 1066 PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0),
1068 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ETH_LINK, SEL_ETH_0), 1067 PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0),
1069 PINMUX_IPSR_DATA(IP7_14_12, VI0_G5), 1068 PINMUX_IPSR_DATA(IP7_14_12, VI0_G5),
1070 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1), 1069 PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
1071 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3), 1070 PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
1072 PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4), 1071 PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4),
1073 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ADICHS2, SEL_RAD_0), 1072 PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0),
1074 PINMUX_IPSR_MODSEL_DATA(IP7_17_15, ETH_REFCLK, SEL_ETH_0), 1073 PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
1075 PINMUX_IPSR_DATA(IP7_17_15, VI0_G6), 1074 PINMUX_IPSR_DATA(IP7_17_15, VI0_G6),
1076 PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2), 1075 PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
1077 PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5), 1076 PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5),
1078 PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1), 1077 PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
1079 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, ETH_TXD1, SEL_ETH_0), 1078 PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0),
1080 PINMUX_IPSR_DATA(IP7_20_18, VI0_G7), 1079 PINMUX_IPSR_DATA(IP7_20_18, VI0_G7),
1081 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2), 1080 PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
1082 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3), 1081 PINMUX_IPSR_MSEL(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3),
1083 PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6), 1082 PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6),
1084 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SSI_WS5_B, SEL_SSI5_1), 1083 PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
1085 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, ETH_TX_EN, SEL_ETH_0), 1084 PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
1086 PINMUX_IPSR_DATA(IP7_23_21, VI0_R0), 1085 PINMUX_IPSR_DATA(IP7_23_21, VI0_R0),
1087 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2), 1086 PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
1088 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3), 1087 PINMUX_IPSR_MSEL(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3),
1089 PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7), 1088 PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7),
1090 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1), 1089 PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
1091 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, ETH_MAGIC, SEL_ETH_0), 1090 PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
1092 PINMUX_IPSR_DATA(IP7_26_24, VI0_R1), 1091 PINMUX_IPSR_DATA(IP7_26_24, VI0_R1),
1093 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1), 1092 PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
1094 PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER), 1093 PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER),
1095 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1), 1094 PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
1096 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, ETH_TXD0, SEL_ETH_0), 1095 PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0),
1097 PINMUX_IPSR_DATA(IP7_29_27, VI0_R2), 1096 PINMUX_IPSR_DATA(IP7_29_27, VI0_R2),
1098 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1), 1097 PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
1099 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4), 1098 PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
1100 PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK), 1099 PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK),
1101 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_WS6_B, SEL_SSI6_1), 1100 PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
1102 PINMUX_IPSR_DATA(IP7_31, DREQ0_N), 1101 PINMUX_IPSR_DATA(IP7_31, DREQ0_N),
1103 PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD), 1102 PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD),
1104 1103
1105 /* IPSR8 */ 1104 /* IPSR8 */
1106 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, ETH_MDC, SEL_ETH_0), 1105 PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0),
1107 PINMUX_IPSR_DATA(IP8_2_0, VI0_R3), 1106 PINMUX_IPSR_DATA(IP8_2_0, VI0_R3),
1108 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1), 1107 PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
1109 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4), 1108 PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
1110 PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC), 1109 PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC),
1111 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1), 1110 PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
1112 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0), 1111 PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
1113 PINMUX_IPSR_DATA(IP8_5_3, VI0_R4), 1112 PINMUX_IPSR_DATA(IP8_5_3, VI0_R4),
1114 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2), 1113 PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
1115 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1), 1114 PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
1116 PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO), 1115 PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO),
1117 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1), 1116 PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
1118 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0), 1117 PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
1119 PINMUX_IPSR_DATA(IP8_8_6, VI0_R5), 1118 PINMUX_IPSR_DATA(IP8_8_6, VI0_R5),
1120 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2), 1119 PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
1121 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1), 1120 PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1122 PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK), 1121 PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK),
1123 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_WS78_B, SEL_SSI7_1), 1122 PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
1124 PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N), 1123 PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N),
1125 PINMUX_IPSR_DATA(IP8_11_9, VI0_R6), 1124 PINMUX_IPSR_DATA(IP8_11_9, VI0_R6),
1126 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3), 1125 PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
1127 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4), 1126 PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
1128 PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC), 1127 PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC),
1129 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1), 1128 PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
1130 PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N), 1129 PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N),
1131 PINMUX_IPSR_DATA(IP8_14_12, VI0_R7), 1130 PINMUX_IPSR_DATA(IP8_14_12, VI0_R7),
1132 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3), 1131 PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
1133 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4), 1132 PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
1134 PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT), 1133 PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT),
1135 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1), 1134 PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
1136 PINMUX_IPSR_MODSEL_DATA(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0), 1135 PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
1137 PINMUX_IPSR_MODSEL_DATA(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1), 1136 PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
1138 PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS), 1137 PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS),
1139 PINMUX_IPSR_MODSEL_DATA(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1), 1138 PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
1140 PINMUX_IPSR_MODSEL_DATA(IP8_19_17, I2C0_SCL, SEL_I2C00_0), 1139 PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
1141 PINMUX_IPSR_MODSEL_DATA(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2), 1140 PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
1142 PINMUX_IPSR_DATA(IP8_19_17, PWM5), 1141 PINMUX_IPSR_DATA(IP8_19_17, PWM5),
1143 PINMUX_IPSR_MODSEL_DATA(IP8_19_17, TCLK1_B, SEL_TMU_1), 1142 PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1),
1144 PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK), 1143 PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK),
1145 PINMUX_IPSR_MODSEL_DATA(IP8_19_17, CAN1_RX_D, SEL_CAN1_3), 1144 PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
1146 PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B), 1145 PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B),
1147 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, I2C0_SDA, SEL_I2C00_0), 1146 PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
1148 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2), 1147 PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
1149 PINMUX_IPSR_DATA(IP8_22_20, TPUTO0), 1148 PINMUX_IPSR_DATA(IP8_22_20, TPUTO0),
1150 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN_CLK, SEL_CAN_0), 1149 PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0),
1151 PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE), 1150 PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE),
1152 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN1_TX_D, SEL_CAN1_3), 1151 PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
1153 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, I2C1_SCL, SEL_I2C01_0), 1152 PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
1154 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0), 1153 PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
1155 PINMUX_IPSR_DATA(IP8_25_23, PWM5_B), 1154 PINMUX_IPSR_DATA(IP8_25_23, PWM5_B),
1156 PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0), 1155 PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0),
1157 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1), 1156 PINMUX_IPSR_MSEL(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1),
1158 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), 1157 PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
1159 PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B), 1158 PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B),
1160 PINMUX_IPSR_MODSEL_DATA(IP8_28_26, I2C1_SDA, SEL_I2C01_0), 1159 PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
1161 PINMUX_IPSR_MODSEL_DATA(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0), 1160 PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
1162 PINMUX_IPSR_DATA(IP8_28_26, IRQ5), 1161 PINMUX_IPSR_DATA(IP8_28_26, IRQ5),
1163 PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1), 1162 PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1),
1164 PINMUX_IPSR_MODSEL_DATA(IP8_28_26, RIF1_CLK_B, SEL_DR2_1), 1163 PINMUX_IPSR_MSEL(IP8_28_26, RIF1_CLK_B, SEL_DR2_1),
1165 PINMUX_IPSR_MODSEL_DATA(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), 1164 PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
1166 PINMUX_IPSR_MODSEL_DATA(IP8_28_26, BPFCLK_C, SEL_DARC_2), 1165 PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
1167 PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD), 1166 PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD),
1168 PINMUX_IPSR_MODSEL_DATA(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0), 1167 PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
1169 PINMUX_IPSR_MODSEL_DATA(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2), 1168 PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
1170 PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2), 1169 PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2),
1171 PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RIF1_D0_B, SEL_DR2_1), 1170 PINMUX_IPSR_MSEL(IP8_31_29, RIF1_D0_B, SEL_DR2_1),
1172 PINMUX_IPSR_MODSEL_DATA(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), 1171 PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
1173 PINMUX_IPSR_MODSEL_DATA(IP8_31_29, FMCLK_C, SEL_DARC_2), 1172 PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
1174 PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RDS_CLK, SEL_RDS_0), 1173 PINMUX_IPSR_MSEL(IP8_31_29, RDS_CLK, SEL_RDS_0),
1175 1174
1176 /* IPSR9 */ 1175 /* IPSR9 */
1177 PINMUX_IPSR_DATA(IP9_2_0, MSIOF0_TXD), 1176 PINMUX_IPSR_DATA(IP9_2_0, MSIOF0_TXD),
1178 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0), 1177 PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
1179 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2), 1178 PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
1180 PINMUX_IPSR_DATA(IP9_2_0, DU1_DR3), 1179 PINMUX_IPSR_DATA(IP9_2_0, DU1_DR3),
1181 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RIF1_D1_B, SEL_DR3_1), 1180 PINMUX_IPSR_MSEL(IP9_2_0, RIF1_D1_B, SEL_DR3_1),
1182 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3), 1181 PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
1183 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, FMIN_C, SEL_DARC_2), 1182 PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
1184 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RDS_DATA, SEL_RDS_0), 1183 PINMUX_IPSR_MSEL(IP9_2_0, RDS_DATA, SEL_RDS_0),
1185 PINMUX_IPSR_DATA(IP9_5_3, MSIOF0_SCK), 1184 PINMUX_IPSR_DATA(IP9_5_3, MSIOF0_SCK),
1186 PINMUX_IPSR_DATA(IP9_5_3, IRQ0), 1185 PINMUX_IPSR_DATA(IP9_5_3, IRQ0),
1187 PINMUX_IPSR_MODSEL_DATA(IP9_5_3, TS_SDATA, SEL_TSIF0_0), 1186 PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
1188 PINMUX_IPSR_DATA(IP9_5_3, DU1_DR4), 1187 PINMUX_IPSR_DATA(IP9_5_3, DU1_DR4),
1189 PINMUX_IPSR_MODSEL_DATA(IP9_5_3, RIF1_SYNC, SEL_DR2_0), 1188 PINMUX_IPSR_MSEL(IP9_5_3, RIF1_SYNC, SEL_DR2_0),
1190 PINMUX_IPSR_DATA(IP9_5_3, TPUTO1_C), 1189 PINMUX_IPSR_DATA(IP9_5_3, TPUTO1_C),
1191 PINMUX_IPSR_DATA(IP9_8_6, MSIOF0_SYNC), 1190 PINMUX_IPSR_DATA(IP9_8_6, MSIOF0_SYNC),
1192 PINMUX_IPSR_DATA(IP9_8_6, PWM1), 1191 PINMUX_IPSR_DATA(IP9_8_6, PWM1),
1193 PINMUX_IPSR_MODSEL_DATA(IP9_8_6, TS_SCK, SEL_TSIF0_0), 1192 PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
1194 PINMUX_IPSR_DATA(IP9_8_6, DU1_DR5), 1193 PINMUX_IPSR_DATA(IP9_8_6, DU1_DR5),
1195 PINMUX_IPSR_MODSEL_DATA(IP9_8_6, RIF1_CLK, SEL_DR2_0), 1194 PINMUX_IPSR_MSEL(IP9_8_6, RIF1_CLK, SEL_DR2_0),
1196 PINMUX_IPSR_MODSEL_DATA(IP9_8_6, BPFCLK_B, SEL_DARC_1), 1195 PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
1197 PINMUX_IPSR_DATA(IP9_11_9, MSIOF0_SS1), 1196 PINMUX_IPSR_DATA(IP9_11_9, MSIOF0_SS1),
1198 PINMUX_IPSR_MODSEL_DATA(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0), 1197 PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
1199 PINMUX_IPSR_MODSEL_DATA(IP9_11_9, TS_SDEN, SEL_TSIF0_0), 1198 PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
1200 PINMUX_IPSR_DATA(IP9_11_9, DU1_DR6), 1199 PINMUX_IPSR_DATA(IP9_11_9, DU1_DR6),
1201 PINMUX_IPSR_MODSEL_DATA(IP9_11_9, RIF1_D0, SEL_DR2_0), 1200 PINMUX_IPSR_MSEL(IP9_11_9, RIF1_D0, SEL_DR2_0),
1202 PINMUX_IPSR_MODSEL_DATA(IP9_11_9, FMCLK_B, SEL_DARC_1), 1201 PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
1203 PINMUX_IPSR_MODSEL_DATA(IP9_11_9, RDS_CLK_B, SEL_RDS_1), 1202 PINMUX_IPSR_MSEL(IP9_11_9, RDS_CLK_B, SEL_RDS_1),
1204 PINMUX_IPSR_DATA(IP9_14_12, MSIOF0_SS2), 1203 PINMUX_IPSR_DATA(IP9_14_12, MSIOF0_SS2),
1205 PINMUX_IPSR_MODSEL_DATA(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0), 1204 PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
1206 PINMUX_IPSR_MODSEL_DATA(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0), 1205 PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
1207 PINMUX_IPSR_DATA(IP9_14_12, DU1_DR7), 1206 PINMUX_IPSR_DATA(IP9_14_12, DU1_DR7),
1208 PINMUX_IPSR_MODSEL_DATA(IP9_14_12, RIF1_D1, SEL_DR3_0), 1207 PINMUX_IPSR_MSEL(IP9_14_12, RIF1_D1, SEL_DR3_0),
1209 PINMUX_IPSR_MODSEL_DATA(IP9_14_12, FMIN_B, SEL_DARC_1), 1208 PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
1210 PINMUX_IPSR_MODSEL_DATA(IP9_14_12, RDS_DATA_B, SEL_RDS_1), 1209 PINMUX_IPSR_MSEL(IP9_14_12, RDS_DATA_B, SEL_RDS_1),
1211 PINMUX_IPSR_MODSEL_DATA(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0), 1210 PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
1212 PINMUX_IPSR_MODSEL_DATA(IP9_16_15, I2C4_SCL, SEL_I2C04_0), 1211 PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
1213 PINMUX_IPSR_DATA(IP9_16_15, PWM6), 1212 PINMUX_IPSR_DATA(IP9_16_15, PWM6),
1214 PINMUX_IPSR_DATA(IP9_16_15, DU1_DG0), 1213 PINMUX_IPSR_DATA(IP9_16_15, DU1_DG0),
1215 PINMUX_IPSR_MODSEL_DATA(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0), 1214 PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0),
1216 PINMUX_IPSR_MODSEL_DATA(IP9_18_17, I2C4_SDA, SEL_I2C04_0), 1215 PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0),
1217 PINMUX_IPSR_DATA(IP9_18_17, TPUTO1), 1216 PINMUX_IPSR_DATA(IP9_18_17, TPUTO1),
1218 PINMUX_IPSR_DATA(IP9_18_17, DU1_DG1), 1217 PINMUX_IPSR_DATA(IP9_18_17, DU1_DG1),
1219 PINMUX_IPSR_DATA(IP9_21_19, HSCIF1_HSCK), 1218 PINMUX_IPSR_DATA(IP9_21_19, HSCIF1_HSCK),
1220 PINMUX_IPSR_DATA(IP9_21_19, PWM2), 1219 PINMUX_IPSR_DATA(IP9_21_19, PWM2),
1221 PINMUX_IPSR_MODSEL_DATA(IP9_21_19, IETX, SEL_IEB_0), 1220 PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0),
1222 PINMUX_IPSR_DATA(IP9_21_19, DU1_DG2), 1221 PINMUX_IPSR_DATA(IP9_21_19, DU1_DG2),
1223 PINMUX_IPSR_MODSEL_DATA(IP9_21_19, REMOCON_B, SEL_RCN_1), 1222 PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
1224 PINMUX_IPSR_MODSEL_DATA(IP9_21_19, SPEEDIN_B, SEL_RSP_1), 1223 PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
1225 PINMUX_IPSR_MODSEL_DATA(IP9_21_19, VSP_B, SEL_SPDM_1), 1224 PINMUX_IPSR_MSEL(IP9_21_19, VSP_B, SEL_SPDM_1),
1226 PINMUX_IPSR_MODSEL_DATA(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0), 1225 PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
1227 PINMUX_IPSR_MODSEL_DATA(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0), 1226 PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
1228 PINMUX_IPSR_MODSEL_DATA(IP9_24_22, IECLK, SEL_IEB_0), 1227 PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
1229 PINMUX_IPSR_DATA(IP9_24_22, DU1_DG3), 1228 PINMUX_IPSR_DATA(IP9_24_22, DU1_DG3),
1230 PINMUX_IPSR_MODSEL_DATA(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1), 1229 PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
1231 PINMUX_IPSR_DATA(IP9_24_22, CAN_DEBUG_HW_TRIGGER), 1230 PINMUX_IPSR_DATA(IP9_24_22, CAN_DEBUG_HW_TRIGGER),
1232 PINMUX_IPSR_DATA(IP9_24_22, CC50_STATE32), 1231 PINMUX_IPSR_DATA(IP9_24_22, CC50_STATE32),
1233 PINMUX_IPSR_MODSEL_DATA(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0), 1232 PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
1234 PINMUX_IPSR_MODSEL_DATA(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0), 1233 PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
1235 PINMUX_IPSR_MODSEL_DATA(IP9_27_25, IERX, SEL_IEB_0), 1234 PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
1236 PINMUX_IPSR_DATA(IP9_27_25, DU1_DG4), 1235 PINMUX_IPSR_DATA(IP9_27_25, DU1_DG4),
1237 PINMUX_IPSR_MODSEL_DATA(IP9_27_25, SSI_WS1_B, SEL_SSI1_1), 1236 PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
1238 PINMUX_IPSR_DATA(IP9_27_25, CAN_STEP0), 1237 PINMUX_IPSR_DATA(IP9_27_25, CAN_STEP0),
1239 PINMUX_IPSR_DATA(IP9_27_25, CC50_STATE33), 1238 PINMUX_IPSR_DATA(IP9_27_25, CC50_STATE33),
1240 PINMUX_IPSR_MODSEL_DATA(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0), 1239 PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
1241 PINMUX_IPSR_DATA(IP9_30_28, PWM3), 1240 PINMUX_IPSR_DATA(IP9_30_28, PWM3),
1242 PINMUX_IPSR_MODSEL_DATA(IP9_30_28, TCLK2, SEL_TMU_0), 1241 PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
1243 PINMUX_IPSR_DATA(IP9_30_28, DU1_DG5), 1242 PINMUX_IPSR_DATA(IP9_30_28, DU1_DG5),
1244 PINMUX_IPSR_MODSEL_DATA(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1), 1243 PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
1245 PINMUX_IPSR_DATA(IP9_30_28, CAN_TXCLK), 1244 PINMUX_IPSR_DATA(IP9_30_28, CAN_TXCLK),
1246 PINMUX_IPSR_DATA(IP9_30_28, CC50_STATE34), 1245 PINMUX_IPSR_DATA(IP9_30_28, CC50_STATE34),
1247 1246
1248 /* IPSR10 */ 1247 /* IPSR10 */
1249 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0), 1248 PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
1250 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, IIC0_SCL, SEL_IIC00_0), 1249 PINMUX_IPSR_MSEL(IP10_2_0, IIC0_SCL, SEL_IIC00_0),
1251 PINMUX_IPSR_DATA(IP10_2_0, DU1_DG6), 1250 PINMUX_IPSR_DATA(IP10_2_0, DU1_DG6),
1252 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1), 1251 PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
1253 PINMUX_IPSR_DATA(IP10_2_0, CAN_DEBUGOUT0), 1252 PINMUX_IPSR_DATA(IP10_2_0, CAN_DEBUGOUT0),
1254 PINMUX_IPSR_DATA(IP10_2_0, CC50_STATE35), 1253 PINMUX_IPSR_DATA(IP10_2_0, CC50_STATE35),
1255 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0), 1254 PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
1256 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, IIC0_SDA, SEL_IIC00_0), 1255 PINMUX_IPSR_MSEL(IP10_5_3, IIC0_SDA, SEL_IIC00_0),
1257 PINMUX_IPSR_DATA(IP10_5_3, DU1_DG7), 1256 PINMUX_IPSR_DATA(IP10_5_3, DU1_DG7),
1258 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_WS2_B, SEL_SSI2_1), 1257 PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
1259 PINMUX_IPSR_DATA(IP10_5_3, CAN_DEBUGOUT1), 1258 PINMUX_IPSR_DATA(IP10_5_3, CAN_DEBUGOUT1),
1260 PINMUX_IPSR_DATA(IP10_5_3, CC50_STATE36), 1259 PINMUX_IPSR_DATA(IP10_5_3, CC50_STATE36),
1261 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0), 1260 PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
1262 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IIC1_SCL, SEL_IIC01_0), 1261 PINMUX_IPSR_MSEL(IP10_8_6, IIC1_SCL, SEL_IIC01_0),
1263 PINMUX_IPSR_DATA(IP10_8_6, DU1_DB0), 1262 PINMUX_IPSR_DATA(IP10_8_6, DU1_DB0),
1264 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1), 1263 PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
1265 PINMUX_IPSR_DATA(IP10_8_6, USB0_EXTLP), 1264 PINMUX_IPSR_DATA(IP10_8_6, USB0_EXTLP),
1266 PINMUX_IPSR_DATA(IP10_8_6, CAN_DEBUGOUT2), 1265 PINMUX_IPSR_DATA(IP10_8_6, CAN_DEBUGOUT2),
1267 PINMUX_IPSR_DATA(IP10_8_6, CC50_STATE37), 1266 PINMUX_IPSR_DATA(IP10_8_6, CC50_STATE37),
1268 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0), 1267 PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
1269 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IIC1_SDA, SEL_IIC01_0), 1268 PINMUX_IPSR_MSEL(IP10_11_9, IIC1_SDA, SEL_IIC01_0),
1270 PINMUX_IPSR_DATA(IP10_11_9, DU1_DB1), 1269 PINMUX_IPSR_DATA(IP10_11_9, DU1_DB1),
1271 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1), 1270 PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
1272 PINMUX_IPSR_DATA(IP10_11_9, USB0_OVC1), 1271 PINMUX_IPSR_DATA(IP10_11_9, USB0_OVC1),
1273 PINMUX_IPSR_DATA(IP10_11_9, CAN_DEBUGOUT3), 1272 PINMUX_IPSR_DATA(IP10_11_9, CAN_DEBUGOUT3),
1274 PINMUX_IPSR_DATA(IP10_11_9, CC50_STATE38), 1273 PINMUX_IPSR_DATA(IP10_11_9, CC50_STATE38),
1275 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0), 1274 PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
1276 PINMUX_IPSR_DATA(IP10_14_12, IRQ1), 1275 PINMUX_IPSR_DATA(IP10_14_12, IRQ1),
1277 PINMUX_IPSR_DATA(IP10_14_12, DU1_DB2), 1276 PINMUX_IPSR_DATA(IP10_14_12, DU1_DB2),
1278 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SSI_WS9_B, SEL_SSI9_1), 1277 PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
1279 PINMUX_IPSR_DATA(IP10_14_12, USB0_IDIN), 1278 PINMUX_IPSR_DATA(IP10_14_12, USB0_IDIN),
1280 PINMUX_IPSR_DATA(IP10_14_12, CAN_DEBUGOUT4), 1279 PINMUX_IPSR_DATA(IP10_14_12, CAN_DEBUGOUT4),
1281 PINMUX_IPSR_DATA(IP10_14_12, CC50_STATE39), 1280 PINMUX_IPSR_DATA(IP10_14_12, CC50_STATE39),
1282 PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0), 1281 PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
1283 PINMUX_IPSR_DATA(IP10_17_15, IRQ2), 1282 PINMUX_IPSR_DATA(IP10_17_15, IRQ2),
1284 PINMUX_IPSR_MODSEL_DATA(IP10_17_15, BPFCLK_D, SEL_DARC_3), 1283 PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
1285 PINMUX_IPSR_DATA(IP10_17_15, DU1_DB3), 1284 PINMUX_IPSR_DATA(IP10_17_15, DU1_DB3),
1286 PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1), 1285 PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
1287 PINMUX_IPSR_DATA(IP10_17_15, TANS2), 1286 PINMUX_IPSR_DATA(IP10_17_15, TANS2),
1288 PINMUX_IPSR_DATA(IP10_17_15, CAN_DEBUGOUT5), 1287 PINMUX_IPSR_DATA(IP10_17_15, CAN_DEBUGOUT5),
1289 PINMUX_IPSR_DATA(IP10_17_15, CC50_OSCOUT), 1288 PINMUX_IPSR_DATA(IP10_17_15, CC50_OSCOUT),
1290 PINMUX_IPSR_MODSEL_DATA(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0), 1289 PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
1291 PINMUX_IPSR_MODSEL_DATA(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4), 1290 PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
1292 PINMUX_IPSR_MODSEL_DATA(IP10_20_18, FMCLK_D, SEL_DARC_3), 1291 PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
1293 PINMUX_IPSR_DATA(IP10_20_18, DU1_DB4), 1292 PINMUX_IPSR_DATA(IP10_20_18, DU1_DB4),
1294 PINMUX_IPSR_MODSEL_DATA(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2), 1293 PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
1295 PINMUX_IPSR_MODSEL_DATA(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1), 1294 PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
1296 PINMUX_IPSR_DATA(IP10_20_18, CAN_DEBUGOUT6), 1295 PINMUX_IPSR_DATA(IP10_20_18, CAN_DEBUGOUT6),
1297 PINMUX_IPSR_MODSEL_DATA(IP10_20_18, RDS_CLK_C, SEL_RDS_2), 1296 PINMUX_IPSR_MSEL(IP10_20_18, RDS_CLK_C, SEL_RDS_2),
1298 PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0), 1297 PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
1299 PINMUX_IPSR_MODSEL_DATA(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4), 1298 PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
1300 PINMUX_IPSR_MODSEL_DATA(IP10_23_21, FMIN_D, SEL_DARC_3), 1299 PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
1301 PINMUX_IPSR_DATA(IP10_23_21, DU1_DB5), 1300 PINMUX_IPSR_DATA(IP10_23_21, DU1_DB5),
1302 PINMUX_IPSR_MODSEL_DATA(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2), 1301 PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
1303 PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SSI_WS4_B, SEL_SSI4_1), 1302 PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
1304 PINMUX_IPSR_DATA(IP10_23_21, CAN_DEBUGOUT7), 1303 PINMUX_IPSR_DATA(IP10_23_21, CAN_DEBUGOUT7),
1305 PINMUX_IPSR_MODSEL_DATA(IP10_23_21, RDS_DATA_C, SEL_RDS_2), 1304 PINMUX_IPSR_MSEL(IP10_23_21, RDS_DATA_C, SEL_RDS_2),
1306 PINMUX_IPSR_MODSEL_DATA(IP10_26_24, I2C2_SCL, SEL_I2C02_0), 1305 PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
1307 PINMUX_IPSR_MODSEL_DATA(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0), 1306 PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
1308 PINMUX_IPSR_DATA(IP10_26_24, DU1_DB6), 1307 PINMUX_IPSR_DATA(IP10_26_24, DU1_DB6),
1309 PINMUX_IPSR_MODSEL_DATA(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2), 1308 PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
1310 PINMUX_IPSR_MODSEL_DATA(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1), 1309 PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
1311 PINMUX_IPSR_DATA(IP10_26_24, CAN_DEBUGOUT8), 1310 PINMUX_IPSR_DATA(IP10_26_24, CAN_DEBUGOUT8),
1312 PINMUX_IPSR_MODSEL_DATA(IP10_29_27, I2C2_SDA, SEL_I2C02_0), 1311 PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
1313 PINMUX_IPSR_MODSEL_DATA(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0), 1312 PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
1314 PINMUX_IPSR_DATA(IP10_29_27, DU1_DB7), 1313 PINMUX_IPSR_DATA(IP10_29_27, DU1_DB7),
1315 PINMUX_IPSR_MODSEL_DATA(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2), 1314 PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
1316 PINMUX_IPSR_DATA(IP10_29_27, CAN_DEBUGOUT9), 1315 PINMUX_IPSR_DATA(IP10_29_27, CAN_DEBUGOUT9),
1317 PINMUX_IPSR_MODSEL_DATA(IP10_31_30, SSI_SCK5, SEL_SSI5_0), 1316 PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
1318 PINMUX_IPSR_MODSEL_DATA(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0), 1317 PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
1319 PINMUX_IPSR_DATA(IP10_31_30, DU1_DOTCLKIN), 1318 PINMUX_IPSR_DATA(IP10_31_30, DU1_DOTCLKIN),
1320 PINMUX_IPSR_DATA(IP10_31_30, CAN_DEBUGOUT10), 1319 PINMUX_IPSR_DATA(IP10_31_30, CAN_DEBUGOUT10),
1321 1320
1322 /* IPSR11 */ 1321 /* IPSR11 */
1323 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SSI_WS5, SEL_SSI5_0), 1322 PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
1324 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0), 1323 PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1325 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2), 1324 PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
1326 PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0), 1325 PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0),
1327 PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11), 1326 PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11),
1328 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SSI_SDATA5, SEL_SSI5_0), 1327 PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
1329 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0), 1328 PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
1330 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2), 1329 PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
1331 PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1), 1330 PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1),
1332 PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12), 1331 PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12),
1333 PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SSI_SCK6, SEL_SSI6_0), 1332 PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
1334 PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1), 1333 PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
1335 PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC), 1334 PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
1336 PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13), 1335 PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13),
1337 PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SSI_WS6, SEL_SSI6_0), 1336 PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
1338 PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1), 1337 PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
1339 PINMUX_IPSR_MODSEL_DATA(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2), 1338 PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
1340 PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC), 1339 PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
1341 PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14), 1340 PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14),
1342 PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SSI_SDATA6, SEL_SSI6_0), 1341 PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
1343 PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1), 1342 PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
1344 PINMUX_IPSR_MODSEL_DATA(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2), 1343 PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
1345 PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE), 1344 PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1346 PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15), 1345 PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15),
1347 PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SSI_SCK78, SEL_SSI7_0), 1346 PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
1348 PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1), 1347 PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
1349 PINMUX_IPSR_MODSEL_DATA(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2), 1348 PINMUX_IPSR_MSEL(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2),
1350 PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP), 1349 PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP),
1351 PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SSI_WS78, SEL_SSI7_0), 1350 PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0),
1352 PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1), 1351 PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
1353 PINMUX_IPSR_MODSEL_DATA(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2), 1352 PINMUX_IPSR_MSEL(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2),
1354 PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE), 1353 PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE),
1355 PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SSI_SDATA7, SEL_SSI7_0), 1354 PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
1356 PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1), 1355 PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
1357 PINMUX_IPSR_DATA(IP11_20_18, IRQ8), 1356 PINMUX_IPSR_DATA(IP11_20_18, IRQ8),
1358 PINMUX_IPSR_MODSEL_DATA(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3), 1357 PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
1359 PINMUX_IPSR_MODSEL_DATA(IP11_20_18, CAN_CLK_D, SEL_CAN_3), 1358 PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
1360 PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N), 1359 PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N),
1361 PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129), 1360 PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129),
1362 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1), 1361 PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
1363 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3), 1362 PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
1364 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, ADIDATA_B, SEL_RAD_1), 1363 PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
1365 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, AD_DI_B, SEL_ADI_1), 1364 PINMUX_IPSR_MSEL(IP11_23_21, AD_DI_B, SEL_ADI_1),
1366 PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N), 1365 PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N),
1367 PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129), 1366 PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129),
1368 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1), 1367 PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
1369 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3), 1368 PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
1370 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), 1369 PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
1371 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, AD_DO_B, SEL_ADI_1), 1370 PINMUX_IPSR_MSEL(IP11_26_24, AD_DO_B, SEL_ADI_1),
1372 PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0), 1371 PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0),
1373 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1), 1372 PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
1374 PINMUX_IPSR_DATA(IP11_29_27, PWM0_B), 1373 PINMUX_IPSR_DATA(IP11_29_27, PWM0_B),
1375 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, ADICLK_B, SEL_RAD_1), 1374 PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
1376 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, AD_CLK_B, SEL_ADI_1), 1375 PINMUX_IPSR_MSEL(IP11_29_27, AD_CLK_B, SEL_ADI_1),
1377 1376
1378 /* IPSR12 */ 1377 /* IPSR12 */
1379 PINMUX_IPSR_DATA(IP12_2_0, SSI_SCK34), 1378 PINMUX_IPSR_DATA(IP12_2_0, SSI_SCK34),
1380 PINMUX_IPSR_MODSEL_DATA(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1), 1379 PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
1381 PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2), 1380 PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
1382 PINMUX_IPSR_MODSEL_DATA(IP12_2_0, ADICHS0_B, SEL_RAD_1), 1381 PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
1383 PINMUX_IPSR_MODSEL_DATA(IP12_2_0, AD_NCS_N_B, SEL_ADI_1), 1382 PINMUX_IPSR_MSEL(IP12_2_0, AD_NCS_N_B, SEL_ADI_1),
1384 PINMUX_IPSR_MODSEL_DATA(IP12_2_0, DREQ1_N_B, SEL_LBS_1), 1383 PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
1385 PINMUX_IPSR_DATA(IP12_5_3, SSI_WS34), 1384 PINMUX_IPSR_DATA(IP12_5_3, SSI_WS34),
1386 PINMUX_IPSR_MODSEL_DATA(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1), 1385 PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
1387 PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2), 1386 PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
1388 PINMUX_IPSR_MODSEL_DATA(IP12_5_3, ADICHS1_B, SEL_RAD_1), 1387 PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1),
1389 PINMUX_IPSR_MODSEL_DATA(IP12_5_3, CAN1_RX_C, SEL_CAN1_2), 1388 PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
1390 PINMUX_IPSR_MODSEL_DATA(IP12_5_3, DACK1_B, SEL_LBS_1), 1389 PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1),
1391 PINMUX_IPSR_DATA(IP12_8_6, SSI_SDATA3), 1390 PINMUX_IPSR_DATA(IP12_8_6, SSI_SDATA3),
1392 PINMUX_IPSR_MODSEL_DATA(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1), 1391 PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
1393 PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2), 1392 PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
1394 PINMUX_IPSR_MODSEL_DATA(IP12_8_6, ADICHS2_B, SEL_RAD_1), 1393 PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1),
1395 PINMUX_IPSR_MODSEL_DATA(IP12_8_6, CAN1_TX_C, SEL_CAN1_2), 1394 PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
1396 PINMUX_IPSR_DATA(IP12_8_6, DREQ2_N), 1395 PINMUX_IPSR_DATA(IP12_8_6, DREQ2_N),
1397 PINMUX_IPSR_MODSEL_DATA(IP12_10_9, SSI_SCK4, SEL_SSI4_0), 1396 PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
1398 PINMUX_IPSR_DATA(IP12_10_9, MLB_CLK), 1397 PINMUX_IPSR_DATA(IP12_10_9, MLB_CLK),
1399 PINMUX_IPSR_MODSEL_DATA(IP12_10_9, IETX_B, SEL_IEB_1), 1398 PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
1400 PINMUX_IPSR_DATA(IP12_10_9, IRD_TX), 1399 PINMUX_IPSR_DATA(IP12_10_9, IRD_TX),
1401 PINMUX_IPSR_MODSEL_DATA(IP12_12_11, SSI_WS4, SEL_SSI4_0), 1400 PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
1402 PINMUX_IPSR_DATA(IP12_12_11, MLB_SIG), 1401 PINMUX_IPSR_DATA(IP12_12_11, MLB_SIG),
1403 PINMUX_IPSR_MODSEL_DATA(IP12_12_11, IECLK_B, SEL_IEB_1), 1402 PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
1404 PINMUX_IPSR_DATA(IP12_12_11, IRD_RX), 1403 PINMUX_IPSR_DATA(IP12_12_11, IRD_RX),
1405 PINMUX_IPSR_MODSEL_DATA(IP12_14_13, SSI_SDATA4, SEL_SSI4_0), 1404 PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
1406 PINMUX_IPSR_DATA(IP12_14_13, MLB_DAT), 1405 PINMUX_IPSR_DATA(IP12_14_13, MLB_DAT),
1407 PINMUX_IPSR_MODSEL_DATA(IP12_14_13, IERX_B, SEL_IEB_1), 1406 PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
1408 PINMUX_IPSR_DATA(IP12_14_13, IRD_SCK), 1407 PINMUX_IPSR_DATA(IP12_14_13, IRD_SCK),
1409 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SSI_SDATA8, SEL_SSI8_0), 1408 PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
1410 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1), 1409 PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
1411 PINMUX_IPSR_DATA(IP12_17_15, PWM1_B), 1410 PINMUX_IPSR_DATA(IP12_17_15, PWM1_B),
1412 PINMUX_IPSR_DATA(IP12_17_15, IRQ9), 1411 PINMUX_IPSR_DATA(IP12_17_15, IRQ9),
1413 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, REMOCON, SEL_RCN_0), 1412 PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0),
1414 PINMUX_IPSR_DATA(IP12_17_15, DACK2), 1413 PINMUX_IPSR_DATA(IP12_17_15, DACK2),
1415 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, ETH_MDIO_B, SEL_ETH_1), 1414 PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
1416 PINMUX_IPSR_MODSEL_DATA(IP12_20_18, SSI_SCK1, SEL_SSI1_0), 1415 PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
1417 PINMUX_IPSR_MODSEL_DATA(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1), 1416 PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1),
1418 PINMUX_IPSR_MODSEL_DATA(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2), 1417 PINMUX_IPSR_MSEL(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2),
1419 PINMUX_IPSR_DATA(IP12_20_18, VI1_CLK), 1418 PINMUX_IPSR_DATA(IP12_20_18, VI1_CLK),
1420 PINMUX_IPSR_MODSEL_DATA(IP12_20_18, CAN0_RX_D, SEL_CAN0_3), 1419 PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
1421 PINMUX_IPSR_MODSEL_DATA(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0), 1420 PINMUX_IPSR_MSEL(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0),
1422 PINMUX_IPSR_MODSEL_DATA(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1), 1421 PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
1423 PINMUX_IPSR_MODSEL_DATA(IP12_23_21, SSI_WS1, SEL_SSI1_0), 1422 PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
1424 PINMUX_IPSR_MODSEL_DATA(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1), 1423 PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
1425 PINMUX_IPSR_MODSEL_DATA(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2), 1424 PINMUX_IPSR_MSEL(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2),
1426 PINMUX_IPSR_DATA(IP12_23_21, VI1_DATA0), 1425 PINMUX_IPSR_DATA(IP12_23_21, VI1_DATA0),
1427 PINMUX_IPSR_MODSEL_DATA(IP12_23_21, CAN0_TX_D, SEL_CAN0_3), 1426 PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
1428 PINMUX_IPSR_MODSEL_DATA(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0), 1427 PINMUX_IPSR_MSEL(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0),
1429 PINMUX_IPSR_MODSEL_DATA(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1), 1428 PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
1430 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SSI_SDATA1, SEL_SSI1_0), 1429 PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
1431 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1), 1430 PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
1432 PINMUX_IPSR_DATA(IP12_26_24, VI1_DATA1), 1431 PINMUX_IPSR_DATA(IP12_26_24, VI1_DATA1),
1433 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SDATA, SEL_FSN_0), 1432 PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0),
1434 PINMUX_IPSR_DATA(IP12_26_24, ATAG0_N), 1433 PINMUX_IPSR_DATA(IP12_26_24, ATAG0_N),
1435 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ETH_RXD0_B, SEL_ETH_1), 1434 PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
1436 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SSI_SCK2, SEL_SSI2_0), 1435 PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
1437 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1), 1436 PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
1438 PINMUX_IPSR_DATA(IP12_29_27, VI1_DATA2), 1437 PINMUX_IPSR_DATA(IP12_29_27, VI1_DATA2),
1439 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MDATA, SEL_FSN_0), 1438 PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0),
1440 PINMUX_IPSR_DATA(IP12_29_27, ATAWR0_N), 1439 PINMUX_IPSR_DATA(IP12_29_27, ATAWR0_N),
1441 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ETH_RXD1_B, SEL_ETH_1), 1440 PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
1442 1441
1443 /* IPSR13 */ 1442 /* IPSR13 */
1444 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_WS2, SEL_SSI2_0), 1443 PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0),
1445 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1), 1444 PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
1446 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3), 1445 PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
1447 PINMUX_IPSR_DATA(IP13_2_0, VI1_DATA3), 1446 PINMUX_IPSR_DATA(IP13_2_0, VI1_DATA3),
1448 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCKZ, SEL_FSN_0), 1447 PINMUX_IPSR_MSEL(IP13_2_0, SCKZ, SEL_FSN_0),
1449 PINMUX_IPSR_DATA(IP13_2_0, ATACS00_N), 1448 PINMUX_IPSR_DATA(IP13_2_0, ATACS00_N),
1450 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ETH_LINK_B, SEL_ETH_1), 1449 PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
1451 PINMUX_IPSR_MODSEL_DATA(IP13_5_3, SSI_SDATA2, SEL_SSI2_0), 1450 PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
1452 PINMUX_IPSR_MODSEL_DATA(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1), 1451 PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
1453 PINMUX_IPSR_MODSEL_DATA(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3), 1452 PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
1454 PINMUX_IPSR_DATA(IP13_5_3, VI1_DATA4), 1453 PINMUX_IPSR_DATA(IP13_5_3, VI1_DATA4),
1455 PINMUX_IPSR_MODSEL_DATA(IP13_5_3, STM_N, SEL_FSN_0), 1454 PINMUX_IPSR_MSEL(IP13_5_3, STM_N, SEL_FSN_0),
1456 PINMUX_IPSR_DATA(IP13_5_3, ATACS10_N), 1455 PINMUX_IPSR_DATA(IP13_5_3, ATACS10_N),
1457 PINMUX_IPSR_MODSEL_DATA(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1), 1456 PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
1458 PINMUX_IPSR_MODSEL_DATA(IP13_8_6, SSI_SCK9, SEL_SSI9_0), 1457 PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
1459 PINMUX_IPSR_MODSEL_DATA(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1), 1458 PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
1460 PINMUX_IPSR_DATA(IP13_8_6, PWM2_B), 1459 PINMUX_IPSR_DATA(IP13_8_6, PWM2_B),
1461 PINMUX_IPSR_DATA(IP13_8_6, VI1_DATA5), 1460 PINMUX_IPSR_DATA(IP13_8_6, VI1_DATA5),
1462 PINMUX_IPSR_MODSEL_DATA(IP13_8_6, MTS_N, SEL_FSN_0), 1461 PINMUX_IPSR_MSEL(IP13_8_6, MTS_N, SEL_FSN_0),
1463 PINMUX_IPSR_DATA(IP13_8_6, EX_WAIT1), 1462 PINMUX_IPSR_DATA(IP13_8_6, EX_WAIT1),
1464 PINMUX_IPSR_MODSEL_DATA(IP13_8_6, ETH_TXD1_B, SEL_ETH_1), 1463 PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
1465 PINMUX_IPSR_MODSEL_DATA(IP13_11_9, SSI_WS9, SEL_SSI9_0), 1464 PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
1466 PINMUX_IPSR_MODSEL_DATA(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1), 1465 PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1),
1467 PINMUX_IPSR_MODSEL_DATA(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4), 1466 PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4),
1468 PINMUX_IPSR_DATA(IP13_11_9, VI1_DATA6), 1467 PINMUX_IPSR_DATA(IP13_11_9, VI1_DATA6),
1469 PINMUX_IPSR_DATA(IP13_11_9, ATARD0_N), 1468 PINMUX_IPSR_DATA(IP13_11_9, ATARD0_N),
1470 PINMUX_IPSR_MODSEL_DATA(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1), 1469 PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1),
1471 PINMUX_IPSR_MODSEL_DATA(IP13_14_12, SSI_SDATA9, SEL_SSI9_0), 1470 PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0),
1472 PINMUX_IPSR_MODSEL_DATA(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1), 1471 PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1),
1473 PINMUX_IPSR_MODSEL_DATA(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4), 1472 PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4),
1474 PINMUX_IPSR_DATA(IP13_14_12, VI1_DATA7), 1473 PINMUX_IPSR_DATA(IP13_14_12, VI1_DATA7),
1475 PINMUX_IPSR_DATA(IP13_14_12, ATADIR0_N), 1474 PINMUX_IPSR_DATA(IP13_14_12, ATADIR0_N),
1476 PINMUX_IPSR_MODSEL_DATA(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1), 1475 PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1),
1477 PINMUX_IPSR_MODSEL_DATA(IP13_17_15, AUDIO_CLKA, SEL_ADG_0), 1476 PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0),
1478 PINMUX_IPSR_MODSEL_DATA(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1), 1477 PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
1479 PINMUX_IPSR_MODSEL_DATA(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3), 1478 PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
1480 PINMUX_IPSR_DATA(IP13_17_15, VI1_CLKENB), 1479 PINMUX_IPSR_DATA(IP13_17_15, VI1_CLKENB),
1481 PINMUX_IPSR_MODSEL_DATA(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2), 1480 PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
1482 PINMUX_IPSR_MODSEL_DATA(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1), 1481 PINMUX_IPSR_MSEL(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1),
1483 PINMUX_IPSR_MODSEL_DATA(IP13_17_15, ETH_TXD0_B, SEL_ETH_1), 1482 PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
1484 PINMUX_IPSR_MODSEL_DATA(IP13_20_18, AUDIO_CLKB, SEL_ADG_0), 1483 PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
1485 PINMUX_IPSR_MODSEL_DATA(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1), 1484 PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
1486 PINMUX_IPSR_MODSEL_DATA(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3), 1485 PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
1487 PINMUX_IPSR_DATA(IP13_20_18, VI1_FIELD), 1486 PINMUX_IPSR_DATA(IP13_20_18, VI1_FIELD),
1488 PINMUX_IPSR_MODSEL_DATA(IP13_20_18, TS_SCK_C, SEL_TSIF0_2), 1487 PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
1489 PINMUX_IPSR_MODSEL_DATA(IP13_20_18, RIF0_CLK_B, SEL_DR0_1), 1488 PINMUX_IPSR_MSEL(IP13_20_18, RIF0_CLK_B, SEL_DR0_1),
1490 PINMUX_IPSR_MODSEL_DATA(IP13_20_18, BPFCLK_E, SEL_DARC_4), 1489 PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
1491 PINMUX_IPSR_MODSEL_DATA(IP13_20_18, ETH_MDC_B, SEL_ETH_1), 1490 PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
1492 PINMUX_IPSR_MODSEL_DATA(IP13_23_21, AUDIO_CLKC, SEL_ADG_0), 1491 PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
1493 PINMUX_IPSR_MODSEL_DATA(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1), 1492 PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
1494 PINMUX_IPSR_MODSEL_DATA(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3), 1493 PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
1495 PINMUX_IPSR_DATA(IP13_23_21, VI1_HSYNC_N), 1494 PINMUX_IPSR_DATA(IP13_23_21, VI1_HSYNC_N),
1496 PINMUX_IPSR_MODSEL_DATA(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2), 1495 PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
1497 PINMUX_IPSR_MODSEL_DATA(IP13_23_21, RIF0_D0_B, SEL_DR0_1), 1496 PINMUX_IPSR_MSEL(IP13_23_21, RIF0_D0_B, SEL_DR0_1),
1498 PINMUX_IPSR_MODSEL_DATA(IP13_23_21, FMCLK_E, SEL_DARC_4), 1497 PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
1499 PINMUX_IPSR_MODSEL_DATA(IP13_23_21, RDS_CLK_D, SEL_RDS_3), 1498 PINMUX_IPSR_MSEL(IP13_23_21, RDS_CLK_D, SEL_RDS_3),
1500 PINMUX_IPSR_MODSEL_DATA(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0), 1499 PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
1501 PINMUX_IPSR_MODSEL_DATA(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1), 1500 PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
1502 PINMUX_IPSR_MODSEL_DATA(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3), 1501 PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
1503 PINMUX_IPSR_DATA(IP13_26_24, VI1_VSYNC_N), 1502 PINMUX_IPSR_DATA(IP13_26_24, VI1_VSYNC_N),
1504 PINMUX_IPSR_MODSEL_DATA(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2), 1503 PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
1505 PINMUX_IPSR_MODSEL_DATA(IP13_26_24, RIF0_D1_B, SEL_DR1_1), 1504 PINMUX_IPSR_MSEL(IP13_26_24, RIF0_D1_B, SEL_DR1_1),
1506 PINMUX_IPSR_MODSEL_DATA(IP13_26_24, FMIN_E, SEL_DARC_4), 1505 PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
1507 PINMUX_IPSR_MODSEL_DATA(IP13_26_24, RDS_DATA_D, SEL_RDS_3), 1506 PINMUX_IPSR_MSEL(IP13_26_24, RDS_DATA_D, SEL_RDS_3),
1508}; 1507};
1509 1508
1510static const struct sh_pfc_pin pinmux_pins[] = { 1509static const struct sh_pfc_pin pinmux_pins[] = {
@@ -2197,13 +2196,6 @@ static const unsigned int scif0_data_pins[] = {
2197static const unsigned int scif0_data_mux[] = { 2196static const unsigned int scif0_data_mux[] = {
2198 SCIF0_RXD_MARK, SCIF0_TXD_MARK, 2197 SCIF0_RXD_MARK, SCIF0_TXD_MARK,
2199}; 2198};
2200static const unsigned int scif0_clk_pins[] = {
2201 /* SCK */
2202 RCAR_GP_PIN(1, 23),
2203};
2204static const unsigned int scif0_clk_mux[] = {
2205 SCIF_CLK_MARK,
2206};
2207static const unsigned int scif0_data_b_pins[] = { 2199static const unsigned int scif0_data_b_pins[] = {
2208 /* RX, TX */ 2200 /* RX, TX */
2209 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), 2201 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
@@ -2211,13 +2203,6 @@ static const unsigned int scif0_data_b_pins[] = {
2211static const unsigned int scif0_data_b_mux[] = { 2203static const unsigned int scif0_data_b_mux[] = {
2212 SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK, 2204 SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK,
2213}; 2205};
2214static const unsigned int scif0_clk_b_pins[] = {
2215 /* SCK */
2216 RCAR_GP_PIN(3, 29),
2217};
2218static const unsigned int scif0_clk_b_mux[] = {
2219 SCIF_CLK_B_MARK,
2220};
2221static const unsigned int scif0_data_c_pins[] = { 2206static const unsigned int scif0_data_c_pins[] = {
2222 /* RX, TX */ 2207 /* RX, TX */
2223 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), 2208 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
@@ -2788,6 +2773,146 @@ static const unsigned int usb1_mux[] = {
2788 USB1_PWEN_MARK, 2773 USB1_PWEN_MARK,
2789 USB1_OVC_MARK, 2774 USB1_OVC_MARK,
2790}; 2775};
2776/* - VIN0 ------------------------------------------------------------------- */
2777static const union vin_data vin0_data_pins = {
2778 .data24 = {
2779 /* B */
2780 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
2781 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
2782 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
2783 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
2784 /* G */
2785 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
2786 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
2787 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
2788 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
2789 /* R */
2790 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
2791 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2792 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
2793 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2794 },
2795};
2796static const union vin_data vin0_data_mux = {
2797 .data24 = {
2798 /* B */
2799 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
2800 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
2801 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2802 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2803 /* G */
2804 VI0_G0_MARK, VI0_G1_MARK,
2805 VI0_G2_MARK, VI0_G3_MARK,
2806 VI0_G4_MARK, VI0_G5_MARK,
2807 VI0_G6_MARK, VI0_G7_MARK,
2808 /* R */
2809 VI0_R0_MARK, VI0_R1_MARK,
2810 VI0_R2_MARK, VI0_R3_MARK,
2811 VI0_R4_MARK, VI0_R5_MARK,
2812 VI0_R6_MARK, VI0_R7_MARK,
2813 },
2814};
2815static const unsigned int vin0_data18_pins[] = {
2816 /* B */
2817 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
2818 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
2819 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
2820 /* G */
2821 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
2822 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
2823 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
2824 /* R */
2825 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2826 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
2827 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2828};
2829static const unsigned int vin0_data18_mux[] = {
2830 /* B */
2831 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
2832 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2833 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2834 /* G */
2835 VI0_G2_MARK, VI0_G3_MARK,
2836 VI0_G4_MARK, VI0_G5_MARK,
2837 VI0_G6_MARK, VI0_G7_MARK,
2838 /* R */
2839 VI0_R2_MARK, VI0_R3_MARK,
2840 VI0_R4_MARK, VI0_R5_MARK,
2841 VI0_R6_MARK, VI0_R7_MARK,
2842};
2843static const unsigned int vin0_sync_pins[] = {
2844 RCAR_GP_PIN(3, 11), /* HSYNC */
2845 RCAR_GP_PIN(3, 12), /* VSYNC */
2846};
2847static const unsigned int vin0_sync_mux[] = {
2848 VI0_HSYNC_N_MARK,
2849 VI0_VSYNC_N_MARK,
2850};
2851static const unsigned int vin0_field_pins[] = {
2852 RCAR_GP_PIN(3, 10),
2853};
2854static const unsigned int vin0_field_mux[] = {
2855 VI0_FIELD_MARK,
2856};
2857static const unsigned int vin0_clkenb_pins[] = {
2858 RCAR_GP_PIN(3, 9),
2859};
2860static const unsigned int vin0_clkenb_mux[] = {
2861 VI0_CLKENB_MARK,
2862};
2863static const unsigned int vin0_clk_pins[] = {
2864 RCAR_GP_PIN(3, 0),
2865};
2866static const unsigned int vin0_clk_mux[] = {
2867 VI0_CLK_MARK,
2868};
2869/* - VIN1 ------------------------------------------------------------------- */
2870static const union vin_data vin1_data_pins = {
2871 .data12 = {
2872 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
2873 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
2874 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
2875 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2876 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
2877 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2878 },
2879};
2880static const union vin_data vin1_data_mux = {
2881 .data12 = {
2882 VI1_DATA0_MARK, VI1_DATA1_MARK,
2883 VI1_DATA2_MARK, VI1_DATA3_MARK,
2884 VI1_DATA4_MARK, VI1_DATA5_MARK,
2885 VI1_DATA6_MARK, VI1_DATA7_MARK,
2886 VI1_DATA8_MARK, VI1_DATA9_MARK,
2887 VI1_DATA10_MARK, VI1_DATA11_MARK,
2888 },
2889};
2890static const unsigned int vin1_sync_pins[] = {
2891 RCAR_GP_PIN(5, 22), /* HSYNC */
2892 RCAR_GP_PIN(5, 23), /* VSYNC */
2893};
2894static const unsigned int vin1_sync_mux[] = {
2895 VI1_HSYNC_N_MARK,
2896 VI1_VSYNC_N_MARK,
2897};
2898static const unsigned int vin1_field_pins[] = {
2899 RCAR_GP_PIN(5, 21),
2900};
2901static const unsigned int vin1_field_mux[] = {
2902 VI1_FIELD_MARK,
2903};
2904static const unsigned int vin1_clkenb_pins[] = {
2905 RCAR_GP_PIN(5, 20),
2906};
2907static const unsigned int vin1_clkenb_mux[] = {
2908 VI1_CLKENB_MARK,
2909};
2910static const unsigned int vin1_clk_pins[] = {
2911 RCAR_GP_PIN(5, 11),
2912};
2913static const unsigned int vin1_clk_mux[] = {
2914 VI1_CLK_MARK,
2915};
2791 2916
2792static const struct sh_pfc_pin_group pinmux_groups[] = { 2917static const struct sh_pfc_pin_group pinmux_groups[] = {
2793 SH_PFC_PIN_GROUP(eth_link), 2918 SH_PFC_PIN_GROUP(eth_link),
@@ -2884,9 +3009,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2884 SH_PFC_PIN_GROUP(qspi_data2), 3009 SH_PFC_PIN_GROUP(qspi_data2),
2885 SH_PFC_PIN_GROUP(qspi_data4), 3010 SH_PFC_PIN_GROUP(qspi_data4),
2886 SH_PFC_PIN_GROUP(scif0_data), 3011 SH_PFC_PIN_GROUP(scif0_data),
2887 SH_PFC_PIN_GROUP(scif0_clk),
2888 SH_PFC_PIN_GROUP(scif0_data_b), 3012 SH_PFC_PIN_GROUP(scif0_data_b),
2889 SH_PFC_PIN_GROUP(scif0_clk_b),
2890 SH_PFC_PIN_GROUP(scif0_data_c), 3013 SH_PFC_PIN_GROUP(scif0_data_c),
2891 SH_PFC_PIN_GROUP(scif0_data_d), 3014 SH_PFC_PIN_GROUP(scif0_data_d),
2892 SH_PFC_PIN_GROUP(scif1_data), 3015 SH_PFC_PIN_GROUP(scif1_data),
@@ -2965,6 +3088,24 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2965 SH_PFC_PIN_GROUP(sdhi2_wp), 3088 SH_PFC_PIN_GROUP(sdhi2_wp),
2966 SH_PFC_PIN_GROUP(usb0), 3089 SH_PFC_PIN_GROUP(usb0),
2967 SH_PFC_PIN_GROUP(usb1), 3090 SH_PFC_PIN_GROUP(usb1),
3091 VIN_DATA_PIN_GROUP(vin0_data, 24),
3092 VIN_DATA_PIN_GROUP(vin0_data, 20),
3093 SH_PFC_PIN_GROUP(vin0_data18),
3094 VIN_DATA_PIN_GROUP(vin0_data, 16),
3095 VIN_DATA_PIN_GROUP(vin0_data, 12),
3096 VIN_DATA_PIN_GROUP(vin0_data, 10),
3097 VIN_DATA_PIN_GROUP(vin0_data, 8),
3098 SH_PFC_PIN_GROUP(vin0_sync),
3099 SH_PFC_PIN_GROUP(vin0_field),
3100 SH_PFC_PIN_GROUP(vin0_clkenb),
3101 SH_PFC_PIN_GROUP(vin0_clk),
3102 VIN_DATA_PIN_GROUP(vin1_data, 12),
3103 VIN_DATA_PIN_GROUP(vin1_data, 10),
3104 VIN_DATA_PIN_GROUP(vin1_data, 8),
3105 SH_PFC_PIN_GROUP(vin1_sync),
3106 SH_PFC_PIN_GROUP(vin1_field),
3107 SH_PFC_PIN_GROUP(vin1_clkenb),
3108 SH_PFC_PIN_GROUP(vin1_clk),
2968}; 3109};
2969 3110
2970static const char * const eth_groups[] = { 3111static const char * const eth_groups[] = {
@@ -3107,9 +3248,7 @@ static const char * const qspi_groups[] = {
3107 3248
3108static const char * const scif0_groups[] = { 3249static const char * const scif0_groups[] = {
3109 "scif0_data", 3250 "scif0_data",
3110 "scif0_clk",
3111 "scif0_data_b", 3251 "scif0_data_b",
3112 "scif0_clk_b",
3113 "scif0_data_c", 3252 "scif0_data_c",
3114 "scif0_data_d", 3253 "scif0_data_d",
3115}; 3254};
@@ -3247,6 +3386,30 @@ static const char * const usb1_groups[] = {
3247 "usb1", 3386 "usb1",
3248}; 3387};
3249 3388
3389static const char * const vin0_groups[] = {
3390 "vin0_data24",
3391 "vin0_data20",
3392 "vin0_data18",
3393 "vin0_data16",
3394 "vin0_data12",
3395 "vin0_data10",
3396 "vin0_data8",
3397 "vin0_sync",
3398 "vin0_field",
3399 "vin0_clkenb",
3400 "vin0_clk",
3401};
3402
3403static const char * const vin1_groups[] = {
3404 "vin1_data12",
3405 "vin1_data10",
3406 "vin1_data8",
3407 "vin1_sync",
3408 "vin1_field",
3409 "vin1_clkenb",
3410 "vin1_clk",
3411};
3412
3250static const struct sh_pfc_function pinmux_functions[] = { 3413static const struct sh_pfc_function pinmux_functions[] = {
3251 SH_PFC_FUNCTION(eth), 3414 SH_PFC_FUNCTION(eth),
3252 SH_PFC_FUNCTION(hscif0), 3415 SH_PFC_FUNCTION(hscif0),
@@ -3283,6 +3446,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
3283 SH_PFC_FUNCTION(sdhi2), 3446 SH_PFC_FUNCTION(sdhi2),
3284 SH_PFC_FUNCTION(usb0), 3447 SH_PFC_FUNCTION(usb0),
3285 SH_PFC_FUNCTION(usb1), 3448 SH_PFC_FUNCTION(usb1),
3449 SH_PFC_FUNCTION(vin0),
3450 SH_PFC_FUNCTION(vin1),
3286}; 3451};
3287 3452
3288static const struct pinmux_cfg_reg pinmux_config_regs[] = { 3453static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -4232,6 +4397,6 @@ const struct sh_pfc_soc_info r8a7794_pinmux_info = {
4232 4397
4233 .cfg_regs = pinmux_config_regs, 4398 .cfg_regs = pinmux_config_regs,
4234 4399
4235 .gpio_data = pinmux_data, 4400 .pinmux_data = pinmux_data,
4236 .gpio_data_size = ARRAY_SIZE(pinmux_data), 4401 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
4237}; 4402};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
new file mode 100644
index 000000000000..7ddb2adfc5a5
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -0,0 +1,2816 @@
1/*
2 * R-Car Gen3 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/kernel.h>
12
13#include "core.h"
14#include "sh_pfc.h"
15
16#define PORT_GP_3(bank, fn, sfx) \
17 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
18 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx)
19
20#define PORT_GP_14(bank, fn, sfx) \
21 PORT_GP_3(bank, fn, sfx), \
22 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
23 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
24 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
25 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
26 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
27 PORT_GP_1(bank, 14, fn, sfx)
28
29#define PORT_GP_15(bank, fn, sfx) \
30 PORT_GP_14(bank, fn, sfx), PORT_GP_1(bank, 15, fn, sfx)
31
32#define PORT_GP_17(bank, fn, sfx) \
33 PORT_GP_15(bank, fn, sfx), \
34 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx)
35
36#define PORT_GP_25(bank, fn, sfx) \
37 PORT_GP_17(bank, fn, sfx), \
38 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
39 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
40 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
41 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx)
42
43#define PORT_GP_27(bank, fn, sfx) \
44 PORT_GP_25(bank, fn, sfx), \
45 PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx)
46
47#define CPU_ALL_PORT(fn, sfx) \
48 PORT_GP_15(0, fn, sfx), \
49 PORT_GP_27(1, fn, sfx), \
50 PORT_GP_14(2, fn, sfx), \
51 PORT_GP_15(3, fn, sfx), \
52 PORT_GP_17(4, fn, sfx), \
53 PORT_GP_25(5, fn, sfx), \
54 PORT_GP_32(6, fn, sfx), \
55 PORT_GP_3(7, fn, sfx)
56/*
57 * F_() : just information
58 * FM() : macro for FN_xxx / xxx_MARK
59 */
60
61/* GPSR0 */
62#define GPSR0_15 F_(D15, IP7_11_8)
63#define GPSR0_14 F_(D14, IP7_7_4)
64#define GPSR0_13 F_(D13, IP7_3_0)
65#define GPSR0_12 F_(D12, IP6_31_28)
66#define GPSR0_11 F_(D11, IP6_27_24)
67#define GPSR0_10 F_(D10, IP6_23_20)
68#define GPSR0_9 F_(D9, IP6_19_16)
69#define GPSR0_8 F_(D8, IP6_15_12)
70#define GPSR0_7 F_(D7, IP6_11_8)
71#define GPSR0_6 F_(D6, IP6_7_4)
72#define GPSR0_5 F_(D5, IP6_3_0)
73#define GPSR0_4 F_(D4, IP5_31_28)
74#define GPSR0_3 F_(D3, IP5_27_24)
75#define GPSR0_2 F_(D2, IP5_23_20)
76#define GPSR0_1 F_(D1, IP5_19_16)
77#define GPSR0_0 F_(D0, IP5_15_12)
78
79/* GPSR1 */
80#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
81#define GPSR1_26 F_(WE1_N, IP5_7_4)
82#define GPSR1_25 F_(WE0_N, IP5_3_0)
83#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
84#define GPSR1_23 F_(RD_N, IP4_27_24)
85#define GPSR1_22 F_(BS_N, IP4_23_20)
86#define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
87#define GPSR1_20 F_(CS0_N, IP4_15_12)
88#define GPSR1_19 F_(A19, IP4_11_8)
89#define GPSR1_18 F_(A18, IP4_7_4)
90#define GPSR1_17 F_(A17, IP4_3_0)
91#define GPSR1_16 F_(A16, IP3_31_28)
92#define GPSR1_15 F_(A15, IP3_27_24)
93#define GPSR1_14 F_(A14, IP3_23_20)
94#define GPSR1_13 F_(A13, IP3_19_16)
95#define GPSR1_12 F_(A12, IP3_15_12)
96#define GPSR1_11 F_(A11, IP3_11_8)
97#define GPSR1_10 F_(A10, IP3_7_4)
98#define GPSR1_9 F_(A9, IP3_3_0)
99#define GPSR1_8 F_(A8, IP2_31_28)
100#define GPSR1_7 F_(A7, IP2_27_24)
101#define GPSR1_6 F_(A6, IP2_23_20)
102#define GPSR1_5 F_(A5, IP2_19_16)
103#define GPSR1_4 F_(A4, IP2_15_12)
104#define GPSR1_3 F_(A3, IP2_11_8)
105#define GPSR1_2 F_(A2, IP2_7_4)
106#define GPSR1_1 F_(A1, IP2_3_0)
107#define GPSR1_0 F_(A0, IP1_31_28)
108
109/* GPSR2 */
110#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
111#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
112#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
113#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
114#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
115#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
116#define GPSR2_8 F_(PWM2_A, IP1_27_24)
117#define GPSR2_7 F_(PWM1_A, IP1_23_20)
118#define GPSR2_6 F_(PWM0, IP1_19_16)
119#define GPSR2_5 F_(IRQ5, IP1_15_12)
120#define GPSR2_4 F_(IRQ4, IP1_11_8)
121#define GPSR2_3 F_(IRQ3, IP1_7_4)
122#define GPSR2_2 F_(IRQ2, IP1_3_0)
123#define GPSR2_1 F_(IRQ1, IP0_31_28)
124#define GPSR2_0 F_(IRQ0, IP0_27_24)
125
126/* GPSR3 */
127#define GPSR3_15 F_(SD1_WP, IP10_23_20)
128#define GPSR3_14 F_(SD1_CD, IP10_19_16)
129#define GPSR3_13 F_(SD0_WP, IP10_15_12)
130#define GPSR3_12 F_(SD0_CD, IP10_11_8)
131#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
132#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
133#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
134#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
135#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
136#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
137#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
138#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
139#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
140#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
141#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
142#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
143
144/* GPSR4 */
145#define GPSR4_17 FM(SD3_DS)
146#define GPSR4_16 F_(SD3_DAT7, IP10_7_4)
147#define GPSR4_15 F_(SD3_DAT6, IP10_3_0)
148#define GPSR4_14 F_(SD3_DAT5, IP9_31_28)
149#define GPSR4_13 F_(SD3_DAT4, IP9_27_24)
150#define GPSR4_12 FM(SD3_DAT3)
151#define GPSR4_11 FM(SD3_DAT2)
152#define GPSR4_10 FM(SD3_DAT1)
153#define GPSR4_9 FM(SD3_DAT0)
154#define GPSR4_8 FM(SD3_CMD)
155#define GPSR4_7 FM(SD3_CLK)
156#define GPSR4_6 F_(SD2_DS, IP9_23_20)
157#define GPSR4_5 F_(SD2_DAT3, IP9_19_16)
158#define GPSR4_4 F_(SD2_DAT2, IP9_15_12)
159#define GPSR4_3 F_(SD2_DAT1, IP9_11_8)
160#define GPSR4_2 F_(SD2_DAT0, IP9_7_4)
161#define GPSR4_1 FM(SD2_CMD)
162#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
163
164/* GPSR5 */
165#define GPSR5_25 F_(MLB_DAT, IP13_19_16)
166#define GPSR5_24 F_(MLB_SIG, IP13_15_12)
167#define GPSR5_23 F_(MLB_CLK, IP13_11_8)
168#define GPSR5_22 FM(MSIOF0_RXD)
169#define GPSR5_21 F_(MSIOF0_SS2, IP13_7_4)
170#define GPSR5_20 FM(MSIOF0_TXD)
171#define GPSR5_19 F_(MSIOF0_SS1, IP13_3_0)
172#define GPSR5_18 F_(MSIOF0_SYNC, IP12_31_28)
173#define GPSR5_17 FM(MSIOF0_SCK)
174#define GPSR5_16 F_(HRTS0_N, IP12_27_24)
175#define GPSR5_15 F_(HCTS0_N, IP12_23_20)
176#define GPSR5_14 F_(HTX0, IP12_19_16)
177#define GPSR5_13 F_(HRX0, IP12_15_12)
178#define GPSR5_12 F_(HSCK0, IP12_11_8)
179#define GPSR5_11 F_(RX2_A, IP12_7_4)
180#define GPSR5_10 F_(TX2_A, IP12_3_0)
181#define GPSR5_9 F_(SCK2, IP11_31_28)
182#define GPSR5_8 F_(RTS1_N_TANS, IP11_27_24)
183#define GPSR5_7 F_(CTS1_N, IP11_23_20)
184#define GPSR5_6 F_(TX1_A, IP11_19_16)
185#define GPSR5_5 F_(RX1_A, IP11_15_12)
186#define GPSR5_4 F_(RTS0_N_TANS, IP11_11_8)
187#define GPSR5_3 F_(CTS0_N, IP11_7_4)
188#define GPSR5_2 F_(TX0, IP11_3_0)
189#define GPSR5_1 F_(RX0, IP10_31_28)
190#define GPSR5_0 F_(SCK0, IP10_27_24)
191
192/* GPSR6 */
193#define GPSR6_31 F_(USB31_OVC, IP17_7_4)
194#define GPSR6_30 F_(USB31_PWEN, IP17_3_0)
195#define GPSR6_29 F_(USB30_OVC, IP16_31_28)
196#define GPSR6_28 F_(USB30_PWEN, IP16_27_24)
197#define GPSR6_27 F_(USB1_OVC, IP16_23_20)
198#define GPSR6_26 F_(USB1_PWEN, IP16_19_16)
199#define GPSR6_25 F_(USB0_OVC, IP16_15_12)
200#define GPSR6_24 F_(USB0_PWEN, IP16_11_8)
201#define GPSR6_23 F_(AUDIO_CLKB_B, IP16_7_4)
202#define GPSR6_22 F_(AUDIO_CLKA_A, IP16_3_0)
203#define GPSR6_21 F_(SSI_SDATA9_A, IP15_31_28)
204#define GPSR6_20 F_(SSI_SDATA8, IP15_27_24)
205#define GPSR6_19 F_(SSI_SDATA7, IP15_23_20)
206#define GPSR6_18 F_(SSI_WS78, IP15_19_16)
207#define GPSR6_17 F_(SSI_SCK78, IP15_15_12)
208#define GPSR6_16 F_(SSI_SDATA6, IP15_11_8)
209#define GPSR6_15 F_(SSI_WS6, IP15_7_4)
210#define GPSR6_14 F_(SSI_SCK6, IP15_3_0)
211#define GPSR6_13 FM(SSI_SDATA5)
212#define GPSR6_12 FM(SSI_WS5)
213#define GPSR6_11 FM(SSI_SCK5)
214#define GPSR6_10 F_(SSI_SDATA4, IP14_31_28)
215#define GPSR6_9 F_(SSI_WS4, IP14_27_24)
216#define GPSR6_8 F_(SSI_SCK4, IP14_23_20)
217#define GPSR6_7 F_(SSI_SDATA3, IP14_19_16)
218#define GPSR6_6 F_(SSI_WS34, IP14_15_12)
219#define GPSR6_5 F_(SSI_SCK34, IP14_11_8)
220#define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4)
221#define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0)
222#define GPSR6_2 F_(SSI_SDATA0, IP13_31_28)
223#define GPSR6_1 F_(SSI_WS0129, IP13_27_24)
224#define GPSR6_0 F_(SSI_SCK0129, IP13_23_20)
225
226/* GPSR7 */
227#define GPSR7_3 FM(HDMI1_CEC)
228#define GPSR7_2 FM(HDMI0_CEC)
229#define GPSR7_1 FM(AVS2)
230#define GPSR7_0 FM(AVS1)
231
232
233/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
234#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253
254/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
255#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297
298/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
299#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) F_(0, 0) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) F_(0, 0) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) F_(0, 0) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) F_(0, 0) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP9_7_4 FM(SD2_DAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP9_11_8 FM(SD2_DAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP9_15_12 FM(SD2_DAT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP9_19_16 FM(SD2_DAT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP9_23_20 FM(SD2_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP9_27_24 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP9_31_28 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP10_3_0 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP10_7_4 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP10_11_8 FM(SD0_CD) F_(0, 0) F_(0, 0) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP10_15_12 FM(SD0_WP) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP10_19_16 FM(SD1_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP10_23_20 FM(SD1_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP10_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP11_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP11_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP12_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP12_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP12_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP12_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP12_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341
342/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
343#define IP12_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP13_3_0 FM(MSIOF0_SS1) FM(RX5) F_(0, 0) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP13_7_4 FM(MSIOF0_SS2) FM(TX5) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP13_23_20 FM(SSI_SCK0129) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP13_27_24 FM(SSI_WS0129) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP14_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP14_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP14_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP15_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP15_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362#define IP15_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363#define IP15_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364#define IP15_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365#define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366#define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367#define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368#define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369#define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370#define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371#define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372#define IP16_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373#define IP16_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374#define IP16_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375#define IP16_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376#define IP17_3_0 FM(USB31_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377#define IP17_7_4 FM(USB31_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378
379#define PINMUX_GPSR \
380\
381 GPSR6_31 \
382 GPSR6_30 \
383 GPSR6_29 \
384 GPSR6_28 \
385 GPSR1_27 GPSR6_27 \
386 GPSR1_26 GPSR6_26 \
387 GPSR1_25 GPSR5_25 GPSR6_25 \
388 GPSR1_24 GPSR5_24 GPSR6_24 \
389 GPSR1_23 GPSR5_23 GPSR6_23 \
390 GPSR1_22 GPSR5_22 GPSR6_22 \
391 GPSR1_21 GPSR5_21 GPSR6_21 \
392 GPSR1_20 GPSR5_20 GPSR6_20 \
393 GPSR1_19 GPSR5_19 GPSR6_19 \
394 GPSR1_18 GPSR5_18 GPSR6_18 \
395 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
396 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
397GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
398GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
399GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
400GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
401GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
402GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
403GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
404GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
405GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
406GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
407GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
408GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
409GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
410GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
411GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
412GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
413
414#define PINMUX_IPSR \
415\
416FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
417FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
418FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
419FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
420FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
421FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
422FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
423FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
424\
425FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
426FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
427FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
428FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
429FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
430FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
431FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
432FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
433\
434FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
435FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
436FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
437FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
438FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
439FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
440FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
441FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
442\
443FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
444FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
445FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
446FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
447FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
448FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
449FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
450FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
451\
452FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 \
453FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 \
454FM(IP16_11_8) IP16_11_8 \
455FM(IP16_15_12) IP16_15_12 \
456FM(IP16_19_16) IP16_19_16 \
457FM(IP16_23_20) IP16_23_20 \
458FM(IP16_27_24) IP16_27_24 \
459FM(IP16_31_28) IP16_31_28
460
461/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
462#define MOD_SEL0_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3)
463#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
464#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
465#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
466#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
467#define MOD_SEL0_21_20 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0)
468#define MOD_SEL0_19 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
469#define MOD_SEL0_18 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
470#define MOD_SEL0_17 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
471#define MOD_SEL0_16_15 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
472#define MOD_SEL0_14 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
473#define MOD_SEL0_13 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
474#define MOD_SEL0_12 FM(SEL_FSO_0) FM(SEL_FSO_1)
475#define MOD_SEL0_11 FM(SEL_FM_0) FM(SEL_FM_1)
476#define MOD_SEL0_10 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
477#define MOD_SEL0_9 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
478#define MOD_SEL0_8 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
479#define MOD_SEL0_7_6 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
480#define MOD_SEL0_5_4 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
481#define MOD_SEL0_3 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
482#define MOD_SEL0_2_1 FM(SEL_ADG_0) FM(SEL_ADG_1) FM(SEL_ADG_2) FM(SEL_ADG_3)
483
484/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
485#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
486#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
487#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
488#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
489#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
490#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
491#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
492#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
493#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
494#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
495#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
496#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
497#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
498#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
499#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
500#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
501#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
502#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
503#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
504#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
505#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
506#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
507
508/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
509#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
510#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
511#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
512#define MOD_SEL2_2_1 FM(SEL_VSP_0) FM(SEL_VSP_1) FM(SEL_VSP_2) FM(SEL_VSP_3)
513#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
514
515#define PINMUX_MOD_SELS\
516\
517 MOD_SEL1_31_30 MOD_SEL2_31 \
518MOD_SEL0_30_29 MOD_SEL2_30 \
519 MOD_SEL1_29_28_27 MOD_SEL2_29 \
520MOD_SEL0_28_27 \
521\
522MOD_SEL0_26_25_24 MOD_SEL1_26 \
523 MOD_SEL1_25_24 \
524\
525MOD_SEL0_23 MOD_SEL1_23_22_21 \
526MOD_SEL0_22 \
527MOD_SEL0_21_20 \
528 MOD_SEL1_20 \
529MOD_SEL0_19 MOD_SEL1_19 \
530MOD_SEL0_18 MOD_SEL1_18_17 \
531MOD_SEL0_17 \
532MOD_SEL0_16_15 MOD_SEL1_16 \
533 MOD_SEL1_15_14 \
534MOD_SEL0_14 \
535MOD_SEL0_13 MOD_SEL1_13 \
536MOD_SEL0_12 MOD_SEL1_12 \
537MOD_SEL0_11 MOD_SEL1_11 \
538MOD_SEL0_10 MOD_SEL1_10 \
539MOD_SEL0_9 MOD_SEL1_9 \
540MOD_SEL0_8 \
541MOD_SEL0_7_6 \
542 MOD_SEL1_6 \
543MOD_SEL0_5_4 MOD_SEL1_5 \
544 MOD_SEL1_4 \
545MOD_SEL0_3 MOD_SEL1_3 \
546MOD_SEL0_2_1 MOD_SEL1_2 MOD_SEL2_2_1 \
547 MOD_SEL1_1 \
548 MOD_SEL1_0 MOD_SEL2_0
549
550
551enum {
552 PINMUX_RESERVED = 0,
553
554 PINMUX_DATA_BEGIN,
555 GP_ALL(DATA),
556 PINMUX_DATA_END,
557
558#define F_(x, y)
559#define FM(x) FN_##x,
560 PINMUX_FUNCTION_BEGIN,
561 GP_ALL(FN),
562 PINMUX_GPSR
563 PINMUX_IPSR
564 PINMUX_MOD_SELS
565 PINMUX_FUNCTION_END,
566#undef F_
567#undef FM
568
569#define F_(x, y)
570#define FM(x) x##_MARK,
571 PINMUX_MARK_BEGIN,
572 PINMUX_GPSR
573 PINMUX_IPSR
574 PINMUX_MOD_SELS
575 PINMUX_MARK_END,
576#undef F_
577#undef FM
578};
579
580static const u16 pinmux_data[] = {
581 PINMUX_DATA_GP_ALL(),
582
583 /* IPSR0 */
584 PINMUX_IPSR_DATA(IP0_3_0, AVB_MDC),
585 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
586
587 PINMUX_IPSR_DATA(IP0_7_4, AVB_MAGIC),
588 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
589 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
590
591 PINMUX_IPSR_DATA(IP0_11_8, AVB_PHY_INT),
592 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
593 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
594
595 PINMUX_IPSR_DATA(IP0_15_12, AVB_LINK),
596 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
597 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
598
599 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
600 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
601 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
602
603 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
604 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
605 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
606
607 PINMUX_IPSR_DATA(IP0_27_24, IRQ0),
608 PINMUX_IPSR_DATA(IP0_27_24, QPOLB),
609 PINMUX_IPSR_DATA(IP0_27_24, DU_CDE),
610 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
611 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
612 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
613
614 PINMUX_IPSR_DATA(IP0_31_28, IRQ1),
615 PINMUX_IPSR_DATA(IP0_31_28, QPOLA),
616 PINMUX_IPSR_DATA(IP0_31_28, DU_DISP),
617 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
618 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
619 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
620
621 /* IPSR1 */
622 PINMUX_IPSR_DATA(IP1_3_0, IRQ2),
623 PINMUX_IPSR_DATA(IP1_3_0, QCPV_QDE),
624 PINMUX_IPSR_DATA(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
625 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
626 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
627
628 PINMUX_IPSR_DATA(IP1_7_4, IRQ3),
629 PINMUX_IPSR_DATA(IP1_7_4, QSTVB_QVE),
630 PINMUX_IPSR_DATA(IP1_7_4, A25),
631 PINMUX_IPSR_DATA(IP1_7_4, DU_DOTCLKOUT1),
632 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
633 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
634
635 PINMUX_IPSR_DATA(IP1_11_8, IRQ4),
636 PINMUX_IPSR_DATA(IP1_11_8, QSTH_QHS),
637 PINMUX_IPSR_DATA(IP1_11_8, A24),
638 PINMUX_IPSR_DATA(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
639 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
640 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
641
642 PINMUX_IPSR_DATA(IP1_15_12, IRQ5),
643 PINMUX_IPSR_DATA(IP1_15_12, QSTB_QHE),
644 PINMUX_IPSR_DATA(IP1_15_12, A23),
645 PINMUX_IPSR_DATA(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
646 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
647 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
648
649 PINMUX_IPSR_DATA(IP1_19_16, PWM0),
650 PINMUX_IPSR_DATA(IP1_19_16, AVB_AVTP_PPS),
651 PINMUX_IPSR_DATA(IP1_19_16, A22),
652 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
653 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
654
655 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
656 PINMUX_IPSR_DATA(IP1_23_20, A21),
657 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
658 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
659 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
660
661 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
662 PINMUX_IPSR_DATA(IP1_27_24, A20),
663 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
664 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
665
666 PINMUX_IPSR_DATA(IP1_31_28, A0),
667 PINMUX_IPSR_DATA(IP1_31_28, LCDOUT16),
668 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
669 PINMUX_IPSR_DATA(IP1_31_28, VI4_DATA8),
670 PINMUX_IPSR_DATA(IP1_31_28, DU_DB0),
671 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
672
673 /* IPSR2 */
674 PINMUX_IPSR_DATA(IP2_3_0, A1),
675 PINMUX_IPSR_DATA(IP2_3_0, LCDOUT17),
676 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
677 PINMUX_IPSR_DATA(IP2_3_0, VI4_DATA9),
678 PINMUX_IPSR_DATA(IP2_3_0, DU_DB1),
679 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
680
681 PINMUX_IPSR_DATA(IP2_7_4, A2),
682 PINMUX_IPSR_DATA(IP2_7_4, LCDOUT18),
683 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
684 PINMUX_IPSR_DATA(IP2_7_4, VI4_DATA10),
685 PINMUX_IPSR_DATA(IP2_7_4, DU_DB2),
686 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
687
688 PINMUX_IPSR_DATA(IP2_11_8, A3),
689 PINMUX_IPSR_DATA(IP2_11_8, LCDOUT19),
690 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
691 PINMUX_IPSR_DATA(IP2_11_8, VI4_DATA11),
692 PINMUX_IPSR_DATA(IP2_11_8, DU_DB3),
693 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
694
695 PINMUX_IPSR_DATA(IP2_15_12, A4),
696 PINMUX_IPSR_DATA(IP2_15_12, LCDOUT20),
697 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
698 PINMUX_IPSR_DATA(IP2_15_12, VI4_DATA12),
699 PINMUX_IPSR_DATA(IP2_15_12, VI5_DATA12),
700 PINMUX_IPSR_DATA(IP2_15_12, DU_DB4),
701
702 PINMUX_IPSR_DATA(IP2_19_16, A5),
703 PINMUX_IPSR_DATA(IP2_19_16, LCDOUT21),
704 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
705 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
706 PINMUX_IPSR_DATA(IP2_19_16, VI4_DATA13),
707 PINMUX_IPSR_DATA(IP2_19_16, VI5_DATA13),
708 PINMUX_IPSR_DATA(IP2_19_16, DU_DB5),
709
710 PINMUX_IPSR_DATA(IP2_23_20, A6),
711 PINMUX_IPSR_DATA(IP2_23_20, LCDOUT22),
712 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
713 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
714 PINMUX_IPSR_DATA(IP2_23_20, VI4_DATA14),
715 PINMUX_IPSR_DATA(IP2_23_20, VI5_DATA14),
716 PINMUX_IPSR_DATA(IP2_23_20, DU_DB6),
717
718 PINMUX_IPSR_DATA(IP2_27_24, A7),
719 PINMUX_IPSR_DATA(IP2_27_24, LCDOUT23),
720 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
721 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
722 PINMUX_IPSR_DATA(IP2_27_24, VI4_DATA15),
723 PINMUX_IPSR_DATA(IP2_27_24, VI5_DATA15),
724 PINMUX_IPSR_DATA(IP2_27_24, DU_DB7),
725
726 PINMUX_IPSR_DATA(IP2_31_28, A8),
727 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
728 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
729 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
730 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
731 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
732 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
733
734 /* IPSR3 */
735 PINMUX_IPSR_DATA(IP3_3_0, A9),
736 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
737 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
738 PINMUX_IPSR_DATA(IP3_3_0, VI5_VSYNC_N),
739
740 PINMUX_IPSR_DATA(IP3_7_4, A10),
741 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
742 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
743 PINMUX_IPSR_DATA(IP3_7_4, VI5_HSYNC_N),
744
745 PINMUX_IPSR_DATA(IP3_11_8, A11),
746 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
747 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
748 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
749 PINMUX_IPSR_DATA(IP3_11_8, HSCK4),
750 PINMUX_IPSR_DATA(IP3_11_8, VI5_FIELD),
751 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
752 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
753 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
754
755 PINMUX_IPSR_DATA(IP3_15_12, A12),
756 PINMUX_IPSR_DATA(IP3_15_12, LCDOUT12),
757 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
758 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
759 PINMUX_IPSR_DATA(IP3_15_12, VI5_DATA8),
760 PINMUX_IPSR_DATA(IP3_15_12, DU_DG4),
761
762 PINMUX_IPSR_DATA(IP3_19_16, A13),
763 PINMUX_IPSR_DATA(IP3_19_16, LCDOUT13),
764 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
765 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
766 PINMUX_IPSR_DATA(IP3_19_16, VI5_DATA9),
767 PINMUX_IPSR_DATA(IP3_19_16, DU_DG5),
768
769 PINMUX_IPSR_DATA(IP3_23_20, A14),
770 PINMUX_IPSR_DATA(IP3_23_20, LCDOUT14),
771 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
772 PINMUX_IPSR_DATA(IP3_23_20, HCTS4_N),
773 PINMUX_IPSR_DATA(IP3_23_20, VI5_DATA10),
774 PINMUX_IPSR_DATA(IP3_23_20, DU_DG6),
775
776 PINMUX_IPSR_DATA(IP3_27_24, A15),
777 PINMUX_IPSR_DATA(IP3_27_24, LCDOUT15),
778 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
779 PINMUX_IPSR_DATA(IP3_27_24, HRTS4_N),
780 PINMUX_IPSR_DATA(IP3_27_24, VI5_DATA11),
781 PINMUX_IPSR_DATA(IP3_27_24, DU_DG7),
782
783 PINMUX_IPSR_DATA(IP3_31_28, A16),
784 PINMUX_IPSR_DATA(IP3_31_28, LCDOUT8),
785 PINMUX_IPSR_DATA(IP3_31_28, VI4_FIELD),
786 PINMUX_IPSR_DATA(IP3_31_28, DU_DG0),
787
788 /* IPSR4 */
789 PINMUX_IPSR_DATA(IP4_3_0, A17),
790 PINMUX_IPSR_DATA(IP4_3_0, LCDOUT9),
791 PINMUX_IPSR_DATA(IP4_3_0, VI4_VSYNC_N),
792 PINMUX_IPSR_DATA(IP4_3_0, DU_DG1),
793
794 PINMUX_IPSR_DATA(IP4_7_4, A18),
795 PINMUX_IPSR_DATA(IP4_7_4, LCDOUT10),
796 PINMUX_IPSR_DATA(IP4_7_4, VI4_HSYNC_N),
797 PINMUX_IPSR_DATA(IP4_7_4, DU_DG2),
798
799 PINMUX_IPSR_DATA(IP4_11_8, A19),
800 PINMUX_IPSR_DATA(IP4_11_8, LCDOUT11),
801 PINMUX_IPSR_DATA(IP4_11_8, VI4_CLKENB),
802 PINMUX_IPSR_DATA(IP4_11_8, DU_DG3),
803
804 PINMUX_IPSR_DATA(IP4_15_12, CS0_N),
805 PINMUX_IPSR_DATA(IP4_15_12, VI5_CLKENB),
806
807 PINMUX_IPSR_DATA(IP4_19_16, CS1_N_A26),
808 PINMUX_IPSR_DATA(IP4_19_16, VI5_CLK),
809 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
810
811 PINMUX_IPSR_DATA(IP4_23_20, BS_N),
812 PINMUX_IPSR_DATA(IP4_23_20, QSTVA_QVS),
813 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
814 PINMUX_IPSR_DATA(IP4_23_20, SCK3),
815 PINMUX_IPSR_DATA(IP4_23_20, HSCK3),
816 PINMUX_IPSR_DATA(IP4_23_20, CAN1_TX),
817 PINMUX_IPSR_DATA(IP4_23_20, CANFD1_TX),
818 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
819
820 PINMUX_IPSR_DATA(IP4_27_24, RD_N),
821 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
822 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
823 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
824 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
825 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
826
827 PINMUX_IPSR_DATA(IP4_31_28, RD_WR_N),
828 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
829 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
830 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
831 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
832 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
833
834 /* IPSR5 */
835 PINMUX_IPSR_DATA(IP5_3_0, WE0_N),
836 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
837 PINMUX_IPSR_DATA(IP5_3_0, CTS3_N),
838 PINMUX_IPSR_DATA(IP5_3_0, HCTS3_N),
839 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
840 PINMUX_IPSR_DATA(IP5_3_0, CAN_CLK),
841 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
842
843 PINMUX_IPSR_DATA(IP5_7_4, WE1_N),
844 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
845 PINMUX_IPSR_DATA(IP5_7_4, RTS3_N_TANS),
846 PINMUX_IPSR_DATA(IP5_7_4, HRTS3_N),
847 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
848 PINMUX_IPSR_DATA(IP5_7_4, CAN1_RX),
849 PINMUX_IPSR_DATA(IP5_7_4, CANFD1_RX),
850 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
851
852 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
853 PINMUX_IPSR_DATA(IP5_11_8, QCLK),
854 PINMUX_IPSR_DATA(IP5_11_8, VI4_CLK),
855 PINMUX_IPSR_DATA(IP5_11_8, DU_DOTCLKOUT0),
856
857 PINMUX_IPSR_DATA(IP5_15_12, D0),
858 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
859 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
860 PINMUX_IPSR_DATA(IP5_15_12, VI4_DATA16),
861 PINMUX_IPSR_DATA(IP5_15_12, VI5_DATA0),
862
863 PINMUX_IPSR_DATA(IP5_19_16, D1),
864 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
865 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
866 PINMUX_IPSR_DATA(IP5_19_16, VI4_DATA17),
867 PINMUX_IPSR_DATA(IP5_19_16, VI5_DATA1),
868
869 PINMUX_IPSR_DATA(IP5_23_20, D2),
870 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
871 PINMUX_IPSR_DATA(IP5_23_20, VI4_DATA18),
872 PINMUX_IPSR_DATA(IP5_23_20, VI5_DATA2),
873
874 PINMUX_IPSR_DATA(IP5_27_24, D3),
875 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
876 PINMUX_IPSR_DATA(IP5_27_24, VI4_DATA19),
877 PINMUX_IPSR_DATA(IP5_27_24, VI5_DATA3),
878
879 PINMUX_IPSR_DATA(IP5_31_28, D4),
880 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
881 PINMUX_IPSR_DATA(IP5_31_28, VI4_DATA20),
882 PINMUX_IPSR_DATA(IP5_31_28, VI5_DATA4),
883
884 /* IPSR6 */
885 PINMUX_IPSR_DATA(IP6_3_0, D5),
886 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
887 PINMUX_IPSR_DATA(IP6_3_0, VI4_DATA21),
888 PINMUX_IPSR_DATA(IP6_3_0, VI5_DATA5),
889
890 PINMUX_IPSR_DATA(IP6_7_4, D6),
891 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
892 PINMUX_IPSR_DATA(IP6_7_4, VI4_DATA22),
893 PINMUX_IPSR_DATA(IP6_7_4, VI5_DATA6),
894
895 PINMUX_IPSR_DATA(IP6_11_8, D7),
896 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
897 PINMUX_IPSR_DATA(IP6_11_8, VI4_DATA23),
898 PINMUX_IPSR_DATA(IP6_11_8, VI5_DATA7),
899
900 PINMUX_IPSR_DATA(IP6_15_12, D8),
901 PINMUX_IPSR_DATA(IP6_15_12, LCDOUT0),
902 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
903 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
904 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
905 PINMUX_IPSR_DATA(IP6_15_12, DU_DR0),
906
907 PINMUX_IPSR_DATA(IP6_19_16, D9),
908 PINMUX_IPSR_DATA(IP6_19_16, LCDOUT1),
909 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
910 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
911 PINMUX_IPSR_DATA(IP6_19_16, DU_DR1),
912
913 PINMUX_IPSR_DATA(IP6_23_20, D10),
914 PINMUX_IPSR_DATA(IP6_23_20, LCDOUT2),
915 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
916 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
917 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
918 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
919 PINMUX_IPSR_DATA(IP6_23_20, DU_DR2),
920
921 PINMUX_IPSR_DATA(IP6_27_24, D11),
922 PINMUX_IPSR_DATA(IP6_27_24, LCDOUT3),
923 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
924 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
925 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
926 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
927 PINMUX_IPSR_DATA(IP6_27_24, DU_DR3),
928
929 PINMUX_IPSR_DATA(IP6_31_28, D12),
930 PINMUX_IPSR_DATA(IP6_31_28, LCDOUT4),
931 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
932 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
933 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
934 PINMUX_IPSR_DATA(IP6_31_28, DU_DR4),
935
936 /* IPSR7 */
937 PINMUX_IPSR_DATA(IP7_3_0, D13),
938 PINMUX_IPSR_DATA(IP7_3_0, LCDOUT5),
939 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
940 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
941 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
942 PINMUX_IPSR_DATA(IP7_3_0, DU_DR5),
943
944 PINMUX_IPSR_DATA(IP7_7_4, D14),
945 PINMUX_IPSR_DATA(IP7_7_4, LCDOUT6),
946 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
947 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
948 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
949 PINMUX_IPSR_DATA(IP7_7_4, DU_DR6),
950 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
951
952 PINMUX_IPSR_DATA(IP7_11_8, D15),
953 PINMUX_IPSR_DATA(IP7_11_8, LCDOUT7),
954 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
955 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
956 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
957 PINMUX_IPSR_DATA(IP7_11_8, DU_DR7),
958 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
959
960 PINMUX_IPSR_DATA(IP7_15_12, FSCLKST),
961
962 PINMUX_IPSR_DATA(IP7_19_16, SD0_CLK),
963 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
964 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
965
966 PINMUX_IPSR_DATA(IP7_23_20, SD0_CMD),
967 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
968 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
969
970 PINMUX_IPSR_DATA(IP7_27_24, SD0_DAT0),
971 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
972 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
973 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
974
975 PINMUX_IPSR_DATA(IP7_31_28, SD0_DAT1),
976 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
977 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
978 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
979
980 /* IPSR8 */
981 PINMUX_IPSR_DATA(IP8_3_0, SD0_DAT2),
982 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
983 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
984 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
985
986 PINMUX_IPSR_DATA(IP8_7_4, SD0_DAT3),
987 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
988 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
989 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
990
991 PINMUX_IPSR_DATA(IP8_11_8, SD1_CLK),
992 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
993 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
994
995 PINMUX_IPSR_DATA(IP8_15_12, SD1_CMD),
996 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
997 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
998 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
999
1000 PINMUX_IPSR_DATA(IP8_19_16, SD1_DAT0),
1001 PINMUX_IPSR_DATA(IP8_19_16, SD2_DAT4),
1002 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1003 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1004 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1005
1006 PINMUX_IPSR_DATA(IP8_23_20, SD1_DAT1),
1007 PINMUX_IPSR_DATA(IP8_23_20, SD2_DAT5),
1008 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1009 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1010 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1011
1012 PINMUX_IPSR_DATA(IP8_27_24, SD1_DAT2),
1013 PINMUX_IPSR_DATA(IP8_27_24, SD2_DAT6),
1014 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1015 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1016 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1017
1018 PINMUX_IPSR_DATA(IP8_31_28, SD1_DAT3),
1019 PINMUX_IPSR_DATA(IP8_31_28, SD2_DAT7),
1020 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1021 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1022 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1023
1024 /* IPSR9 */
1025 PINMUX_IPSR_DATA(IP9_3_0, SD2_CLK),
1026
1027 PINMUX_IPSR_DATA(IP9_7_4, SD2_DAT0),
1028
1029 PINMUX_IPSR_DATA(IP9_11_8, SD2_DAT1),
1030
1031 PINMUX_IPSR_DATA(IP9_15_12, SD2_DAT2),
1032
1033 PINMUX_IPSR_DATA(IP9_19_16, SD2_DAT3),
1034
1035 PINMUX_IPSR_DATA(IP9_23_20, SD2_DS),
1036 PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SCIF_1),
1037
1038 PINMUX_IPSR_DATA(IP9_27_24, SD3_DAT4),
1039 PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0),
1040
1041 PINMUX_IPSR_DATA(IP9_31_28, SD3_DAT5),
1042 PINMUX_IPSR_MSEL(IP9_31_28, SD2_WP_A, SEL_SDHI2_0),
1043
1044 /* IPSR10 */
1045 PINMUX_IPSR_DATA(IP10_3_0, SD3_DAT6),
1046 PINMUX_IPSR_DATA(IP10_3_0, SD3_CD),
1047
1048 PINMUX_IPSR_DATA(IP10_7_4, SD3_DAT7),
1049 PINMUX_IPSR_DATA(IP10_7_4, SD3_WP),
1050
1051 PINMUX_IPSR_DATA(IP10_11_8, SD0_CD),
1052 PINMUX_IPSR_MSEL(IP10_11_8, SCL2_B, SEL_I2C2_1),
1053 PINMUX_IPSR_MSEL(IP10_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1054
1055 PINMUX_IPSR_DATA(IP10_15_12, SD0_WP),
1056 PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1),
1057
1058 PINMUX_IPSR_DATA(IP10_19_16, SD1_CD),
1059 PINMUX_IPSR_MSEL(IP10_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1060
1061 PINMUX_IPSR_DATA(IP10_23_20, SD1_WP),
1062 PINMUX_IPSR_MSEL(IP10_23_20, SIM0_D_B, SEL_SIMCARD_1),
1063
1064 PINMUX_IPSR_DATA(IP10_27_24, SCK0),
1065 PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1),
1066 PINMUX_IPSR_MSEL(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1067 PINMUX_IPSR_MSEL(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1),
1068 PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
1069 PINMUX_IPSR_MSEL(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1070 PINMUX_IPSR_MSEL(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1071 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1072 PINMUX_IPSR_DATA(IP10_27_24, ADICHS2),
1073
1074 PINMUX_IPSR_DATA(IP10_31_28, RX0),
1075 PINMUX_IPSR_MSEL(IP10_31_28, HRX1_B, SEL_HSCIF1_1),
1076 PINMUX_IPSR_MSEL(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2),
1077 PINMUX_IPSR_MSEL(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1078 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1079
1080 /* IPSR11 */
1081 PINMUX_IPSR_DATA(IP11_3_0, TX0),
1082 PINMUX_IPSR_MSEL(IP11_3_0, HTX1_B, SEL_HSCIF1_1),
1083 PINMUX_IPSR_MSEL(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1084 PINMUX_IPSR_MSEL(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1085 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
1086
1087 PINMUX_IPSR_DATA(IP11_7_4, CTS0_N),
1088 PINMUX_IPSR_MSEL(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1089 PINMUX_IPSR_MSEL(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1090 PINMUX_IPSR_MSEL(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1091 PINMUX_IPSR_MSEL(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1092 PINMUX_IPSR_MSEL(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1093 PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2),
1094 PINMUX_IPSR_DATA(IP11_7_4, ADICS_SAMP),
1095
1096 PINMUX_IPSR_DATA(IP11_11_8, RTS0_N_TANS),
1097 PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1098 PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1099 PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1),
1100 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_A, SEL_I2C2_0),
1101 PINMUX_IPSR_MSEL(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1102 PINMUX_IPSR_MSEL(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1103 PINMUX_IPSR_DATA(IP11_11_8, ADICHS1),
1104
1105 PINMUX_IPSR_MSEL(IP11_15_12, RX1_A, SEL_SCIF1_0),
1106 PINMUX_IPSR_MSEL(IP11_15_12, HRX1_A, SEL_HSCIF1_0),
1107 PINMUX_IPSR_MSEL(IP11_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1108 PINMUX_IPSR_MSEL(IP11_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1109 PINMUX_IPSR_MSEL(IP11_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1110
1111 PINMUX_IPSR_MSEL(IP11_19_16, TX1_A, SEL_SCIF1_0),
1112 PINMUX_IPSR_MSEL(IP11_19_16, HTX1_A, SEL_HSCIF1_0),
1113 PINMUX_IPSR_MSEL(IP11_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1114 PINMUX_IPSR_MSEL(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1115 PINMUX_IPSR_MSEL(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2),
1116
1117 PINMUX_IPSR_DATA(IP11_23_20, CTS1_N),
1118 PINMUX_IPSR_MSEL(IP11_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1119 PINMUX_IPSR_MSEL(IP11_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1120 PINMUX_IPSR_MSEL(IP11_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1121 PINMUX_IPSR_MSEL(IP11_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1122 PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1),
1123 PINMUX_IPSR_DATA(IP11_23_20, ADIDATA),
1124
1125 PINMUX_IPSR_DATA(IP11_27_24, RTS1_N_TANS),
1126 PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1127 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1128 PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1129 PINMUX_IPSR_MSEL(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1130 PINMUX_IPSR_MSEL(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1),
1131 PINMUX_IPSR_DATA(IP11_27_24, ADICHS0),
1132
1133 PINMUX_IPSR_DATA(IP11_31_28, SCK2),
1134 PINMUX_IPSR_MSEL(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1),
1135 PINMUX_IPSR_MSEL(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1136 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2),
1137 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1138 PINMUX_IPSR_MSEL(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1139 PINMUX_IPSR_DATA(IP11_31_28, ADICLK),
1140
1141 /* IPSR12 */
1142 PINMUX_IPSR_MSEL(IP12_3_0, TX2_A, SEL_SCIF2_0),
1143 PINMUX_IPSR_MSEL(IP12_3_0, SD2_CD_B, SEL_SDHI2_1),
1144 PINMUX_IPSR_MSEL(IP12_3_0, SCL1_A, SEL_I2C1_0),
1145 PINMUX_IPSR_MSEL(IP12_3_0, FMCLK_A, SEL_FM_0),
1146 PINMUX_IPSR_MSEL(IP12_3_0, RIF1_D1_C, SEL_DRIF1_2),
1147 PINMUX_IPSR_MSEL(IP12_3_0, FSO_CFE_0_B, SEL_FSO_1),
1148
1149 PINMUX_IPSR_MSEL(IP12_7_4, RX2_A, SEL_SCIF2_0),
1150 PINMUX_IPSR_MSEL(IP12_7_4, SD2_WP_B, SEL_SDHI2_1),
1151 PINMUX_IPSR_MSEL(IP12_7_4, SDA1_A, SEL_I2C1_0),
1152 PINMUX_IPSR_MSEL(IP12_7_4, FMIN_A, SEL_FM_0),
1153 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1154 PINMUX_IPSR_MSEL(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1),
1155
1156 PINMUX_IPSR_DATA(IP12_11_8, HSCK0),
1157 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1158 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0),
1159 PINMUX_IPSR_MSEL(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1),
1160 PINMUX_IPSR_MSEL(IP12_11_8, TS_SCK0_D, SEL_TSIF0_3),
1161 PINMUX_IPSR_MSEL(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1162 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1163
1164 PINMUX_IPSR_DATA(IP12_15_12, HRX0),
1165 PINMUX_IPSR_MSEL(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1166 PINMUX_IPSR_MSEL(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1),
1167 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1168 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1169 PINMUX_IPSR_MSEL(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2),
1170
1171 PINMUX_IPSR_DATA(IP12_19_16, HTX0),
1172 PINMUX_IPSR_MSEL(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1173 PINMUX_IPSR_MSEL(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1),
1174 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1175 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1176 PINMUX_IPSR_MSEL(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2),
1177
1178 PINMUX_IPSR_DATA(IP12_23_20, HCTS0_N),
1179 PINMUX_IPSR_MSEL(IP12_23_20, RX2_B, SEL_SCIF2_1),
1180 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1181 PINMUX_IPSR_MSEL(IP12_23_20, SSI_SCK9_A, SEL_SSI_0),
1182 PINMUX_IPSR_MSEL(IP12_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1183 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1184 PINMUX_IPSR_MSEL(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1185 PINMUX_IPSR_MSEL(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0),
1186
1187 PINMUX_IPSR_DATA(IP12_27_24, HRTS0_N),
1188 PINMUX_IPSR_MSEL(IP12_27_24, TX2_B, SEL_SCIF2_1),
1189 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1190 PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS9_A, SEL_SSI_0),
1191 PINMUX_IPSR_MSEL(IP12_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1192 PINMUX_IPSR_MSEL(IP12_27_24, BPFCLK_A, SEL_FM_0),
1193 PINMUX_IPSR_MSEL(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0),
1194
1195 PINMUX_IPSR_DATA(IP12_31_28, MSIOF0_SYNC),
1196 PINMUX_IPSR_MSEL(IP12_31_28, AUDIO_CLKOUT_A, SEL_ADG_0),
1197
1198 /* IPSR13 */
1199 PINMUX_IPSR_DATA(IP13_3_0, MSIOF0_SS1),
1200 PINMUX_IPSR_DATA(IP13_3_0, RX5),
1201 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKA_C, SEL_ADG_2),
1202 PINMUX_IPSR_MSEL(IP13_3_0, SSI_SCK2_A, SEL_SSI_0),
1203 PINMUX_IPSR_MSEL(IP13_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1204 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKOUT3_A, SEL_ADG_0),
1205 PINMUX_IPSR_MSEL(IP13_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1206
1207 PINMUX_IPSR_DATA(IP13_7_4, MSIOF0_SS2),
1208 PINMUX_IPSR_DATA(IP13_7_4, TX5),
1209 PINMUX_IPSR_MSEL(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1210 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0),
1211 PINMUX_IPSR_MSEL(IP13_7_4, SSI_WS2_A, SEL_SSI_0),
1212 PINMUX_IPSR_MSEL(IP13_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1213 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3),
1214 PINMUX_IPSR_MSEL(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1215
1216 PINMUX_IPSR_DATA(IP13_11_8, MLB_CLK),
1217 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1218 PINMUX_IPSR_MSEL(IP13_11_8, SCL1_B, SEL_I2C1_1),
1219
1220 PINMUX_IPSR_DATA(IP13_15_12, MLB_SIG),
1221 PINMUX_IPSR_MSEL(IP13_15_12, RX1_B, SEL_SCIF1_1),
1222 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1223 PINMUX_IPSR_MSEL(IP13_15_12, SDA1_B, SEL_I2C1_1),
1224
1225 PINMUX_IPSR_DATA(IP13_19_16, MLB_DAT),
1226 PINMUX_IPSR_MSEL(IP13_19_16, TX1_B, SEL_SCIF1_1),
1227 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1228
1229 PINMUX_IPSR_DATA(IP13_23_20, SSI_SCK0129),
1230 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1231
1232 PINMUX_IPSR_DATA(IP13_27_24, SSI_WS0129),
1233 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1234
1235 PINMUX_IPSR_DATA(IP13_31_28, SSI_SDATA0),
1236 PINMUX_IPSR_MSEL(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1237
1238 /* IPSR14 */
1239 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SDATA1_A, SEL_SSI_0),
1240
1241 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0),
1242 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1),
1243
1244 PINMUX_IPSR_DATA(IP14_11_8, SSI_SCK34),
1245 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1246 PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1247
1248 PINMUX_IPSR_DATA(IP14_15_12, SSI_WS34),
1249 PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1250 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1251 PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1252
1253 PINMUX_IPSR_DATA(IP14_19_16, SSI_SDATA3),
1254 PINMUX_IPSR_MSEL(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1255 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1256 PINMUX_IPSR_MSEL(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0),
1257 PINMUX_IPSR_MSEL(IP14_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1258 PINMUX_IPSR_MSEL(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0),
1259 PINMUX_IPSR_MSEL(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0),
1260
1261 PINMUX_IPSR_DATA(IP14_23_20, SSI_SCK4),
1262 PINMUX_IPSR_MSEL(IP14_23_20, HRX2_A, SEL_HSCIF2_0),
1263 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1264 PINMUX_IPSR_MSEL(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1265 PINMUX_IPSR_MSEL(IP14_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1266 PINMUX_IPSR_MSEL(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1267 PINMUX_IPSR_MSEL(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1268
1269 PINMUX_IPSR_DATA(IP14_27_24, SSI_WS4),
1270 PINMUX_IPSR_MSEL(IP14_27_24, HTX2_A, SEL_HSCIF2_0),
1271 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1272 PINMUX_IPSR_MSEL(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1273 PINMUX_IPSR_MSEL(IP14_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1274 PINMUX_IPSR_MSEL(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1275 PINMUX_IPSR_MSEL(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1276
1277 PINMUX_IPSR_DATA(IP14_31_28, SSI_SDATA4),
1278 PINMUX_IPSR_MSEL(IP14_31_28, HSCK2_A, SEL_HSCIF2_0),
1279 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1280 PINMUX_IPSR_MSEL(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1281 PINMUX_IPSR_MSEL(IP14_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1282 PINMUX_IPSR_MSEL(IP14_31_28, RIF0_D0_A, SEL_DRIF0_0),
1283 PINMUX_IPSR_MSEL(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0),
1284
1285 /* IPSR15 */
1286 PINMUX_IPSR_DATA(IP15_3_0, SSI_SCK6),
1287 PINMUX_IPSR_DATA(IP15_3_0, USB2_PWEN),
1288 PINMUX_IPSR_MSEL(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1289
1290 PINMUX_IPSR_DATA(IP15_7_4, SSI_WS6),
1291 PINMUX_IPSR_DATA(IP15_7_4, USB2_OVC),
1292 PINMUX_IPSR_MSEL(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3),
1293
1294 PINMUX_IPSR_DATA(IP15_11_8, SSI_SDATA6),
1295 PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1296 PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SCIF_0),
1297
1298 PINMUX_IPSR_DATA(IP15_15_12, SSI_SCK78),
1299 PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1),
1300 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1301 PINMUX_IPSR_MSEL(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0),
1302 PINMUX_IPSR_MSEL(IP15_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1303 PINMUX_IPSR_MSEL(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1304 PINMUX_IPSR_MSEL(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1305
1306 PINMUX_IPSR_DATA(IP15_19_16, SSI_WS78),
1307 PINMUX_IPSR_MSEL(IP15_19_16, HTX2_B, SEL_HSCIF2_1),
1308 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1309 PINMUX_IPSR_MSEL(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1310 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1311 PINMUX_IPSR_MSEL(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1312 PINMUX_IPSR_MSEL(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1313
1314 PINMUX_IPSR_DATA(IP15_23_20, SSI_SDATA7),
1315 PINMUX_IPSR_MSEL(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1316 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1317 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1318 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1319 PINMUX_IPSR_MSEL(IP15_23_20, RIF1_D0_A, SEL_DRIF1_0),
1320 PINMUX_IPSR_MSEL(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0),
1321 PINMUX_IPSR_MSEL(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0),
1322
1323 PINMUX_IPSR_DATA(IP15_27_24, SSI_SDATA8),
1324 PINMUX_IPSR_MSEL(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1325 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1326 PINMUX_IPSR_MSEL(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1327 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1328 PINMUX_IPSR_MSEL(IP15_27_24, RIF1_D1_A, SEL_DRIF1_0),
1329 PINMUX_IPSR_MSEL(IP15_27_24, RIF3_D1_A, SEL_DRIF3_0),
1330
1331 PINMUX_IPSR_MSEL(IP15_31_28, SSI_SDATA9_A, SEL_SSI_0),
1332 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_B, SEL_HSCIF2_1),
1333 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1334 PINMUX_IPSR_MSEL(IP15_31_28, HSCK1_A, SEL_HSCIF1_0),
1335 PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS1_B, SEL_SSI_1),
1336 PINMUX_IPSR_DATA(IP15_31_28, SCK1),
1337 PINMUX_IPSR_MSEL(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1338 PINMUX_IPSR_DATA(IP15_31_28, SCK5),
1339
1340 /* IPSR16 */
1341 PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0),
1342 PINMUX_IPSR_DATA(IP16_3_0, CC5_OSCOUT),
1343
1344 PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1),
1345 PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0),
1346 PINMUX_IPSR_MSEL(IP16_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1347 PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_REMOCON_0),
1348 PINMUX_IPSR_MSEL(IP16_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1349
1350 PINMUX_IPSR_DATA(IP16_11_8, USB0_PWEN),
1351 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1352 PINMUX_IPSR_MSEL(IP16_11_8, TS_SCK1_D, SEL_TSIF1_3),
1353 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1354 PINMUX_IPSR_MSEL(IP16_11_8, BPFCLK_B, SEL_FM_1),
1355 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1356
1357 PINMUX_IPSR_DATA(IP16_15_12, USB0_OVC),
1358 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_D_C, SEL_SIMCARD_2),
1359 PINMUX_IPSR_MSEL(IP16_11_8, TS_SDAT1_D, SEL_TSIF1_3),
1360 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISD_1_D, SEL_SSP1_1_3),
1361 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_SYNC_B, SEL_DRIF3_1),
1362
1363 PINMUX_IPSR_DATA(IP16_19_16, USB1_PWEN),
1364 PINMUX_IPSR_MSEL(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1365 PINMUX_IPSR_MSEL(IP16_19_16, SSI_SCK1_A, SEL_SSI_0),
1366 PINMUX_IPSR_MSEL(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4),
1367 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1368 PINMUX_IPSR_MSEL(IP16_19_16, FMCLK_B, SEL_FM_1),
1369 PINMUX_IPSR_MSEL(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1370 PINMUX_IPSR_MSEL(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1371
1372 PINMUX_IPSR_DATA(IP16_23_20, USB1_OVC),
1373 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1374 PINMUX_IPSR_MSEL(IP16_23_20, SSI_WS1_A, SEL_SSI_0),
1375 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1376 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1377 PINMUX_IPSR_MSEL(IP16_23_20, FMIN_B, SEL_FM_1),
1378 PINMUX_IPSR_MSEL(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1379 PINMUX_IPSR_MSEL(IP16_23_20, REMOCON_B, SEL_REMOCON_1),
1380
1381 PINMUX_IPSR_DATA(IP16_27_24, USB30_PWEN),
1382 PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1),
1383 PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1),
1384 PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1385 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_2),
1386 PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1387 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1),
1388 PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1),
1389 PINMUX_IPSR_DATA(IP16_27_24, TPU0TO0),
1390
1391 PINMUX_IPSR_DATA(IP16_31_28, USB30_OVC),
1392 PINMUX_IPSR_MSEL(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1),
1393 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS2_B, SEL_SSI_1),
1394 PINMUX_IPSR_MSEL(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1395 PINMUX_IPSR_MSEL(IP16_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1396 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1397 PINMUX_IPSR_MSEL(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1),
1398 PINMUX_IPSR_MSEL(IP16_31_28, FSO_TOE_B, SEL_FSO_1),
1399 PINMUX_IPSR_DATA(IP16_31_28, TPU0TO1),
1400
1401 /* IPSR17 */
1402 PINMUX_IPSR_DATA(IP17_3_0, USB31_PWEN),
1403 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1),
1404 PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_B, SEL_SSI_1),
1405 PINMUX_IPSR_MSEL(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1406 PINMUX_IPSR_MSEL(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1407 PINMUX_IPSR_MSEL(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1),
1408 PINMUX_IPSR_DATA(IP17_3_0, TPU0TO2),
1409
1410 PINMUX_IPSR_DATA(IP17_7_4, USB31_OVC),
1411 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1),
1412 PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_B, SEL_SSI_1),
1413 PINMUX_IPSR_MSEL(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1414 PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1415 PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1),
1416 PINMUX_IPSR_DATA(IP17_7_4, TPU0TO3),
1417
1418 /* I2C */
1419 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
1420 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
1421 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
1422};
1423
1424static const struct sh_pfc_pin pinmux_pins[] = {
1425 PINMUX_GPIO_GP_ALL(),
1426};
1427
1428/* - AUDIO CLOCK ------------------------------------------------------------ */
1429static const unsigned int audio_clk_a_a_pins[] = {
1430 /* CLK A */
1431 RCAR_GP_PIN(6, 22),
1432};
1433static const unsigned int audio_clk_a_a_mux[] = {
1434 AUDIO_CLKA_A_MARK,
1435};
1436static const unsigned int audio_clk_a_b_pins[] = {
1437 /* CLK A */
1438 RCAR_GP_PIN(5, 4),
1439};
1440static const unsigned int audio_clk_a_b_mux[] = {
1441 AUDIO_CLKA_B_MARK,
1442};
1443static const unsigned int audio_clk_a_c_pins[] = {
1444 /* CLK A */
1445 RCAR_GP_PIN(5, 19),
1446};
1447static const unsigned int audio_clk_a_c_mux[] = {
1448 AUDIO_CLKA_C_MARK,
1449};
1450static const unsigned int audio_clk_b_a_pins[] = {
1451 /* CLK B */
1452 RCAR_GP_PIN(5, 12),
1453};
1454static const unsigned int audio_clk_b_a_mux[] = {
1455 AUDIO_CLKB_A_MARK,
1456};
1457static const unsigned int audio_clk_b_b_pins[] = {
1458 /* CLK B */
1459 RCAR_GP_PIN(6, 23),
1460};
1461static const unsigned int audio_clk_b_b_mux[] = {
1462 AUDIO_CLKB_B_MARK,
1463};
1464static const unsigned int audio_clk_c_a_pins[] = {
1465 /* CLK C */
1466 RCAR_GP_PIN(5, 21),
1467};
1468static const unsigned int audio_clk_c_a_mux[] = {
1469 AUDIO_CLKC_A_MARK,
1470};
1471static const unsigned int audio_clk_c_b_pins[] = {
1472 /* CLK C */
1473 RCAR_GP_PIN(5, 0),
1474};
1475static const unsigned int audio_clk_c_b_mux[] = {
1476 AUDIO_CLKC_B_MARK,
1477};
1478static const unsigned int audio_clkout_a_pins[] = {
1479 /* CLKOUT */
1480 RCAR_GP_PIN(5, 18),
1481};
1482static const unsigned int audio_clkout_a_mux[] = {
1483 AUDIO_CLKOUT_A_MARK,
1484};
1485static const unsigned int audio_clkout_b_pins[] = {
1486 /* CLKOUT */
1487 RCAR_GP_PIN(6, 28),
1488};
1489static const unsigned int audio_clkout_b_mux[] = {
1490 AUDIO_CLKOUT_B_MARK,
1491};
1492static const unsigned int audio_clkout_c_pins[] = {
1493 /* CLKOUT */
1494 RCAR_GP_PIN(5, 3),
1495};
1496static const unsigned int audio_clkout_c_mux[] = {
1497 AUDIO_CLKOUT_C_MARK,
1498};
1499static const unsigned int audio_clkout_d_pins[] = {
1500 /* CLKOUT */
1501 RCAR_GP_PIN(5, 21),
1502};
1503static const unsigned int audio_clkout_d_mux[] = {
1504 AUDIO_CLKOUT_D_MARK,
1505};
1506static const unsigned int audio_clkout1_a_pins[] = {
1507 /* CLKOUT1 */
1508 RCAR_GP_PIN(5, 15),
1509};
1510static const unsigned int audio_clkout1_a_mux[] = {
1511 AUDIO_CLKOUT1_A_MARK,
1512};
1513static const unsigned int audio_clkout1_b_pins[] = {
1514 /* CLKOUT1 */
1515 RCAR_GP_PIN(6, 29),
1516};
1517static const unsigned int audio_clkout1_b_mux[] = {
1518 AUDIO_CLKOUT1_B_MARK,
1519};
1520static const unsigned int audio_clkout2_a_pins[] = {
1521 /* CLKOUT2 */
1522 RCAR_GP_PIN(5, 16),
1523};
1524static const unsigned int audio_clkout2_a_mux[] = {
1525 AUDIO_CLKOUT2_A_MARK,
1526};
1527static const unsigned int audio_clkout2_b_pins[] = {
1528 /* CLKOUT2 */
1529 RCAR_GP_PIN(6, 30),
1530};
1531static const unsigned int audio_clkout2_b_mux[] = {
1532 AUDIO_CLKOUT2_B_MARK,
1533};
1534
1535static const unsigned int audio_clkout3_a_pins[] = {
1536 /* CLKOUT3 */
1537 RCAR_GP_PIN(5, 19),
1538};
1539static const unsigned int audio_clkout3_a_mux[] = {
1540 AUDIO_CLKOUT3_A_MARK,
1541};
1542static const unsigned int audio_clkout3_b_pins[] = {
1543 /* CLKOUT3 */
1544 RCAR_GP_PIN(6, 31),
1545};
1546static const unsigned int audio_clkout3_b_mux[] = {
1547 AUDIO_CLKOUT3_B_MARK,
1548};
1549
1550/* - EtherAVB --------------------------------------------------------------- */
1551static const unsigned int avb_link_pins[] = {
1552 /* AVB_LINK */
1553 RCAR_GP_PIN(2, 12),
1554};
1555static const unsigned int avb_link_mux[] = {
1556 AVB_LINK_MARK,
1557};
1558static const unsigned int avb_magic_pins[] = {
1559 /* AVB_MAGIC_ */
1560 RCAR_GP_PIN(2, 10),
1561};
1562static const unsigned int avb_magic_mux[] = {
1563 AVB_MAGIC_MARK,
1564};
1565static const unsigned int avb_phy_int_pins[] = {
1566 /* AVB_PHY_INT */
1567 RCAR_GP_PIN(2, 11),
1568};
1569static const unsigned int avb_phy_int_mux[] = {
1570 AVB_PHY_INT_MARK,
1571};
1572static const unsigned int avb_mdc_pins[] = {
1573 /* AVB_MDC */
1574 RCAR_GP_PIN(2, 9),
1575};
1576static const unsigned int avb_mdc_mux[] = {
1577 AVB_MDC_MARK,
1578};
1579static const unsigned int avb_avtp_pps_pins[] = {
1580 /* AVB_AVTP_PPS */
1581 RCAR_GP_PIN(2, 6),
1582};
1583static const unsigned int avb_avtp_pps_mux[] = {
1584 AVB_AVTP_PPS_MARK,
1585};
1586static const unsigned int avb_avtp_match_a_pins[] = {
1587 /* AVB_AVTP_MATCH_A */
1588 RCAR_GP_PIN(2, 13),
1589};
1590static const unsigned int avb_avtp_match_a_mux[] = {
1591 AVB_AVTP_MATCH_A_MARK,
1592};
1593static const unsigned int avb_avtp_capture_a_pins[] = {
1594 /* AVB_AVTP_CAPTURE_A */
1595 RCAR_GP_PIN(2, 14),
1596};
1597static const unsigned int avb_avtp_capture_a_mux[] = {
1598 AVB_AVTP_CAPTURE_A_MARK,
1599};
1600static const unsigned int avb_avtp_match_b_pins[] = {
1601 /* AVB_AVTP_MATCH_B */
1602 RCAR_GP_PIN(1, 8),
1603};
1604static const unsigned int avb_avtp_match_b_mux[] = {
1605 AVB_AVTP_MATCH_B_MARK,
1606};
1607static const unsigned int avb_avtp_capture_b_pins[] = {
1608 /* AVB_AVTP_CAPTURE_B */
1609 RCAR_GP_PIN(1, 11),
1610};
1611static const unsigned int avb_avtp_capture_b_mux[] = {
1612 AVB_AVTP_CAPTURE_B_MARK,
1613};
1614
1615/* - I2C -------------------------------------------------------------------- */
1616static const unsigned int i2c1_a_pins[] = {
1617 /* SDA, SCL */
1618 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
1619};
1620static const unsigned int i2c1_a_mux[] = {
1621 SDA1_A_MARK, SCL1_A_MARK,
1622};
1623static const unsigned int i2c1_b_pins[] = {
1624 /* SDA, SCL */
1625 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
1626};
1627static const unsigned int i2c1_b_mux[] = {
1628 SDA1_B_MARK, SCL1_B_MARK,
1629};
1630static const unsigned int i2c2_a_pins[] = {
1631 /* SDA, SCL */
1632 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1633};
1634static const unsigned int i2c2_a_mux[] = {
1635 SDA2_A_MARK, SCL2_A_MARK,
1636};
1637static const unsigned int i2c2_b_pins[] = {
1638 /* SDA, SCL */
1639 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
1640};
1641static const unsigned int i2c2_b_mux[] = {
1642 SDA2_B_MARK, SCL2_B_MARK,
1643};
1644static const unsigned int i2c6_a_pins[] = {
1645 /* SDA, SCL */
1646 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
1647};
1648static const unsigned int i2c6_a_mux[] = {
1649 SDA6_A_MARK, SCL6_A_MARK,
1650};
1651static const unsigned int i2c6_b_pins[] = {
1652 /* SDA, SCL */
1653 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1654};
1655static const unsigned int i2c6_b_mux[] = {
1656 SDA6_B_MARK, SCL6_B_MARK,
1657};
1658static const unsigned int i2c6_c_pins[] = {
1659 /* SDA, SCL */
1660 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
1661};
1662static const unsigned int i2c6_c_mux[] = {
1663 SDA6_C_MARK, SCL6_C_MARK,
1664};
1665
1666/* - SCIF0 ------------------------------------------------------------------ */
1667static const unsigned int scif0_data_pins[] = {
1668 /* RX, TX */
1669 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1670};
1671static const unsigned int scif0_data_mux[] = {
1672 RX0_MARK, TX0_MARK,
1673};
1674static const unsigned int scif0_clk_pins[] = {
1675 /* SCK */
1676 RCAR_GP_PIN(5, 0),
1677};
1678static const unsigned int scif0_clk_mux[] = {
1679 SCK0_MARK,
1680};
1681static const unsigned int scif0_ctrl_pins[] = {
1682 /* RTS, CTS */
1683 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
1684};
1685static const unsigned int scif0_ctrl_mux[] = {
1686 RTS0_N_TANS_MARK, CTS0_N_MARK,
1687};
1688/* - SCIF1 ------------------------------------------------------------------ */
1689static const unsigned int scif1_data_a_pins[] = {
1690 /* RX, TX */
1691 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
1692};
1693static const unsigned int scif1_data_a_mux[] = {
1694 RX1_A_MARK, TX1_A_MARK,
1695};
1696static const unsigned int scif1_clk_pins[] = {
1697 /* SCK */
1698 RCAR_GP_PIN(6, 21),
1699};
1700static const unsigned int scif1_clk_mux[] = {
1701 SCK1_MARK,
1702};
1703static const unsigned int scif1_ctrl_pins[] = {
1704 /* RTS, CTS */
1705 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
1706};
1707static const unsigned int scif1_ctrl_mux[] = {
1708 RTS1_N_TANS_MARK, CTS1_N_MARK,
1709};
1710
1711static const unsigned int scif1_data_b_pins[] = {
1712 /* RX, TX */
1713 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1714};
1715static const unsigned int scif1_data_b_mux[] = {
1716 RX1_B_MARK, TX1_B_MARK,
1717};
1718/* - SCIF2 ------------------------------------------------------------------ */
1719static const unsigned int scif2_data_a_pins[] = {
1720 /* RX, TX */
1721 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
1722};
1723static const unsigned int scif2_data_a_mux[] = {
1724 RX2_A_MARK, TX2_A_MARK,
1725};
1726static const unsigned int scif2_clk_pins[] = {
1727 /* SCK */
1728 RCAR_GP_PIN(5, 9),
1729};
1730static const unsigned int scif2_clk_mux[] = {
1731 SCK2_MARK,
1732};
1733static const unsigned int scif2_data_b_pins[] = {
1734 /* RX, TX */
1735 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1736};
1737static const unsigned int scif2_data_b_mux[] = {
1738 RX2_B_MARK, TX2_B_MARK,
1739};
1740/* - SCIF3 ------------------------------------------------------------------ */
1741static const unsigned int scif3_data_a_pins[] = {
1742 /* RX, TX */
1743 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1744};
1745static const unsigned int scif3_data_a_mux[] = {
1746 RX3_A_MARK, TX3_A_MARK,
1747};
1748static const unsigned int scif3_clk_pins[] = {
1749 /* SCK */
1750 RCAR_GP_PIN(1, 22),
1751};
1752static const unsigned int scif3_clk_mux[] = {
1753 SCK3_MARK,
1754};
1755static const unsigned int scif3_ctrl_pins[] = {
1756 /* RTS, CTS */
1757 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1758};
1759static const unsigned int scif3_ctrl_mux[] = {
1760 RTS3_N_TANS_MARK, CTS3_N_MARK,
1761};
1762static const unsigned int scif3_data_b_pins[] = {
1763 /* RX, TX */
1764 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
1765};
1766static const unsigned int scif3_data_b_mux[] = {
1767 RX3_B_MARK, TX3_B_MARK,
1768};
1769/* - SCIF4 ------------------------------------------------------------------ */
1770static const unsigned int scif4_data_a_pins[] = {
1771 /* RX, TX */
1772 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1773};
1774static const unsigned int scif4_data_a_mux[] = {
1775 RX4_A_MARK, TX4_A_MARK,
1776};
1777static const unsigned int scif4_clk_a_pins[] = {
1778 /* SCK */
1779 RCAR_GP_PIN(2, 10),
1780};
1781static const unsigned int scif4_clk_a_mux[] = {
1782 SCK4_A_MARK,
1783};
1784static const unsigned int scif4_ctrl_a_pins[] = {
1785 /* RTS, CTS */
1786 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1787};
1788static const unsigned int scif4_ctrl_a_mux[] = {
1789 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
1790};
1791static const unsigned int scif4_data_b_pins[] = {
1792 /* RX, TX */
1793 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
1794};
1795static const unsigned int scif4_data_b_mux[] = {
1796 RX4_B_MARK, TX4_B_MARK,
1797};
1798static const unsigned int scif4_clk_b_pins[] = {
1799 /* SCK */
1800 RCAR_GP_PIN(1, 5),
1801};
1802static const unsigned int scif4_clk_b_mux[] = {
1803 SCK4_B_MARK,
1804};
1805static const unsigned int scif4_ctrl_b_pins[] = {
1806 /* RTS, CTS */
1807 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
1808};
1809static const unsigned int scif4_ctrl_b_mux[] = {
1810 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
1811};
1812static const unsigned int scif4_data_c_pins[] = {
1813 /* RX, TX */
1814 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1815};
1816static const unsigned int scif4_data_c_mux[] = {
1817 RX4_C_MARK, TX4_C_MARK,
1818};
1819static const unsigned int scif4_clk_c_pins[] = {
1820 /* SCK */
1821 RCAR_GP_PIN(0, 8),
1822};
1823static const unsigned int scif4_clk_c_mux[] = {
1824 SCK4_C_MARK,
1825};
1826static const unsigned int scif4_ctrl_c_pins[] = {
1827 /* RTS, CTS */
1828 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1829};
1830static const unsigned int scif4_ctrl_c_mux[] = {
1831 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
1832};
1833/* - SCIF5 ------------------------------------------------------------------ */
1834static const unsigned int scif5_data_pins[] = {
1835 /* RX, TX */
1836 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
1837};
1838static const unsigned int scif5_data_mux[] = {
1839 RX5_MARK, TX5_MARK,
1840};
1841static const unsigned int scif5_clk_pins[] = {
1842 /* SCK */
1843 RCAR_GP_PIN(6, 21),
1844};
1845static const unsigned int scif5_clk_mux[] = {
1846 SCK5_MARK,
1847};
1848
1849/* - SSI -------------------------------------------------------------------- */
1850static const unsigned int ssi0_data_pins[] = {
1851 /* SDATA */
1852 RCAR_GP_PIN(6, 2),
1853};
1854static const unsigned int ssi0_data_mux[] = {
1855 SSI_SDATA0_MARK,
1856};
1857static const unsigned int ssi01239_ctrl_pins[] = {
1858 /* SCK, WS */
1859 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
1860};
1861static const unsigned int ssi01239_ctrl_mux[] = {
1862 SSI_SCK0129_MARK, SSI_WS0129_MARK,
1863};
1864static const unsigned int ssi1_data_a_pins[] = {
1865 /* SDATA */
1866 RCAR_GP_PIN(6, 3),
1867};
1868static const unsigned int ssi1_data_a_mux[] = {
1869 SSI_SDATA1_A_MARK,
1870};
1871static const unsigned int ssi1_data_b_pins[] = {
1872 /* SDATA */
1873 RCAR_GP_PIN(5, 12),
1874};
1875static const unsigned int ssi1_data_b_mux[] = {
1876 SSI_SDATA1_B_MARK,
1877};
1878static const unsigned int ssi1_ctrl_a_pins[] = {
1879 /* SCK, WS */
1880 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1881};
1882static const unsigned int ssi1_ctrl_a_mux[] = {
1883 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
1884};
1885static const unsigned int ssi1_ctrl_b_pins[] = {
1886 /* SCK, WS */
1887 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
1888};
1889static const unsigned int ssi1_ctrl_b_mux[] = {
1890 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
1891};
1892static const unsigned int ssi2_data_a_pins[] = {
1893 /* SDATA */
1894 RCAR_GP_PIN(6, 4),
1895};
1896static const unsigned int ssi2_data_a_mux[] = {
1897 SSI_SDATA2_A_MARK,
1898};
1899static const unsigned int ssi2_data_b_pins[] = {
1900 /* SDATA */
1901 RCAR_GP_PIN(5, 13),
1902};
1903static const unsigned int ssi2_data_b_mux[] = {
1904 SSI_SDATA2_B_MARK,
1905};
1906static const unsigned int ssi2_ctrl_a_pins[] = {
1907 /* SCK, WS */
1908 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
1909};
1910static const unsigned int ssi2_ctrl_a_mux[] = {
1911 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
1912};
1913static const unsigned int ssi2_ctrl_b_pins[] = {
1914 /* SCK, WS */
1915 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
1916};
1917static const unsigned int ssi2_ctrl_b_mux[] = {
1918 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
1919};
1920static const unsigned int ssi3_data_pins[] = {
1921 /* SDATA */
1922 RCAR_GP_PIN(6, 7),
1923};
1924static const unsigned int ssi3_data_mux[] = {
1925 SSI_SDATA3_MARK,
1926};
1927static const unsigned int ssi34_ctrl_pins[] = {
1928 /* SCK, WS */
1929 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
1930};
1931static const unsigned int ssi34_ctrl_mux[] = {
1932 SSI_SCK34_MARK, SSI_WS34_MARK,
1933};
1934static const unsigned int ssi4_data_pins[] = {
1935 /* SDATA */
1936 RCAR_GP_PIN(6, 10),
1937};
1938static const unsigned int ssi4_data_mux[] = {
1939 SSI_SDATA4_MARK,
1940};
1941static const unsigned int ssi4_ctrl_pins[] = {
1942 /* SCK, WS */
1943 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1944};
1945static const unsigned int ssi4_ctrl_mux[] = {
1946 SSI_SCK4_MARK, SSI_WS4_MARK,
1947};
1948static const unsigned int ssi5_data_pins[] = {
1949 /* SDATA */
1950 RCAR_GP_PIN(6, 13),
1951};
1952static const unsigned int ssi5_data_mux[] = {
1953 SSI_SDATA5_MARK,
1954};
1955static const unsigned int ssi5_ctrl_pins[] = {
1956 /* SCK, WS */
1957 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
1958};
1959static const unsigned int ssi5_ctrl_mux[] = {
1960 SSI_SCK5_MARK, SSI_WS5_MARK,
1961};
1962static const unsigned int ssi6_data_pins[] = {
1963 /* SDATA */
1964 RCAR_GP_PIN(6, 16),
1965};
1966static const unsigned int ssi6_data_mux[] = {
1967 SSI_SDATA6_MARK,
1968};
1969static const unsigned int ssi6_ctrl_pins[] = {
1970 /* SCK, WS */
1971 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1972};
1973static const unsigned int ssi6_ctrl_mux[] = {
1974 SSI_SCK6_MARK, SSI_WS6_MARK,
1975};
1976static const unsigned int ssi7_data_pins[] = {
1977 /* SDATA */
1978 RCAR_GP_PIN(6, 19),
1979};
1980static const unsigned int ssi7_data_mux[] = {
1981 SSI_SDATA7_MARK,
1982};
1983static const unsigned int ssi78_ctrl_pins[] = {
1984 /* SCK, WS */
1985 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1986};
1987static const unsigned int ssi78_ctrl_mux[] = {
1988 SSI_SCK78_MARK, SSI_WS78_MARK,
1989};
1990static const unsigned int ssi8_data_pins[] = {
1991 /* SDATA */
1992 RCAR_GP_PIN(6, 20),
1993};
1994static const unsigned int ssi8_data_mux[] = {
1995 SSI_SDATA8_MARK,
1996};
1997static const unsigned int ssi9_data_a_pins[] = {
1998 /* SDATA */
1999 RCAR_GP_PIN(6, 21),
2000};
2001static const unsigned int ssi9_data_a_mux[] = {
2002 SSI_SDATA9_A_MARK,
2003};
2004static const unsigned int ssi9_data_b_pins[] = {
2005 /* SDATA */
2006 RCAR_GP_PIN(5, 14),
2007};
2008static const unsigned int ssi9_data_b_mux[] = {
2009 SSI_SDATA9_B_MARK,
2010};
2011static const unsigned int ssi9_ctrl_a_pins[] = {
2012 /* SCK, WS */
2013 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2014};
2015static const unsigned int ssi9_ctrl_a_mux[] = {
2016 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
2017};
2018static const unsigned int ssi9_ctrl_b_pins[] = {
2019 /* SCK, WS */
2020 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
2021};
2022static const unsigned int ssi9_ctrl_b_mux[] = {
2023 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
2024};
2025
2026static const struct sh_pfc_pin_group pinmux_groups[] = {
2027 SH_PFC_PIN_GROUP(audio_clk_a_a),
2028 SH_PFC_PIN_GROUP(audio_clk_a_b),
2029 SH_PFC_PIN_GROUP(audio_clk_a_c),
2030 SH_PFC_PIN_GROUP(audio_clk_b_a),
2031 SH_PFC_PIN_GROUP(audio_clk_b_b),
2032 SH_PFC_PIN_GROUP(audio_clk_c_a),
2033 SH_PFC_PIN_GROUP(audio_clk_c_b),
2034 SH_PFC_PIN_GROUP(audio_clkout_a),
2035 SH_PFC_PIN_GROUP(audio_clkout_b),
2036 SH_PFC_PIN_GROUP(audio_clkout_c),
2037 SH_PFC_PIN_GROUP(audio_clkout_d),
2038 SH_PFC_PIN_GROUP(audio_clkout1_a),
2039 SH_PFC_PIN_GROUP(audio_clkout1_b),
2040 SH_PFC_PIN_GROUP(audio_clkout2_a),
2041 SH_PFC_PIN_GROUP(audio_clkout2_b),
2042 SH_PFC_PIN_GROUP(audio_clkout3_a),
2043 SH_PFC_PIN_GROUP(audio_clkout3_b),
2044 SH_PFC_PIN_GROUP(avb_link),
2045 SH_PFC_PIN_GROUP(avb_magic),
2046 SH_PFC_PIN_GROUP(avb_phy_int),
2047 SH_PFC_PIN_GROUP(avb_mdc),
2048 SH_PFC_PIN_GROUP(avb_avtp_pps),
2049 SH_PFC_PIN_GROUP(avb_avtp_match_a),
2050 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
2051 SH_PFC_PIN_GROUP(avb_avtp_match_b),
2052 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
2053 SH_PFC_PIN_GROUP(i2c1_a),
2054 SH_PFC_PIN_GROUP(i2c1_b),
2055 SH_PFC_PIN_GROUP(i2c2_a),
2056 SH_PFC_PIN_GROUP(i2c2_b),
2057 SH_PFC_PIN_GROUP(i2c6_a),
2058 SH_PFC_PIN_GROUP(i2c6_b),
2059 SH_PFC_PIN_GROUP(i2c6_c),
2060 SH_PFC_PIN_GROUP(scif0_data),
2061 SH_PFC_PIN_GROUP(scif0_clk),
2062 SH_PFC_PIN_GROUP(scif0_ctrl),
2063 SH_PFC_PIN_GROUP(scif1_data_a),
2064 SH_PFC_PIN_GROUP(scif1_clk),
2065 SH_PFC_PIN_GROUP(scif1_ctrl),
2066 SH_PFC_PIN_GROUP(scif1_data_b),
2067 SH_PFC_PIN_GROUP(scif2_data_a),
2068 SH_PFC_PIN_GROUP(scif2_clk),
2069 SH_PFC_PIN_GROUP(scif2_data_b),
2070 SH_PFC_PIN_GROUP(scif3_data_a),
2071 SH_PFC_PIN_GROUP(scif3_clk),
2072 SH_PFC_PIN_GROUP(scif3_ctrl),
2073 SH_PFC_PIN_GROUP(scif3_data_b),
2074 SH_PFC_PIN_GROUP(scif4_data_a),
2075 SH_PFC_PIN_GROUP(scif4_clk_a),
2076 SH_PFC_PIN_GROUP(scif4_ctrl_a),
2077 SH_PFC_PIN_GROUP(scif4_data_b),
2078 SH_PFC_PIN_GROUP(scif4_clk_b),
2079 SH_PFC_PIN_GROUP(scif4_ctrl_b),
2080 SH_PFC_PIN_GROUP(scif4_data_c),
2081 SH_PFC_PIN_GROUP(scif4_clk_c),
2082 SH_PFC_PIN_GROUP(scif4_ctrl_c),
2083 SH_PFC_PIN_GROUP(scif5_data),
2084 SH_PFC_PIN_GROUP(scif5_clk),
2085 SH_PFC_PIN_GROUP(ssi0_data),
2086 SH_PFC_PIN_GROUP(ssi01239_ctrl),
2087 SH_PFC_PIN_GROUP(ssi1_data_a),
2088 SH_PFC_PIN_GROUP(ssi1_data_b),
2089 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
2090 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
2091 SH_PFC_PIN_GROUP(ssi2_data_a),
2092 SH_PFC_PIN_GROUP(ssi2_data_b),
2093 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
2094 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
2095 SH_PFC_PIN_GROUP(ssi3_data),
2096 SH_PFC_PIN_GROUP(ssi34_ctrl),
2097 SH_PFC_PIN_GROUP(ssi4_data),
2098 SH_PFC_PIN_GROUP(ssi4_ctrl),
2099 SH_PFC_PIN_GROUP(ssi5_data),
2100 SH_PFC_PIN_GROUP(ssi5_ctrl),
2101 SH_PFC_PIN_GROUP(ssi6_data),
2102 SH_PFC_PIN_GROUP(ssi6_ctrl),
2103 SH_PFC_PIN_GROUP(ssi7_data),
2104 SH_PFC_PIN_GROUP(ssi78_ctrl),
2105 SH_PFC_PIN_GROUP(ssi8_data),
2106 SH_PFC_PIN_GROUP(ssi9_data_a),
2107 SH_PFC_PIN_GROUP(ssi9_data_b),
2108 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
2109 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
2110};
2111
2112static const char * const audio_clk_groups[] = {
2113 "audio_clk_a_a",
2114 "audio_clk_a_b",
2115 "audio_clk_a_c",
2116 "audio_clk_b_a",
2117 "audio_clk_b_b",
2118 "audio_clk_c_a",
2119 "audio_clk_c_b",
2120 "audio_clkout_a",
2121 "audio_clkout_b",
2122 "audio_clkout_c",
2123 "audio_clkout_d",
2124 "audio_clkout1_a",
2125 "audio_clkout1_b",
2126 "audio_clkout2_a",
2127 "audio_clkout2_b",
2128 "audio_clkout3_a",
2129 "audio_clkout3_b",
2130};
2131
2132static const char * const avb_groups[] = {
2133 "avb_link",
2134 "avb_magic",
2135 "avb_phy_int",
2136 "avb_mdc",
2137 "avb_avtp_pps",
2138 "avb_avtp_match_a",
2139 "avb_avtp_capture_a",
2140 "avb_avtp_match_b",
2141 "avb_avtp_capture_b",
2142};
2143
2144static const char * const i2c1_groups[] = {
2145 "i2c1_a",
2146 "i2c1_b",
2147};
2148
2149static const char * const i2c2_groups[] = {
2150 "i2c2_a",
2151 "i2c2_b",
2152};
2153
2154static const char * const i2c6_groups[] = {
2155 "i2c6_a",
2156 "i2c6_b",
2157 "i2c6_c",
2158};
2159
2160static const char * const scif0_groups[] = {
2161 "scif0_data",
2162 "scif0_clk",
2163 "scif0_ctrl",
2164};
2165
2166static const char * const scif1_groups[] = {
2167 "scif1_data_a",
2168 "scif1_clk",
2169 "scif1_ctrl",
2170 "scif1_data_b",
2171};
2172
2173static const char * const scif2_groups[] = {
2174 "scif2_data_a",
2175 "scif2_clk",
2176 "scif2_data_b",
2177};
2178
2179static const char * const scif3_groups[] = {
2180 "scif3_data_a",
2181 "scif3_clk",
2182 "scif3_ctrl",
2183 "scif3_data_b",
2184};
2185
2186static const char * const scif4_groups[] = {
2187 "scif4_data_a",
2188 "scif4_clk_a",
2189 "scif4_ctrl_a",
2190 "scif4_data_b",
2191 "scif4_clk_b",
2192 "scif4_ctrl_b",
2193 "scif4_data_c",
2194 "scif4_clk_c",
2195 "scif4_ctrl_c",
2196};
2197
2198static const char * const scif5_groups[] = {
2199 "scif5_data",
2200 "scif5_clk",
2201};
2202
2203static const char * const ssi_groups[] = {
2204 "ssi0_data",
2205 "ssi01239_ctrl",
2206 "ssi1_data_a",
2207 "ssi1_data_b",
2208 "ssi1_ctrl_a",
2209 "ssi1_ctrl_b",
2210 "ssi2_data_a",
2211 "ssi2_data_b",
2212 "ssi2_ctrl_a",
2213 "ssi2_ctrl_b",
2214 "ssi3_data",
2215 "ssi34_ctrl",
2216 "ssi4_data",
2217 "ssi4_ctrl",
2218 "ssi5_data",
2219 "ssi5_ctrl",
2220 "ssi6_data",
2221 "ssi6_ctrl",
2222 "ssi7_data",
2223 "ssi78_ctrl",
2224 "ssi8_data",
2225 "ssi9_data_a",
2226 "ssi9_data_b",
2227 "ssi9_ctrl_a",
2228 "ssi9_ctrl_b",
2229};
2230
2231static const struct sh_pfc_function pinmux_functions[] = {
2232 SH_PFC_FUNCTION(audio_clk),
2233 SH_PFC_FUNCTION(avb),
2234 SH_PFC_FUNCTION(i2c1),
2235 SH_PFC_FUNCTION(i2c2),
2236 SH_PFC_FUNCTION(i2c6),
2237 SH_PFC_FUNCTION(scif0),
2238 SH_PFC_FUNCTION(scif1),
2239 SH_PFC_FUNCTION(scif2),
2240 SH_PFC_FUNCTION(scif3),
2241 SH_PFC_FUNCTION(scif4),
2242 SH_PFC_FUNCTION(scif5),
2243 SH_PFC_FUNCTION(ssi),
2244};
2245
2246static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2247#define F_(x, y) FN_##y
2248#define FM(x) FN_##x
2249 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
2250 0, 0,
2251 0, 0,
2252 0, 0,
2253 0, 0,
2254 0, 0,
2255 0, 0,
2256 0, 0,
2257 0, 0,
2258 0, 0,
2259 0, 0,
2260 0, 0,
2261 0, 0,
2262 0, 0,
2263 0, 0,
2264 0, 0,
2265 0, 0,
2266 GP_0_15_FN, GPSR0_15,
2267 GP_0_14_FN, GPSR0_14,
2268 GP_0_13_FN, GPSR0_13,
2269 GP_0_12_FN, GPSR0_12,
2270 GP_0_11_FN, GPSR0_11,
2271 GP_0_10_FN, GPSR0_10,
2272 GP_0_9_FN, GPSR0_9,
2273 GP_0_8_FN, GPSR0_8,
2274 GP_0_7_FN, GPSR0_7,
2275 GP_0_6_FN, GPSR0_6,
2276 GP_0_5_FN, GPSR0_5,
2277 GP_0_4_FN, GPSR0_4,
2278 GP_0_3_FN, GPSR0_3,
2279 GP_0_2_FN, GPSR0_2,
2280 GP_0_1_FN, GPSR0_1,
2281 GP_0_0_FN, GPSR0_0, }
2282 },
2283 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
2284 0, 0,
2285 0, 0,
2286 0, 0,
2287 0, 0,
2288 GP_1_27_FN, GPSR1_27,
2289 GP_1_26_FN, GPSR1_26,
2290 GP_1_25_FN, GPSR1_25,
2291 GP_1_24_FN, GPSR1_24,
2292 GP_1_23_FN, GPSR1_23,
2293 GP_1_22_FN, GPSR1_22,
2294 GP_1_21_FN, GPSR1_21,
2295 GP_1_20_FN, GPSR1_20,
2296 GP_1_19_FN, GPSR1_19,
2297 GP_1_18_FN, GPSR1_18,
2298 GP_1_17_FN, GPSR1_17,
2299 GP_1_16_FN, GPSR1_16,
2300 GP_1_15_FN, GPSR1_15,
2301 GP_1_14_FN, GPSR1_14,
2302 GP_1_13_FN, GPSR1_13,
2303 GP_1_12_FN, GPSR1_12,
2304 GP_1_11_FN, GPSR1_11,
2305 GP_1_10_FN, GPSR1_10,
2306 GP_1_9_FN, GPSR1_9,
2307 GP_1_8_FN, GPSR1_8,
2308 GP_1_7_FN, GPSR1_7,
2309 GP_1_6_FN, GPSR1_6,
2310 GP_1_5_FN, GPSR1_5,
2311 GP_1_4_FN, GPSR1_4,
2312 GP_1_3_FN, GPSR1_3,
2313 GP_1_2_FN, GPSR1_2,
2314 GP_1_1_FN, GPSR1_1,
2315 GP_1_0_FN, GPSR1_0, }
2316 },
2317 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
2318 0, 0,
2319 0, 0,
2320 0, 0,
2321 0, 0,
2322 0, 0,
2323 0, 0,
2324 0, 0,
2325 0, 0,
2326 0, 0,
2327 0, 0,
2328 0, 0,
2329 0, 0,
2330 0, 0,
2331 0, 0,
2332 0, 0,
2333 0, 0,
2334 0, 0,
2335 GP_2_14_FN, GPSR2_14,
2336 GP_2_13_FN, GPSR2_13,
2337 GP_2_12_FN, GPSR2_12,
2338 GP_2_11_FN, GPSR2_11,
2339 GP_2_10_FN, GPSR2_10,
2340 GP_2_9_FN, GPSR2_9,
2341 GP_2_8_FN, GPSR2_8,
2342 GP_2_7_FN, GPSR2_7,
2343 GP_2_6_FN, GPSR2_6,
2344 GP_2_5_FN, GPSR2_5,
2345 GP_2_4_FN, GPSR2_4,
2346 GP_2_3_FN, GPSR2_3,
2347 GP_2_2_FN, GPSR2_2,
2348 GP_2_1_FN, GPSR2_1,
2349 GP_2_0_FN, GPSR2_0, }
2350 },
2351 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
2352 0, 0,
2353 0, 0,
2354 0, 0,
2355 0, 0,
2356 0, 0,
2357 0, 0,
2358 0, 0,
2359 0, 0,
2360 0, 0,
2361 0, 0,
2362 0, 0,
2363 0, 0,
2364 0, 0,
2365 0, 0,
2366 0, 0,
2367 0, 0,
2368 GP_3_15_FN, GPSR3_15,
2369 GP_3_14_FN, GPSR3_14,
2370 GP_3_13_FN, GPSR3_13,
2371 GP_3_12_FN, GPSR3_12,
2372 GP_3_11_FN, GPSR3_11,
2373 GP_3_10_FN, GPSR3_10,
2374 GP_3_9_FN, GPSR3_9,
2375 GP_3_8_FN, GPSR3_8,
2376 GP_3_7_FN, GPSR3_7,
2377 GP_3_6_FN, GPSR3_6,
2378 GP_3_5_FN, GPSR3_5,
2379 GP_3_4_FN, GPSR3_4,
2380 GP_3_3_FN, GPSR3_3,
2381 GP_3_2_FN, GPSR3_2,
2382 GP_3_1_FN, GPSR3_1,
2383 GP_3_0_FN, GPSR3_0, }
2384 },
2385 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
2386 0, 0,
2387 0, 0,
2388 0, 0,
2389 0, 0,
2390 0, 0,
2391 0, 0,
2392 0, 0,
2393 0, 0,
2394 0, 0,
2395 0, 0,
2396 0, 0,
2397 0, 0,
2398 0, 0,
2399 0, 0,
2400 GP_4_17_FN, GPSR4_17,
2401 GP_4_16_FN, GPSR4_16,
2402 GP_4_15_FN, GPSR4_15,
2403 GP_4_14_FN, GPSR4_14,
2404 GP_4_13_FN, GPSR4_13,
2405 GP_4_12_FN, GPSR4_12,
2406 GP_4_11_FN, GPSR4_11,
2407 GP_4_10_FN, GPSR4_10,
2408 GP_4_9_FN, GPSR4_9,
2409 GP_4_8_FN, GPSR4_8,
2410 GP_4_7_FN, GPSR4_7,
2411 GP_4_6_FN, GPSR4_6,
2412 GP_4_5_FN, GPSR4_5,
2413 GP_4_4_FN, GPSR4_4,
2414 GP_4_3_FN, GPSR4_3,
2415 GP_4_2_FN, GPSR4_2,
2416 GP_4_1_FN, GPSR4_1,
2417 GP_4_0_FN, GPSR4_0, }
2418 },
2419 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
2420 0, 0,
2421 0, 0,
2422 0, 0,
2423 0, 0,
2424 0, 0,
2425 0, 0,
2426 GP_5_25_FN, GPSR5_25,
2427 GP_5_24_FN, GPSR5_24,
2428 GP_5_23_FN, GPSR5_23,
2429 GP_5_22_FN, GPSR5_22,
2430 GP_5_21_FN, GPSR5_21,
2431 GP_5_20_FN, GPSR5_20,
2432 GP_5_19_FN, GPSR5_19,
2433 GP_5_18_FN, GPSR5_18,
2434 GP_5_17_FN, GPSR5_17,
2435 GP_5_16_FN, GPSR5_16,
2436 GP_5_15_FN, GPSR5_15,
2437 GP_5_14_FN, GPSR5_14,
2438 GP_5_13_FN, GPSR5_13,
2439 GP_5_12_FN, GPSR5_12,
2440 GP_5_11_FN, GPSR5_11,
2441 GP_5_10_FN, GPSR5_10,
2442 GP_5_9_FN, GPSR5_9,
2443 GP_5_8_FN, GPSR5_8,
2444 GP_5_7_FN, GPSR5_7,
2445 GP_5_6_FN, GPSR5_6,
2446 GP_5_5_FN, GPSR5_5,
2447 GP_5_4_FN, GPSR5_4,
2448 GP_5_3_FN, GPSR5_3,
2449 GP_5_2_FN, GPSR5_2,
2450 GP_5_1_FN, GPSR5_1,
2451 GP_5_0_FN, GPSR5_0, }
2452 },
2453 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
2454 GP_6_31_FN, GPSR6_31,
2455 GP_6_30_FN, GPSR6_30,
2456 GP_6_29_FN, GPSR6_29,
2457 GP_6_28_FN, GPSR6_28,
2458 GP_6_27_FN, GPSR6_27,
2459 GP_6_26_FN, GPSR6_26,
2460 GP_6_25_FN, GPSR6_25,
2461 GP_6_24_FN, GPSR6_24,
2462 GP_6_23_FN, GPSR6_23,
2463 GP_6_22_FN, GPSR6_22,
2464 GP_6_21_FN, GPSR6_21,
2465 GP_6_20_FN, GPSR6_20,
2466 GP_6_19_FN, GPSR6_19,
2467 GP_6_18_FN, GPSR6_18,
2468 GP_6_17_FN, GPSR6_17,
2469 GP_6_16_FN, GPSR6_16,
2470 GP_6_15_FN, GPSR6_15,
2471 GP_6_14_FN, GPSR6_14,
2472 GP_6_13_FN, GPSR6_13,
2473 GP_6_12_FN, GPSR6_12,
2474 GP_6_11_FN, GPSR6_11,
2475 GP_6_10_FN, GPSR6_10,
2476 GP_6_9_FN, GPSR6_9,
2477 GP_6_8_FN, GPSR6_8,
2478 GP_6_7_FN, GPSR6_7,
2479 GP_6_6_FN, GPSR6_6,
2480 GP_6_5_FN, GPSR6_5,
2481 GP_6_4_FN, GPSR6_4,
2482 GP_6_3_FN, GPSR6_3,
2483 GP_6_2_FN, GPSR6_2,
2484 GP_6_1_FN, GPSR6_1,
2485 GP_6_0_FN, GPSR6_0, }
2486 },
2487 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
2488 0, 0,
2489 0, 0,
2490 0, 0,
2491 0, 0,
2492 0, 0,
2493 0, 0,
2494 0, 0,
2495 0, 0,
2496 0, 0,
2497 0, 0,
2498 0, 0,
2499 0, 0,
2500 0, 0,
2501 0, 0,
2502 0, 0,
2503 0, 0,
2504 0, 0,
2505 0, 0,
2506 0, 0,
2507 0, 0,
2508 0, 0,
2509 0, 0,
2510 0, 0,
2511 0, 0,
2512 0, 0,
2513 0, 0,
2514 0, 0,
2515 0, 0,
2516 GP_7_3_FN, GPSR7_3,
2517 GP_7_2_FN, GPSR7_2,
2518 GP_7_1_FN, GPSR7_1,
2519 GP_7_0_FN, GPSR7_0, }
2520 },
2521#undef F_
2522#undef FM
2523
2524#define F_(x, y) x,
2525#define FM(x) FN_##x,
2526 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
2527 IP0_31_28
2528 IP0_27_24
2529 IP0_23_20
2530 IP0_19_16
2531 IP0_15_12
2532 IP0_11_8
2533 IP0_7_4
2534 IP0_3_0 }
2535 },
2536 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
2537 IP1_31_28
2538 IP1_27_24
2539 IP1_23_20
2540 IP1_19_16
2541 IP1_15_12
2542 IP1_11_8
2543 IP1_7_4
2544 IP1_3_0 }
2545 },
2546 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
2547 IP2_31_28
2548 IP2_27_24
2549 IP2_23_20
2550 IP2_19_16
2551 IP2_15_12
2552 IP2_11_8
2553 IP2_7_4
2554 IP2_3_0 }
2555 },
2556 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
2557 IP3_31_28
2558 IP3_27_24
2559 IP3_23_20
2560 IP3_19_16
2561 IP3_15_12
2562 IP3_11_8
2563 IP3_7_4
2564 IP3_3_0 }
2565 },
2566 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
2567 IP4_31_28
2568 IP4_27_24
2569 IP4_23_20
2570 IP4_19_16
2571 IP4_15_12
2572 IP4_11_8
2573 IP4_7_4
2574 IP4_3_0 }
2575 },
2576 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
2577 IP5_31_28
2578 IP5_27_24
2579 IP5_23_20
2580 IP5_19_16
2581 IP5_15_12
2582 IP5_11_8
2583 IP5_7_4
2584 IP5_3_0 }
2585 },
2586 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
2587 IP6_31_28
2588 IP6_27_24
2589 IP6_23_20
2590 IP6_19_16
2591 IP6_15_12
2592 IP6_11_8
2593 IP6_7_4
2594 IP6_3_0 }
2595 },
2596 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
2597 IP7_31_28
2598 IP7_27_24
2599 IP7_23_20
2600 IP7_19_16
2601 IP7_15_12
2602 IP7_11_8
2603 IP7_7_4
2604 IP7_3_0 }
2605 },
2606 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
2607 IP8_31_28
2608 IP8_27_24
2609 IP8_23_20
2610 IP8_19_16
2611 IP8_15_12
2612 IP8_11_8
2613 IP8_7_4
2614 IP8_3_0 }
2615 },
2616 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
2617 IP9_31_28
2618 IP9_27_24
2619 IP9_23_20
2620 IP9_19_16
2621 IP9_15_12
2622 IP9_11_8
2623 IP9_7_4
2624 IP9_3_0 }
2625 },
2626 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
2627 IP10_31_28
2628 IP10_27_24
2629 IP10_23_20
2630 IP10_19_16
2631 IP10_15_12
2632 IP10_11_8
2633 IP10_7_4
2634 IP10_3_0 }
2635 },
2636 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
2637 IP11_31_28
2638 IP11_27_24
2639 IP11_23_20
2640 IP11_19_16
2641 IP11_15_12
2642 IP11_11_8
2643 IP11_7_4
2644 IP11_3_0 }
2645 },
2646 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
2647 IP12_31_28
2648 IP12_27_24
2649 IP12_23_20
2650 IP12_19_16
2651 IP12_15_12
2652 IP12_11_8
2653 IP12_7_4
2654 IP12_3_0 }
2655 },
2656 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
2657 IP13_31_28
2658 IP13_27_24
2659 IP13_23_20
2660 IP13_19_16
2661 IP13_15_12
2662 IP13_11_8
2663 IP13_7_4
2664 IP13_3_0 }
2665 },
2666 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
2667 IP14_31_28
2668 IP14_27_24
2669 IP14_23_20
2670 IP14_19_16
2671 IP14_15_12
2672 IP14_11_8
2673 IP14_7_4
2674 IP14_3_0 }
2675 },
2676 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
2677 IP15_31_28
2678 IP15_27_24
2679 IP15_23_20
2680 IP15_19_16
2681 IP15_15_12
2682 IP15_11_8
2683 IP15_7_4
2684 IP15_3_0 }
2685 },
2686 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
2687 IP16_31_28
2688 IP16_27_24
2689 IP16_23_20
2690 IP16_19_16
2691 IP16_15_12
2692 IP16_11_8
2693 IP16_7_4
2694 IP16_3_0 }
2695 },
2696 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
2697 /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2698 /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2699 /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2700 /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2701 /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2702 /* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2703 IP17_7_4
2704 IP17_3_0 }
2705 },
2706#undef F_
2707#undef FM
2708
2709#define F_(x, y) x,
2710#define FM(x) FN_##x,
2711 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2712 1, 2, 2, 3, 1, 1, 2, 1, 1, 1,
2713 2, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) {
2714 0, 0, /* RESERVED 31 */
2715 MOD_SEL0_30_29
2716 MOD_SEL0_28_27
2717 MOD_SEL0_26_25_24
2718 MOD_SEL0_23
2719 MOD_SEL0_22
2720 MOD_SEL0_21_20
2721 MOD_SEL0_19
2722 MOD_SEL0_18
2723 MOD_SEL0_17
2724 MOD_SEL0_16_15
2725 MOD_SEL0_14
2726 MOD_SEL0_13
2727 MOD_SEL0_12
2728 MOD_SEL0_11
2729 MOD_SEL0_10
2730 MOD_SEL0_9
2731 MOD_SEL0_8
2732 MOD_SEL0_7_6
2733 MOD_SEL0_5_4
2734 MOD_SEL0_3
2735 MOD_SEL0_2_1
2736 0, 0, /* RESERVED 0 */ }
2737 },
2738 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2739 2, 3, 1, 2, 3, 1, 1, 2, 1,
2740 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
2741 MOD_SEL1_31_30
2742 MOD_SEL1_29_28_27
2743 MOD_SEL1_26
2744 MOD_SEL1_25_24
2745 MOD_SEL1_23_22_21
2746 MOD_SEL1_20
2747 MOD_SEL1_19
2748 MOD_SEL1_18_17
2749 MOD_SEL1_16
2750 MOD_SEL1_15_14
2751 MOD_SEL1_13
2752 MOD_SEL1_12
2753 MOD_SEL1_11
2754 MOD_SEL1_10
2755 MOD_SEL1_9
2756 0, 0, 0, 0, /* RESERVED 8, 7 */
2757 MOD_SEL1_6
2758 MOD_SEL1_5
2759 MOD_SEL1_4
2760 MOD_SEL1_3
2761 MOD_SEL1_2
2762 MOD_SEL1_1
2763 MOD_SEL1_0 }
2764 },
2765 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
2766 1, 1, 1, 1, 4, 4, 4,
2767 4, 4, 4, 1, 2, 1) {
2768 MOD_SEL2_31
2769 MOD_SEL2_30
2770 MOD_SEL2_29
2771 /* RESERVED 28 */
2772 0, 0,
2773 /* RESERVED 27, 26, 25, 24 */
2774 0, 0, 0, 0, 0, 0, 0, 0,
2775 0, 0, 0, 0, 0, 0, 0, 0,
2776 /* RESERVED 23, 22, 21, 20 */
2777 0, 0, 0, 0, 0, 0, 0, 0,
2778 0, 0, 0, 0, 0, 0, 0, 0,
2779 /* RESERVED 19, 18, 17, 16 */
2780 0, 0, 0, 0, 0, 0, 0, 0,
2781 0, 0, 0, 0, 0, 0, 0, 0,
2782 /* RESERVED 15, 14, 13, 12 */
2783 0, 0, 0, 0, 0, 0, 0, 0,
2784 0, 0, 0, 0, 0, 0, 0, 0,
2785 /* RESERVED 11, 10, 9, 8 */
2786 0, 0, 0, 0, 0, 0, 0, 0,
2787 0, 0, 0, 0, 0, 0, 0, 0,
2788 /* RESERVED 7, 6, 5, 4 */
2789 0, 0, 0, 0, 0, 0, 0, 0,
2790 0, 0, 0, 0, 0, 0, 0, 0,
2791 /* RESERVED 3 */
2792 0, 0,
2793 MOD_SEL2_2_1
2794 MOD_SEL2_0 }
2795 },
2796 { },
2797};
2798
2799const struct sh_pfc_soc_info r8a7795_pinmux_info = {
2800 .name = "r8a77950_pfc",
2801 .unlock_reg = 0xe6060000, /* PMMR */
2802
2803 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2804
2805 .pins = pinmux_pins,
2806 .nr_pins = ARRAY_SIZE(pinmux_pins),
2807 .groups = pinmux_groups,
2808 .nr_groups = ARRAY_SIZE(pinmux_groups),
2809 .functions = pinmux_functions,
2810 .nr_functions = ARRAY_SIZE(pinmux_functions),
2811
2812 .cfg_regs = pinmux_config_regs,
2813
2814 .pinmux_data = pinmux_data,
2815 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2816};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
index 3bda7bafd0ab..61b27ec48876 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
@@ -1587,6 +1587,6 @@ const struct sh_pfc_soc_info sh7203_pinmux_info = {
1587 .cfg_regs = pinmux_config_regs, 1587 .cfg_regs = pinmux_config_regs,
1588 .data_regs = pinmux_data_regs, 1588 .data_regs = pinmux_data_regs,
1589 1589
1590 .gpio_data = pinmux_data, 1590 .pinmux_data = pinmux_data,
1591 .gpio_data_size = ARRAY_SIZE(pinmux_data), 1591 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
1592}; 1592};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
index e1cb6dc05028..8070765311db 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
@@ -2126,6 +2126,6 @@ const struct sh_pfc_soc_info sh7264_pinmux_info = {
2126 .cfg_regs = pinmux_config_regs, 2126 .cfg_regs = pinmux_config_regs,
2127 .data_regs = pinmux_data_regs, 2127 .data_regs = pinmux_data_regs,
2128 2128
2129 .gpio_data = pinmux_data, 2129 .pinmux_data = pinmux_data,
2130 .gpio_data_size = ARRAY_SIZE(pinmux_data), 2130 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2131}; 2131};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
index 7a11320ad96d..a50d22bef1f4 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
@@ -2830,6 +2830,6 @@ const struct sh_pfc_soc_info sh7269_pinmux_info = {
2830 .cfg_regs = pinmux_config_regs, 2830 .cfg_regs = pinmux_config_regs,
2831 .data_regs = pinmux_data_regs, 2831 .data_regs = pinmux_data_regs,
2832 2832
2833 .gpio_data = pinmux_data, 2833 .pinmux_data = pinmux_data,
2834 .gpio_data_size = ARRAY_SIZE(pinmux_data), 2834 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2835}; 2835};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 097526576f88..6a69c8c5d943 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -3649,38 +3649,38 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
3649}; 3649};
3650 3650
3651static const struct pinmux_irq pinmux_irqs[] = { 3651static const struct pinmux_irq pinmux_irqs[] = {
3652 PINMUX_IRQ(irq_pin(0), 11), 3652 PINMUX_IRQ(11), /* IRQ0 */
3653 PINMUX_IRQ(irq_pin(1), 10), 3653 PINMUX_IRQ(10), /* IRQ1 */
3654 PINMUX_IRQ(irq_pin(2), 149), 3654 PINMUX_IRQ(149), /* IRQ2 */
3655 PINMUX_IRQ(irq_pin(3), 224), 3655 PINMUX_IRQ(224), /* IRQ3 */
3656 PINMUX_IRQ(irq_pin(4), 159), 3656 PINMUX_IRQ(159), /* IRQ4 */
3657 PINMUX_IRQ(irq_pin(5), 227), 3657 PINMUX_IRQ(227), /* IRQ5 */
3658 PINMUX_IRQ(irq_pin(6), 147), 3658 PINMUX_IRQ(147), /* IRQ6 */
3659 PINMUX_IRQ(irq_pin(7), 150), 3659 PINMUX_IRQ(150), /* IRQ7 */
3660 PINMUX_IRQ(irq_pin(8), 223), 3660 PINMUX_IRQ(223), /* IRQ8 */
3661 PINMUX_IRQ(irq_pin(9), 56, 308), 3661 PINMUX_IRQ(56, 308), /* IRQ9 */
3662 PINMUX_IRQ(irq_pin(10), 54), 3662 PINMUX_IRQ(54), /* IRQ10 */
3663 PINMUX_IRQ(irq_pin(11), 238), 3663 PINMUX_IRQ(238), /* IRQ11 */
3664 PINMUX_IRQ(irq_pin(12), 156), 3664 PINMUX_IRQ(156), /* IRQ12 */
3665 PINMUX_IRQ(irq_pin(13), 239), 3665 PINMUX_IRQ(239), /* IRQ13 */
3666 PINMUX_IRQ(irq_pin(14), 251), 3666 PINMUX_IRQ(251), /* IRQ14 */
3667 PINMUX_IRQ(irq_pin(15), 0), 3667 PINMUX_IRQ(0), /* IRQ15 */
3668 PINMUX_IRQ(irq_pin(16), 249), 3668 PINMUX_IRQ(249), /* IRQ16 */
3669 PINMUX_IRQ(irq_pin(17), 234), 3669 PINMUX_IRQ(234), /* IRQ17 */
3670 PINMUX_IRQ(irq_pin(18), 13), 3670 PINMUX_IRQ(13), /* IRQ18 */
3671 PINMUX_IRQ(irq_pin(19), 9), 3671 PINMUX_IRQ(9), /* IRQ19 */
3672 PINMUX_IRQ(irq_pin(20), 14), 3672 PINMUX_IRQ(14), /* IRQ20 */
3673 PINMUX_IRQ(irq_pin(21), 15), 3673 PINMUX_IRQ(15), /* IRQ21 */
3674 PINMUX_IRQ(irq_pin(22), 40), 3674 PINMUX_IRQ(40), /* IRQ22 */
3675 PINMUX_IRQ(irq_pin(23), 53), 3675 PINMUX_IRQ(53), /* IRQ23 */
3676 PINMUX_IRQ(irq_pin(24), 118), 3676 PINMUX_IRQ(118), /* IRQ24 */
3677 PINMUX_IRQ(irq_pin(25), 164), 3677 PINMUX_IRQ(164), /* IRQ25 */
3678 PINMUX_IRQ(irq_pin(26), 115), 3678 PINMUX_IRQ(115), /* IRQ26 */
3679 PINMUX_IRQ(irq_pin(27), 116), 3679 PINMUX_IRQ(116), /* IRQ27 */
3680 PINMUX_IRQ(irq_pin(28), 117), 3680 PINMUX_IRQ(117), /* IRQ28 */
3681 PINMUX_IRQ(irq_pin(29), 28), 3681 PINMUX_IRQ(28), /* IRQ29 */
3682 PINMUX_IRQ(irq_pin(30), 27), 3682 PINMUX_IRQ(27), /* IRQ30 */
3683 PINMUX_IRQ(irq_pin(31), 26), 3683 PINMUX_IRQ(26), /* IRQ31 */
3684}; 3684};
3685 3685
3686/* ----------------------------------------------------------------------------- 3686/* -----------------------------------------------------------------------------
@@ -3865,8 +3865,8 @@ const struct sh_pfc_soc_info sh73a0_pinmux_info = {
3865 .cfg_regs = pinmux_config_regs, 3865 .cfg_regs = pinmux_config_regs,
3866 .data_regs = pinmux_data_regs, 3866 .data_regs = pinmux_data_regs,
3867 3867
3868 .gpio_data = pinmux_data, 3868 .pinmux_data = pinmux_data,
3869 .gpio_data_size = ARRAY_SIZE(pinmux_data), 3869 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3870 3870
3871 .gpio_irq = pinmux_irqs, 3871 .gpio_irq = pinmux_irqs,
3872 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs), 3872 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
index 13d05f88bc01..e07a82df42c8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
@@ -1201,6 +1201,6 @@ const struct sh_pfc_soc_info sh7720_pinmux_info = {
1201 .cfg_regs = pinmux_config_regs, 1201 .cfg_regs = pinmux_config_regs,
1202 .data_regs = pinmux_data_regs, 1202 .data_regs = pinmux_data_regs,
1203 1203
1204 .gpio_data = pinmux_data, 1204 .pinmux_data = pinmux_data,
1205 .gpio_data_size = ARRAY_SIZE(pinmux_data), 1205 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
1206}; 1206};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
index 914d872c37a4..29c69133b0ef 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
@@ -1741,6 +1741,6 @@ const struct sh_pfc_soc_info sh7722_pinmux_info = {
1741 .cfg_regs = pinmux_config_regs, 1741 .cfg_regs = pinmux_config_regs,
1742 .data_regs = pinmux_data_regs, 1742 .data_regs = pinmux_data_regs,
1743 1743
1744 .gpio_data = pinmux_data, 1744 .pinmux_data = pinmux_data,
1745 .gpio_data_size = ARRAY_SIZE(pinmux_data), 1745 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
1746}; 1746};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
index 4eb7eae2e6d0..8ea18df03492 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
@@ -1893,6 +1893,6 @@ const struct sh_pfc_soc_info sh7723_pinmux_info = {
1893 .cfg_regs = pinmux_config_regs, 1893 .cfg_regs = pinmux_config_regs,
1894 .data_regs = pinmux_data_regs, 1894 .data_regs = pinmux_data_regs,
1895 1895
1896 .gpio_data = pinmux_data, 1896 .pinmux_data = pinmux_data,
1897 .gpio_data_size = ARRAY_SIZE(pinmux_data), 1897 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
1898}; 1898};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
index 74a1a7f1317c..7f6c36c1a8fa 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
@@ -2175,6 +2175,6 @@ const struct sh_pfc_soc_info sh7724_pinmux_info = {
2175 .cfg_regs = pinmux_config_regs, 2175 .cfg_regs = pinmux_config_regs,
2176 .data_regs = pinmux_data_regs, 2176 .data_regs = pinmux_data_regs,
2177 2177
2178 .gpio_data = pinmux_data, 2178 .pinmux_data = pinmux_data,
2179 .gpio_data_size = ARRAY_SIZE(pinmux_data), 2179 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2180}; 2180};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
index e53dd1cb1625..e7deb51de7dc 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
@@ -598,502 +598,502 @@ static const u16 pinmux_data[] = {
598 /* IPSR0 */ 598 /* IPSR0 */
599 PINMUX_IPSR_DATA(IP0_1_0, A0), 599 PINMUX_IPSR_DATA(IP0_1_0, A0),
600 PINMUX_IPSR_DATA(IP0_1_0, ST0_CLKIN), 600 PINMUX_IPSR_DATA(IP0_1_0, ST0_CLKIN),
601 PINMUX_IPSR_MODSEL_DATA(IP0_1_0, LCD_DATA0_A, SEL_LCDC_0), 601 PINMUX_IPSR_MSEL(IP0_1_0, LCD_DATA0_A, SEL_LCDC_0),
602 PINMUX_IPSR_MODSEL_DATA(IP0_1_0, TCLKA_C, SEL_MTU2_CLK_1), 602 PINMUX_IPSR_MSEL(IP0_1_0, TCLKA_C, SEL_MTU2_CLK_1),
603 603
604 PINMUX_IPSR_DATA(IP0_3_2, A1), 604 PINMUX_IPSR_DATA(IP0_3_2, A1),
605 PINMUX_IPSR_DATA(IP0_3_2, ST0_REQ), 605 PINMUX_IPSR_DATA(IP0_3_2, ST0_REQ),
606 PINMUX_IPSR_MODSEL_DATA(IP0_3_2, LCD_DATA1_A, SEL_LCDC_0), 606 PINMUX_IPSR_MSEL(IP0_3_2, LCD_DATA1_A, SEL_LCDC_0),
607 PINMUX_IPSR_MODSEL_DATA(IP0_3_2, TCLKB_C, SEL_MTU2_CLK_1), 607 PINMUX_IPSR_MSEL(IP0_3_2, TCLKB_C, SEL_MTU2_CLK_1),
608 608
609 PINMUX_IPSR_DATA(IP0_5_4, A2), 609 PINMUX_IPSR_DATA(IP0_5_4, A2),
610 PINMUX_IPSR_DATA(IP0_5_4, ST0_SYC), 610 PINMUX_IPSR_DATA(IP0_5_4, ST0_SYC),
611 PINMUX_IPSR_MODSEL_DATA(IP0_5_4, LCD_DATA2_A, SEL_LCDC_0), 611 PINMUX_IPSR_MSEL(IP0_5_4, LCD_DATA2_A, SEL_LCDC_0),
612 PINMUX_IPSR_MODSEL_DATA(IP0_5_4, TCLKC_C, SEL_MTU2_CLK_1), 612 PINMUX_IPSR_MSEL(IP0_5_4, TCLKC_C, SEL_MTU2_CLK_1),
613 613
614 PINMUX_IPSR_DATA(IP0_7_6, A3), 614 PINMUX_IPSR_DATA(IP0_7_6, A3),
615 PINMUX_IPSR_DATA(IP0_7_6, ST0_VLD), 615 PINMUX_IPSR_DATA(IP0_7_6, ST0_VLD),
616 PINMUX_IPSR_MODSEL_DATA(IP0_7_6, LCD_DATA3_A, SEL_LCDC_0), 616 PINMUX_IPSR_MSEL(IP0_7_6, LCD_DATA3_A, SEL_LCDC_0),
617 PINMUX_IPSR_MODSEL_DATA(IP0_7_6, TCLKD_C, SEL_MTU2_CLK_1), 617 PINMUX_IPSR_MSEL(IP0_7_6, TCLKD_C, SEL_MTU2_CLK_1),
618 618
619 PINMUX_IPSR_DATA(IP0_9_8, A4), 619 PINMUX_IPSR_DATA(IP0_9_8, A4),
620 PINMUX_IPSR_DATA(IP0_9_8, ST0_D0), 620 PINMUX_IPSR_DATA(IP0_9_8, ST0_D0),
621 PINMUX_IPSR_MODSEL_DATA(IP0_9_8, LCD_DATA4_A, SEL_LCDC_0), 621 PINMUX_IPSR_MSEL(IP0_9_8, LCD_DATA4_A, SEL_LCDC_0),
622 PINMUX_IPSR_MODSEL_DATA(IP0_9_8, TIOC0A_C, SEL_MTU2_CH0_1), 622 PINMUX_IPSR_MSEL(IP0_9_8, TIOC0A_C, SEL_MTU2_CH0_1),
623 623
624 PINMUX_IPSR_DATA(IP0_11_10, A5), 624 PINMUX_IPSR_DATA(IP0_11_10, A5),
625 PINMUX_IPSR_DATA(IP0_11_10, ST0_D1), 625 PINMUX_IPSR_DATA(IP0_11_10, ST0_D1),
626 PINMUX_IPSR_MODSEL_DATA(IP0_11_10, LCD_DATA5_A, SEL_LCDC_0), 626 PINMUX_IPSR_MSEL(IP0_11_10, LCD_DATA5_A, SEL_LCDC_0),
627 PINMUX_IPSR_MODSEL_DATA(IP0_11_10, TIOC0B_C, SEL_MTU2_CH0_1), 627 PINMUX_IPSR_MSEL(IP0_11_10, TIOC0B_C, SEL_MTU2_CH0_1),
628 628
629 PINMUX_IPSR_DATA(IP0_13_12, A6), 629 PINMUX_IPSR_DATA(IP0_13_12, A6),
630 PINMUX_IPSR_DATA(IP0_13_12, ST0_D2), 630 PINMUX_IPSR_DATA(IP0_13_12, ST0_D2),
631 PINMUX_IPSR_MODSEL_DATA(IP0_13_12, LCD_DATA6_A, SEL_LCDC_0), 631 PINMUX_IPSR_MSEL(IP0_13_12, LCD_DATA6_A, SEL_LCDC_0),
632 PINMUX_IPSR_MODSEL_DATA(IP0_13_12, TIOC0C_C, SEL_MTU2_CH0_1), 632 PINMUX_IPSR_MSEL(IP0_13_12, TIOC0C_C, SEL_MTU2_CH0_1),
633 633
634 PINMUX_IPSR_DATA(IP0_15_14, A7), 634 PINMUX_IPSR_DATA(IP0_15_14, A7),
635 PINMUX_IPSR_DATA(IP0_15_14, ST0_D3), 635 PINMUX_IPSR_DATA(IP0_15_14, ST0_D3),
636 PINMUX_IPSR_MODSEL_DATA(IP0_15_14, LCD_DATA7_A, SEL_LCDC_0), 636 PINMUX_IPSR_MSEL(IP0_15_14, LCD_DATA7_A, SEL_LCDC_0),
637 PINMUX_IPSR_MODSEL_DATA(IP0_15_14, TIOC0D_C, SEL_MTU2_CH0_1), 637 PINMUX_IPSR_MSEL(IP0_15_14, TIOC0D_C, SEL_MTU2_CH0_1),
638 638
639 PINMUX_IPSR_DATA(IP0_17_16, A8), 639 PINMUX_IPSR_DATA(IP0_17_16, A8),
640 PINMUX_IPSR_DATA(IP0_17_16, ST0_D4), 640 PINMUX_IPSR_DATA(IP0_17_16, ST0_D4),
641 PINMUX_IPSR_MODSEL_DATA(IP0_17_16, LCD_DATA8_A, SEL_LCDC_0), 641 PINMUX_IPSR_MSEL(IP0_17_16, LCD_DATA8_A, SEL_LCDC_0),
642 PINMUX_IPSR_MODSEL_DATA(IP0_17_16, TIOC1A_C, SEL_MTU2_CH1_2), 642 PINMUX_IPSR_MSEL(IP0_17_16, TIOC1A_C, SEL_MTU2_CH1_2),
643 643
644 PINMUX_IPSR_DATA(IP0_19_18, A9), 644 PINMUX_IPSR_DATA(IP0_19_18, A9),
645 PINMUX_IPSR_DATA(IP0_19_18, ST0_D5), 645 PINMUX_IPSR_DATA(IP0_19_18, ST0_D5),
646 PINMUX_IPSR_MODSEL_DATA(IP0_19_18, LCD_DATA9_A, SEL_LCDC_0), 646 PINMUX_IPSR_MSEL(IP0_19_18, LCD_DATA9_A, SEL_LCDC_0),
647 PINMUX_IPSR_MODSEL_DATA(IP0_19_18, TIOC1B_C, SEL_MTU2_CH1_2), 647 PINMUX_IPSR_MSEL(IP0_19_18, TIOC1B_C, SEL_MTU2_CH1_2),
648 648
649 PINMUX_IPSR_DATA(IP0_21_20, A10), 649 PINMUX_IPSR_DATA(IP0_21_20, A10),
650 PINMUX_IPSR_DATA(IP0_21_20, ST0_D6), 650 PINMUX_IPSR_DATA(IP0_21_20, ST0_D6),
651 PINMUX_IPSR_MODSEL_DATA(IP0_21_20, LCD_DATA10_A, SEL_LCDC_0), 651 PINMUX_IPSR_MSEL(IP0_21_20, LCD_DATA10_A, SEL_LCDC_0),
652 PINMUX_IPSR_MODSEL_DATA(IP0_21_20, TIOC2A_C, SEL_MTU2_CH2_2), 652 PINMUX_IPSR_MSEL(IP0_21_20, TIOC2A_C, SEL_MTU2_CH2_2),
653 653
654 PINMUX_IPSR_DATA(IP0_23_22, A11), 654 PINMUX_IPSR_DATA(IP0_23_22, A11),
655 PINMUX_IPSR_DATA(IP0_23_22, ST0_D7), 655 PINMUX_IPSR_DATA(IP0_23_22, ST0_D7),
656 PINMUX_IPSR_MODSEL_DATA(IP0_23_22, LCD_DATA11_A, SEL_LCDC_0), 656 PINMUX_IPSR_MSEL(IP0_23_22, LCD_DATA11_A, SEL_LCDC_0),
657 PINMUX_IPSR_MODSEL_DATA(IP0_23_22, TIOC2B_C, SEL_MTU2_CH2_2), 657 PINMUX_IPSR_MSEL(IP0_23_22, TIOC2B_C, SEL_MTU2_CH2_2),
658 658
659 PINMUX_IPSR_DATA(IP0_25_24, A12), 659 PINMUX_IPSR_DATA(IP0_25_24, A12),
660 PINMUX_IPSR_MODSEL_DATA(IP0_25_24, LCD_DATA12_A, SEL_LCDC_0), 660 PINMUX_IPSR_MSEL(IP0_25_24, LCD_DATA12_A, SEL_LCDC_0),
661 PINMUX_IPSR_MODSEL_DATA(IP0_25_24, TIOC3A_C, SEL_MTU2_CH3_1), 661 PINMUX_IPSR_MSEL(IP0_25_24, TIOC3A_C, SEL_MTU2_CH3_1),
662 662
663 PINMUX_IPSR_DATA(IP0_27_26, A13), 663 PINMUX_IPSR_DATA(IP0_27_26, A13),
664 PINMUX_IPSR_MODSEL_DATA(IP0_27_26, LCD_DATA13_A, SEL_LCDC_0), 664 PINMUX_IPSR_MSEL(IP0_27_26, LCD_DATA13_A, SEL_LCDC_0),
665 PINMUX_IPSR_MODSEL_DATA(IP0_27_26, TIOC3B_C, SEL_MTU2_CH3_1), 665 PINMUX_IPSR_MSEL(IP0_27_26, TIOC3B_C, SEL_MTU2_CH3_1),
666 666
667 PINMUX_IPSR_DATA(IP0_29_28, A14), 667 PINMUX_IPSR_DATA(IP0_29_28, A14),
668 PINMUX_IPSR_MODSEL_DATA(IP0_29_28, LCD_DATA14_A, SEL_LCDC_0), 668 PINMUX_IPSR_MSEL(IP0_29_28, LCD_DATA14_A, SEL_LCDC_0),
669 PINMUX_IPSR_MODSEL_DATA(IP0_29_28, TIOC3C_C, SEL_MTU2_CH3_1), 669 PINMUX_IPSR_MSEL(IP0_29_28, TIOC3C_C, SEL_MTU2_CH3_1),
670 670
671 PINMUX_IPSR_DATA(IP0_31_30, A15), 671 PINMUX_IPSR_DATA(IP0_31_30, A15),
672 PINMUX_IPSR_DATA(IP0_31_30, ST0_VCO_CLKIN), 672 PINMUX_IPSR_DATA(IP0_31_30, ST0_VCO_CLKIN),
673 PINMUX_IPSR_MODSEL_DATA(IP0_31_30, LCD_DATA15_A, SEL_LCDC_0), 673 PINMUX_IPSR_MSEL(IP0_31_30, LCD_DATA15_A, SEL_LCDC_0),
674 PINMUX_IPSR_MODSEL_DATA(IP0_31_30, TIOC3D_C, SEL_MTU2_CH3_1), 674 PINMUX_IPSR_MSEL(IP0_31_30, TIOC3D_C, SEL_MTU2_CH3_1),
675 675
676 676
677 /* IPSR1 */ 677 /* IPSR1 */
678 PINMUX_IPSR_DATA(IP1_1_0, A16), 678 PINMUX_IPSR_DATA(IP1_1_0, A16),
679 PINMUX_IPSR_DATA(IP1_1_0, ST0_PWM), 679 PINMUX_IPSR_DATA(IP1_1_0, ST0_PWM),
680 PINMUX_IPSR_MODSEL_DATA(IP1_1_0, LCD_DON_A, SEL_LCDC_0), 680 PINMUX_IPSR_MSEL(IP1_1_0, LCD_DON_A, SEL_LCDC_0),
681 PINMUX_IPSR_MODSEL_DATA(IP1_1_0, TIOC4A_C, SEL_MTU2_CH4_1), 681 PINMUX_IPSR_MSEL(IP1_1_0, TIOC4A_C, SEL_MTU2_CH4_1),
682 682
683 PINMUX_IPSR_DATA(IP1_3_2, A17), 683 PINMUX_IPSR_DATA(IP1_3_2, A17),
684 PINMUX_IPSR_DATA(IP1_3_2, ST1_VCO_CLKIN), 684 PINMUX_IPSR_DATA(IP1_3_2, ST1_VCO_CLKIN),
685 PINMUX_IPSR_MODSEL_DATA(IP1_3_2, LCD_CL1_A, SEL_LCDC_0), 685 PINMUX_IPSR_MSEL(IP1_3_2, LCD_CL1_A, SEL_LCDC_0),
686 PINMUX_IPSR_MODSEL_DATA(IP1_3_2, TIOC4B_C, SEL_MTU2_CH4_1), 686 PINMUX_IPSR_MSEL(IP1_3_2, TIOC4B_C, SEL_MTU2_CH4_1),
687 687
688 PINMUX_IPSR_DATA(IP1_5_4, A18), 688 PINMUX_IPSR_DATA(IP1_5_4, A18),
689 PINMUX_IPSR_DATA(IP1_5_4, ST1_PWM), 689 PINMUX_IPSR_DATA(IP1_5_4, ST1_PWM),
690 PINMUX_IPSR_MODSEL_DATA(IP1_5_4, LCD_CL2_A, SEL_LCDC_0), 690 PINMUX_IPSR_MSEL(IP1_5_4, LCD_CL2_A, SEL_LCDC_0),
691 PINMUX_IPSR_MODSEL_DATA(IP1_5_4, TIOC4C_C, SEL_MTU2_CH4_1), 691 PINMUX_IPSR_MSEL(IP1_5_4, TIOC4C_C, SEL_MTU2_CH4_1),
692 692
693 PINMUX_IPSR_DATA(IP1_7_6, A19), 693 PINMUX_IPSR_DATA(IP1_7_6, A19),
694 PINMUX_IPSR_DATA(IP1_7_6, ST1_CLKIN), 694 PINMUX_IPSR_DATA(IP1_7_6, ST1_CLKIN),
695 PINMUX_IPSR_MODSEL_DATA(IP1_7_6, LCD_CLK_A, SEL_LCDC_0), 695 PINMUX_IPSR_MSEL(IP1_7_6, LCD_CLK_A, SEL_LCDC_0),
696 PINMUX_IPSR_MODSEL_DATA(IP1_7_6, TIOC4D_C, SEL_MTU2_CH4_1), 696 PINMUX_IPSR_MSEL(IP1_7_6, TIOC4D_C, SEL_MTU2_CH4_1),
697 697
698 PINMUX_IPSR_DATA(IP1_9_8, A20), 698 PINMUX_IPSR_DATA(IP1_9_8, A20),
699 PINMUX_IPSR_DATA(IP1_9_8, ST1_REQ), 699 PINMUX_IPSR_DATA(IP1_9_8, ST1_REQ),
700 PINMUX_IPSR_MODSEL_DATA(IP1_9_8, LCD_FLM_A, SEL_LCDC_0), 700 PINMUX_IPSR_MSEL(IP1_9_8, LCD_FLM_A, SEL_LCDC_0),
701 701
702 PINMUX_IPSR_DATA(IP1_11_10, A21), 702 PINMUX_IPSR_DATA(IP1_11_10, A21),
703 PINMUX_IPSR_DATA(IP1_11_10, ST1_SYC), 703 PINMUX_IPSR_DATA(IP1_11_10, ST1_SYC),
704 PINMUX_IPSR_MODSEL_DATA(IP1_11_10, LCD_VCPWC_A, SEL_LCDC_0), 704 PINMUX_IPSR_MSEL(IP1_11_10, LCD_VCPWC_A, SEL_LCDC_0),
705 705
706 PINMUX_IPSR_DATA(IP1_13_12, A22), 706 PINMUX_IPSR_DATA(IP1_13_12, A22),
707 PINMUX_IPSR_DATA(IP1_13_12, ST1_VLD), 707 PINMUX_IPSR_DATA(IP1_13_12, ST1_VLD),
708 PINMUX_IPSR_MODSEL_DATA(IP1_13_12, LCD_VEPWC_A, SEL_LCDC_0), 708 PINMUX_IPSR_MSEL(IP1_13_12, LCD_VEPWC_A, SEL_LCDC_0),
709 709
710 PINMUX_IPSR_DATA(IP1_15_14, A23), 710 PINMUX_IPSR_DATA(IP1_15_14, A23),
711 PINMUX_IPSR_DATA(IP1_15_14, ST1_D0), 711 PINMUX_IPSR_DATA(IP1_15_14, ST1_D0),
712 PINMUX_IPSR_MODSEL_DATA(IP1_15_14, LCD_M_DISP_A, SEL_LCDC_0), 712 PINMUX_IPSR_MSEL(IP1_15_14, LCD_M_DISP_A, SEL_LCDC_0),
713 713
714 PINMUX_IPSR_DATA(IP1_17_16, A24), 714 PINMUX_IPSR_DATA(IP1_17_16, A24),
715 PINMUX_IPSR_MODSEL_DATA(IP1_17_16, RX2_D, SEL_SCIF2_3), 715 PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3),
716 PINMUX_IPSR_DATA(IP1_17_16, ST1_D1), 716 PINMUX_IPSR_DATA(IP1_17_16, ST1_D1),
717 717
718 PINMUX_IPSR_DATA(IP1_19_18, A25), 718 PINMUX_IPSR_DATA(IP1_19_18, A25),
719 PINMUX_IPSR_MODSEL_DATA(IP1_17_16, RX2_D, SEL_SCIF2_3), 719 PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3),
720 PINMUX_IPSR_DATA(IP1_17_16, ST1_D2), 720 PINMUX_IPSR_DATA(IP1_17_16, ST1_D2),
721 721
722 PINMUX_IPSR_DATA(IP1_22_20, D0), 722 PINMUX_IPSR_DATA(IP1_22_20, D0),
723 PINMUX_IPSR_MODSEL_DATA(IP1_22_20, SD0_DAT0_A, SEL_SDHI0_0), 723 PINMUX_IPSR_MSEL(IP1_22_20, SD0_DAT0_A, SEL_SDHI0_0),
724 PINMUX_IPSR_MODSEL_DATA(IP1_22_20, MMC_D0_A, SEL_MMC_0), 724 PINMUX_IPSR_MSEL(IP1_22_20, MMC_D0_A, SEL_MMC_0),
725 PINMUX_IPSR_DATA(IP1_22_20, ST1_D3), 725 PINMUX_IPSR_DATA(IP1_22_20, ST1_D3),
726 PINMUX_IPSR_MODSEL_DATA(IP1_22_20, FD0_A, SEL_FLCTL_0), 726 PINMUX_IPSR_MSEL(IP1_22_20, FD0_A, SEL_FLCTL_0),
727 727
728 PINMUX_IPSR_DATA(IP1_25_23, D1), 728 PINMUX_IPSR_DATA(IP1_25_23, D1),
729 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, SD0_DAT0_A, SEL_SDHI0_0), 729 PINMUX_IPSR_MSEL(IP1_25_23, SD0_DAT0_A, SEL_SDHI0_0),
730 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, MMC_D1_A, SEL_MMC_0), 730 PINMUX_IPSR_MSEL(IP1_25_23, MMC_D1_A, SEL_MMC_0),
731 PINMUX_IPSR_DATA(IP1_25_23, ST1_D4), 731 PINMUX_IPSR_DATA(IP1_25_23, ST1_D4),
732 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, FD1_A, SEL_FLCTL_0), 732 PINMUX_IPSR_MSEL(IP1_25_23, FD1_A, SEL_FLCTL_0),
733 733
734 PINMUX_IPSR_DATA(IP1_28_26, D2), 734 PINMUX_IPSR_DATA(IP1_28_26, D2),
735 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, SD0_DAT0_A, SEL_SDHI0_0), 735 PINMUX_IPSR_MSEL(IP1_28_26, SD0_DAT0_A, SEL_SDHI0_0),
736 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, MMC_D2_A, SEL_MMC_0), 736 PINMUX_IPSR_MSEL(IP1_28_26, MMC_D2_A, SEL_MMC_0),
737 PINMUX_IPSR_DATA(IP1_28_26, ST1_D5), 737 PINMUX_IPSR_DATA(IP1_28_26, ST1_D5),
738 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, FD2_A, SEL_FLCTL_0), 738 PINMUX_IPSR_MSEL(IP1_28_26, FD2_A, SEL_FLCTL_0),
739 739
740 PINMUX_IPSR_DATA(IP1_31_29, D3), 740 PINMUX_IPSR_DATA(IP1_31_29, D3),
741 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SD0_DAT0_A, SEL_SDHI0_0), 741 PINMUX_IPSR_MSEL(IP1_31_29, SD0_DAT0_A, SEL_SDHI0_0),
742 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, MMC_D3_A, SEL_MMC_0), 742 PINMUX_IPSR_MSEL(IP1_31_29, MMC_D3_A, SEL_MMC_0),
743 PINMUX_IPSR_DATA(IP1_31_29, ST1_D6), 743 PINMUX_IPSR_DATA(IP1_31_29, ST1_D6),
744 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, FD3_A, SEL_FLCTL_0), 744 PINMUX_IPSR_MSEL(IP1_31_29, FD3_A, SEL_FLCTL_0),
745 745
746 /* IPSR2 */ 746 /* IPSR2 */
747 PINMUX_IPSR_DATA(IP2_2_0, D4), 747 PINMUX_IPSR_DATA(IP2_2_0, D4),
748 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SD0_CD_A, SEL_SDHI0_0), 748 PINMUX_IPSR_MSEL(IP2_2_0, SD0_CD_A, SEL_SDHI0_0),
749 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MMC_D4_A, SEL_MMC_0), 749 PINMUX_IPSR_MSEL(IP2_2_0, MMC_D4_A, SEL_MMC_0),
750 PINMUX_IPSR_DATA(IP2_2_0, ST1_D7), 750 PINMUX_IPSR_DATA(IP2_2_0, ST1_D7),
751 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, FD4_A, SEL_FLCTL_0), 751 PINMUX_IPSR_MSEL(IP2_2_0, FD4_A, SEL_FLCTL_0),
752 752
753 PINMUX_IPSR_DATA(IP2_4_3, D5), 753 PINMUX_IPSR_DATA(IP2_4_3, D5),
754 PINMUX_IPSR_MODSEL_DATA(IP2_4_3, SD0_WP_A, SEL_SDHI0_0), 754 PINMUX_IPSR_MSEL(IP2_4_3, SD0_WP_A, SEL_SDHI0_0),
755 PINMUX_IPSR_MODSEL_DATA(IP2_4_3, MMC_D5_A, SEL_MMC_0), 755 PINMUX_IPSR_MSEL(IP2_4_3, MMC_D5_A, SEL_MMC_0),
756 PINMUX_IPSR_MODSEL_DATA(IP2_4_3, FD5_A, SEL_FLCTL_0), 756 PINMUX_IPSR_MSEL(IP2_4_3, FD5_A, SEL_FLCTL_0),
757 757
758 PINMUX_IPSR_DATA(IP2_7_5, D6), 758 PINMUX_IPSR_DATA(IP2_7_5, D6),
759 PINMUX_IPSR_MODSEL_DATA(IP2_7_5, RSPI_RSPCK_A, SEL_RSPI_0), 759 PINMUX_IPSR_MSEL(IP2_7_5, RSPI_RSPCK_A, SEL_RSPI_0),
760 PINMUX_IPSR_MODSEL_DATA(IP2_7_5, MMC_D6_A, SEL_MMC_0), 760 PINMUX_IPSR_MSEL(IP2_7_5, MMC_D6_A, SEL_MMC_0),
761 PINMUX_IPSR_MODSEL_DATA(IP2_7_5, QSPCLK_A, SEL_RQSPI_0), 761 PINMUX_IPSR_MSEL(IP2_7_5, QSPCLK_A, SEL_RQSPI_0),
762 PINMUX_IPSR_MODSEL_DATA(IP2_7_5, FD6_A, SEL_FLCTL_0), 762 PINMUX_IPSR_MSEL(IP2_7_5, FD6_A, SEL_FLCTL_0),
763 763
764 PINMUX_IPSR_DATA(IP2_10_8, D7), 764 PINMUX_IPSR_DATA(IP2_10_8, D7),
765 PINMUX_IPSR_MODSEL_DATA(IP2_10_8, RSPI_SSL_A, SEL_RSPI_0), 765 PINMUX_IPSR_MSEL(IP2_10_8, RSPI_SSL_A, SEL_RSPI_0),
766 PINMUX_IPSR_MODSEL_DATA(IP2_10_8, MMC_D7_A, SEL_MMC_0), 766 PINMUX_IPSR_MSEL(IP2_10_8, MMC_D7_A, SEL_MMC_0),
767 PINMUX_IPSR_MODSEL_DATA(IP2_10_8, QSSL_A, SEL_RQSPI_0), 767 PINMUX_IPSR_MSEL(IP2_10_8, QSSL_A, SEL_RQSPI_0),
768 PINMUX_IPSR_MODSEL_DATA(IP2_10_8, FD7_A, SEL_FLCTL_0), 768 PINMUX_IPSR_MSEL(IP2_10_8, FD7_A, SEL_FLCTL_0),
769 769
770 PINMUX_IPSR_DATA(IP2_13_11, D8), 770 PINMUX_IPSR_DATA(IP2_13_11, D8),
771 PINMUX_IPSR_MODSEL_DATA(IP2_13_11, SD0_CLK_A, SEL_SDHI0_0), 771 PINMUX_IPSR_MSEL(IP2_13_11, SD0_CLK_A, SEL_SDHI0_0),
772 PINMUX_IPSR_MODSEL_DATA(IP2_13_11, MMC_CLK_A, SEL_MMC_0), 772 PINMUX_IPSR_MSEL(IP2_13_11, MMC_CLK_A, SEL_MMC_0),
773 PINMUX_IPSR_MODSEL_DATA(IP2_13_11, QIO2_A, SEL_RQSPI_0), 773 PINMUX_IPSR_MSEL(IP2_13_11, QIO2_A, SEL_RQSPI_0),
774 PINMUX_IPSR_MODSEL_DATA(IP2_13_11, FCE_A, SEL_FLCTL_0), 774 PINMUX_IPSR_MSEL(IP2_13_11, FCE_A, SEL_FLCTL_0),
775 PINMUX_IPSR_MODSEL_DATA(IP2_13_11, ET0_GTX_CLK_B, SEL_ET0_1), 775 PINMUX_IPSR_MSEL(IP2_13_11, ET0_GTX_CLK_B, SEL_ET0_1),
776 776
777 PINMUX_IPSR_DATA(IP2_16_14, D9), 777 PINMUX_IPSR_DATA(IP2_16_14, D9),
778 PINMUX_IPSR_MODSEL_DATA(IP2_16_14, SD0_CMD_A, SEL_SDHI0_0), 778 PINMUX_IPSR_MSEL(IP2_16_14, SD0_CMD_A, SEL_SDHI0_0),
779 PINMUX_IPSR_MODSEL_DATA(IP2_16_14, MMC_CMD_A, SEL_MMC_0), 779 PINMUX_IPSR_MSEL(IP2_16_14, MMC_CMD_A, SEL_MMC_0),
780 PINMUX_IPSR_MODSEL_DATA(IP2_16_14, QIO3_A, SEL_RQSPI_0), 780 PINMUX_IPSR_MSEL(IP2_16_14, QIO3_A, SEL_RQSPI_0),
781 PINMUX_IPSR_MODSEL_DATA(IP2_16_14, FCLE_A, SEL_FLCTL_0), 781 PINMUX_IPSR_MSEL(IP2_16_14, FCLE_A, SEL_FLCTL_0),
782 PINMUX_IPSR_MODSEL_DATA(IP2_16_14, ET0_ETXD1_B, SEL_ET0_1), 782 PINMUX_IPSR_MSEL(IP2_16_14, ET0_ETXD1_B, SEL_ET0_1),
783 783
784 PINMUX_IPSR_DATA(IP2_19_17, D10), 784 PINMUX_IPSR_DATA(IP2_19_17, D10),
785 PINMUX_IPSR_MODSEL_DATA(IP2_19_17, RSPI_MOSI_A, SEL_RSPI_0), 785 PINMUX_IPSR_MSEL(IP2_19_17, RSPI_MOSI_A, SEL_RSPI_0),
786 PINMUX_IPSR_MODSEL_DATA(IP2_19_17, QMO_QIO0_A, SEL_RQSPI_0), 786 PINMUX_IPSR_MSEL(IP2_19_17, QMO_QIO0_A, SEL_RQSPI_0),
787 PINMUX_IPSR_MODSEL_DATA(IP2_19_17, FALE_A, SEL_FLCTL_0), 787 PINMUX_IPSR_MSEL(IP2_19_17, FALE_A, SEL_FLCTL_0),
788 PINMUX_IPSR_MODSEL_DATA(IP2_19_17, ET0_ETXD2_B, SEL_ET0_1), 788 PINMUX_IPSR_MSEL(IP2_19_17, ET0_ETXD2_B, SEL_ET0_1),
789 789
790 PINMUX_IPSR_DATA(IP2_22_20, D11), 790 PINMUX_IPSR_DATA(IP2_22_20, D11),
791 PINMUX_IPSR_MODSEL_DATA(IP2_22_20, RSPI_MISO_A, SEL_RSPI_0), 791 PINMUX_IPSR_MSEL(IP2_22_20, RSPI_MISO_A, SEL_RSPI_0),
792 PINMUX_IPSR_MODSEL_DATA(IP2_22_20, QMI_QIO1_A, SEL_RQSPI_0), 792 PINMUX_IPSR_MSEL(IP2_22_20, QMI_QIO1_A, SEL_RQSPI_0),
793 PINMUX_IPSR_MODSEL_DATA(IP2_22_20, FRE_A, SEL_FLCTL_0), 793 PINMUX_IPSR_MSEL(IP2_22_20, FRE_A, SEL_FLCTL_0),
794 794
795 PINMUX_IPSR_DATA(IP2_24_23, D12), 795 PINMUX_IPSR_DATA(IP2_24_23, D12),
796 PINMUX_IPSR_MODSEL_DATA(IP2_24_23, FWE_A, SEL_FLCTL_0), 796 PINMUX_IPSR_MSEL(IP2_24_23, FWE_A, SEL_FLCTL_0),
797 PINMUX_IPSR_MODSEL_DATA(IP2_24_23, ET0_ETXD5_B, SEL_ET0_1), 797 PINMUX_IPSR_MSEL(IP2_24_23, ET0_ETXD5_B, SEL_ET0_1),
798 798
799 PINMUX_IPSR_DATA(IP2_27_25, D13), 799 PINMUX_IPSR_DATA(IP2_27_25, D13),
800 PINMUX_IPSR_MODSEL_DATA(IP2_27_25, RX2_B, SEL_SCIF2_1), 800 PINMUX_IPSR_MSEL(IP2_27_25, RX2_B, SEL_SCIF2_1),
801 PINMUX_IPSR_MODSEL_DATA(IP2_27_25, FRB_A, SEL_FLCTL_0), 801 PINMUX_IPSR_MSEL(IP2_27_25, FRB_A, SEL_FLCTL_0),
802 PINMUX_IPSR_MODSEL_DATA(IP2_27_25, ET0_ETXD6_B, SEL_ET0_1), 802 PINMUX_IPSR_MSEL(IP2_27_25, ET0_ETXD6_B, SEL_ET0_1),
803 803
804 PINMUX_IPSR_DATA(IP2_30_28, D14), 804 PINMUX_IPSR_DATA(IP2_30_28, D14),
805 PINMUX_IPSR_MODSEL_DATA(IP2_30_28, TX2_B, SEL_SCIF2_1), 805 PINMUX_IPSR_MSEL(IP2_30_28, TX2_B, SEL_SCIF2_1),
806 PINMUX_IPSR_MODSEL_DATA(IP2_30_28, FSE_A, SEL_FLCTL_0), 806 PINMUX_IPSR_MSEL(IP2_30_28, FSE_A, SEL_FLCTL_0),
807 PINMUX_IPSR_MODSEL_DATA(IP2_30_28, ET0_TX_CLK_B, SEL_ET0_1), 807 PINMUX_IPSR_MSEL(IP2_30_28, ET0_TX_CLK_B, SEL_ET0_1),
808 808
809 /* IPSR3 */ 809 /* IPSR3 */
810 PINMUX_IPSR_DATA(IP3_1_0, D15), 810 PINMUX_IPSR_DATA(IP3_1_0, D15),
811 PINMUX_IPSR_MODSEL_DATA(IP3_1_0, SCK2_B, SEL_SCIF2_1), 811 PINMUX_IPSR_MSEL(IP3_1_0, SCK2_B, SEL_SCIF2_1),
812 812
813 PINMUX_IPSR_DATA(IP3_2, CS1_A26), 813 PINMUX_IPSR_DATA(IP3_2, CS1_A26),
814 PINMUX_IPSR_MODSEL_DATA(IP3_2, QIO3_B, SEL_RQSPI_1), 814 PINMUX_IPSR_MSEL(IP3_2, QIO3_B, SEL_RQSPI_1),
815 815
816 PINMUX_IPSR_DATA(IP3_5_3, EX_CS1), 816 PINMUX_IPSR_DATA(IP3_5_3, EX_CS1),
817 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, RX3_B, SEL_SCIF2_1), 817 PINMUX_IPSR_MSEL(IP3_5_3, RX3_B, SEL_SCIF2_1),
818 PINMUX_IPSR_DATA(IP3_5_3, ATACS0), 818 PINMUX_IPSR_DATA(IP3_5_3, ATACS0),
819 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, QIO2_B, SEL_RQSPI_1), 819 PINMUX_IPSR_MSEL(IP3_5_3, QIO2_B, SEL_RQSPI_1),
820 PINMUX_IPSR_DATA(IP3_5_3, ET0_ETXD0), 820 PINMUX_IPSR_DATA(IP3_5_3, ET0_ETXD0),
821 821
822 PINMUX_IPSR_DATA(IP3_8_6, EX_CS2), 822 PINMUX_IPSR_DATA(IP3_8_6, EX_CS2),
823 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, TX3_B, SEL_SCIF3_1), 823 PINMUX_IPSR_MSEL(IP3_8_6, TX3_B, SEL_SCIF3_1),
824 PINMUX_IPSR_DATA(IP3_8_6, ATACS1), 824 PINMUX_IPSR_DATA(IP3_8_6, ATACS1),
825 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, QSPCLK_B, SEL_RQSPI_1), 825 PINMUX_IPSR_MSEL(IP3_8_6, QSPCLK_B, SEL_RQSPI_1),
826 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, ET0_GTX_CLK_A, SEL_ET0_0), 826 PINMUX_IPSR_MSEL(IP3_8_6, ET0_GTX_CLK_A, SEL_ET0_0),
827 827
828 PINMUX_IPSR_DATA(IP3_11_9, EX_CS3), 828 PINMUX_IPSR_DATA(IP3_11_9, EX_CS3),
829 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SD1_CD_A, SEL_SDHI1_0), 829 PINMUX_IPSR_MSEL(IP3_11_9, SD1_CD_A, SEL_SDHI1_0),
830 PINMUX_IPSR_DATA(IP3_11_9, ATARD), 830 PINMUX_IPSR_DATA(IP3_11_9, ATARD),
831 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, QMO_QIO0_B, SEL_RQSPI_1), 831 PINMUX_IPSR_MSEL(IP3_11_9, QMO_QIO0_B, SEL_RQSPI_1),
832 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, ET0_ETXD1_A, SEL_ET0_0), 832 PINMUX_IPSR_MSEL(IP3_11_9, ET0_ETXD1_A, SEL_ET0_0),
833 833
834 PINMUX_IPSR_DATA(IP3_14_12, EX_CS4), 834 PINMUX_IPSR_DATA(IP3_14_12, EX_CS4),
835 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SD1_WP_A, SEL_SDHI1_0), 835 PINMUX_IPSR_MSEL(IP3_14_12, SD1_WP_A, SEL_SDHI1_0),
836 PINMUX_IPSR_DATA(IP3_14_12, ATAWR), 836 PINMUX_IPSR_DATA(IP3_14_12, ATAWR),
837 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, QMI_QIO1_B, SEL_RQSPI_1), 837 PINMUX_IPSR_MSEL(IP3_14_12, QMI_QIO1_B, SEL_RQSPI_1),
838 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, ET0_ETXD2_A, SEL_ET0_0), 838 PINMUX_IPSR_MSEL(IP3_14_12, ET0_ETXD2_A, SEL_ET0_0),
839 839
840 PINMUX_IPSR_DATA(IP3_17_15, EX_CS5), 840 PINMUX_IPSR_DATA(IP3_17_15, EX_CS5),
841 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SD1_CMD_A, SEL_SDHI1_0), 841 PINMUX_IPSR_MSEL(IP3_17_15, SD1_CMD_A, SEL_SDHI1_0),
842 PINMUX_IPSR_DATA(IP3_17_15, ATADIR), 842 PINMUX_IPSR_DATA(IP3_17_15, ATADIR),
843 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, QSSL_B, SEL_RQSPI_1), 843 PINMUX_IPSR_MSEL(IP3_17_15, QSSL_B, SEL_RQSPI_1),
844 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, ET0_ETXD3_A, SEL_ET0_0), 844 PINMUX_IPSR_MSEL(IP3_17_15, ET0_ETXD3_A, SEL_ET0_0),
845 845
846 PINMUX_IPSR_DATA(IP3_19_18, RD_WR), 846 PINMUX_IPSR_DATA(IP3_19_18, RD_WR),
847 PINMUX_IPSR_DATA(IP3_19_18, TCLK0), 847 PINMUX_IPSR_DATA(IP3_19_18, TCLK0),
848 PINMUX_IPSR_MODSEL_DATA(IP3_19_18, CAN_CLK_B, SEL_RCAN_CLK_1), 848 PINMUX_IPSR_MSEL(IP3_19_18, CAN_CLK_B, SEL_RCAN_CLK_1),
849 PINMUX_IPSR_DATA(IP3_19_18, ET0_ETXD4), 849 PINMUX_IPSR_DATA(IP3_19_18, ET0_ETXD4),
850 850
851 PINMUX_IPSR_DATA(IP3_20, EX_WAIT0), 851 PINMUX_IPSR_DATA(IP3_20, EX_WAIT0),
852 PINMUX_IPSR_MODSEL_DATA(IP3_20, TCLK1_B, SEL_TMU_1), 852 PINMUX_IPSR_MSEL(IP3_20, TCLK1_B, SEL_TMU_1),
853 853
854 PINMUX_IPSR_DATA(IP3_23_21, EX_WAIT1), 854 PINMUX_IPSR_DATA(IP3_23_21, EX_WAIT1),
855 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, SD1_DAT0_A, SEL_SDHI1_0), 855 PINMUX_IPSR_MSEL(IP3_23_21, SD1_DAT0_A, SEL_SDHI1_0),
856 PINMUX_IPSR_DATA(IP3_23_21, DREQ2), 856 PINMUX_IPSR_DATA(IP3_23_21, DREQ2),
857 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, CAN1_TX_C, SEL_RCAN1_2), 857 PINMUX_IPSR_MSEL(IP3_23_21, CAN1_TX_C, SEL_RCAN1_2),
858 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, ET0_LINK_C, SEL_ET0_CTL_2), 858 PINMUX_IPSR_MSEL(IP3_23_21, ET0_LINK_C, SEL_ET0_CTL_2),
859 PINMUX_IPSR_MODSEL_DATA(IP3_23_21, ET0_ETXD5_A, SEL_ET0_0), 859 PINMUX_IPSR_MSEL(IP3_23_21, ET0_ETXD5_A, SEL_ET0_0),
860 860
861 PINMUX_IPSR_DATA(IP3_26_24, EX_WAIT2), 861 PINMUX_IPSR_DATA(IP3_26_24, EX_WAIT2),
862 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SD1_DAT1_A, SEL_SDHI1_0), 862 PINMUX_IPSR_MSEL(IP3_26_24, SD1_DAT1_A, SEL_SDHI1_0),
863 PINMUX_IPSR_DATA(IP3_26_24, DACK2), 863 PINMUX_IPSR_DATA(IP3_26_24, DACK2),
864 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, CAN1_RX_C, SEL_RCAN1_2), 864 PINMUX_IPSR_MSEL(IP3_26_24, CAN1_RX_C, SEL_RCAN1_2),
865 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, ET0_MAGIC_C, SEL_ET0_CTL_2), 865 PINMUX_IPSR_MSEL(IP3_26_24, ET0_MAGIC_C, SEL_ET0_CTL_2),
866 PINMUX_IPSR_MODSEL_DATA(IP3_26_24, ET0_ETXD6_A, SEL_ET0_0), 866 PINMUX_IPSR_MSEL(IP3_26_24, ET0_ETXD6_A, SEL_ET0_0),
867 867
868 PINMUX_IPSR_DATA(IP3_29_27, DRACK0), 868 PINMUX_IPSR_DATA(IP3_29_27, DRACK0),
869 PINMUX_IPSR_MODSEL_DATA(IP3_29_27, SD1_DAT2_A, SEL_SDHI1_0), 869 PINMUX_IPSR_MSEL(IP3_29_27, SD1_DAT2_A, SEL_SDHI1_0),
870 PINMUX_IPSR_DATA(IP3_29_27, ATAG), 870 PINMUX_IPSR_DATA(IP3_29_27, ATAG),
871 PINMUX_IPSR_MODSEL_DATA(IP3_29_27, TCLK1_A, SEL_TMU_0), 871 PINMUX_IPSR_MSEL(IP3_29_27, TCLK1_A, SEL_TMU_0),
872 PINMUX_IPSR_DATA(IP3_29_27, ET0_ETXD7), 872 PINMUX_IPSR_DATA(IP3_29_27, ET0_ETXD7),
873 873
874 /* IPSR4 */ 874 /* IPSR4 */
875 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, HCTS0_A, SEL_HSCIF_0), 875 PINMUX_IPSR_MSEL(IP4_2_0, HCTS0_A, SEL_HSCIF_0),
876 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, CTS1_A, SEL_SCIF1_0), 876 PINMUX_IPSR_MSEL(IP4_2_0, CTS1_A, SEL_SCIF1_0),
877 PINMUX_IPSR_DATA(IP4_2_0, VI0_FIELD), 877 PINMUX_IPSR_DATA(IP4_2_0, VI0_FIELD),
878 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, RMII0_RXD1_A, SEL_RMII_0), 878 PINMUX_IPSR_MSEL(IP4_2_0, RMII0_RXD1_A, SEL_RMII_0),
879 PINMUX_IPSR_DATA(IP4_2_0, ET0_ERXD7), 879 PINMUX_IPSR_DATA(IP4_2_0, ET0_ERXD7),
880 880
881 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, HRTS0_A, SEL_HSCIF_0), 881 PINMUX_IPSR_MSEL(IP4_5_3, HRTS0_A, SEL_HSCIF_0),
882 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, RTS1_A, SEL_SCIF1_0), 882 PINMUX_IPSR_MSEL(IP4_5_3, RTS1_A, SEL_SCIF1_0),
883 PINMUX_IPSR_DATA(IP4_5_3, VI0_HSYNC), 883 PINMUX_IPSR_DATA(IP4_5_3, VI0_HSYNC),
884 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, RMII0_TXD_EN_A, SEL_RMII_0), 884 PINMUX_IPSR_MSEL(IP4_5_3, RMII0_TXD_EN_A, SEL_RMII_0),
885 PINMUX_IPSR_DATA(IP4_5_3, ET0_RX_DV), 885 PINMUX_IPSR_DATA(IP4_5_3, ET0_RX_DV),
886 886
887 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, HSCK0_A, SEL_HSCIF_0), 887 PINMUX_IPSR_MSEL(IP4_8_6, HSCK0_A, SEL_HSCIF_0),
888 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, SCK1_A, SEL_SCIF1_0), 888 PINMUX_IPSR_MSEL(IP4_8_6, SCK1_A, SEL_SCIF1_0),
889 PINMUX_IPSR_DATA(IP4_8_6, VI0_VSYNC), 889 PINMUX_IPSR_DATA(IP4_8_6, VI0_VSYNC),
890 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, RMII0_RX_ER_A, SEL_RMII_0), 890 PINMUX_IPSR_MSEL(IP4_8_6, RMII0_RX_ER_A, SEL_RMII_0),
891 PINMUX_IPSR_DATA(IP4_8_6, ET0_RX_ER), 891 PINMUX_IPSR_DATA(IP4_8_6, ET0_RX_ER),
892 892
893 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, HRX0_A, SEL_HSCIF_0), 893 PINMUX_IPSR_MSEL(IP4_11_9, HRX0_A, SEL_HSCIF_0),
894 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, RX1_A, SEL_SCIF1_0), 894 PINMUX_IPSR_MSEL(IP4_11_9, RX1_A, SEL_SCIF1_0),
895 PINMUX_IPSR_DATA(IP4_11_9, VI0_DATA0_VI0_B0), 895 PINMUX_IPSR_DATA(IP4_11_9, VI0_DATA0_VI0_B0),
896 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, RMII0_CRS_DV_A, SEL_RMII_0), 896 PINMUX_IPSR_MSEL(IP4_11_9, RMII0_CRS_DV_A, SEL_RMII_0),
897 PINMUX_IPSR_DATA(IP4_11_9, ET0_CRS), 897 PINMUX_IPSR_DATA(IP4_11_9, ET0_CRS),
898 898
899 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, HTX0_A, SEL_HSCIF_0), 899 PINMUX_IPSR_MSEL(IP4_14_12, HTX0_A, SEL_HSCIF_0),
900 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, TX1_A, SEL_SCIF1_0), 900 PINMUX_IPSR_MSEL(IP4_14_12, TX1_A, SEL_SCIF1_0),
901 PINMUX_IPSR_DATA(IP4_14_12, VI0_DATA1_VI0_B1), 901 PINMUX_IPSR_DATA(IP4_14_12, VI0_DATA1_VI0_B1),
902 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, RMII0_MDC_A, SEL_RMII_0), 902 PINMUX_IPSR_MSEL(IP4_14_12, RMII0_MDC_A, SEL_RMII_0),
903 PINMUX_IPSR_DATA(IP4_14_12, ET0_COL), 903 PINMUX_IPSR_DATA(IP4_14_12, ET0_COL),
904 904
905 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, CTS0_B, SEL_SCIF0_1), 905 PINMUX_IPSR_MSEL(IP4_17_15, CTS0_B, SEL_SCIF0_1),
906 PINMUX_IPSR_DATA(IP4_17_15, VI0_DATA2_VI0_B2), 906 PINMUX_IPSR_DATA(IP4_17_15, VI0_DATA2_VI0_B2),
907 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, RMII0_MDIO_A, SEL_RMII_0), 907 PINMUX_IPSR_MSEL(IP4_17_15, RMII0_MDIO_A, SEL_RMII_0),
908 PINMUX_IPSR_DATA(IP4_17_15, ET0_MDC), 908 PINMUX_IPSR_DATA(IP4_17_15, ET0_MDC),
909 909
910 PINMUX_IPSR_MODSEL_DATA(IP4_19_18, RTS0_B, SEL_SCIF0_1), 910 PINMUX_IPSR_MSEL(IP4_19_18, RTS0_B, SEL_SCIF0_1),
911 PINMUX_IPSR_DATA(IP4_19_18, VI0_DATA3_VI0_B3), 911 PINMUX_IPSR_DATA(IP4_19_18, VI0_DATA3_VI0_B3),
912 PINMUX_IPSR_MODSEL_DATA(IP4_19_18, ET0_MDIO_A, SEL_ET0_0), 912 PINMUX_IPSR_MSEL(IP4_19_18, ET0_MDIO_A, SEL_ET0_0),
913 913
914 PINMUX_IPSR_MODSEL_DATA(IP4_21_20, SCK1_B, SEL_SCIF1_1), 914 PINMUX_IPSR_MSEL(IP4_21_20, SCK1_B, SEL_SCIF1_1),
915 PINMUX_IPSR_DATA(IP4_21_20, VI0_DATA4_VI0_B4), 915 PINMUX_IPSR_DATA(IP4_21_20, VI0_DATA4_VI0_B4),
916 PINMUX_IPSR_MODSEL_DATA(IP4_21_20, ET0_LINK_A, SEL_ET0_CTL_0), 916 PINMUX_IPSR_MSEL(IP4_21_20, ET0_LINK_A, SEL_ET0_CTL_0),
917 917
918 PINMUX_IPSR_MODSEL_DATA(IP4_23_22, RX1_B, SEL_SCIF1_1), 918 PINMUX_IPSR_MSEL(IP4_23_22, RX1_B, SEL_SCIF1_1),
919 PINMUX_IPSR_DATA(IP4_23_22, VI0_DATA5_VI0_B5), 919 PINMUX_IPSR_DATA(IP4_23_22, VI0_DATA5_VI0_B5),
920 PINMUX_IPSR_MODSEL_DATA(IP4_23_22, ET0_MAGIC_A, SEL_ET0_CTL_0), 920 PINMUX_IPSR_MSEL(IP4_23_22, ET0_MAGIC_A, SEL_ET0_CTL_0),
921 921
922 PINMUX_IPSR_MODSEL_DATA(IP4_25_24, TX1_B, SEL_SCIF1_1), 922 PINMUX_IPSR_MSEL(IP4_25_24, TX1_B, SEL_SCIF1_1),
923 PINMUX_IPSR_DATA(IP4_25_24, VI0_DATA6_VI0_G0), 923 PINMUX_IPSR_DATA(IP4_25_24, VI0_DATA6_VI0_G0),
924 PINMUX_IPSR_MODSEL_DATA(IP4_25_24, ET0_PHY_INT_A, SEL_ET0_CTL_0), 924 PINMUX_IPSR_MSEL(IP4_25_24, ET0_PHY_INT_A, SEL_ET0_CTL_0),
925 925
926 PINMUX_IPSR_MODSEL_DATA(IP4_27_26, CTS1_B, SEL_SCIF1_1), 926 PINMUX_IPSR_MSEL(IP4_27_26, CTS1_B, SEL_SCIF1_1),
927 PINMUX_IPSR_DATA(IP4_27_26, VI0_DATA7_VI0_G1), 927 PINMUX_IPSR_DATA(IP4_27_26, VI0_DATA7_VI0_G1),
928 928
929 PINMUX_IPSR_MODSEL_DATA(IP4_29_28, RTS1_B, SEL_SCIF1_1), 929 PINMUX_IPSR_MSEL(IP4_29_28, RTS1_B, SEL_SCIF1_1),
930 PINMUX_IPSR_DATA(IP4_29_28, VI0_G2), 930 PINMUX_IPSR_DATA(IP4_29_28, VI0_G2),
931 931
932 PINMUX_IPSR_MODSEL_DATA(IP4_31_30, SCK2_A, SEL_SCIF2_0), 932 PINMUX_IPSR_MSEL(IP4_31_30, SCK2_A, SEL_SCIF2_0),
933 PINMUX_IPSR_DATA(IP4_31_30, VI0_G3), 933 PINMUX_IPSR_DATA(IP4_31_30, VI0_G3),
934 934
935 /* IPSR5 */ 935 /* IPSR5 */
936 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, SD2_CLK_A, SEL_SDHI2_0), 936 PINMUX_IPSR_MSEL(IP5_2_0, SD2_CLK_A, SEL_SDHI2_0),
937 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RX2_A, SEL_SCIF2_0), 937 PINMUX_IPSR_MSEL(IP5_2_0, RX2_A, SEL_SCIF2_0),
938 PINMUX_IPSR_DATA(IP5_2_0, VI0_G4), 938 PINMUX_IPSR_DATA(IP5_2_0, VI0_G4),
939 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, ET0_RX_CLK_B, SEL_ET0_1), 939 PINMUX_IPSR_MSEL(IP5_2_0, ET0_RX_CLK_B, SEL_ET0_1),
940 940
941 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SD2_CMD_A, SEL_SDHI2_0), 941 PINMUX_IPSR_MSEL(IP5_5_3, SD2_CMD_A, SEL_SDHI2_0),
942 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, TX2_A, SEL_SCIF2_0), 942 PINMUX_IPSR_MSEL(IP5_5_3, TX2_A, SEL_SCIF2_0),
943 PINMUX_IPSR_DATA(IP5_5_3, VI0_G5), 943 PINMUX_IPSR_DATA(IP5_5_3, VI0_G5),
944 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, ET0_ERXD2_B, SEL_ET0_1), 944 PINMUX_IPSR_MSEL(IP5_5_3, ET0_ERXD2_B, SEL_ET0_1),
945 945
946 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, SD2_DAT0_A, SEL_SDHI2_0), 946 PINMUX_IPSR_MSEL(IP5_8_6, SD2_DAT0_A, SEL_SDHI2_0),
947 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, RX3_A, SEL_SCIF3_0), 947 PINMUX_IPSR_MSEL(IP5_8_6, RX3_A, SEL_SCIF3_0),
948 PINMUX_IPSR_DATA(IP4_8_6, VI0_R0), 948 PINMUX_IPSR_DATA(IP4_8_6, VI0_R0),
949 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, ET0_ERXD2_B, SEL_ET0_1), 949 PINMUX_IPSR_MSEL(IP4_8_6, ET0_ERXD2_B, SEL_ET0_1),
950 950
951 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, SD2_DAT1_A, SEL_SDHI2_0), 951 PINMUX_IPSR_MSEL(IP5_11_9, SD2_DAT1_A, SEL_SDHI2_0),
952 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, TX3_A, SEL_SCIF3_0), 952 PINMUX_IPSR_MSEL(IP5_11_9, TX3_A, SEL_SCIF3_0),
953 PINMUX_IPSR_DATA(IP5_11_9, VI0_R1), 953 PINMUX_IPSR_DATA(IP5_11_9, VI0_R1),
954 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, ET0_MDIO_B, SEL_ET0_1), 954 PINMUX_IPSR_MSEL(IP5_11_9, ET0_MDIO_B, SEL_ET0_1),
955 955
956 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, SD2_DAT2_A, SEL_SDHI2_0), 956 PINMUX_IPSR_MSEL(IP5_14_12, SD2_DAT2_A, SEL_SDHI2_0),
957 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, RX4_A, SEL_SCIF4_0), 957 PINMUX_IPSR_MSEL(IP5_14_12, RX4_A, SEL_SCIF4_0),
958 PINMUX_IPSR_DATA(IP5_14_12, VI0_R2), 958 PINMUX_IPSR_DATA(IP5_14_12, VI0_R2),
959 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, ET0_LINK_B, SEL_ET0_CTL_1), 959 PINMUX_IPSR_MSEL(IP5_14_12, ET0_LINK_B, SEL_ET0_CTL_1),
960 960
961 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SD2_DAT3_A, SEL_SDHI2_0), 961 PINMUX_IPSR_MSEL(IP5_17_15, SD2_DAT3_A, SEL_SDHI2_0),
962 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, TX4_A, SEL_SCIF4_0), 962 PINMUX_IPSR_MSEL(IP5_17_15, TX4_A, SEL_SCIF4_0),
963 PINMUX_IPSR_DATA(IP5_17_15, VI0_R3), 963 PINMUX_IPSR_DATA(IP5_17_15, VI0_R3),
964 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, ET0_MAGIC_B, SEL_ET0_CTL_1), 964 PINMUX_IPSR_MSEL(IP5_17_15, ET0_MAGIC_B, SEL_ET0_CTL_1),
965 965
966 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SD2_CD_A, SEL_SDHI2_0), 966 PINMUX_IPSR_MSEL(IP5_20_18, SD2_CD_A, SEL_SDHI2_0),
967 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, RX5_A, SEL_SCIF5_0), 967 PINMUX_IPSR_MSEL(IP5_20_18, RX5_A, SEL_SCIF5_0),
968 PINMUX_IPSR_DATA(IP5_20_18, VI0_R4), 968 PINMUX_IPSR_DATA(IP5_20_18, VI0_R4),
969 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, ET0_PHY_INT_B, SEL_ET0_CTL_1), 969 PINMUX_IPSR_MSEL(IP5_20_18, ET0_PHY_INT_B, SEL_ET0_CTL_1),
970 970
971 PINMUX_IPSR_MODSEL_DATA(IP5_22_21, SD2_WP_A, SEL_SDHI2_0), 971 PINMUX_IPSR_MSEL(IP5_22_21, SD2_WP_A, SEL_SDHI2_0),
972 PINMUX_IPSR_MODSEL_DATA(IP5_22_21, TX5_A, SEL_SCIF5_0), 972 PINMUX_IPSR_MSEL(IP5_22_21, TX5_A, SEL_SCIF5_0),
973 PINMUX_IPSR_DATA(IP5_22_21, VI0_R5), 973 PINMUX_IPSR_DATA(IP5_22_21, VI0_R5),
974 974
975 PINMUX_IPSR_DATA(IP5_24_23, REF125CK), 975 PINMUX_IPSR_DATA(IP5_24_23, REF125CK),
976 PINMUX_IPSR_DATA(IP5_24_23, ADTRG), 976 PINMUX_IPSR_DATA(IP5_24_23, ADTRG),
977 PINMUX_IPSR_MODSEL_DATA(IP5_24_23, RX5_C, SEL_SCIF5_2), 977 PINMUX_IPSR_MSEL(IP5_24_23, RX5_C, SEL_SCIF5_2),
978 PINMUX_IPSR_DATA(IP5_26_25, REF50CK), 978 PINMUX_IPSR_DATA(IP5_26_25, REF50CK),
979 PINMUX_IPSR_MODSEL_DATA(IP5_26_25, CTS1_E, SEL_SCIF1_3), 979 PINMUX_IPSR_MSEL(IP5_26_25, CTS1_E, SEL_SCIF1_3),
980 PINMUX_IPSR_MODSEL_DATA(IP5_26_25, HCTS0_D, SEL_HSCIF_3), 980 PINMUX_IPSR_MSEL(IP5_26_25, HCTS0_D, SEL_HSCIF_3),
981 981
982 /* IPSR6 */ 982 /* IPSR6 */
983 PINMUX_IPSR_DATA(IP6_2_0, DU0_DR0), 983 PINMUX_IPSR_DATA(IP6_2_0, DU0_DR0),
984 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK_B, SEL_SCIF_CLK_1), 984 PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK_B, SEL_SCIF_CLK_1),
985 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, HRX0_D, SEL_HSCIF_3), 985 PINMUX_IPSR_MSEL(IP6_2_0, HRX0_D, SEL_HSCIF_3),
986 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, IETX_A, SEL_IEBUS_0), 986 PINMUX_IPSR_MSEL(IP6_2_0, IETX_A, SEL_IEBUS_0),
987 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, TCLKA_A, SEL_MTU2_CLK_0), 987 PINMUX_IPSR_MSEL(IP6_2_0, TCLKA_A, SEL_MTU2_CLK_0),
988 PINMUX_IPSR_DATA(IP6_2_0, HIFD00), 988 PINMUX_IPSR_DATA(IP6_2_0, HIFD00),
989 989
990 PINMUX_IPSR_DATA(IP6_5_3, DU0_DR1), 990 PINMUX_IPSR_DATA(IP6_5_3, DU0_DR1),
991 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCK0_B, SEL_SCIF0_1), 991 PINMUX_IPSR_MSEL(IP6_5_3, SCK0_B, SEL_SCIF0_1),
992 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, HTX0_D, SEL_HSCIF_3), 992 PINMUX_IPSR_MSEL(IP6_5_3, HTX0_D, SEL_HSCIF_3),
993 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, IERX_A, SEL_IEBUS_0), 993 PINMUX_IPSR_MSEL(IP6_5_3, IERX_A, SEL_IEBUS_0),
994 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TCLKB_A, SEL_MTU2_CLK_0), 994 PINMUX_IPSR_MSEL(IP6_5_3, TCLKB_A, SEL_MTU2_CLK_0),
995 PINMUX_IPSR_DATA(IP6_5_3, HIFD01), 995 PINMUX_IPSR_DATA(IP6_5_3, HIFD01),
996 996
997 PINMUX_IPSR_DATA(IP6_7_6, DU0_DR2), 997 PINMUX_IPSR_DATA(IP6_7_6, DU0_DR2),
998 PINMUX_IPSR_MODSEL_DATA(IP6_7_6, RX0_B, SEL_SCIF0_1), 998 PINMUX_IPSR_MSEL(IP6_7_6, RX0_B, SEL_SCIF0_1),
999 PINMUX_IPSR_MODSEL_DATA(IP6_7_6, TCLKC_A, SEL_MTU2_CLK_0), 999 PINMUX_IPSR_MSEL(IP6_7_6, TCLKC_A, SEL_MTU2_CLK_0),
1000 PINMUX_IPSR_DATA(IP6_7_6, HIFD02), 1000 PINMUX_IPSR_DATA(IP6_7_6, HIFD02),
1001 1001
1002 PINMUX_IPSR_DATA(IP6_9_8, DU0_DR3), 1002 PINMUX_IPSR_DATA(IP6_9_8, DU0_DR3),
1003 PINMUX_IPSR_MODSEL_DATA(IP6_9_8, TX0_B, SEL_SCIF0_1), 1003 PINMUX_IPSR_MSEL(IP6_9_8, TX0_B, SEL_SCIF0_1),
1004 PINMUX_IPSR_MODSEL_DATA(IP6_9_8, TCLKD_A, SEL_MTU2_CLK_0), 1004 PINMUX_IPSR_MSEL(IP6_9_8, TCLKD_A, SEL_MTU2_CLK_0),
1005 PINMUX_IPSR_DATA(IP6_9_8, HIFD03), 1005 PINMUX_IPSR_DATA(IP6_9_8, HIFD03),
1006 1006
1007 PINMUX_IPSR_DATA(IP6_11_10, DU0_DR4), 1007 PINMUX_IPSR_DATA(IP6_11_10, DU0_DR4),
1008 PINMUX_IPSR_MODSEL_DATA(IP6_11_10, CTS0_C, SEL_SCIF0_2), 1008 PINMUX_IPSR_MSEL(IP6_11_10, CTS0_C, SEL_SCIF0_2),
1009 PINMUX_IPSR_MODSEL_DATA(IP6_11_10, TIOC0A_A, SEL_MTU2_CH0_0), 1009 PINMUX_IPSR_MSEL(IP6_11_10, TIOC0A_A, SEL_MTU2_CH0_0),
1010 PINMUX_IPSR_DATA(IP6_11_10, HIFD04), 1010 PINMUX_IPSR_DATA(IP6_11_10, HIFD04),
1011 1011
1012 PINMUX_IPSR_DATA(IP6_13_12, DU0_DR5), 1012 PINMUX_IPSR_DATA(IP6_13_12, DU0_DR5),
1013 PINMUX_IPSR_MODSEL_DATA(IP6_13_12, RTS0_C, SEL_SCIF0_1), 1013 PINMUX_IPSR_MSEL(IP6_13_12, RTS0_C, SEL_SCIF0_1),
1014 PINMUX_IPSR_MODSEL_DATA(IP6_13_12, TIOC0B_A, SEL_MTU2_CH0_0), 1014 PINMUX_IPSR_MSEL(IP6_13_12, TIOC0B_A, SEL_MTU2_CH0_0),
1015 PINMUX_IPSR_DATA(IP6_13_12, HIFD05), 1015 PINMUX_IPSR_DATA(IP6_13_12, HIFD05),
1016 1016
1017 PINMUX_IPSR_DATA(IP6_15_14, DU0_DR6), 1017 PINMUX_IPSR_DATA(IP6_15_14, DU0_DR6),
1018 PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCK1_C, SEL_SCIF1_2), 1018 PINMUX_IPSR_MSEL(IP6_15_14, SCK1_C, SEL_SCIF1_2),
1019 PINMUX_IPSR_MODSEL_DATA(IP6_15_14, TIOC0C_A, SEL_MTU2_CH0_0), 1019 PINMUX_IPSR_MSEL(IP6_15_14, TIOC0C_A, SEL_MTU2_CH0_0),
1020 PINMUX_IPSR_DATA(IP6_15_14, HIFD06), 1020 PINMUX_IPSR_DATA(IP6_15_14, HIFD06),
1021 1021
1022 PINMUX_IPSR_DATA(IP6_17_16, DU0_DR7), 1022 PINMUX_IPSR_DATA(IP6_17_16, DU0_DR7),
1023 PINMUX_IPSR_MODSEL_DATA(IP6_17_16, RX1_C, SEL_SCIF1_2), 1023 PINMUX_IPSR_MSEL(IP6_17_16, RX1_C, SEL_SCIF1_2),
1024 PINMUX_IPSR_MODSEL_DATA(IP6_17_16, TIOC0D_A, SEL_MTU2_CH0_0), 1024 PINMUX_IPSR_MSEL(IP6_17_16, TIOC0D_A, SEL_MTU2_CH0_0),
1025 PINMUX_IPSR_DATA(IP6_17_16, HIFD07), 1025 PINMUX_IPSR_DATA(IP6_17_16, HIFD07),
1026 1026
1027 PINMUX_IPSR_DATA(IP6_20_18, DU0_DG0), 1027 PINMUX_IPSR_DATA(IP6_20_18, DU0_DG0),
1028 PINMUX_IPSR_MODSEL_DATA(IP6_20_18, TX1_C, SEL_SCIF1_2), 1028 PINMUX_IPSR_MSEL(IP6_20_18, TX1_C, SEL_SCIF1_2),
1029 PINMUX_IPSR_MODSEL_DATA(IP6_20_18, HSCK0_D, SEL_HSCIF_3), 1029 PINMUX_IPSR_MSEL(IP6_20_18, HSCK0_D, SEL_HSCIF_3),
1030 PINMUX_IPSR_MODSEL_DATA(IP6_20_18, IECLK_A, SEL_IEBUS_0), 1030 PINMUX_IPSR_MSEL(IP6_20_18, IECLK_A, SEL_IEBUS_0),
1031 PINMUX_IPSR_MODSEL_DATA(IP6_20_18, TIOC1A_A, SEL_MTU2_CH1_0), 1031 PINMUX_IPSR_MSEL(IP6_20_18, TIOC1A_A, SEL_MTU2_CH1_0),
1032 PINMUX_IPSR_DATA(IP6_20_18, HIFD08), 1032 PINMUX_IPSR_DATA(IP6_20_18, HIFD08),
1033 1033
1034 PINMUX_IPSR_DATA(IP6_23_21, DU0_DG1), 1034 PINMUX_IPSR_DATA(IP6_23_21, DU0_DG1),
1035 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, CTS1_C, SEL_SCIF1_2), 1035 PINMUX_IPSR_MSEL(IP6_23_21, CTS1_C, SEL_SCIF1_2),
1036 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HRTS0_D, SEL_HSCIF_3), 1036 PINMUX_IPSR_MSEL(IP6_23_21, HRTS0_D, SEL_HSCIF_3),
1037 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, TIOC1B_A, SEL_MTU2_CH1_0), 1037 PINMUX_IPSR_MSEL(IP6_23_21, TIOC1B_A, SEL_MTU2_CH1_0),
1038 PINMUX_IPSR_DATA(IP6_23_21, HIFD09), 1038 PINMUX_IPSR_DATA(IP6_23_21, HIFD09),
1039 1039
1040 /* IPSR7 */ 1040 /* IPSR7 */
1041 PINMUX_IPSR_DATA(IP7_2_0, DU0_DG2), 1041 PINMUX_IPSR_DATA(IP7_2_0, DU0_DG2),
1042 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, RTS1_C, SEL_SCIF1_2), 1042 PINMUX_IPSR_MSEL(IP7_2_0, RTS1_C, SEL_SCIF1_2),
1043 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, RMII0_MDC_B, SEL_RMII_1), 1043 PINMUX_IPSR_MSEL(IP7_2_0, RMII0_MDC_B, SEL_RMII_1),
1044 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, TIOC2A_A, SEL_MTU2_CH2_0), 1044 PINMUX_IPSR_MSEL(IP7_2_0, TIOC2A_A, SEL_MTU2_CH2_0),
1045 PINMUX_IPSR_DATA(IP7_2_0, HIFD10), 1045 PINMUX_IPSR_DATA(IP7_2_0, HIFD10),
1046 1046
1047 PINMUX_IPSR_DATA(IP7_5_3, DU0_DG3), 1047 PINMUX_IPSR_DATA(IP7_5_3, DU0_DG3),
1048 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, SCK2_C, SEL_SCIF2_2), 1048 PINMUX_IPSR_MSEL(IP7_5_3, SCK2_C, SEL_SCIF2_2),
1049 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RMII0_MDIO_B, SEL_RMII_1), 1049 PINMUX_IPSR_MSEL(IP7_5_3, RMII0_MDIO_B, SEL_RMII_1),
1050 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, TIOC2B_A, SEL_MTU2_CH2_0), 1050 PINMUX_IPSR_MSEL(IP7_5_3, TIOC2B_A, SEL_MTU2_CH2_0),
1051 PINMUX_IPSR_DATA(IP7_5_3, HIFD11), 1051 PINMUX_IPSR_DATA(IP7_5_3, HIFD11),
1052 1052
1053 PINMUX_IPSR_DATA(IP7_8_6, DU0_DG4), 1053 PINMUX_IPSR_DATA(IP7_8_6, DU0_DG4),
1054 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RX2_C, SEL_SCIF2_2), 1054 PINMUX_IPSR_MSEL(IP7_8_6, RX2_C, SEL_SCIF2_2),
1055 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RMII0_CRS_DV_B, SEL_RMII_1), 1055 PINMUX_IPSR_MSEL(IP7_8_6, RMII0_CRS_DV_B, SEL_RMII_1),
1056 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, TIOC3A_A, SEL_MTU2_CH3_0), 1056 PINMUX_IPSR_MSEL(IP7_8_6, TIOC3A_A, SEL_MTU2_CH3_0),
1057 PINMUX_IPSR_DATA(IP7_8_6, HIFD12), 1057 PINMUX_IPSR_DATA(IP7_8_6, HIFD12),
1058 1058
1059 PINMUX_IPSR_DATA(IP7_11_9, DU0_DG5), 1059 PINMUX_IPSR_DATA(IP7_11_9, DU0_DG5),
1060 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, TX2_C, SEL_SCIF2_2), 1060 PINMUX_IPSR_MSEL(IP7_11_9, TX2_C, SEL_SCIF2_2),
1061 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, RMII0_RX_ER_B, SEL_RMII_1), 1061 PINMUX_IPSR_MSEL(IP7_11_9, RMII0_RX_ER_B, SEL_RMII_1),
1062 PINMUX_IPSR_MODSEL_DATA(IP7_11_9, TIOC3B_A, SEL_MTU2_CH3_0), 1062 PINMUX_IPSR_MSEL(IP7_11_9, TIOC3B_A, SEL_MTU2_CH3_0),
1063 PINMUX_IPSR_DATA(IP7_11_9, HIFD13), 1063 PINMUX_IPSR_DATA(IP7_11_9, HIFD13),
1064 1064
1065 PINMUX_IPSR_DATA(IP7_14_12, DU0_DG6), 1065 PINMUX_IPSR_DATA(IP7_14_12, DU0_DG6),
1066 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, RX3_C, SEL_SCIF3_2), 1066 PINMUX_IPSR_MSEL(IP7_14_12, RX3_C, SEL_SCIF3_2),
1067 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, RMII0_RXD0_B, SEL_RMII_1), 1067 PINMUX_IPSR_MSEL(IP7_14_12, RMII0_RXD0_B, SEL_RMII_1),
1068 PINMUX_IPSR_MODSEL_DATA(IP7_14_12, TIOC3C_A, SEL_MTU2_CH3_0), 1068 PINMUX_IPSR_MSEL(IP7_14_12, TIOC3C_A, SEL_MTU2_CH3_0),
1069 PINMUX_IPSR_DATA(IP7_14_12, HIFD14), 1069 PINMUX_IPSR_DATA(IP7_14_12, HIFD14),
1070 1070
1071 PINMUX_IPSR_DATA(IP7_17_15, DU0_DG7), 1071 PINMUX_IPSR_DATA(IP7_17_15, DU0_DG7),
1072 PINMUX_IPSR_MODSEL_DATA(IP7_17_15, TX3_C, SEL_SCIF3_2), 1072 PINMUX_IPSR_MSEL(IP7_17_15, TX3_C, SEL_SCIF3_2),
1073 PINMUX_IPSR_MODSEL_DATA(IP7_17_15, RMII0_RXD1_B, SEL_RMII_1), 1073 PINMUX_IPSR_MSEL(IP7_17_15, RMII0_RXD1_B, SEL_RMII_1),
1074 PINMUX_IPSR_MODSEL_DATA(IP7_17_15, TIOC3D_A, SEL_MTU2_CH3_0), 1074 PINMUX_IPSR_MSEL(IP7_17_15, TIOC3D_A, SEL_MTU2_CH3_0),
1075 PINMUX_IPSR_DATA(IP7_17_15, HIFD15), 1075 PINMUX_IPSR_DATA(IP7_17_15, HIFD15),
1076 1076
1077 PINMUX_IPSR_DATA(IP7_20_18, DU0_DB0), 1077 PINMUX_IPSR_DATA(IP7_20_18, DU0_DB0),
1078 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, RX4_C, SEL_SCIF4_2), 1078 PINMUX_IPSR_MSEL(IP7_20_18, RX4_C, SEL_SCIF4_2),
1079 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, RMII0_TXD_EN_B, SEL_RMII_1), 1079 PINMUX_IPSR_MSEL(IP7_20_18, RMII0_TXD_EN_B, SEL_RMII_1),
1080 PINMUX_IPSR_MODSEL_DATA(IP7_20_18, TIOC4A_A, SEL_MTU2_CH4_0), 1080 PINMUX_IPSR_MSEL(IP7_20_18, TIOC4A_A, SEL_MTU2_CH4_0),
1081 PINMUX_IPSR_DATA(IP7_20_18, HIFCS), 1081 PINMUX_IPSR_DATA(IP7_20_18, HIFCS),
1082 1082
1083 PINMUX_IPSR_DATA(IP7_23_21, DU0_DB1), 1083 PINMUX_IPSR_DATA(IP7_23_21, DU0_DB1),
1084 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TX4_C, SEL_SCIF4_2), 1084 PINMUX_IPSR_MSEL(IP7_23_21, TX4_C, SEL_SCIF4_2),
1085 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, RMII0_TXD0_B, SEL_RMII_1), 1085 PINMUX_IPSR_MSEL(IP7_23_21, RMII0_TXD0_B, SEL_RMII_1),
1086 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TIOC4B_A, SEL_MTU2_CH4_0), 1086 PINMUX_IPSR_MSEL(IP7_23_21, TIOC4B_A, SEL_MTU2_CH4_0),
1087 PINMUX_IPSR_DATA(IP7_23_21, HIFWR), 1087 PINMUX_IPSR_DATA(IP7_23_21, HIFWR),
1088 1088
1089 PINMUX_IPSR_DATA(IP7_26_24, DU0_DB2), 1089 PINMUX_IPSR_DATA(IP7_26_24, DU0_DB2),
1090 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RX5_B, SEL_SCIF5_1), 1090 PINMUX_IPSR_MSEL(IP7_26_24, RX5_B, SEL_SCIF5_1),
1091 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RMII0_TXD1_B, SEL_RMII_1), 1091 PINMUX_IPSR_MSEL(IP7_26_24, RMII0_TXD1_B, SEL_RMII_1),
1092 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, TIOC4C_A, SEL_MTU2_CH4_0), 1092 PINMUX_IPSR_MSEL(IP7_26_24, TIOC4C_A, SEL_MTU2_CH4_0),
1093 1093
1094 PINMUX_IPSR_DATA(IP7_28_27, DU0_DB3), 1094 PINMUX_IPSR_DATA(IP7_28_27, DU0_DB3),
1095 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, TX5_B, SEL_SCIF5_1), 1095 PINMUX_IPSR_MSEL(IP7_28_27, TX5_B, SEL_SCIF5_1),
1096 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, TIOC4D_A, SEL_MTU2_CH4_0), 1096 PINMUX_IPSR_MSEL(IP7_28_27, TIOC4D_A, SEL_MTU2_CH4_0),
1097 PINMUX_IPSR_DATA(IP7_28_27, HIFRD), 1097 PINMUX_IPSR_DATA(IP7_28_27, HIFRD),
1098 1098
1099 PINMUX_IPSR_DATA(IP7_30_29, DU0_DB4), 1099 PINMUX_IPSR_DATA(IP7_30_29, DU0_DB4),
@@ -1107,251 +1107,251 @@ static const u16 pinmux_data[] = {
1107 PINMUX_IPSR_DATA(IP8_3_2, HIFRDY), 1107 PINMUX_IPSR_DATA(IP8_3_2, HIFRDY),
1108 1108
1109 PINMUX_IPSR_DATA(IP8_5_4, DU0_DB7), 1109 PINMUX_IPSR_DATA(IP8_5_4, DU0_DB7),
1110 PINMUX_IPSR_MODSEL_DATA(IP8_5_4, SSI_SCK0_B, SEL_SSI0_1), 1110 PINMUX_IPSR_MSEL(IP8_5_4, SSI_SCK0_B, SEL_SSI0_1),
1111 PINMUX_IPSR_MODSEL_DATA(IP8_5_4, HIFEBL_B, SEL_HIF_1), 1111 PINMUX_IPSR_MSEL(IP8_5_4, HIFEBL_B, SEL_HIF_1),
1112 1112
1113 PINMUX_IPSR_DATA(IP8_7_6, DU0_DOTCLKIN), 1113 PINMUX_IPSR_DATA(IP8_7_6, DU0_DOTCLKIN),
1114 PINMUX_IPSR_MODSEL_DATA(IP8_7_6, HSPI_CS0_C, SEL_HSPI_2), 1114 PINMUX_IPSR_MSEL(IP8_7_6, HSPI_CS0_C, SEL_HSPI_2),
1115 PINMUX_IPSR_MODSEL_DATA(IP8_7_6, SSI_WS0_B, SEL_SSI0_1), 1115 PINMUX_IPSR_MSEL(IP8_7_6, SSI_WS0_B, SEL_SSI0_1),
1116 1116
1117 PINMUX_IPSR_DATA(IP8_9_8, DU0_DOTCLKOUT), 1117 PINMUX_IPSR_DATA(IP8_9_8, DU0_DOTCLKOUT),
1118 PINMUX_IPSR_MODSEL_DATA(IP8_9_8, HSPI_CLK0_C, SEL_HSPI_2), 1118 PINMUX_IPSR_MSEL(IP8_9_8, HSPI_CLK0_C, SEL_HSPI_2),
1119 PINMUX_IPSR_MODSEL_DATA(IP8_9_8, SSI_SDATA0_B, SEL_SSI0_1), 1119 PINMUX_IPSR_MSEL(IP8_9_8, SSI_SDATA0_B, SEL_SSI0_1),
1120 1120
1121 PINMUX_IPSR_DATA(IP8_11_10, DU0_EXHSYNC_DU0_HSYNC), 1121 PINMUX_IPSR_DATA(IP8_11_10, DU0_EXHSYNC_DU0_HSYNC),
1122 PINMUX_IPSR_MODSEL_DATA(IP8_11_10, HSPI_TX0_C, SEL_HSPI_2), 1122 PINMUX_IPSR_MSEL(IP8_11_10, HSPI_TX0_C, SEL_HSPI_2),
1123 PINMUX_IPSR_MODSEL_DATA(IP8_11_10, SSI_SCK1_B, SEL_SSI1_1), 1123 PINMUX_IPSR_MSEL(IP8_11_10, SSI_SCK1_B, SEL_SSI1_1),
1124 1124
1125 PINMUX_IPSR_DATA(IP8_13_12, DU0_EXVSYNC_DU0_VSYNC), 1125 PINMUX_IPSR_DATA(IP8_13_12, DU0_EXVSYNC_DU0_VSYNC),
1126 PINMUX_IPSR_MODSEL_DATA(IP8_13_12, HSPI_RX0_C, SEL_HSPI_2), 1126 PINMUX_IPSR_MSEL(IP8_13_12, HSPI_RX0_C, SEL_HSPI_2),
1127 PINMUX_IPSR_MODSEL_DATA(IP8_13_12, SSI_WS1_B, SEL_SSI1_1), 1127 PINMUX_IPSR_MSEL(IP8_13_12, SSI_WS1_B, SEL_SSI1_1),
1128 1128
1129 PINMUX_IPSR_DATA(IP8_15_14, DU0_EXODDF_DU0_ODDF), 1129 PINMUX_IPSR_DATA(IP8_15_14, DU0_EXODDF_DU0_ODDF),
1130 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, CAN0_RX_B, SEL_RCAN0_1), 1130 PINMUX_IPSR_MSEL(IP8_15_14, CAN0_RX_B, SEL_RCAN0_1),
1131 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, HSCK0_B, SEL_HSCIF_1), 1131 PINMUX_IPSR_MSEL(IP8_15_14, HSCK0_B, SEL_HSCIF_1),
1132 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, SSI_SDATA1_B, SEL_SSI1_1), 1132 PINMUX_IPSR_MSEL(IP8_15_14, SSI_SDATA1_B, SEL_SSI1_1),
1133 1133
1134 PINMUX_IPSR_DATA(IP8_17_16, DU0_DISP), 1134 PINMUX_IPSR_DATA(IP8_17_16, DU0_DISP),
1135 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, CAN0_TX_B, SEL_RCAN0_1), 1135 PINMUX_IPSR_MSEL(IP8_17_16, CAN0_TX_B, SEL_RCAN0_1),
1136 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, HRX0_B, SEL_HSCIF_1), 1136 PINMUX_IPSR_MSEL(IP8_17_16, HRX0_B, SEL_HSCIF_1),
1137 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, AUDIO_CLKA_B, SEL_AUDIO_CLKA_1), 1137 PINMUX_IPSR_MSEL(IP8_17_16, AUDIO_CLKA_B, SEL_AUDIO_CLKA_1),
1138 1138
1139 PINMUX_IPSR_DATA(IP8_19_18, DU0_CDE), 1139 PINMUX_IPSR_DATA(IP8_19_18, DU0_CDE),
1140 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, HTX0_B, SEL_HSCIF_1), 1140 PINMUX_IPSR_MSEL(IP8_19_18, HTX0_B, SEL_HSCIF_1),
1141 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, AUDIO_CLKB_B, SEL_AUDIO_CLKB_1), 1141 PINMUX_IPSR_MSEL(IP8_19_18, AUDIO_CLKB_B, SEL_AUDIO_CLKB_1),
1142 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, LCD_VCPWC_B, SEL_LCDC_1), 1142 PINMUX_IPSR_MSEL(IP8_19_18, LCD_VCPWC_B, SEL_LCDC_1),
1143 1143
1144 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, IRQ0_A, SEL_INTC_0), 1144 PINMUX_IPSR_MSEL(IP8_22_20, IRQ0_A, SEL_INTC_0),
1145 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, HSPI_TX_B, SEL_HSPI_1), 1145 PINMUX_IPSR_MSEL(IP8_22_20, HSPI_TX_B, SEL_HSPI_1),
1146 PINMUX_IPSR_MODSEL_DATA(IP8_22_20, RX3_E, SEL_SCIF3_4), 1146 PINMUX_IPSR_MSEL(IP8_22_20, RX3_E, SEL_SCIF3_4),
1147 PINMUX_IPSR_DATA(IP8_22_20, ET0_ERXD0), 1147 PINMUX_IPSR_DATA(IP8_22_20, ET0_ERXD0),
1148 1148
1149 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, IRQ1_A, SEL_INTC_0), 1149 PINMUX_IPSR_MSEL(IP8_25_23, IRQ1_A, SEL_INTC_0),
1150 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, HSPI_RX_B, SEL_HSPI_1), 1150 PINMUX_IPSR_MSEL(IP8_25_23, HSPI_RX_B, SEL_HSPI_1),
1151 PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TX3_E, SEL_SCIF3_4), 1151 PINMUX_IPSR_MSEL(IP8_25_23, TX3_E, SEL_SCIF3_4),
1152 PINMUX_IPSR_DATA(IP8_25_23, ET0_ERXD1), 1152 PINMUX_IPSR_DATA(IP8_25_23, ET0_ERXD1),
1153 1153
1154 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, IRQ2_A, SEL_INTC_0), 1154 PINMUX_IPSR_MSEL(IP8_27_26, IRQ2_A, SEL_INTC_0),
1155 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, CTS0_A, SEL_SCIF0_0), 1155 PINMUX_IPSR_MSEL(IP8_27_26, CTS0_A, SEL_SCIF0_0),
1156 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, HCTS0_B, SEL_HSCIF_1), 1156 PINMUX_IPSR_MSEL(IP8_27_26, HCTS0_B, SEL_HSCIF_1),
1157 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, ET0_ERXD2_A, SEL_ET0_0), 1157 PINMUX_IPSR_MSEL(IP8_27_26, ET0_ERXD2_A, SEL_ET0_0),
1158 1158
1159 PINMUX_IPSR_MODSEL_DATA(IP8_29_28, IRQ3_A, SEL_INTC_0), 1159 PINMUX_IPSR_MSEL(IP8_29_28, IRQ3_A, SEL_INTC_0),
1160 PINMUX_IPSR_MODSEL_DATA(IP8_29_28, RTS0_A, SEL_SCIF0_0), 1160 PINMUX_IPSR_MSEL(IP8_29_28, RTS0_A, SEL_SCIF0_0),
1161 PINMUX_IPSR_MODSEL_DATA(IP8_29_28, HRTS0_B, SEL_HSCIF_1), 1161 PINMUX_IPSR_MSEL(IP8_29_28, HRTS0_B, SEL_HSCIF_1),
1162 PINMUX_IPSR_MODSEL_DATA(IP8_29_28, ET0_ERXD3_A, SEL_ET0_0), 1162 PINMUX_IPSR_MSEL(IP8_29_28, ET0_ERXD3_A, SEL_ET0_0),
1163 1163
1164 /* IPSR9 */ 1164 /* IPSR9 */
1165 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_CLK_A, SEL_VIN1_0), 1165 PINMUX_IPSR_MSEL(IP9_1_0, VI1_CLK_A, SEL_VIN1_0),
1166 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, FD0_B, SEL_FLCTL_1), 1166 PINMUX_IPSR_MSEL(IP9_1_0, FD0_B, SEL_FLCTL_1),
1167 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, LCD_DATA0_B, SEL_LCDC_1), 1167 PINMUX_IPSR_MSEL(IP9_1_0, LCD_DATA0_B, SEL_LCDC_1),
1168 1168
1169 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_0_A, SEL_VIN1_0), 1169 PINMUX_IPSR_MSEL(IP9_3_2, VI1_0_A, SEL_VIN1_0),
1170 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, FD1_B, SEL_FLCTL_1), 1170 PINMUX_IPSR_MSEL(IP9_3_2, FD1_B, SEL_FLCTL_1),
1171 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, LCD_DATA1_B, SEL_LCDC_1), 1171 PINMUX_IPSR_MSEL(IP9_3_2, LCD_DATA1_B, SEL_LCDC_1),
1172 1172
1173 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_1_A, SEL_VIN1_0), 1173 PINMUX_IPSR_MSEL(IP9_5_4, VI1_1_A, SEL_VIN1_0),
1174 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, FD2_B, SEL_FLCTL_1), 1174 PINMUX_IPSR_MSEL(IP9_5_4, FD2_B, SEL_FLCTL_1),
1175 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, LCD_DATA2_B, SEL_LCDC_1), 1175 PINMUX_IPSR_MSEL(IP9_5_4, LCD_DATA2_B, SEL_LCDC_1),
1176 1176
1177 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_2_A, SEL_VIN1_0), 1177 PINMUX_IPSR_MSEL(IP9_7_6, VI1_2_A, SEL_VIN1_0),
1178 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, FD3_B, SEL_FLCTL_1), 1178 PINMUX_IPSR_MSEL(IP9_7_6, FD3_B, SEL_FLCTL_1),
1179 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, LCD_DATA3_B, SEL_LCDC_1), 1179 PINMUX_IPSR_MSEL(IP9_7_6, LCD_DATA3_B, SEL_LCDC_1),
1180 1180
1181 PINMUX_IPSR_MODSEL_DATA(IP9_9_8, VI1_3_A, SEL_VIN1_0), 1181 PINMUX_IPSR_MSEL(IP9_9_8, VI1_3_A, SEL_VIN1_0),
1182 PINMUX_IPSR_MODSEL_DATA(IP9_9_8, FD4_B, SEL_FLCTL_1), 1182 PINMUX_IPSR_MSEL(IP9_9_8, FD4_B, SEL_FLCTL_1),
1183 PINMUX_IPSR_MODSEL_DATA(IP9_9_8, LCD_DATA4_B, SEL_LCDC_1), 1183 PINMUX_IPSR_MSEL(IP9_9_8, LCD_DATA4_B, SEL_LCDC_1),
1184 1184
1185 PINMUX_IPSR_MODSEL_DATA(IP9_11_10, VI1_4_A, SEL_VIN1_0), 1185 PINMUX_IPSR_MSEL(IP9_11_10, VI1_4_A, SEL_VIN1_0),
1186 PINMUX_IPSR_MODSEL_DATA(IP9_11_10, FD5_B, SEL_FLCTL_1), 1186 PINMUX_IPSR_MSEL(IP9_11_10, FD5_B, SEL_FLCTL_1),
1187 PINMUX_IPSR_MODSEL_DATA(IP9_11_10, LCD_DATA5_B, SEL_LCDC_1), 1187 PINMUX_IPSR_MSEL(IP9_11_10, LCD_DATA5_B, SEL_LCDC_1),
1188 1188
1189 PINMUX_IPSR_MODSEL_DATA(IP9_13_12, VI1_5_A, SEL_VIN1_0), 1189 PINMUX_IPSR_MSEL(IP9_13_12, VI1_5_A, SEL_VIN1_0),
1190 PINMUX_IPSR_MODSEL_DATA(IP9_13_12, FD6_B, SEL_FLCTL_1), 1190 PINMUX_IPSR_MSEL(IP9_13_12, FD6_B, SEL_FLCTL_1),
1191 PINMUX_IPSR_MODSEL_DATA(IP9_13_12, LCD_DATA6_B, SEL_LCDC_1), 1191 PINMUX_IPSR_MSEL(IP9_13_12, LCD_DATA6_B, SEL_LCDC_1),
1192 1192
1193 PINMUX_IPSR_MODSEL_DATA(IP9_15_14, VI1_6_A, SEL_VIN1_0), 1193 PINMUX_IPSR_MSEL(IP9_15_14, VI1_6_A, SEL_VIN1_0),
1194 PINMUX_IPSR_MODSEL_DATA(IP9_15_14, FD7_B, SEL_FLCTL_1), 1194 PINMUX_IPSR_MSEL(IP9_15_14, FD7_B, SEL_FLCTL_1),
1195 PINMUX_IPSR_MODSEL_DATA(IP9_15_14, LCD_DATA7_B, SEL_LCDC_1), 1195 PINMUX_IPSR_MSEL(IP9_15_14, LCD_DATA7_B, SEL_LCDC_1),
1196 1196
1197 PINMUX_IPSR_MODSEL_DATA(IP9_17_16, VI1_7_A, SEL_VIN1_0), 1197 PINMUX_IPSR_MSEL(IP9_17_16, VI1_7_A, SEL_VIN1_0),
1198 PINMUX_IPSR_MODSEL_DATA(IP9_17_16, FCE_B, SEL_FLCTL_1), 1198 PINMUX_IPSR_MSEL(IP9_17_16, FCE_B, SEL_FLCTL_1),
1199 PINMUX_IPSR_MODSEL_DATA(IP9_17_16, LCD_DATA8_B, SEL_LCDC_1), 1199 PINMUX_IPSR_MSEL(IP9_17_16, LCD_DATA8_B, SEL_LCDC_1),
1200 1200
1201 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SSI_SCK0_A, SEL_SSI0_0), 1201 PINMUX_IPSR_MSEL(IP9_19_18, SSI_SCK0_A, SEL_SSI0_0),
1202 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, TIOC1A_B, SEL_MTU2_CH1_1), 1202 PINMUX_IPSR_MSEL(IP9_19_18, TIOC1A_B, SEL_MTU2_CH1_1),
1203 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, LCD_DATA9_B, SEL_LCDC_1), 1203 PINMUX_IPSR_MSEL(IP9_19_18, LCD_DATA9_B, SEL_LCDC_1),
1204 1204
1205 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SSI_WS0_A, SEL_SSI0_0), 1205 PINMUX_IPSR_MSEL(IP9_21_20, SSI_WS0_A, SEL_SSI0_0),
1206 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, TIOC1B_B, SEL_MTU2_CH1_1), 1206 PINMUX_IPSR_MSEL(IP9_21_20, TIOC1B_B, SEL_MTU2_CH1_1),
1207 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, LCD_DATA10_B, SEL_LCDC_1), 1207 PINMUX_IPSR_MSEL(IP9_21_20, LCD_DATA10_B, SEL_LCDC_1),
1208 1208
1209 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SSI_SDATA0_A, SEL_SSI0_0), 1209 PINMUX_IPSR_MSEL(IP9_23_22, SSI_SDATA0_A, SEL_SSI0_0),
1210 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, VI1_0_B, SEL_VIN1_1), 1210 PINMUX_IPSR_MSEL(IP9_23_22, VI1_0_B, SEL_VIN1_1),
1211 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, TIOC2A_B, SEL_MTU2_CH2_1), 1211 PINMUX_IPSR_MSEL(IP9_23_22, TIOC2A_B, SEL_MTU2_CH2_1),
1212 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, LCD_DATA11_B, SEL_LCDC_1), 1212 PINMUX_IPSR_MSEL(IP9_23_22, LCD_DATA11_B, SEL_LCDC_1),
1213 1213
1214 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SSI_SCK1_A, SEL_SSI1_0), 1214 PINMUX_IPSR_MSEL(IP9_25_24, SSI_SCK1_A, SEL_SSI1_0),
1215 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, VI1_1_B, SEL_VIN1_1), 1215 PINMUX_IPSR_MSEL(IP9_25_24, VI1_1_B, SEL_VIN1_1),
1216 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, TIOC2B_B, SEL_MTU2_CH2_1), 1216 PINMUX_IPSR_MSEL(IP9_25_24, TIOC2B_B, SEL_MTU2_CH2_1),
1217 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, LCD_DATA12_B, SEL_LCDC_1), 1217 PINMUX_IPSR_MSEL(IP9_25_24, LCD_DATA12_B, SEL_LCDC_1),
1218 1218
1219 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SSI_WS1_A, SEL_SSI1_0), 1219 PINMUX_IPSR_MSEL(IP9_27_26, SSI_WS1_A, SEL_SSI1_0),
1220 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, VI1_2_B, SEL_VIN1_1), 1220 PINMUX_IPSR_MSEL(IP9_27_26, VI1_2_B, SEL_VIN1_1),
1221 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, LCD_DATA13_B, SEL_LCDC_1), 1221 PINMUX_IPSR_MSEL(IP9_27_26, LCD_DATA13_B, SEL_LCDC_1),
1222 1222
1223 PINMUX_IPSR_MODSEL_DATA(IP9_29_28, SSI_SDATA1_A, SEL_SSI1_0), 1223 PINMUX_IPSR_MSEL(IP9_29_28, SSI_SDATA1_A, SEL_SSI1_0),
1224 PINMUX_IPSR_MODSEL_DATA(IP9_29_28, VI1_3_B, SEL_VIN1_1), 1224 PINMUX_IPSR_MSEL(IP9_29_28, VI1_3_B, SEL_VIN1_1),
1225 PINMUX_IPSR_MODSEL_DATA(IP9_29_28, LCD_DATA14_B, SEL_LCDC_1), 1225 PINMUX_IPSR_MSEL(IP9_29_28, LCD_DATA14_B, SEL_LCDC_1),
1226 1226
1227 /* IPSE10 */ 1227 /* IPSE10 */
1228 PINMUX_IPSR_DATA(IP10_2_0, SSI_SCK23), 1228 PINMUX_IPSR_DATA(IP10_2_0, SSI_SCK23),
1229 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, VI1_4_B, SEL_VIN1_1), 1229 PINMUX_IPSR_MSEL(IP10_2_0, VI1_4_B, SEL_VIN1_1),
1230 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, RX1_D, SEL_SCIF1_3), 1230 PINMUX_IPSR_MSEL(IP10_2_0, RX1_D, SEL_SCIF1_3),
1231 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, FCLE_B, SEL_FLCTL_1), 1231 PINMUX_IPSR_MSEL(IP10_2_0, FCLE_B, SEL_FLCTL_1),
1232 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, LCD_DATA15_B, SEL_LCDC_1), 1232 PINMUX_IPSR_MSEL(IP10_2_0, LCD_DATA15_B, SEL_LCDC_1),
1233 1233
1234 PINMUX_IPSR_DATA(IP10_5_3, SSI_WS23), 1234 PINMUX_IPSR_DATA(IP10_5_3, SSI_WS23),
1235 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, VI1_5_B, SEL_VIN1_1), 1235 PINMUX_IPSR_MSEL(IP10_5_3, VI1_5_B, SEL_VIN1_1),
1236 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, TX1_D, SEL_SCIF1_3), 1236 PINMUX_IPSR_MSEL(IP10_5_3, TX1_D, SEL_SCIF1_3),
1237 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, HSCK0_C, SEL_HSCIF_2), 1237 PINMUX_IPSR_MSEL(IP10_5_3, HSCK0_C, SEL_HSCIF_2),
1238 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, FALE_B, SEL_FLCTL_1), 1238 PINMUX_IPSR_MSEL(IP10_5_3, FALE_B, SEL_FLCTL_1),
1239 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, LCD_DON_B, SEL_LCDC_1), 1239 PINMUX_IPSR_MSEL(IP10_5_3, LCD_DON_B, SEL_LCDC_1),
1240 1240
1241 PINMUX_IPSR_DATA(IP10_8_6, SSI_SDATA2), 1241 PINMUX_IPSR_DATA(IP10_8_6, SSI_SDATA2),
1242 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, VI1_6_B, SEL_VIN1_1), 1242 PINMUX_IPSR_MSEL(IP10_8_6, VI1_6_B, SEL_VIN1_1),
1243 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, HRX0_C, SEL_HSCIF_2), 1243 PINMUX_IPSR_MSEL(IP10_8_6, HRX0_C, SEL_HSCIF_2),
1244 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, FRE_B, SEL_FLCTL_1), 1244 PINMUX_IPSR_MSEL(IP10_8_6, FRE_B, SEL_FLCTL_1),
1245 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, LCD_CL1_B, SEL_LCDC_1), 1245 PINMUX_IPSR_MSEL(IP10_8_6, LCD_CL1_B, SEL_LCDC_1),
1246 1246
1247 PINMUX_IPSR_DATA(IP10_11_9, SSI_SDATA3), 1247 PINMUX_IPSR_DATA(IP10_11_9, SSI_SDATA3),
1248 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, VI1_7_B, SEL_VIN1_1), 1248 PINMUX_IPSR_MSEL(IP10_11_9, VI1_7_B, SEL_VIN1_1),
1249 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, HTX0_C, SEL_HSCIF_2), 1249 PINMUX_IPSR_MSEL(IP10_11_9, HTX0_C, SEL_HSCIF_2),
1250 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, FWE_B, SEL_FLCTL_1), 1250 PINMUX_IPSR_MSEL(IP10_11_9, FWE_B, SEL_FLCTL_1),
1251 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, LCD_CL2_B, SEL_LCDC_1), 1251 PINMUX_IPSR_MSEL(IP10_11_9, LCD_CL2_B, SEL_LCDC_1),
1252 1252
1253 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, AUDIO_CLKA_A, SEL_AUDIO_CLKA_0), 1253 PINMUX_IPSR_MSEL(IP10_14_12, AUDIO_CLKA_A, SEL_AUDIO_CLKA_0),
1254 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, VI1_CLK_B, SEL_VIN1_1), 1254 PINMUX_IPSR_MSEL(IP10_14_12, VI1_CLK_B, SEL_VIN1_1),
1255 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCK1_D, SEL_SCIF1_3), 1255 PINMUX_IPSR_MSEL(IP10_14_12, SCK1_D, SEL_SCIF1_3),
1256 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, IECLK_B, SEL_IEBUS_1), 1256 PINMUX_IPSR_MSEL(IP10_14_12, IECLK_B, SEL_IEBUS_1),
1257 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, LCD_FLM_B, SEL_LCDC_1), 1257 PINMUX_IPSR_MSEL(IP10_14_12, LCD_FLM_B, SEL_LCDC_1),
1258 1258
1259 PINMUX_IPSR_MODSEL_DATA(IP10_15, AUDIO_CLKB_A, SEL_AUDIO_CLKB_0), 1259 PINMUX_IPSR_MSEL(IP10_15, AUDIO_CLKB_A, SEL_AUDIO_CLKB_0),
1260 PINMUX_IPSR_MODSEL_DATA(IP10_15, LCD_CLK_B, SEL_LCDC_1), 1260 PINMUX_IPSR_MSEL(IP10_15, LCD_CLK_B, SEL_LCDC_1),
1261 1261
1262 PINMUX_IPSR_DATA(IP10_18_16, AUDIO_CLKC), 1262 PINMUX_IPSR_DATA(IP10_18_16, AUDIO_CLKC),
1263 PINMUX_IPSR_MODSEL_DATA(IP10_18_16, SCK1_E, SEL_SCIF1_4), 1263 PINMUX_IPSR_MSEL(IP10_18_16, SCK1_E, SEL_SCIF1_4),
1264 PINMUX_IPSR_MODSEL_DATA(IP10_18_16, HCTS0_C, SEL_HSCIF_2), 1264 PINMUX_IPSR_MSEL(IP10_18_16, HCTS0_C, SEL_HSCIF_2),
1265 PINMUX_IPSR_MODSEL_DATA(IP10_18_16, FRB_B, SEL_FLCTL_1), 1265 PINMUX_IPSR_MSEL(IP10_18_16, FRB_B, SEL_FLCTL_1),
1266 PINMUX_IPSR_MODSEL_DATA(IP10_18_16, LCD_VEPWC_B, SEL_LCDC_1), 1266 PINMUX_IPSR_MSEL(IP10_18_16, LCD_VEPWC_B, SEL_LCDC_1),
1267 1267
1268 PINMUX_IPSR_DATA(IP10_21_19, AUDIO_CLKOUT), 1268 PINMUX_IPSR_DATA(IP10_21_19, AUDIO_CLKOUT),
1269 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, TX1_E, SEL_SCIF1_4), 1269 PINMUX_IPSR_MSEL(IP10_21_19, TX1_E, SEL_SCIF1_4),
1270 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, HRTS0_C, SEL_HSCIF_2), 1270 PINMUX_IPSR_MSEL(IP10_21_19, HRTS0_C, SEL_HSCIF_2),
1271 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, FSE_B, SEL_FLCTL_1), 1271 PINMUX_IPSR_MSEL(IP10_21_19, FSE_B, SEL_FLCTL_1),
1272 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, LCD_M_DISP_B, SEL_LCDC_1), 1272 PINMUX_IPSR_MSEL(IP10_21_19, LCD_M_DISP_B, SEL_LCDC_1),
1273 1273
1274 PINMUX_IPSR_MODSEL_DATA(IP10_22, CAN_CLK_A, SEL_RCAN_CLK_0), 1274 PINMUX_IPSR_MSEL(IP10_22, CAN_CLK_A, SEL_RCAN_CLK_0),
1275 PINMUX_IPSR_MODSEL_DATA(IP10_22, RX4_D, SEL_SCIF4_3), 1275 PINMUX_IPSR_MSEL(IP10_22, RX4_D, SEL_SCIF4_3),
1276 1276
1277 PINMUX_IPSR_MODSEL_DATA(IP10_24_23, CAN0_TX_A, SEL_RCAN0_0), 1277 PINMUX_IPSR_MSEL(IP10_24_23, CAN0_TX_A, SEL_RCAN0_0),
1278 PINMUX_IPSR_MODSEL_DATA(IP10_24_23, TX4_D, SEL_SCIF4_3), 1278 PINMUX_IPSR_MSEL(IP10_24_23, TX4_D, SEL_SCIF4_3),
1279 PINMUX_IPSR_DATA(IP10_24_23, MLB_CLK), 1279 PINMUX_IPSR_DATA(IP10_24_23, MLB_CLK),
1280 1280
1281 PINMUX_IPSR_MODSEL_DATA(IP10_25, CAN1_RX_A, SEL_RCAN1_0), 1281 PINMUX_IPSR_MSEL(IP10_25, CAN1_RX_A, SEL_RCAN1_0),
1282 PINMUX_IPSR_MODSEL_DATA(IP10_25, IRQ1_B, SEL_INTC_1), 1282 PINMUX_IPSR_MSEL(IP10_25, IRQ1_B, SEL_INTC_1),
1283 1283
1284 PINMUX_IPSR_MODSEL_DATA(IP10_27_26, CAN0_RX_A, SEL_RCAN0_0), 1284 PINMUX_IPSR_MSEL(IP10_27_26, CAN0_RX_A, SEL_RCAN0_0),
1285 PINMUX_IPSR_MODSEL_DATA(IP10_27_26, IRQ0_B, SEL_INTC_1), 1285 PINMUX_IPSR_MSEL(IP10_27_26, IRQ0_B, SEL_INTC_1),
1286 PINMUX_IPSR_DATA(IP10_27_26, MLB_SIG), 1286 PINMUX_IPSR_DATA(IP10_27_26, MLB_SIG),
1287 1287
1288 PINMUX_IPSR_MODSEL_DATA(IP10_29_28, CAN1_TX_A, SEL_RCAN1_0), 1288 PINMUX_IPSR_MSEL(IP10_29_28, CAN1_TX_A, SEL_RCAN1_0),
1289 PINMUX_IPSR_MODSEL_DATA(IP10_29_28, TX5_C, SEL_SCIF1_2), 1289 PINMUX_IPSR_MSEL(IP10_29_28, TX5_C, SEL_SCIF1_2),
1290 PINMUX_IPSR_DATA(IP10_29_28, MLB_DAT), 1290 PINMUX_IPSR_DATA(IP10_29_28, MLB_DAT),
1291 1291
1292 /* IPSR11 */ 1292 /* IPSR11 */
1293 PINMUX_IPSR_DATA(IP11_0, SCL1), 1293 PINMUX_IPSR_DATA(IP11_0, SCL1),
1294 PINMUX_IPSR_MODSEL_DATA(IP11_0, SCIF_CLK_C, SEL_SCIF_CLK_2), 1294 PINMUX_IPSR_MSEL(IP11_0, SCIF_CLK_C, SEL_SCIF_CLK_2),
1295 1295
1296 PINMUX_IPSR_DATA(IP11_1, SDA1), 1296 PINMUX_IPSR_DATA(IP11_1, SDA1),
1297 PINMUX_IPSR_MODSEL_DATA(IP11_0, RX1_E, SEL_SCIF1_4), 1297 PINMUX_IPSR_MSEL(IP11_0, RX1_E, SEL_SCIF1_4),
1298 1298
1299 PINMUX_IPSR_DATA(IP11_2, SDA0), 1299 PINMUX_IPSR_DATA(IP11_2, SDA0),
1300 PINMUX_IPSR_MODSEL_DATA(IP11_2, HIFEBL_A, SEL_HIF_0), 1300 PINMUX_IPSR_MSEL(IP11_2, HIFEBL_A, SEL_HIF_0),
1301 1301
1302 PINMUX_IPSR_DATA(IP11_3, SDSELF), 1302 PINMUX_IPSR_DATA(IP11_3, SDSELF),
1303 PINMUX_IPSR_MODSEL_DATA(IP11_3, RTS1_E, SEL_SCIF1_3), 1303 PINMUX_IPSR_MSEL(IP11_3, RTS1_E, SEL_SCIF1_3),
1304 1304
1305 PINMUX_IPSR_MODSEL_DATA(IP11_6_4, SCIF_CLK_A, SEL_SCIF_CLK_0), 1305 PINMUX_IPSR_MSEL(IP11_6_4, SCIF_CLK_A, SEL_SCIF_CLK_0),
1306 PINMUX_IPSR_MODSEL_DATA(IP11_6_4, HSPI_CLK_A, SEL_HSPI_0), 1306 PINMUX_IPSR_MSEL(IP11_6_4, HSPI_CLK_A, SEL_HSPI_0),
1307 PINMUX_IPSR_DATA(IP11_6_4, VI0_CLK), 1307 PINMUX_IPSR_DATA(IP11_6_4, VI0_CLK),
1308 PINMUX_IPSR_MODSEL_DATA(IP11_6_4, RMII0_TXD0_A, SEL_RMII_0), 1308 PINMUX_IPSR_MSEL(IP11_6_4, RMII0_TXD0_A, SEL_RMII_0),
1309 PINMUX_IPSR_DATA(IP11_6_4, ET0_ERXD4), 1309 PINMUX_IPSR_DATA(IP11_6_4, ET0_ERXD4),
1310 1310
1311 PINMUX_IPSR_MODSEL_DATA(IP11_9_7, SCK0_A, SEL_SCIF0_0), 1311 PINMUX_IPSR_MSEL(IP11_9_7, SCK0_A, SEL_SCIF0_0),
1312 PINMUX_IPSR_MODSEL_DATA(IP11_9_7, HSPI_CS_A, SEL_HSPI_0), 1312 PINMUX_IPSR_MSEL(IP11_9_7, HSPI_CS_A, SEL_HSPI_0),
1313 PINMUX_IPSR_DATA(IP11_9_7, VI0_CLKENB), 1313 PINMUX_IPSR_DATA(IP11_9_7, VI0_CLKENB),
1314 PINMUX_IPSR_MODSEL_DATA(IP11_9_7, RMII0_TXD1_A, SEL_RMII_0), 1314 PINMUX_IPSR_MSEL(IP11_9_7, RMII0_TXD1_A, SEL_RMII_0),
1315 PINMUX_IPSR_DATA(IP11_9_7, ET0_ERXD5), 1315 PINMUX_IPSR_DATA(IP11_9_7, ET0_ERXD5),
1316 1316
1317 PINMUX_IPSR_MODSEL_DATA(IP11_11_10, RX0_A, SEL_SCIF0_0), 1317 PINMUX_IPSR_MSEL(IP11_11_10, RX0_A, SEL_SCIF0_0),
1318 PINMUX_IPSR_MODSEL_DATA(IP11_11_10, HSPI_RX_A, SEL_HSPI_0), 1318 PINMUX_IPSR_MSEL(IP11_11_10, HSPI_RX_A, SEL_HSPI_0),
1319 PINMUX_IPSR_MODSEL_DATA(IP11_11_10, RMII0_RXD0_A, SEL_RMII_0), 1319 PINMUX_IPSR_MSEL(IP11_11_10, RMII0_RXD0_A, SEL_RMII_0),
1320 PINMUX_IPSR_DATA(IP11_11_10, ET0_ERXD6), 1320 PINMUX_IPSR_DATA(IP11_11_10, ET0_ERXD6),
1321 1321
1322 PINMUX_IPSR_MODSEL_DATA(IP11_12, TX0_A, SEL_SCIF0_0), 1322 PINMUX_IPSR_MSEL(IP11_12, TX0_A, SEL_SCIF0_0),
1323 PINMUX_IPSR_MODSEL_DATA(IP11_12, HSPI_TX_A, SEL_HSPI_0), 1323 PINMUX_IPSR_MSEL(IP11_12, HSPI_TX_A, SEL_HSPI_0),
1324 1324
1325 PINMUX_IPSR_DATA(IP11_15_13, PENC1), 1325 PINMUX_IPSR_DATA(IP11_15_13, PENC1),
1326 PINMUX_IPSR_MODSEL_DATA(IP11_15_13, TX3_D, SEL_SCIF3_3), 1326 PINMUX_IPSR_MSEL(IP11_15_13, TX3_D, SEL_SCIF3_3),
1327 PINMUX_IPSR_MODSEL_DATA(IP11_15_13, CAN1_TX_B, SEL_RCAN1_1), 1327 PINMUX_IPSR_MSEL(IP11_15_13, CAN1_TX_B, SEL_RCAN1_1),
1328 PINMUX_IPSR_MODSEL_DATA(IP11_15_13, TX5_D, SEL_SCIF5_3), 1328 PINMUX_IPSR_MSEL(IP11_15_13, TX5_D, SEL_SCIF5_3),
1329 PINMUX_IPSR_MODSEL_DATA(IP11_15_13, IETX_B, SEL_IEBUS_1), 1329 PINMUX_IPSR_MSEL(IP11_15_13, IETX_B, SEL_IEBUS_1),
1330 1330
1331 PINMUX_IPSR_DATA(IP11_18_16, USB_OVC1), 1331 PINMUX_IPSR_DATA(IP11_18_16, USB_OVC1),
1332 PINMUX_IPSR_MODSEL_DATA(IP11_18_16, RX3_D, SEL_SCIF3_3), 1332 PINMUX_IPSR_MSEL(IP11_18_16, RX3_D, SEL_SCIF3_3),
1333 PINMUX_IPSR_MODSEL_DATA(IP11_18_16, CAN1_RX_B, SEL_RCAN1_1), 1333 PINMUX_IPSR_MSEL(IP11_18_16, CAN1_RX_B, SEL_RCAN1_1),
1334 PINMUX_IPSR_MODSEL_DATA(IP11_18_16, RX5_D, SEL_SCIF5_3), 1334 PINMUX_IPSR_MSEL(IP11_18_16, RX5_D, SEL_SCIF5_3),
1335 PINMUX_IPSR_MODSEL_DATA(IP11_18_16, IERX_B, SEL_IEBUS_1), 1335 PINMUX_IPSR_MSEL(IP11_18_16, IERX_B, SEL_IEBUS_1),
1336 1336
1337 PINMUX_IPSR_DATA(IP11_20_19, DREQ0), 1337 PINMUX_IPSR_DATA(IP11_20_19, DREQ0),
1338 PINMUX_IPSR_MODSEL_DATA(IP11_20_19, SD1_CLK_A, SEL_SDHI1_0), 1338 PINMUX_IPSR_MSEL(IP11_20_19, SD1_CLK_A, SEL_SDHI1_0),
1339 PINMUX_IPSR_DATA(IP11_20_19, ET0_TX_EN), 1339 PINMUX_IPSR_DATA(IP11_20_19, ET0_TX_EN),
1340 1340
1341 PINMUX_IPSR_DATA(IP11_22_21, DACK0), 1341 PINMUX_IPSR_DATA(IP11_22_21, DACK0),
1342 PINMUX_IPSR_MODSEL_DATA(IP11_22_21, SD1_DAT3_A, SEL_SDHI1_0), 1342 PINMUX_IPSR_MSEL(IP11_22_21, SD1_DAT3_A, SEL_SDHI1_0),
1343 PINMUX_IPSR_DATA(IP11_22_21, ET0_TX_ER), 1343 PINMUX_IPSR_DATA(IP11_22_21, ET0_TX_ER),
1344 1344
1345 PINMUX_IPSR_DATA(IP11_25_23, DREQ1), 1345 PINMUX_IPSR_DATA(IP11_25_23, DREQ1),
1346 PINMUX_IPSR_MODSEL_DATA(IP11_25_23, HSPI_CLK_B, SEL_HSPI_1), 1346 PINMUX_IPSR_MSEL(IP11_25_23, HSPI_CLK_B, SEL_HSPI_1),
1347 PINMUX_IPSR_MODSEL_DATA(IP11_25_23, RX4_B, SEL_SCIF4_1), 1347 PINMUX_IPSR_MSEL(IP11_25_23, RX4_B, SEL_SCIF4_1),
1348 PINMUX_IPSR_MODSEL_DATA(IP11_25_23, ET0_PHY_INT_C, SEL_ET0_CTL_0), 1348 PINMUX_IPSR_MSEL(IP11_25_23, ET0_PHY_INT_C, SEL_ET0_CTL_0),
1349 PINMUX_IPSR_MODSEL_DATA(IP11_25_23, ET0_TX_CLK_A, SEL_ET0_0), 1349 PINMUX_IPSR_MSEL(IP11_25_23, ET0_TX_CLK_A, SEL_ET0_0),
1350 1350
1351 PINMUX_IPSR_DATA(IP11_27_26, DACK1), 1351 PINMUX_IPSR_DATA(IP11_27_26, DACK1),
1352 PINMUX_IPSR_MODSEL_DATA(IP11_27_26, HSPI_CS_B, SEL_HSPI_1), 1352 PINMUX_IPSR_MSEL(IP11_27_26, HSPI_CS_B, SEL_HSPI_1),
1353 PINMUX_IPSR_MODSEL_DATA(IP11_27_26, TX4_B, SEL_SCIF3_1), 1353 PINMUX_IPSR_MSEL(IP11_27_26, TX4_B, SEL_SCIF3_1),
1354 PINMUX_IPSR_MODSEL_DATA(IP11_27_26, ET0_RX_CLK_A, SEL_ET0_0), 1354 PINMUX_IPSR_MSEL(IP11_27_26, ET0_RX_CLK_A, SEL_ET0_0),
1355 1355
1356 PINMUX_IPSR_DATA(IP11_28, PRESETOUT), 1356 PINMUX_IPSR_DATA(IP11_28, PRESETOUT),
1357 PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT), 1357 PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT),
@@ -2445,6 +2445,6 @@ const struct sh_pfc_soc_info sh7734_pinmux_info = {
2445 .cfg_regs = pinmux_config_regs, 2445 .cfg_regs = pinmux_config_regs,
2446 .data_regs = pinmux_data_regs, 2446 .data_regs = pinmux_data_regs,
2447 2447
2448 .gpio_data = pinmux_data, 2448 .pinmux_data = pinmux_data,
2449 .gpio_data_size = ARRAY_SIZE(pinmux_data), 2449 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2450}; 2450};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
index 625661a88c52..0555a1fe076e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
@@ -2238,6 +2238,6 @@ const struct sh_pfc_soc_info sh7757_pinmux_info = {
2238 .cfg_regs = pinmux_config_regs, 2238 .cfg_regs = pinmux_config_regs,
2239 .data_regs = pinmux_data_regs, 2239 .data_regs = pinmux_data_regs,
2240 2240
2241 .gpio_data = pinmux_data, 2241 .pinmux_data = pinmux_data,
2242 .gpio_data_size = ARRAY_SIZE(pinmux_data), 2242 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2243}; 2243};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
index b38dd7e3e375..1934cbec3965 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
@@ -1269,6 +1269,6 @@ const struct sh_pfc_soc_info sh7785_pinmux_info = {
1269 .cfg_regs = pinmux_config_regs, 1269 .cfg_regs = pinmux_config_regs,
1270 .data_regs = pinmux_data_regs, 1270 .data_regs = pinmux_data_regs,
1271 1271
1272 .gpio_data = pinmux_data, 1272 .pinmux_data = pinmux_data,
1273 .gpio_data_size = ARRAY_SIZE(pinmux_data), 1273 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
1274}; 1274};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
index 6cb4e0aaf20b..c98585d80de8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
@@ -813,6 +813,6 @@ const struct sh_pfc_soc_info sh7786_pinmux_info = {
813 .cfg_regs = pinmux_config_regs, 813 .cfg_regs = pinmux_config_regs,
814 .data_regs = pinmux_data_regs, 814 .data_regs = pinmux_data_regs,
815 815
816 .gpio_data = pinmux_data, 816 .pinmux_data = pinmux_data,
817 .gpio_data_size = ARRAY_SIZE(pinmux_data), 817 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
818}; 818};
diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c
index a3fcb2284d91..3f60c900645e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-shx3.c
+++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c
@@ -554,8 +554,8 @@ const struct sh_pfc_soc_info shx3_pinmux_info = {
554 .nr_pins = ARRAY_SIZE(pinmux_pins), 554 .nr_pins = ARRAY_SIZE(pinmux_pins),
555 .func_gpios = pinmux_func_gpios, 555 .func_gpios = pinmux_func_gpios,
556 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), 556 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
557 .gpio_data = pinmux_data, 557 .pinmux_data = pinmux_data,
558 .gpio_data_size = ARRAY_SIZE(pinmux_data), 558 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
559 .cfg_regs = pinmux_config_regs, 559 .cfg_regs = pinmux_config_regs,
560 .data_regs = pinmux_data_regs, 560 .data_regs = pinmux_data_regs,
561}; 561};
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 15afd49fd4e3..7b373d43d981 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -52,6 +52,29 @@ struct sh_pfc_pin_group {
52 unsigned int nr_pins; 52 unsigned int nr_pins;
53}; 53};
54 54
55/*
56 * Using union vin_data saves memory occupied by the VIN data pins.
57 * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
58 * in this case.
59 */
60#define VIN_DATA_PIN_GROUP(n, s) \
61 { \
62 .name = #n#s, \
63 .pins = n##_pins.data##s, \
64 .mux = n##_mux.data##s, \
65 .nr_pins = ARRAY_SIZE(n##_pins.data##s), \
66 }
67
68union vin_data {
69 unsigned int data24[24];
70 unsigned int data20[20];
71 unsigned int data16[16];
72 unsigned int data12[12];
73 unsigned int data10[10];
74 unsigned int data8[8];
75 unsigned int data4[4];
76};
77
55#define SH_PFC_FUNCTION(n) \ 78#define SH_PFC_FUNCTION(n) \
56 { \ 79 { \
57 .name = #n, \ 80 .name = #n, \
@@ -98,17 +121,11 @@ struct pinmux_data_reg {
98 .enum_ids = (const u16 [r_width]) \ 121 .enum_ids = (const u16 [r_width]) \
99 122
100struct pinmux_irq { 123struct pinmux_irq {
101 int irq;
102 const short *gpios; 124 const short *gpios;
103}; 125};
104 126
105#ifdef CONFIG_ARCH_MULTIPLATFORM 127#define PINMUX_IRQ(ids...) \
106#define PINMUX_IRQ(irq_nr, ids...) \
107 { .gpios = (const short []) { ids, -1 } } 128 { .gpios = (const short []) { ids, -1 } }
108#else
109#define PINMUX_IRQ(irq_nr, ids...) \
110 { .irq = irq_nr, .gpios = (const short []) { ids, -1 } }
111#endif
112 129
113struct pinmux_range { 130struct pinmux_range {
114 u16 begin; 131 u16 begin;
@@ -143,14 +160,16 @@ struct sh_pfc_soc_info {
143 const struct sh_pfc_function *functions; 160 const struct sh_pfc_function *functions;
144 unsigned int nr_functions; 161 unsigned int nr_functions;
145 162
163#ifdef CONFIG_SUPERH
146 const struct pinmux_func *func_gpios; 164 const struct pinmux_func *func_gpios;
147 unsigned int nr_func_gpios; 165 unsigned int nr_func_gpios;
166#endif
148 167
149 const struct pinmux_cfg_reg *cfg_regs; 168 const struct pinmux_cfg_reg *cfg_regs;
150 const struct pinmux_data_reg *data_regs; 169 const struct pinmux_data_reg *data_regs;
151 170
152 const u16 *gpio_data; 171 const u16 *pinmux_data;
153 unsigned int gpio_data_size; 172 unsigned int pinmux_data_size;
154 173
155 const struct pinmux_irq *gpio_irq; 174 const struct pinmux_irq *gpio_irq;
156 unsigned int gpio_irq_size; 175 unsigned int gpio_irq_size;
@@ -163,7 +182,7 @@ struct sh_pfc_soc_info {
163 */ 182 */
164 183
165/* 184/*
166 * sh_pfc_soc_info gpio_data array macros 185 * sh_pfc_soc_info pinmux_data array macros
167 */ 186 */
168 187
169#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 188#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
@@ -177,33 +196,33 @@ struct sh_pfc_soc_info {
177#define PINMUX_IPSR_NOFN(ipsr, fn, ms) \ 196#define PINMUX_IPSR_NOFN(ipsr, fn, ms) \
178 PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##ms) 197 PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##ms)
179#define PINMUX_IPSR_MSEL(ipsr, fn, ms) \ 198#define PINMUX_IPSR_MSEL(ipsr, fn, ms) \
180 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms)
181#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) \
182 PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn) 199 PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn)
183 200
184/* 201/*
185 * GP port style (32 ports banks) 202 * GP port style (32 ports banks)
186 */ 203 */
187 204
188#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx) 205#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
189 206#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
190#define PORT_GP_32(bank, fn, sfx) \ 207
191 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ 208#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
192 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ 209 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
193 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ 210 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), PORT_GP_CFG_1(bank, 3, fn, sfx, cfg), \
194 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ 211 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \
195 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ 212 PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), PORT_GP_CFG_1(bank, 7, fn, sfx, cfg), \
196 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ 213 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg), PORT_GP_CFG_1(bank, 9, fn, sfx, cfg), \
197 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ 214 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), PORT_GP_CFG_1(bank, 11, fn, sfx, cfg), \
198 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ 215 PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), PORT_GP_CFG_1(bank, 13, fn, sfx, cfg), \
199 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ 216 PORT_GP_CFG_1(bank, 14, fn, sfx, cfg), PORT_GP_CFG_1(bank, 15, fn, sfx, cfg), \
200 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ 217 PORT_GP_CFG_1(bank, 16, fn, sfx, cfg), PORT_GP_CFG_1(bank, 17, fn, sfx, cfg), \
201 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ 218 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \
202 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ 219 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
203 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ 220 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg), PORT_GP_CFG_1(bank, 23, fn, sfx, cfg), \
204 PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ 221 PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), PORT_GP_CFG_1(bank, 25, fn, sfx, cfg), \
205 PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \ 222 PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), PORT_GP_CFG_1(bank, 27, fn, sfx, cfg), \
206 PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx) 223 PORT_GP_CFG_1(bank, 28, fn, sfx, cfg), PORT_GP_CFG_1(bank, 29, fn, sfx, cfg), \
224 PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
225#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
207 226
208#define PORT_GP_32_REV(bank, fn, sfx) \ 227#define PORT_GP_32_REV(bank, fn, sfx) \
209 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ 228 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
@@ -224,20 +243,21 @@ struct sh_pfc_soc_info {
224 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) 243 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
225 244
226/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */ 245/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
227#define _GP_ALL(bank, pin, name, sfx) name##_##sfx 246#define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
228#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str) 247#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
229 248
230/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ 249/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
231#define _GP_GPIO(bank, _pin, _name, sfx) \ 250#define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
232 { \ 251 { \
233 .pin = (bank * 32) + _pin, \ 252 .pin = (bank * 32) + _pin, \
234 .name = __stringify(_name), \ 253 .name = __stringify(_name), \
235 .enum_id = _name##_DATA, \ 254 .enum_id = _name##_DATA, \
255 .configs = cfg, \
236 } 256 }
237#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) 257#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
238 258
239/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */ 259/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
240#define _GP_DATA(bank, pin, name, sfx) PINMUX_DATA(name##_DATA, name##_FN) 260#define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
241#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) 261#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
242 262
243/* 263/*
@@ -326,4 +346,9 @@ struct sh_pfc_soc_info {
326 } \ 346 } \
327 } 347 }
328 348
349/*
350 * GPIO number helper macro for R-Car
351 */
352#define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
353
329#endif /* __SH_PFC_H */ 354#endif /* __SH_PFC_H */
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c
index 0d24d9e4b70c..829018c812bd 100644
--- a/drivers/pinctrl/sirf/pinctrl-atlas7.c
+++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c
@@ -544,6 +544,11 @@ static const struct pinctrl_pin_desc atlas7_ioc_pads[] = {
544 PINCTRL_PIN(156, "lvds_tx0d1n"), 544 PINCTRL_PIN(156, "lvds_tx0d1n"),
545 PINCTRL_PIN(157, "lvds_tx0d0p"), 545 PINCTRL_PIN(157, "lvds_tx0d0p"),
546 PINCTRL_PIN(158, "lvds_tx0d0n"), 546 PINCTRL_PIN(158, "lvds_tx0d0n"),
547 PINCTRL_PIN(159, "jtag_tdo"),
548 PINCTRL_PIN(160, "jtag_tms"),
549 PINCTRL_PIN(161, "jtag_tck"),
550 PINCTRL_PIN(162, "jtag_tdi"),
551 PINCTRL_PIN(163, "jtag_trstn"),
547}; 552};
548 553
549struct atlas7_pad_config atlas7_ioc_pad_confs[] = { 554struct atlas7_pad_config atlas7_ioc_pad_confs[] = {
@@ -708,6 +713,11 @@ struct atlas7_pad_config atlas7_ioc_pad_confs[] = {
708 PADCONF(156, 7, 0x130, 0x270, -1, 0x480, 28, 14, 0, 7), 713 PADCONF(156, 7, 0x130, 0x270, -1, 0x480, 28, 14, 0, 7),
709 PADCONF(157, 7, 0x138, 0x278, -1, 0x480, 0, 0, 0, 8), 714 PADCONF(157, 7, 0x138, 0x278, -1, 0x480, 0, 0, 0, 8),
710 PADCONF(158, 7, 0x138, 0x278, -1, 0x480, 4, 2, 0, 9), 715 PADCONF(158, 7, 0x138, 0x278, -1, 0x480, 4, 2, 0, 9),
716 PADCONF(159, 5, 0x140, 0x280, 0x380, -1, 0, 0, 0, 0),
717 PADCONF(160, 6, 0x140, 0x280, 0x380, -1, 4, 2, 2, 0),
718 PADCONF(161, 5, 0x140, 0x280, 0x380, -1, 8, 4, 4, 0),
719 PADCONF(162, 6, 0x140, 0x280, 0x380, -1, 12, 6, 6, 0),
720 PADCONF(163, 6, 0x140, 0x280, 0x380, -1, 16, 8, 8, 0),
711}; 721};
712 722
713/* pin list of each pin group */ 723/* pin list of each pin group */
@@ -724,12 +734,15 @@ static const unsigned int sp_rgmii_gpio_pins[] = { 97, 98, 99, 100, 101, 102,
724 141, 142, 143, 144, 145, 146, 147, 148, }; 734 141, 142, 143, 144, 145, 146, 147, 148, };
725static const unsigned int lvds_gpio_pins[] = { 157, 158, 155, 156, 153, 154, 735static const unsigned int lvds_gpio_pins[] = { 157, 158, 155, 156, 153, 154,
726 151, 152, 149, 150, }; 736 151, 152, 149, 150, };
727static const unsigned int uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40, 39, 737static const unsigned int jtag_uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40,
728 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135, 136, 738 39, 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135,
729 137, 138, 139, 140, }; 739 136, 137, 138, 139, 140, 159, 160, 161, 162, 163, };
730static const unsigned int rtc_gpio_pins[] = { 0, 1, 2, 3, 4, 10, 11, 12, 13, 740static const unsigned int rtc_gpio_pins[] = { 0, 1, 2, 3, 4, 10, 11, 12, 13,
731 14, 15, 16, 17, }; 741 14, 15, 16, 17, 9, };
732static const unsigned int audio_ac97_pins[] = { 113, 118, 115, 114, }; 742static const unsigned int audio_ac97_pins[] = { 113, 118, 115, 114, };
743static const unsigned int audio_digmic_pins0[] = { 51, };
744static const unsigned int audio_digmic_pins1[] = { 122, };
745static const unsigned int audio_digmic_pins2[] = { 161, };
733static const unsigned int audio_func_dbg_pins[] = { 141, 144, 44, 43, 42, 41, 746static const unsigned int audio_func_dbg_pins[] = { 141, 144, 44, 43, 42, 41,
734 40, 39, 38, 37, 74, 75, 76, 77, 78, 79, 81, 113, 114, 118, 747 40, 39, 38, 37, 74, 75, 76, 77, 78, 79, 81, 113, 114, 118,
735 115, 49, 50, 142, 143, 80, }; 748 115, 49, 50, 142, 143, 80, };
@@ -737,16 +750,49 @@ static const unsigned int audio_i2s_pins[] = { 118, 115, 116, 117, 112, 113,
737 114, }; 750 114, };
738static const unsigned int audio_i2s_2ch_pins[] = { 118, 115, 112, 113, 114, }; 751static const unsigned int audio_i2s_2ch_pins[] = { 118, 115, 112, 113, 114, };
739static const unsigned int audio_i2s_extclk_pins[] = { 112, }; 752static const unsigned int audio_i2s_extclk_pins[] = { 112, };
740static const unsigned int audio_uart0_pins[] = { 143, 142, 141, 144, }; 753static const unsigned int audio_spdif_out_pins0[] = { 112, };
741static const unsigned int audio_uart1_pins[] = { 147, 146, 145, 148, }; 754static const unsigned int audio_spdif_out_pins1[] = { 116, };
742static const unsigned int audio_uart2_pins0[] = { 20, 21, 19, 18, }; 755static const unsigned int audio_spdif_out_pins2[] = { 142, };
743static const unsigned int audio_uart2_pins1[] = { 109, 110, 101, 111, }; 756static const unsigned int audio_uart0_basic_pins[] = { 143, 142, 141, 144, };
744static const unsigned int c_can_trnsvr_pins[] = { 1, }; 757static const unsigned int audio_uart0_urfs_pins0[] = { 117, };
745static const unsigned int c0_can_pins0[] = { 11, 10, }; 758static const unsigned int audio_uart0_urfs_pins1[] = { 139, };
746static const unsigned int c0_can_pins1[] = { 2, 3, }; 759static const unsigned int audio_uart0_urfs_pins2[] = { 163, };
747static const unsigned int c1_can_pins0[] = { 138, 137, }; 760static const unsigned int audio_uart0_urfs_pins3[] = { 162, };
748static const unsigned int c1_can_pins1[] = { 147, 146, }; 761static const unsigned int audio_uart1_basic_pins[] = { 147, 146, 145, 148, };
749static const unsigned int c1_can_pins2[] = { 2, 3, }; 762static const unsigned int audio_uart1_urfs_pins0[] = { 117, };
763static const unsigned int audio_uart1_urfs_pins1[] = { 140, };
764static const unsigned int audio_uart1_urfs_pins2[] = { 163, };
765static const unsigned int audio_uart2_urfs_pins0[] = { 139, };
766static const unsigned int audio_uart2_urfs_pins1[] = { 163, };
767static const unsigned int audio_uart2_urfs_pins2[] = { 96, };
768static const unsigned int audio_uart2_urxd_pins0[] = { 20, };
769static const unsigned int audio_uart2_urxd_pins1[] = { 109, };
770static const unsigned int audio_uart2_urxd_pins2[] = { 93, };
771static const unsigned int audio_uart2_usclk_pins0[] = { 19, };
772static const unsigned int audio_uart2_usclk_pins1[] = { 101, };
773static const unsigned int audio_uart2_usclk_pins2[] = { 91, };
774static const unsigned int audio_uart2_utfs_pins0[] = { 18, };
775static const unsigned int audio_uart2_utfs_pins1[] = { 111, };
776static const unsigned int audio_uart2_utfs_pins2[] = { 94, };
777static const unsigned int audio_uart2_utxd_pins0[] = { 21, };
778static const unsigned int audio_uart2_utxd_pins1[] = { 110, };
779static const unsigned int audio_uart2_utxd_pins2[] = { 92, };
780static const unsigned int c_can_trnsvr_en_pins0[] = { 2, };
781static const unsigned int c_can_trnsvr_en_pins1[] = { 0, };
782static const unsigned int c_can_trnsvr_intr_pins[] = { 1, };
783static const unsigned int c_can_trnsvr_stb_n_pins[] = { 3, };
784static const unsigned int c0_can_rxd_trnsv0_pins[] = { 11, };
785static const unsigned int c0_can_rxd_trnsv1_pins[] = { 2, };
786static const unsigned int c0_can_txd_trnsv0_pins[] = { 10, };
787static const unsigned int c0_can_txd_trnsv1_pins[] = { 3, };
788static const unsigned int c1_can_rxd_pins0[] = { 138, };
789static const unsigned int c1_can_rxd_pins1[] = { 147, };
790static const unsigned int c1_can_rxd_pins2[] = { 2, };
791static const unsigned int c1_can_rxd_pins3[] = { 162, };
792static const unsigned int c1_can_txd_pins0[] = { 137, };
793static const unsigned int c1_can_txd_pins1[] = { 146, };
794static const unsigned int c1_can_txd_pins2[] = { 3, };
795static const unsigned int c1_can_txd_pins3[] = { 161, };
750static const unsigned int ca_audio_lpc_pins[] = { 62, 63, 64, 65, 66, 67, 68, 796static const unsigned int ca_audio_lpc_pins[] = { 62, 63, 64, 65, 66, 67, 68,
751 69, 70, 71, }; 797 69, 70, 71, };
752static const unsigned int ca_bt_lpc_pins[] = { 85, 86, 87, 88, 89, 90, }; 798static const unsigned int ca_bt_lpc_pins[] = { 85, 86, 87, 88, 89, 90, };
@@ -804,7 +850,29 @@ static const unsigned int gn_trg_shutdown_pins2[] = { 117, };
804static const unsigned int gn_trg_shutdown_pins3[] = { 123, }; 850static const unsigned int gn_trg_shutdown_pins3[] = { 123, };
805static const unsigned int i2c0_pins[] = { 128, 127, }; 851static const unsigned int i2c0_pins[] = { 128, 127, };
806static const unsigned int i2c1_pins[] = { 126, 125, }; 852static const unsigned int i2c1_pins[] = { 126, 125, };
807static const unsigned int jtag_pins0[] = { 125, 4, 2, 0, 1, 3, }; 853static const unsigned int i2s0_pins[] = { 91, 93, 94, 92, };
854static const unsigned int i2s1_basic_pins[] = { 95, 96, };
855static const unsigned int i2s1_rxd0_pins0[] = { 61, };
856static const unsigned int i2s1_rxd0_pins1[] = { 131, };
857static const unsigned int i2s1_rxd0_pins2[] = { 129, };
858static const unsigned int i2s1_rxd0_pins3[] = { 117, };
859static const unsigned int i2s1_rxd0_pins4[] = { 83, };
860static const unsigned int i2s1_rxd1_pins0[] = { 72, };
861static const unsigned int i2s1_rxd1_pins1[] = { 132, };
862static const unsigned int i2s1_rxd1_pins2[] = { 130, };
863static const unsigned int i2s1_rxd1_pins3[] = { 118, };
864static const unsigned int i2s1_rxd1_pins4[] = { 84, };
865static const unsigned int jtag_jt_dbg_nsrst_pins[] = { 125, };
866static const unsigned int jtag_ntrst_pins0[] = { 4, };
867static const unsigned int jtag_ntrst_pins1[] = { 163, };
868static const unsigned int jtag_swdiotms_pins0[] = { 2, };
869static const unsigned int jtag_swdiotms_pins1[] = { 160, };
870static const unsigned int jtag_tck_pins0[] = { 0, };
871static const unsigned int jtag_tck_pins1[] = { 161, };
872static const unsigned int jtag_tdi_pins0[] = { 1, };
873static const unsigned int jtag_tdi_pins1[] = { 162, };
874static const unsigned int jtag_tdo_pins0[] = { 3, };
875static const unsigned int jtag_tdo_pins1[] = { 159, };
808static const unsigned int ks_kas_spi_pins0[] = { 141, 144, 143, 142, }; 876static const unsigned int ks_kas_spi_pins0[] = { 141, 144, 143, 142, };
809static const unsigned int ld_ldd_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64, 877static const unsigned int ld_ldd_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64,
810 65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80, 878 65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80,
@@ -821,7 +889,7 @@ static const unsigned int nd_df_pins[] = { 44, 43, 42, 41, 40, 39, 38, 37,
821 47, 46, 52, 51, 45, 49, 50, 48, 124, }; 889 47, 46, 52, 51, 45, 49, 50, 48, 124, };
822static const unsigned int nd_df_nowp_pins[] = { 44, 43, 42, 41, 40, 39, 38, 890static const unsigned int nd_df_nowp_pins[] = { 44, 43, 42, 41, 40, 39, 38,
823 37, 47, 46, 52, 51, 45, 49, 50, 48, }; 891 37, 47, 46, 52, 51, 45, 49, 50, 48, };
824static const unsigned int ps_pins[] = { 120, 119, }; 892static const unsigned int ps_pins[] = { 120, 119, 121, };
825static const unsigned int pwc_core_on_pins[] = { 8, }; 893static const unsigned int pwc_core_on_pins[] = { 8, };
826static const unsigned int pwc_ext_on_pins[] = { 6, }; 894static const unsigned int pwc_ext_on_pins[] = { 6, };
827static const unsigned int pwc_gpio3_clk_pins[] = { 3, }; 895static const unsigned int pwc_gpio3_clk_pins[] = { 3, };
@@ -836,18 +904,26 @@ static const unsigned int pwc_wakeup_src3_pins[] = { 3, };
836static const unsigned int pw_cko0_pins0[] = { 123, }; 904static const unsigned int pw_cko0_pins0[] = { 123, };
837static const unsigned int pw_cko0_pins1[] = { 101, }; 905static const unsigned int pw_cko0_pins1[] = { 101, };
838static const unsigned int pw_cko0_pins2[] = { 82, }; 906static const unsigned int pw_cko0_pins2[] = { 82, };
907static const unsigned int pw_cko0_pins3[] = { 162, };
839static const unsigned int pw_cko1_pins0[] = { 124, }; 908static const unsigned int pw_cko1_pins0[] = { 124, };
840static const unsigned int pw_cko1_pins1[] = { 110, }; 909static const unsigned int pw_cko1_pins1[] = { 110, };
910static const unsigned int pw_cko1_pins2[] = { 163, };
841static const unsigned int pw_i2s01_clk_pins0[] = { 125, }; 911static const unsigned int pw_i2s01_clk_pins0[] = { 125, };
842static const unsigned int pw_i2s01_clk_pins1[] = { 117, }; 912static const unsigned int pw_i2s01_clk_pins1[] = { 117, };
843static const unsigned int pw_pwm0_pins[] = { 119, }; 913static const unsigned int pw_i2s01_clk_pins2[] = { 132, };
844static const unsigned int pw_pwm1_pins[] = { 120, }; 914static const unsigned int pw_pwm0_pins0[] = { 119, };
915static const unsigned int pw_pwm0_pins1[] = { 159, };
916static const unsigned int pw_pwm1_pins0[] = { 120, };
917static const unsigned int pw_pwm1_pins1[] = { 160, };
918static const unsigned int pw_pwm1_pins2[] = { 131, };
845static const unsigned int pw_pwm2_pins0[] = { 121, }; 919static const unsigned int pw_pwm2_pins0[] = { 121, };
846static const unsigned int pw_pwm2_pins1[] = { 98, }; 920static const unsigned int pw_pwm2_pins1[] = { 98, };
921static const unsigned int pw_pwm2_pins2[] = { 161, };
847static const unsigned int pw_pwm3_pins0[] = { 122, }; 922static const unsigned int pw_pwm3_pins0[] = { 122, };
848static const unsigned int pw_pwm3_pins1[] = { 73, }; 923static const unsigned int pw_pwm3_pins1[] = { 73, };
849static const unsigned int pw_pwm_cpu_vol_pins0[] = { 121, }; 924static const unsigned int pw_pwm_cpu_vol_pins0[] = { 121, };
850static const unsigned int pw_pwm_cpu_vol_pins1[] = { 98, }; 925static const unsigned int pw_pwm_cpu_vol_pins1[] = { 98, };
926static const unsigned int pw_pwm_cpu_vol_pins2[] = { 161, };
851static const unsigned int pw_backlight_pins0[] = { 122, }; 927static const unsigned int pw_backlight_pins0[] = { 122, };
852static const unsigned int pw_backlight_pins1[] = { 73, }; 928static const unsigned int pw_backlight_pins1[] = { 73, };
853static const unsigned int rg_eth_mac_pins[] = { 108, 103, 104, 105, 106, 107, 929static const unsigned int rg_eth_mac_pins[] = { 108, 103, 104, 105, 106, 107,
@@ -863,8 +939,11 @@ static const unsigned int sd1_pins[] = { 48, 49, 44, 43, 42, 41, 40, 39, 38,
863 37, }; 939 37, };
864static const unsigned int sd1_4bit_pins0[] = { 48, 49, 44, 43, 42, 41, }; 940static const unsigned int sd1_4bit_pins0[] = { 48, 49, 44, 43, 42, 41, };
865static const unsigned int sd1_4bit_pins1[] = { 48, 49, 40, 39, 38, 37, }; 941static const unsigned int sd1_4bit_pins1[] = { 48, 49, 40, 39, 38, 37, };
866static const unsigned int sd2_pins0[] = { 124, 31, 32, 33, 34, 35, 36, 123, }; 942static const unsigned int sd2_basic_pins[] = { 31, 32, 33, 34, 35, 36, };
867static const unsigned int sd2_no_cdb_pins0[] = { 31, 32, 33, 34, 35, 36, 123, }; 943static const unsigned int sd2_cdb_pins0[] = { 124, };
944static const unsigned int sd2_cdb_pins1[] = { 161, };
945static const unsigned int sd2_wpb_pins0[] = { 123, };
946static const unsigned int sd2_wpb_pins1[] = { 163, };
868static const unsigned int sd3_pins[] = { 85, 86, 87, 88, 89, 90, }; 947static const unsigned int sd3_pins[] = { 85, 86, 87, 88, 89, 90, };
869static const unsigned int sd5_pins[] = { 91, 92, 93, 94, 95, 96, }; 948static const unsigned int sd5_pins[] = { 91, 92, 93, 94, 95, 96, };
870static const unsigned int sd6_pins0[] = { 79, 78, 74, 75, 76, 77, }; 949static const unsigned int sd6_pins0[] = { 79, 78, 74, 75, 76, 77, };
@@ -877,19 +956,39 @@ static const unsigned int tpiu_trace_pins[] = { 53, 56, 57, 58, 59, 60, 61,
877static const unsigned int uart0_pins[] = { 121, 120, 134, 133, }; 956static const unsigned int uart0_pins[] = { 121, 120, 134, 133, };
878static const unsigned int uart0_nopause_pins[] = { 134, 133, }; 957static const unsigned int uart0_nopause_pins[] = { 134, 133, };
879static const unsigned int uart1_pins[] = { 136, 135, }; 958static const unsigned int uart1_pins[] = { 136, 135, };
880static const unsigned int uart2_pins[] = { 11, 10, }; 959static const unsigned int uart2_cts_pins0[] = { 132, };
881static const unsigned int uart3_pins0[] = { 125, 126, 138, 137, }; 960static const unsigned int uart2_cts_pins1[] = { 162, };
882static const unsigned int uart3_pins1[] = { 111, 109, 84, 83, }; 961static const unsigned int uart2_rts_pins0[] = { 131, };
883static const unsigned int uart3_pins2[] = { 140, 139, 138, 137, }; 962static const unsigned int uart2_rts_pins1[] = { 161, };
884static const unsigned int uart3_pins3[] = { 139, 140, 84, 83, }; 963static const unsigned int uart2_rxd_pins0[] = { 11, };
885static const unsigned int uart3_nopause_pins0[] = { 138, 137, }; 964static const unsigned int uart2_rxd_pins1[] = { 160, };
886static const unsigned int uart3_nopause_pins1[] = { 84, 83, }; 965static const unsigned int uart2_rxd_pins2[] = { 130, };
887static const unsigned int uart4_pins0[] = { 122, 123, 140, 139, }; 966static const unsigned int uart2_txd_pins0[] = { 10, };
888static const unsigned int uart4_pins1[] = { 100, 99, 140, 139, }; 967static const unsigned int uart2_txd_pins1[] = { 159, };
889static const unsigned int uart4_pins2[] = { 117, 116, 140, 139, }; 968static const unsigned int uart2_txd_pins2[] = { 129, };
890static const unsigned int uart4_nopause_pins[] = { 140, 139, }; 969static const unsigned int uart3_cts_pins0[] = { 125, };
891static const unsigned int usb0_drvvbus_pins[] = { 51, }; 970static const unsigned int uart3_cts_pins1[] = { 111, };
892static const unsigned int usb1_drvvbus_pins[] = { 134, }; 971static const unsigned int uart3_cts_pins2[] = { 140, };
972static const unsigned int uart3_rts_pins0[] = { 126, };
973static const unsigned int uart3_rts_pins1[] = { 109, };
974static const unsigned int uart3_rts_pins2[] = { 139, };
975static const unsigned int uart3_rxd_pins0[] = { 138, };
976static const unsigned int uart3_rxd_pins1[] = { 84, };
977static const unsigned int uart3_rxd_pins2[] = { 162, };
978static const unsigned int uart3_txd_pins0[] = { 137, };
979static const unsigned int uart3_txd_pins1[] = { 83, };
980static const unsigned int uart3_txd_pins2[] = { 161, };
981static const unsigned int uart4_basic_pins[] = { 140, 139, };
982static const unsigned int uart4_cts_pins0[] = { 122, };
983static const unsigned int uart4_cts_pins1[] = { 100, };
984static const unsigned int uart4_cts_pins2[] = { 117, };
985static const unsigned int uart4_rts_pins0[] = { 123, };
986static const unsigned int uart4_rts_pins1[] = { 99, };
987static const unsigned int uart4_rts_pins2[] = { 116, };
988static const unsigned int usb0_drvvbus_pins0[] = { 51, };
989static const unsigned int usb0_drvvbus_pins1[] = { 162, };
990static const unsigned int usb1_drvvbus_pins0[] = { 134, };
991static const unsigned int usb1_drvvbus_pins1[] = { 163, };
893static const unsigned int visbus_dout_pins[] = { 57, 58, 59, 60, 61, 62, 63, 992static const unsigned int visbus_dout_pins[] = { 57, 58, 59, 60, 61, 62, 63,
894 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 54, 55, 56, 85, 86, 993 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 54, 55, 56, 85, 86,
895 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, }; 994 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, };
@@ -910,23 +1009,59 @@ struct atlas7_pin_group altas7_pin_groups[] = {
910 GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins), 1009 GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins),
911 GROUP("sp_rgmii_gpio_grp", sp_rgmii_gpio_pins), 1010 GROUP("sp_rgmii_gpio_grp", sp_rgmii_gpio_pins),
912 GROUP("lvds_gpio_grp", lvds_gpio_pins), 1011 GROUP("lvds_gpio_grp", lvds_gpio_pins),
913 GROUP("uart_nand_gpio_grp", uart_nand_gpio_pins), 1012 GROUP("jtag_uart_nand_gpio_grp", jtag_uart_nand_gpio_pins),
914 GROUP("rtc_gpio_grp", rtc_gpio_pins), 1013 GROUP("rtc_gpio_grp", rtc_gpio_pins),
915 GROUP("audio_ac97_grp", audio_ac97_pins), 1014 GROUP("audio_ac97_grp", audio_ac97_pins),
1015 GROUP("audio_digmic_grp0", audio_digmic_pins0),
1016 GROUP("audio_digmic_grp1", audio_digmic_pins1),
1017 GROUP("audio_digmic_grp2", audio_digmic_pins2),
916 GROUP("audio_func_dbg_grp", audio_func_dbg_pins), 1018 GROUP("audio_func_dbg_grp", audio_func_dbg_pins),
917 GROUP("audio_i2s_grp", audio_i2s_pins), 1019 GROUP("audio_i2s_grp", audio_i2s_pins),
918 GROUP("audio_i2s_2ch_grp", audio_i2s_2ch_pins), 1020 GROUP("audio_i2s_2ch_grp", audio_i2s_2ch_pins),
919 GROUP("audio_i2s_extclk_grp", audio_i2s_extclk_pins), 1021 GROUP("audio_i2s_extclk_grp", audio_i2s_extclk_pins),
920 GROUP("audio_uart0_grp", audio_uart0_pins), 1022 GROUP("audio_spdif_out_grp0", audio_spdif_out_pins0),
921 GROUP("audio_uart1_grp", audio_uart1_pins), 1023 GROUP("audio_spdif_out_grp1", audio_spdif_out_pins1),
922 GROUP("audio_uart2_grp0", audio_uart2_pins0), 1024 GROUP("audio_spdif_out_grp2", audio_spdif_out_pins2),
923 GROUP("audio_uart2_grp1", audio_uart2_pins1), 1025 GROUP("audio_uart0_basic_grp", audio_uart0_basic_pins),
924 GROUP("c_can_trnsvr_grp", c_can_trnsvr_pins), 1026 GROUP("audio_uart0_urfs_grp0", audio_uart0_urfs_pins0),
925 GROUP("c0_can_grp0", c0_can_pins0), 1027 GROUP("audio_uart0_urfs_grp1", audio_uart0_urfs_pins1),
926 GROUP("c0_can_grp1", c0_can_pins1), 1028 GROUP("audio_uart0_urfs_grp2", audio_uart0_urfs_pins2),
927 GROUP("c1_can_grp0", c1_can_pins0), 1029 GROUP("audio_uart0_urfs_grp3", audio_uart0_urfs_pins3),
928 GROUP("c1_can_grp1", c1_can_pins1), 1030 GROUP("audio_uart1_basic_grp", audio_uart1_basic_pins),
929 GROUP("c1_can_grp2", c1_can_pins2), 1031 GROUP("audio_uart1_urfs_grp0", audio_uart1_urfs_pins0),
1032 GROUP("audio_uart1_urfs_grp1", audio_uart1_urfs_pins1),
1033 GROUP("audio_uart1_urfs_grp2", audio_uart1_urfs_pins2),
1034 GROUP("audio_uart2_urfs_grp0", audio_uart2_urfs_pins0),
1035 GROUP("audio_uart2_urfs_grp1", audio_uart2_urfs_pins1),
1036 GROUP("audio_uart2_urfs_grp2", audio_uart2_urfs_pins2),
1037 GROUP("audio_uart2_urxd_grp0", audio_uart2_urxd_pins0),
1038 GROUP("audio_uart2_urxd_grp1", audio_uart2_urxd_pins1),
1039 GROUP("audio_uart2_urxd_grp2", audio_uart2_urxd_pins2),
1040 GROUP("audio_uart2_usclk_grp0", audio_uart2_usclk_pins0),
1041 GROUP("audio_uart2_usclk_grp1", audio_uart2_usclk_pins1),
1042 GROUP("audio_uart2_usclk_grp2", audio_uart2_usclk_pins2),
1043 GROUP("audio_uart2_utfs_grp0", audio_uart2_utfs_pins0),
1044 GROUP("audio_uart2_utfs_grp1", audio_uart2_utfs_pins1),
1045 GROUP("audio_uart2_utfs_grp2", audio_uart2_utfs_pins2),
1046 GROUP("audio_uart2_utxd_grp0", audio_uart2_utxd_pins0),
1047 GROUP("audio_uart2_utxd_grp1", audio_uart2_utxd_pins1),
1048 GROUP("audio_uart2_utxd_grp2", audio_uart2_utxd_pins2),
1049 GROUP("c_can_trnsvr_en_grp0", c_can_trnsvr_en_pins0),
1050 GROUP("c_can_trnsvr_en_grp1", c_can_trnsvr_en_pins1),
1051 GROUP("c_can_trnsvr_intr_grp", c_can_trnsvr_intr_pins),
1052 GROUP("c_can_trnsvr_stb_n_grp", c_can_trnsvr_stb_n_pins),
1053 GROUP("c0_can_rxd_trnsv0_grp", c0_can_rxd_trnsv0_pins),
1054 GROUP("c0_can_rxd_trnsv1_grp", c0_can_rxd_trnsv1_pins),
1055 GROUP("c0_can_txd_trnsv0_grp", c0_can_txd_trnsv0_pins),
1056 GROUP("c0_can_txd_trnsv1_grp", c0_can_txd_trnsv1_pins),
1057 GROUP("c1_can_rxd_grp0", c1_can_rxd_pins0),
1058 GROUP("c1_can_rxd_grp1", c1_can_rxd_pins1),
1059 GROUP("c1_can_rxd_grp2", c1_can_rxd_pins2),
1060 GROUP("c1_can_rxd_grp3", c1_can_rxd_pins3),
1061 GROUP("c1_can_txd_grp0", c1_can_txd_pins0),
1062 GROUP("c1_can_txd_grp1", c1_can_txd_pins1),
1063 GROUP("c1_can_txd_grp2", c1_can_txd_pins2),
1064 GROUP("c1_can_txd_grp3", c1_can_txd_pins3),
930 GROUP("ca_audio_lpc_grp", ca_audio_lpc_pins), 1065 GROUP("ca_audio_lpc_grp", ca_audio_lpc_pins),
931 GROUP("ca_bt_lpc_grp", ca_bt_lpc_pins), 1066 GROUP("ca_bt_lpc_grp", ca_bt_lpc_pins),
932 GROUP("ca_coex_grp", ca_coex_pins), 1067 GROUP("ca_coex_grp", ca_coex_pins),
@@ -977,7 +1112,29 @@ struct atlas7_pin_group altas7_pin_groups[] = {
977 GROUP("gn_trg_shutdown_grp3", gn_trg_shutdown_pins3), 1112 GROUP("gn_trg_shutdown_grp3", gn_trg_shutdown_pins3),
978 GROUP("i2c0_grp", i2c0_pins), 1113 GROUP("i2c0_grp", i2c0_pins),
979 GROUP("i2c1_grp", i2c1_pins), 1114 GROUP("i2c1_grp", i2c1_pins),
980 GROUP("jtag_grp0", jtag_pins0), 1115 GROUP("i2s0_grp", i2s0_pins),
1116 GROUP("i2s1_basic_grp", i2s1_basic_pins),
1117 GROUP("i2s1_rxd0_grp0", i2s1_rxd0_pins0),
1118 GROUP("i2s1_rxd0_grp1", i2s1_rxd0_pins1),
1119 GROUP("i2s1_rxd0_grp2", i2s1_rxd0_pins2),
1120 GROUP("i2s1_rxd0_grp3", i2s1_rxd0_pins3),
1121 GROUP("i2s1_rxd0_grp4", i2s1_rxd0_pins4),
1122 GROUP("i2s1_rxd1_grp0", i2s1_rxd1_pins0),
1123 GROUP("i2s1_rxd1_grp1", i2s1_rxd1_pins1),
1124 GROUP("i2s1_rxd1_grp2", i2s1_rxd1_pins2),
1125 GROUP("i2s1_rxd1_grp3", i2s1_rxd1_pins3),
1126 GROUP("i2s1_rxd1_grp4", i2s1_rxd1_pins4),
1127 GROUP("jtag_jt_dbg_nsrst_grp", jtag_jt_dbg_nsrst_pins),
1128 GROUP("jtag_ntrst_grp0", jtag_ntrst_pins0),
1129 GROUP("jtag_ntrst_grp1", jtag_ntrst_pins1),
1130 GROUP("jtag_swdiotms_grp0", jtag_swdiotms_pins0),
1131 GROUP("jtag_swdiotms_grp1", jtag_swdiotms_pins1),
1132 GROUP("jtag_tck_grp0", jtag_tck_pins0),
1133 GROUP("jtag_tck_grp1", jtag_tck_pins1),
1134 GROUP("jtag_tdi_grp0", jtag_tdi_pins0),
1135 GROUP("jtag_tdi_grp1", jtag_tdi_pins1),
1136 GROUP("jtag_tdo_grp0", jtag_tdo_pins0),
1137 GROUP("jtag_tdo_grp1", jtag_tdo_pins1),
981 GROUP("ks_kas_spi_grp0", ks_kas_spi_pins0), 1138 GROUP("ks_kas_spi_grp0", ks_kas_spi_pins0),
982 GROUP("ld_ldd_grp", ld_ldd_pins), 1139 GROUP("ld_ldd_grp", ld_ldd_pins),
983 GROUP("ld_ldd_16bit_grp", ld_ldd_16bit_pins), 1140 GROUP("ld_ldd_16bit_grp", ld_ldd_16bit_pins),
@@ -1002,18 +1159,26 @@ struct atlas7_pin_group altas7_pin_groups[] = {
1002 GROUP("pw_cko0_grp0", pw_cko0_pins0), 1159 GROUP("pw_cko0_grp0", pw_cko0_pins0),
1003 GROUP("pw_cko0_grp1", pw_cko0_pins1), 1160 GROUP("pw_cko0_grp1", pw_cko0_pins1),
1004 GROUP("pw_cko0_grp2", pw_cko0_pins2), 1161 GROUP("pw_cko0_grp2", pw_cko0_pins2),
1162 GROUP("pw_cko0_grp3", pw_cko0_pins3),
1005 GROUP("pw_cko1_grp0", pw_cko1_pins0), 1163 GROUP("pw_cko1_grp0", pw_cko1_pins0),
1006 GROUP("pw_cko1_grp1", pw_cko1_pins1), 1164 GROUP("pw_cko1_grp1", pw_cko1_pins1),
1165 GROUP("pw_cko1_grp2", pw_cko1_pins2),
1007 GROUP("pw_i2s01_clk_grp0", pw_i2s01_clk_pins0), 1166 GROUP("pw_i2s01_clk_grp0", pw_i2s01_clk_pins0),
1008 GROUP("pw_i2s01_clk_grp1", pw_i2s01_clk_pins1), 1167 GROUP("pw_i2s01_clk_grp1", pw_i2s01_clk_pins1),
1009 GROUP("pw_pwm0_grp", pw_pwm0_pins), 1168 GROUP("pw_i2s01_clk_grp2", pw_i2s01_clk_pins2),
1010 GROUP("pw_pwm1_grp", pw_pwm1_pins), 1169 GROUP("pw_pwm0_grp0", pw_pwm0_pins0),
1170 GROUP("pw_pwm0_grp1", pw_pwm0_pins1),
1171 GROUP("pw_pwm1_grp0", pw_pwm1_pins0),
1172 GROUP("pw_pwm1_grp1", pw_pwm1_pins1),
1173 GROUP("pw_pwm1_grp2", pw_pwm1_pins2),
1011 GROUP("pw_pwm2_grp0", pw_pwm2_pins0), 1174 GROUP("pw_pwm2_grp0", pw_pwm2_pins0),
1012 GROUP("pw_pwm2_grp1", pw_pwm2_pins1), 1175 GROUP("pw_pwm2_grp1", pw_pwm2_pins1),
1176 GROUP("pw_pwm2_grp2", pw_pwm2_pins2),
1013 GROUP("pw_pwm3_grp0", pw_pwm3_pins0), 1177 GROUP("pw_pwm3_grp0", pw_pwm3_pins0),
1014 GROUP("pw_pwm3_grp1", pw_pwm3_pins1), 1178 GROUP("pw_pwm3_grp1", pw_pwm3_pins1),
1015 GROUP("pw_pwm_cpu_vol_grp0", pw_pwm_cpu_vol_pins0), 1179 GROUP("pw_pwm_cpu_vol_grp0", pw_pwm_cpu_vol_pins0),
1016 GROUP("pw_pwm_cpu_vol_grp1", pw_pwm_cpu_vol_pins1), 1180 GROUP("pw_pwm_cpu_vol_grp1", pw_pwm_cpu_vol_pins1),
1181 GROUP("pw_pwm_cpu_vol_grp2", pw_pwm_cpu_vol_pins2),
1017 GROUP("pw_backlight_grp0", pw_backlight_pins0), 1182 GROUP("pw_backlight_grp0", pw_backlight_pins0),
1018 GROUP("pw_backlight_grp1", pw_backlight_pins1), 1183 GROUP("pw_backlight_grp1", pw_backlight_pins1),
1019 GROUP("rg_eth_mac_grp", rg_eth_mac_pins), 1184 GROUP("rg_eth_mac_grp", rg_eth_mac_pins),
@@ -1026,8 +1191,11 @@ struct atlas7_pin_group altas7_pin_groups[] = {
1026 GROUP("sd1_grp", sd1_pins), 1191 GROUP("sd1_grp", sd1_pins),
1027 GROUP("sd1_4bit_grp0", sd1_4bit_pins0), 1192 GROUP("sd1_4bit_grp0", sd1_4bit_pins0),
1028 GROUP("sd1_4bit_grp1", sd1_4bit_pins1), 1193 GROUP("sd1_4bit_grp1", sd1_4bit_pins1),
1029 GROUP("sd2_grp0", sd2_pins0), 1194 GROUP("sd2_basic_grp", sd2_basic_pins),
1030 GROUP("sd2_no_cdb_grp0", sd2_no_cdb_pins0), 1195 GROUP("sd2_cdb_grp0", sd2_cdb_pins0),
1196 GROUP("sd2_cdb_grp1", sd2_cdb_pins1),
1197 GROUP("sd2_wpb_grp0", sd2_wpb_pins0),
1198 GROUP("sd2_wpb_grp1", sd2_wpb_pins1),
1031 GROUP("sd3_grp", sd3_pins), 1199 GROUP("sd3_grp", sd3_pins),
1032 GROUP("sd5_grp", sd5_pins), 1200 GROUP("sd5_grp", sd5_pins),
1033 GROUP("sd6_grp0", sd6_pins0), 1201 GROUP("sd6_grp0", sd6_pins0),
@@ -1039,19 +1207,39 @@ struct atlas7_pin_group altas7_pin_groups[] = {
1039 GROUP("uart0_grp", uart0_pins), 1207 GROUP("uart0_grp", uart0_pins),
1040 GROUP("uart0_nopause_grp", uart0_nopause_pins), 1208 GROUP("uart0_nopause_grp", uart0_nopause_pins),
1041 GROUP("uart1_grp", uart1_pins), 1209 GROUP("uart1_grp", uart1_pins),
1042 GROUP("uart2_grp", uart2_pins), 1210 GROUP("uart2_cts_grp0", uart2_cts_pins0),
1043 GROUP("uart3_grp0", uart3_pins0), 1211 GROUP("uart2_cts_grp1", uart2_cts_pins1),
1044 GROUP("uart3_grp1", uart3_pins1), 1212 GROUP("uart2_rts_grp0", uart2_rts_pins0),
1045 GROUP("uart3_grp2", uart3_pins2), 1213 GROUP("uart2_rts_grp1", uart2_rts_pins1),
1046 GROUP("uart3_grp3", uart3_pins3), 1214 GROUP("uart2_rxd_grp0", uart2_rxd_pins0),
1047 GROUP("uart3_nopause_grp0", uart3_nopause_pins0), 1215 GROUP("uart2_rxd_grp1", uart2_rxd_pins1),
1048 GROUP("uart3_nopause_grp1", uart3_nopause_pins1), 1216 GROUP("uart2_rxd_grp2", uart2_rxd_pins2),
1049 GROUP("uart4_grp0", uart4_pins0), 1217 GROUP("uart2_txd_grp0", uart2_txd_pins0),
1050 GROUP("uart4_grp1", uart4_pins1), 1218 GROUP("uart2_txd_grp1", uart2_txd_pins1),
1051 GROUP("uart4_grp2", uart4_pins2), 1219 GROUP("uart2_txd_grp2", uart2_txd_pins2),
1052 GROUP("uart4_nopause_grp", uart4_nopause_pins), 1220 GROUP("uart3_cts_grp0", uart3_cts_pins0),
1053 GROUP("usb0_drvvbus_grp", usb0_drvvbus_pins), 1221 GROUP("uart3_cts_grp1", uart3_cts_pins1),
1054 GROUP("usb1_drvvbus_grp", usb1_drvvbus_pins), 1222 GROUP("uart3_cts_grp2", uart3_cts_pins2),
1223 GROUP("uart3_rts_grp0", uart3_rts_pins0),
1224 GROUP("uart3_rts_grp1", uart3_rts_pins1),
1225 GROUP("uart3_rts_grp2", uart3_rts_pins2),
1226 GROUP("uart3_rxd_grp0", uart3_rxd_pins0),
1227 GROUP("uart3_rxd_grp1", uart3_rxd_pins1),
1228 GROUP("uart3_rxd_grp2", uart3_rxd_pins2),
1229 GROUP("uart3_txd_grp0", uart3_txd_pins0),
1230 GROUP("uart3_txd_grp1", uart3_txd_pins1),
1231 GROUP("uart3_txd_grp2", uart3_txd_pins2),
1232 GROUP("uart4_basic_grp", uart4_basic_pins),
1233 GROUP("uart4_cts_grp0", uart4_cts_pins0),
1234 GROUP("uart4_cts_grp1", uart4_cts_pins1),
1235 GROUP("uart4_cts_grp2", uart4_cts_pins2),
1236 GROUP("uart4_rts_grp0", uart4_rts_pins0),
1237 GROUP("uart4_rts_grp1", uart4_rts_pins1),
1238 GROUP("uart4_rts_grp2", uart4_rts_pins2),
1239 GROUP("usb0_drvvbus_grp0", usb0_drvvbus_pins0),
1240 GROUP("usb0_drvvbus_grp1", usb0_drvvbus_pins1),
1241 GROUP("usb1_drvvbus_grp0", usb1_drvvbus_pins0),
1242 GROUP("usb1_drvvbus_grp1", usb1_drvvbus_pins1),
1055 GROUP("visbus_dout_grp", visbus_dout_pins), 1243 GROUP("visbus_dout_grp", visbus_dout_pins),
1056 GROUP("vi_vip1_grp", vi_vip1_pins), 1244 GROUP("vi_vip1_grp", vi_vip1_pins),
1057 GROUP("vi_vip1_ext_grp", vi_vip1_ext_pins), 1245 GROUP("vi_vip1_ext_grp", vi_vip1_ext_pins),
@@ -1065,23 +1253,90 @@ static const char * const lcd_vip_gpio_grp[] = { "lcd_vip_gpio_grp", };
1065static const char * const sdio_i2s_gpio_grp[] = { "sdio_i2s_gpio_grp", }; 1253static const char * const sdio_i2s_gpio_grp[] = { "sdio_i2s_gpio_grp", };
1066static const char * const sp_rgmii_gpio_grp[] = { "sp_rgmii_gpio_grp", }; 1254static const char * const sp_rgmii_gpio_grp[] = { "sp_rgmii_gpio_grp", };
1067static const char * const lvds_gpio_grp[] = { "lvds_gpio_grp", }; 1255static const char * const lvds_gpio_grp[] = { "lvds_gpio_grp", };
1068static const char * const uart_nand_gpio_grp[] = { "uart_nand_gpio_grp", }; 1256static const char * const jtag_uart_nand_gpio_grp[] = {
1257 "jtag_uart_nand_gpio_grp", };
1069static const char * const rtc_gpio_grp[] = { "rtc_gpio_grp", }; 1258static const char * const rtc_gpio_grp[] = { "rtc_gpio_grp", };
1070static const char * const audio_ac97_grp[] = { "audio_ac97_grp", }; 1259static const char * const audio_ac97_grp[] = { "audio_ac97_grp", };
1260static const char * const audio_digmic_grp0[] = { "audio_digmic_grp0", };
1261static const char * const audio_digmic_grp1[] = { "audio_digmic_grp1", };
1262static const char * const audio_digmic_grp2[] = { "audio_digmic_grp2", };
1071static const char * const audio_func_dbg_grp[] = { "audio_func_dbg_grp", }; 1263static const char * const audio_func_dbg_grp[] = { "audio_func_dbg_grp", };
1072static const char * const audio_i2s_grp[] = { "audio_i2s_grp", }; 1264static const char * const audio_i2s_grp[] = { "audio_i2s_grp", };
1073static const char * const audio_i2s_2ch_grp[] = { "audio_i2s_2ch_grp", }; 1265static const char * const audio_i2s_2ch_grp[] = { "audio_i2s_2ch_grp", };
1074static const char * const audio_i2s_extclk_grp[] = { "audio_i2s_extclk_grp", }; 1266static const char * const audio_i2s_extclk_grp[] = { "audio_i2s_extclk_grp", };
1075static const char * const audio_uart0_grp[] = { "audio_uart0_grp", }; 1267static const char * const audio_spdif_out_grp0[] = { "audio_spdif_out_grp0", };
1076static const char * const audio_uart1_grp[] = { "audio_uart1_grp", }; 1268static const char * const audio_spdif_out_grp1[] = { "audio_spdif_out_grp1", };
1077static const char * const audio_uart2_grp0[] = { "audio_uart2_grp0", }; 1269static const char * const audio_spdif_out_grp2[] = { "audio_spdif_out_grp2", };
1078static const char * const audio_uart2_grp1[] = { "audio_uart2_grp1", }; 1270static const char * const audio_uart0_basic_grp[] = {
1079static const char * const c_can_trnsvr_grp[] = { "c_can_trnsvr_grp", }; 1271 "audio_uart0_basic_grp", };
1080static const char * const c0_can_grp0[] = { "c0_can_grp0", }; 1272static const char * const audio_uart0_urfs_grp0[] = {
1081static const char * const c0_can_grp1[] = { "c0_can_grp1", }; 1273 "audio_uart0_urfs_grp0", };
1082static const char * const c1_can_grp0[] = { "c1_can_grp0", }; 1274static const char * const audio_uart0_urfs_grp1[] = {
1083static const char * const c1_can_grp1[] = { "c1_can_grp1", }; 1275 "audio_uart0_urfs_grp1", };
1084static const char * const c1_can_grp2[] = { "c1_can_grp2", }; 1276static const char * const audio_uart0_urfs_grp2[] = {
1277 "audio_uart0_urfs_grp2", };
1278static const char * const audio_uart0_urfs_grp3[] = {
1279 "audio_uart0_urfs_grp3", };
1280static const char * const audio_uart1_basic_grp[] = {
1281 "audio_uart1_basic_grp", };
1282static const char * const audio_uart1_urfs_grp0[] = {
1283 "audio_uart1_urfs_grp0", };
1284static const char * const audio_uart1_urfs_grp1[] = {
1285 "audio_uart1_urfs_grp1", };
1286static const char * const audio_uart1_urfs_grp2[] = {
1287 "audio_uart1_urfs_grp2", };
1288static const char * const audio_uart2_urfs_grp0[] = {
1289 "audio_uart2_urfs_grp0", };
1290static const char * const audio_uart2_urfs_grp1[] = {
1291 "audio_uart2_urfs_grp1", };
1292static const char * const audio_uart2_urfs_grp2[] = {
1293 "audio_uart2_urfs_grp2", };
1294static const char * const audio_uart2_urxd_grp0[] = {
1295 "audio_uart2_urxd_grp0", };
1296static const char * const audio_uart2_urxd_grp1[] = {
1297 "audio_uart2_urxd_grp1", };
1298static const char * const audio_uart2_urxd_grp2[] = {
1299 "audio_uart2_urxd_grp2", };
1300static const char * const audio_uart2_usclk_grp0[] = {
1301 "audio_uart2_usclk_grp0", };
1302static const char * const audio_uart2_usclk_grp1[] = {
1303 "audio_uart2_usclk_grp1", };
1304static const char * const audio_uart2_usclk_grp2[] = {
1305 "audio_uart2_usclk_grp2", };
1306static const char * const audio_uart2_utfs_grp0[] = {
1307 "audio_uart2_utfs_grp0", };
1308static const char * const audio_uart2_utfs_grp1[] = {
1309 "audio_uart2_utfs_grp1", };
1310static const char * const audio_uart2_utfs_grp2[] = {
1311 "audio_uart2_utfs_grp2", };
1312static const char * const audio_uart2_utxd_grp0[] = {
1313 "audio_uart2_utxd_grp0", };
1314static const char * const audio_uart2_utxd_grp1[] = {
1315 "audio_uart2_utxd_grp1", };
1316static const char * const audio_uart2_utxd_grp2[] = {
1317 "audio_uart2_utxd_grp2", };
1318static const char * const c_can_trnsvr_en_grp0[] = { "c_can_trnsvr_en_grp0", };
1319static const char * const c_can_trnsvr_en_grp1[] = { "c_can_trnsvr_en_grp1", };
1320static const char * const c_can_trnsvr_intr_grp[] = {
1321 "c_can_trnsvr_intr_grp", };
1322static const char * const c_can_trnsvr_stb_n_grp[] = {
1323 "c_can_trnsvr_stb_n_grp", };
1324static const char * const c0_can_rxd_trnsv0_grp[] = {
1325 "c0_can_rxd_trnsv0_grp", };
1326static const char * const c0_can_rxd_trnsv1_grp[] = {
1327 "c0_can_rxd_trnsv1_grp", };
1328static const char * const c0_can_txd_trnsv0_grp[] = {
1329 "c0_can_txd_trnsv0_grp", };
1330static const char * const c0_can_txd_trnsv1_grp[] = {
1331 "c0_can_txd_trnsv1_grp", };
1332static const char * const c1_can_rxd_grp0[] = { "c1_can_rxd_grp0", };
1333static const char * const c1_can_rxd_grp1[] = { "c1_can_rxd_grp1", };
1334static const char * const c1_can_rxd_grp2[] = { "c1_can_rxd_grp2", };
1335static const char * const c1_can_rxd_grp3[] = { "c1_can_rxd_grp3", };
1336static const char * const c1_can_txd_grp0[] = { "c1_can_txd_grp0", };
1337static const char * const c1_can_txd_grp1[] = { "c1_can_txd_grp1", };
1338static const char * const c1_can_txd_grp2[] = { "c1_can_txd_grp2", };
1339static const char * const c1_can_txd_grp3[] = { "c1_can_txd_grp3", };
1085static const char * const ca_audio_lpc_grp[] = { "ca_audio_lpc_grp", }; 1340static const char * const ca_audio_lpc_grp[] = { "ca_audio_lpc_grp", };
1086static const char * const ca_bt_lpc_grp[] = { "ca_bt_lpc_grp", }; 1341static const char * const ca_bt_lpc_grp[] = { "ca_bt_lpc_grp", };
1087static const char * const ca_coex_grp[] = { "ca_coex_grp", }; 1342static const char * const ca_coex_grp[] = { "ca_coex_grp", };
@@ -1135,7 +1390,30 @@ static const char * const gn_trg_shutdown_grp2[] = { "gn_trg_shutdown_grp2", };
1135static const char * const gn_trg_shutdown_grp3[] = { "gn_trg_shutdown_grp3", }; 1390static const char * const gn_trg_shutdown_grp3[] = { "gn_trg_shutdown_grp3", };
1136static const char * const i2c0_grp[] = { "i2c0_grp", }; 1391static const char * const i2c0_grp[] = { "i2c0_grp", };
1137static const char * const i2c1_grp[] = { "i2c1_grp", }; 1392static const char * const i2c1_grp[] = { "i2c1_grp", };
1138static const char * const jtag_grp0[] = { "jtag_grp0", }; 1393static const char * const i2s0_grp[] = { "i2s0_grp", };
1394static const char * const i2s1_basic_grp[] = { "i2s1_basic_grp", };
1395static const char * const i2s1_rxd0_grp0[] = { "i2s1_rxd0_grp0", };
1396static const char * const i2s1_rxd0_grp1[] = { "i2s1_rxd0_grp1", };
1397static const char * const i2s1_rxd0_grp2[] = { "i2s1_rxd0_grp2", };
1398static const char * const i2s1_rxd0_grp3[] = { "i2s1_rxd0_grp3", };
1399static const char * const i2s1_rxd0_grp4[] = { "i2s1_rxd0_grp4", };
1400static const char * const i2s1_rxd1_grp0[] = { "i2s1_rxd1_grp0", };
1401static const char * const i2s1_rxd1_grp1[] = { "i2s1_rxd1_grp1", };
1402static const char * const i2s1_rxd1_grp2[] = { "i2s1_rxd1_grp2", };
1403static const char * const i2s1_rxd1_grp3[] = { "i2s1_rxd1_grp3", };
1404static const char * const i2s1_rxd1_grp4[] = { "i2s1_rxd1_grp4", };
1405static const char * const jtag_jt_dbg_nsrst_grp[] = {
1406 "jtag_jt_dbg_nsrst_grp", };
1407static const char * const jtag_ntrst_grp0[] = { "jtag_ntrst_grp0", };
1408static const char * const jtag_ntrst_grp1[] = { "jtag_ntrst_grp1", };
1409static const char * const jtag_swdiotms_grp0[] = { "jtag_swdiotms_grp0", };
1410static const char * const jtag_swdiotms_grp1[] = { "jtag_swdiotms_grp1", };
1411static const char * const jtag_tck_grp0[] = { "jtag_tck_grp0", };
1412static const char * const jtag_tck_grp1[] = { "jtag_tck_grp1", };
1413static const char * const jtag_tdi_grp0[] = { "jtag_tdi_grp0", };
1414static const char * const jtag_tdi_grp1[] = { "jtag_tdi_grp1", };
1415static const char * const jtag_tdo_grp0[] = { "jtag_tdo_grp0", };
1416static const char * const jtag_tdo_grp1[] = { "jtag_tdo_grp1", };
1139static const char * const ks_kas_spi_grp0[] = { "ks_kas_spi_grp0", }; 1417static const char * const ks_kas_spi_grp0[] = { "ks_kas_spi_grp0", };
1140static const char * const ld_ldd_grp[] = { "ld_ldd_grp", }; 1418static const char * const ld_ldd_grp[] = { "ld_ldd_grp", };
1141static const char * const ld_ldd_16bit_grp[] = { "ld_ldd_16bit_grp", }; 1419static const char * const ld_ldd_16bit_grp[] = { "ld_ldd_16bit_grp", };
@@ -1160,18 +1438,26 @@ static const char * const pwc_wakeup_src3_grp[] = { "pwc_wakeup_src3_grp", };
1160static const char * const pw_cko0_grp0[] = { "pw_cko0_grp0", }; 1438static const char * const pw_cko0_grp0[] = { "pw_cko0_grp0", };
1161static const char * const pw_cko0_grp1[] = { "pw_cko0_grp1", }; 1439static const char * const pw_cko0_grp1[] = { "pw_cko0_grp1", };
1162static const char * const pw_cko0_grp2[] = { "pw_cko0_grp2", }; 1440static const char * const pw_cko0_grp2[] = { "pw_cko0_grp2", };
1441static const char * const pw_cko0_grp3[] = { "pw_cko0_grp3", };
1163static const char * const pw_cko1_grp0[] = { "pw_cko1_grp0", }; 1442static const char * const pw_cko1_grp0[] = { "pw_cko1_grp0", };
1164static const char * const pw_cko1_grp1[] = { "pw_cko1_grp1", }; 1443static const char * const pw_cko1_grp1[] = { "pw_cko1_grp1", };
1444static const char * const pw_cko1_grp2[] = { "pw_cko1_grp2", };
1165static const char * const pw_i2s01_clk_grp0[] = { "pw_i2s01_clk_grp0", }; 1445static const char * const pw_i2s01_clk_grp0[] = { "pw_i2s01_clk_grp0", };
1166static const char * const pw_i2s01_clk_grp1[] = { "pw_i2s01_clk_grp1", }; 1446static const char * const pw_i2s01_clk_grp1[] = { "pw_i2s01_clk_grp1", };
1167static const char * const pw_pwm0_grp[] = { "pw_pwm0_grp", }; 1447static const char * const pw_i2s01_clk_grp2[] = { "pw_i2s01_clk_grp2", };
1168static const char * const pw_pwm1_grp[] = { "pw_pwm1_grp", }; 1448static const char * const pw_pwm0_grp0[] = { "pw_pwm0_grp0", };
1449static const char * const pw_pwm0_grp1[] = { "pw_pwm0_grp1", };
1450static const char * const pw_pwm1_grp0[] = { "pw_pwm1_grp0", };
1451static const char * const pw_pwm1_grp1[] = { "pw_pwm1_grp1", };
1452static const char * const pw_pwm1_grp2[] = { "pw_pwm1_grp2", };
1169static const char * const pw_pwm2_grp0[] = { "pw_pwm2_grp0", }; 1453static const char * const pw_pwm2_grp0[] = { "pw_pwm2_grp0", };
1170static const char * const pw_pwm2_grp1[] = { "pw_pwm2_grp1", }; 1454static const char * const pw_pwm2_grp1[] = { "pw_pwm2_grp1", };
1455static const char * const pw_pwm2_grp2[] = { "pw_pwm2_grp2", };
1171static const char * const pw_pwm3_grp0[] = { "pw_pwm3_grp0", }; 1456static const char * const pw_pwm3_grp0[] = { "pw_pwm3_grp0", };
1172static const char * const pw_pwm3_grp1[] = { "pw_pwm3_grp1", }; 1457static const char * const pw_pwm3_grp1[] = { "pw_pwm3_grp1", };
1173static const char * const pw_pwm_cpu_vol_grp0[] = { "pw_pwm_cpu_vol_grp0", }; 1458static const char * const pw_pwm_cpu_vol_grp0[] = { "pw_pwm_cpu_vol_grp0", };
1174static const char * const pw_pwm_cpu_vol_grp1[] = { "pw_pwm_cpu_vol_grp1", }; 1459static const char * const pw_pwm_cpu_vol_grp1[] = { "pw_pwm_cpu_vol_grp1", };
1460static const char * const pw_pwm_cpu_vol_grp2[] = { "pw_pwm_cpu_vol_grp2", };
1175static const char * const pw_backlight_grp0[] = { "pw_backlight_grp0", }; 1461static const char * const pw_backlight_grp0[] = { "pw_backlight_grp0", };
1176static const char * const pw_backlight_grp1[] = { "pw_backlight_grp1", }; 1462static const char * const pw_backlight_grp1[] = { "pw_backlight_grp1", };
1177static const char * const rg_eth_mac_grp[] = { "rg_eth_mac_grp", }; 1463static const char * const rg_eth_mac_grp[] = { "rg_eth_mac_grp", };
@@ -1187,8 +1473,11 @@ static const char * const sd0_4bit_grp[] = { "sd0_4bit_grp", };
1187static const char * const sd1_grp[] = { "sd1_grp", }; 1473static const char * const sd1_grp[] = { "sd1_grp", };
1188static const char * const sd1_4bit_grp0[] = { "sd1_4bit_grp0", }; 1474static const char * const sd1_4bit_grp0[] = { "sd1_4bit_grp0", };
1189static const char * const sd1_4bit_grp1[] = { "sd1_4bit_grp1", }; 1475static const char * const sd1_4bit_grp1[] = { "sd1_4bit_grp1", };
1190static const char * const sd2_grp0[] = { "sd2_grp0", }; 1476static const char * const sd2_basic_grp[] = { "sd2_basic_grp", };
1191static const char * const sd2_no_cdb_grp0[] = { "sd2_no_cdb_grp0", }; 1477static const char * const sd2_cdb_grp0[] = { "sd2_cdb_grp0", };
1478static const char * const sd2_cdb_grp1[] = { "sd2_cdb_grp1", };
1479static const char * const sd2_wpb_grp0[] = { "sd2_wpb_grp0", };
1480static const char * const sd2_wpb_grp1[] = { "sd2_wpb_grp1", };
1192static const char * const sd3_grp[] = { "sd3_grp", }; 1481static const char * const sd3_grp[] = { "sd3_grp", };
1193static const char * const sd5_grp[] = { "sd5_grp", }; 1482static const char * const sd5_grp[] = { "sd5_grp", };
1194static const char * const sd6_grp0[] = { "sd6_grp0", }; 1483static const char * const sd6_grp0[] = { "sd6_grp0", };
@@ -1200,19 +1489,39 @@ static const char * const tpiu_trace_grp[] = { "tpiu_trace_grp", };
1200static const char * const uart0_grp[] = { "uart0_grp", }; 1489static const char * const uart0_grp[] = { "uart0_grp", };
1201static const char * const uart0_nopause_grp[] = { "uart0_nopause_grp", }; 1490static const char * const uart0_nopause_grp[] = { "uart0_nopause_grp", };
1202static const char * const uart1_grp[] = { "uart1_grp", }; 1491static const char * const uart1_grp[] = { "uart1_grp", };
1203static const char * const uart2_grp[] = { "uart2_grp", }; 1492static const char * const uart2_cts_grp0[] = { "uart2_cts_grp0", };
1204static const char * const uart3_grp0[] = { "uart3_grp0", }; 1493static const char * const uart2_cts_grp1[] = { "uart2_cts_grp1", };
1205static const char * const uart3_grp1[] = { "uart3_grp1", }; 1494static const char * const uart2_rts_grp0[] = { "uart2_rts_grp0", };
1206static const char * const uart3_grp2[] = { "uart3_grp2", }; 1495static const char * const uart2_rts_grp1[] = { "uart2_rts_grp1", };
1207static const char * const uart3_grp3[] = { "uart3_grp3", }; 1496static const char * const uart2_rxd_grp0[] = { "uart2_rxd_grp0", };
1208static const char * const uart3_nopause_grp0[] = { "uart3_nopause_grp0", }; 1497static const char * const uart2_rxd_grp1[] = { "uart2_rxd_grp1", };
1209static const char * const uart3_nopause_grp1[] = { "uart3_nopause_grp1", }; 1498static const char * const uart2_rxd_grp2[] = { "uart2_rxd_grp2", };
1210static const char * const uart4_grp0[] = { "uart4_grp0", }; 1499static const char * const uart2_txd_grp0[] = { "uart2_txd_grp0", };
1211static const char * const uart4_grp1[] = { "uart4_grp1", }; 1500static const char * const uart2_txd_grp1[] = { "uart2_txd_grp1", };
1212static const char * const uart4_grp2[] = { "uart4_grp2", }; 1501static const char * const uart2_txd_grp2[] = { "uart2_txd_grp2", };
1213static const char * const uart4_nopause_grp[] = { "uart4_nopause_grp", }; 1502static const char * const uart3_cts_grp0[] = { "uart3_cts_grp0", };
1214static const char * const usb0_drvvbus_grp[] = { "usb0_drvvbus_grp", }; 1503static const char * const uart3_cts_grp1[] = { "uart3_cts_grp1", };
1215static const char * const usb1_drvvbus_grp[] = { "usb1_drvvbus_grp", }; 1504static const char * const uart3_cts_grp2[] = { "uart3_cts_grp2", };
1505static const char * const uart3_rts_grp0[] = { "uart3_rts_grp0", };
1506static const char * const uart3_rts_grp1[] = { "uart3_rts_grp1", };
1507static const char * const uart3_rts_grp2[] = { "uart3_rts_grp2", };
1508static const char * const uart3_rxd_grp0[] = { "uart3_rxd_grp0", };
1509static const char * const uart3_rxd_grp1[] = { "uart3_rxd_grp1", };
1510static const char * const uart3_rxd_grp2[] = { "uart3_rxd_grp2", };
1511static const char * const uart3_txd_grp0[] = { "uart3_txd_grp0", };
1512static const char * const uart3_txd_grp1[] = { "uart3_txd_grp1", };
1513static const char * const uart3_txd_grp2[] = { "uart3_txd_grp2", };
1514static const char * const uart4_basic_grp[] = { "uart4_basic_grp", };
1515static const char * const uart4_cts_grp0[] = { "uart4_cts_grp0", };
1516static const char * const uart4_cts_grp1[] = { "uart4_cts_grp1", };
1517static const char * const uart4_cts_grp2[] = { "uart4_cts_grp2", };
1518static const char * const uart4_rts_grp0[] = { "uart4_rts_grp0", };
1519static const char * const uart4_rts_grp1[] = { "uart4_rts_grp1", };
1520static const char * const uart4_rts_grp2[] = { "uart4_rts_grp2", };
1521static const char * const usb0_drvvbus_grp0[] = { "usb0_drvvbus_grp0", };
1522static const char * const usb0_drvvbus_grp1[] = { "usb0_drvvbus_grp1", };
1523static const char * const usb1_drvvbus_grp0[] = { "usb1_drvvbus_grp0", };
1524static const char * const usb1_drvvbus_grp1[] = { "usb1_drvvbus_grp1", };
1216static const char * const visbus_dout_grp[] = { "visbus_dout_grp", }; 1525static const char * const visbus_dout_grp[] = { "visbus_dout_grp", };
1217static const char * const vi_vip1_grp[] = { "vi_vip1_grp", }; 1526static const char * const vi_vip1_grp[] = { "vi_vip1_grp", };
1218static const char * const vi_vip1_ext_grp[] = { "vi_vip1_ext_grp", }; 1527static const char * const vi_vip1_ext_grp[] = { "vi_vip1_ext_grp", };
@@ -1376,7 +1685,7 @@ static struct atlas7_grp_mux lvds_gpio_grp_mux = {
1376 .pad_mux_list = lvds_gpio_grp_pad_mux, 1685 .pad_mux_list = lvds_gpio_grp_pad_mux,
1377}; 1686};
1378 1687
1379static struct atlas7_pad_mux uart_nand_gpio_grp_pad_mux[] = { 1688static struct atlas7_pad_mux jtag_uart_nand_gpio_grp_pad_mux[] = {
1380 MUX(1, 44, 0, N, N, N, N), 1689 MUX(1, 44, 0, N, N, N, N),
1381 MUX(1, 43, 0, N, N, N, N), 1690 MUX(1, 43, 0, N, N, N, N),
1382 MUX(1, 42, 0, N, N, N, N), 1691 MUX(1, 42, 0, N, N, N, N),
@@ -1401,11 +1710,16 @@ static struct atlas7_pad_mux uart_nand_gpio_grp_pad_mux[] = {
1401 MUX(1, 138, 0, N, N, N, N), 1710 MUX(1, 138, 0, N, N, N, N),
1402 MUX(1, 139, 0, N, N, N, N), 1711 MUX(1, 139, 0, N, N, N, N),
1403 MUX(1, 140, 0, N, N, N, N), 1712 MUX(1, 140, 0, N, N, N, N),
1713 MUX(1, 159, 0, N, N, N, N),
1714 MUX(1, 160, 0, N, N, N, N),
1715 MUX(1, 161, 0, N, N, N, N),
1716 MUX(1, 162, 0, N, N, N, N),
1717 MUX(1, 163, 0, N, N, N, N),
1404}; 1718};
1405 1719
1406static struct atlas7_grp_mux uart_nand_gpio_grp_mux = { 1720static struct atlas7_grp_mux jtag_uart_nand_gpio_grp_mux = {
1407 .pad_mux_count = ARRAY_SIZE(uart_nand_gpio_grp_pad_mux), 1721 .pad_mux_count = ARRAY_SIZE(jtag_uart_nand_gpio_grp_pad_mux),
1408 .pad_mux_list = uart_nand_gpio_grp_pad_mux, 1722 .pad_mux_list = jtag_uart_nand_gpio_grp_pad_mux,
1409}; 1723};
1410 1724
1411static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = { 1725static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = {
@@ -1422,6 +1736,7 @@ static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = {
1422 MUX(0, 15, 0, N, N, N, N), 1736 MUX(0, 15, 0, N, N, N, N),
1423 MUX(0, 16, 0, N, N, N, N), 1737 MUX(0, 16, 0, N, N, N, N),
1424 MUX(0, 17, 0, N, N, N, N), 1738 MUX(0, 17, 0, N, N, N, N),
1739 MUX(0, 9, 0, N, N, N, N),
1425}; 1740};
1426 1741
1427static struct atlas7_grp_mux rtc_gpio_grp_mux = { 1742static struct atlas7_grp_mux rtc_gpio_grp_mux = {
@@ -1441,6 +1756,33 @@ static struct atlas7_grp_mux audio_ac97_grp_mux = {
1441 .pad_mux_list = audio_ac97_grp_pad_mux, 1756 .pad_mux_list = audio_ac97_grp_pad_mux,
1442}; 1757};
1443 1758
1759static struct atlas7_pad_mux audio_digmic_grp0_pad_mux[] = {
1760 MUX(1, 51, 3, 0xa10, 20, 0xa90, 20),
1761};
1762
1763static struct atlas7_grp_mux audio_digmic_grp0_mux = {
1764 .pad_mux_count = ARRAY_SIZE(audio_digmic_grp0_pad_mux),
1765 .pad_mux_list = audio_digmic_grp0_pad_mux,
1766};
1767
1768static struct atlas7_pad_mux audio_digmic_grp1_pad_mux[] = {
1769 MUX(1, 122, 5, 0xa10, 20, 0xa90, 20),
1770};
1771
1772static struct atlas7_grp_mux audio_digmic_grp1_mux = {
1773 .pad_mux_count = ARRAY_SIZE(audio_digmic_grp1_pad_mux),
1774 .pad_mux_list = audio_digmic_grp1_pad_mux,
1775};
1776
1777static struct atlas7_pad_mux audio_digmic_grp2_pad_mux[] = {
1778 MUX(1, 161, 7, 0xa10, 20, 0xa90, 20),
1779};
1780
1781static struct atlas7_grp_mux audio_digmic_grp2_mux = {
1782 .pad_mux_count = ARRAY_SIZE(audio_digmic_grp2_pad_mux),
1783 .pad_mux_list = audio_digmic_grp2_pad_mux,
1784};
1785
1444static struct atlas7_pad_mux audio_func_dbg_grp_pad_mux[] = { 1786static struct atlas7_pad_mux audio_func_dbg_grp_pad_mux[] = {
1445 MUX(1, 141, 4, N, N, N, N), 1787 MUX(1, 141, 4, N, N, N, N),
1446 MUX(1, 144, 4, N, N, N, N), 1788 MUX(1, 144, 4, N, N, N, N),
@@ -1512,111 +1854,397 @@ static struct atlas7_grp_mux audio_i2s_extclk_grp_mux = {
1512 .pad_mux_list = audio_i2s_extclk_grp_pad_mux, 1854 .pad_mux_list = audio_i2s_extclk_grp_pad_mux,
1513}; 1855};
1514 1856
1515static struct atlas7_pad_mux audio_uart0_grp_pad_mux[] = { 1857static struct atlas7_pad_mux audio_spdif_out_grp0_pad_mux[] = {
1858 MUX(1, 112, 3, N, N, N, N),
1859};
1860
1861static struct atlas7_grp_mux audio_spdif_out_grp0_mux = {
1862 .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp0_pad_mux),
1863 .pad_mux_list = audio_spdif_out_grp0_pad_mux,
1864};
1865
1866static struct atlas7_pad_mux audio_spdif_out_grp1_pad_mux[] = {
1867 MUX(1, 116, 3, N, N, N, N),
1868};
1869
1870static struct atlas7_grp_mux audio_spdif_out_grp1_mux = {
1871 .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp1_pad_mux),
1872 .pad_mux_list = audio_spdif_out_grp1_pad_mux,
1873};
1874
1875static struct atlas7_pad_mux audio_spdif_out_grp2_pad_mux[] = {
1876 MUX(1, 142, 3, N, N, N, N),
1877};
1878
1879static struct atlas7_grp_mux audio_spdif_out_grp2_mux = {
1880 .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp2_pad_mux),
1881 .pad_mux_list = audio_spdif_out_grp2_pad_mux,
1882};
1883
1884static struct atlas7_pad_mux audio_uart0_basic_grp_pad_mux[] = {
1516 MUX(1, 143, 1, N, N, N, N), 1885 MUX(1, 143, 1, N, N, N, N),
1517 MUX(1, 142, 1, N, N, N, N), 1886 MUX(1, 142, 1, N, N, N, N),
1518 MUX(1, 141, 1, N, N, N, N), 1887 MUX(1, 141, 1, N, N, N, N),
1519 MUX(1, 144, 1, N, N, N, N), 1888 MUX(1, 144, 1, N, N, N, N),
1520}; 1889};
1521 1890
1522static struct atlas7_grp_mux audio_uart0_grp_mux = { 1891static struct atlas7_grp_mux audio_uart0_basic_grp_mux = {
1523 .pad_mux_count = ARRAY_SIZE(audio_uart0_grp_pad_mux), 1892 .pad_mux_count = ARRAY_SIZE(audio_uart0_basic_grp_pad_mux),
1524 .pad_mux_list = audio_uart0_grp_pad_mux, 1893 .pad_mux_list = audio_uart0_basic_grp_pad_mux,
1894};
1895
1896static struct atlas7_pad_mux audio_uart0_urfs_grp0_pad_mux[] = {
1897 MUX(1, 117, 5, 0xa10, 28, 0xa90, 28),
1525}; 1898};
1526 1899
1527static struct atlas7_pad_mux audio_uart1_grp_pad_mux[] = { 1900static struct atlas7_grp_mux audio_uart0_urfs_grp0_mux = {
1528 MUX(1, 147, 1, N, N, N, N), 1901 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp0_pad_mux),
1529 MUX(1, 146, 1, N, N, N, N), 1902 .pad_mux_list = audio_uart0_urfs_grp0_pad_mux,
1530 MUX(1, 145, 1, N, N, N, N),
1531 MUX(1, 148, 1, N, N, N, N),
1532}; 1903};
1533 1904
1534static struct atlas7_grp_mux audio_uart1_grp_mux = { 1905static struct atlas7_pad_mux audio_uart0_urfs_grp1_pad_mux[] = {
1535 .pad_mux_count = ARRAY_SIZE(audio_uart1_grp_pad_mux), 1906 MUX(1, 139, 3, 0xa10, 28, 0xa90, 28),
1536 .pad_mux_list = audio_uart1_grp_pad_mux,
1537}; 1907};
1538 1908
1539static struct atlas7_pad_mux audio_uart2_grp0_pad_mux[] = { 1909static struct atlas7_grp_mux audio_uart0_urfs_grp1_mux = {
1910 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp1_pad_mux),
1911 .pad_mux_list = audio_uart0_urfs_grp1_pad_mux,
1912};
1913
1914static struct atlas7_pad_mux audio_uart0_urfs_grp2_pad_mux[] = {
1915 MUX(1, 163, 3, 0xa10, 28, 0xa90, 28),
1916};
1917
1918static struct atlas7_grp_mux audio_uart0_urfs_grp2_mux = {
1919 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp2_pad_mux),
1920 .pad_mux_list = audio_uart0_urfs_grp2_pad_mux,
1921};
1922
1923static struct atlas7_pad_mux audio_uart0_urfs_grp3_pad_mux[] = {
1924 MUX(1, 162, 6, 0xa10, 28, 0xa90, 28),
1925};
1926
1927static struct atlas7_grp_mux audio_uart0_urfs_grp3_mux = {
1928 .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp3_pad_mux),
1929 .pad_mux_list = audio_uart0_urfs_grp3_pad_mux,
1930};
1931
1932static struct atlas7_pad_mux audio_uart1_basic_grp_pad_mux[] = {
1933 MUX(1, 147, 1, 0xa10, 24, 0xa90, 24),
1934 MUX(1, 146, 1, 0xa10, 25, 0xa90, 25),
1935 MUX(1, 145, 1, 0xa10, 23, 0xa90, 23),
1936 MUX(1, 148, 1, 0xa10, 22, 0xa90, 22),
1937};
1938
1939static struct atlas7_grp_mux audio_uart1_basic_grp_mux = {
1940 .pad_mux_count = ARRAY_SIZE(audio_uart1_basic_grp_pad_mux),
1941 .pad_mux_list = audio_uart1_basic_grp_pad_mux,
1942};
1943
1944static struct atlas7_pad_mux audio_uart1_urfs_grp0_pad_mux[] = {
1945 MUX(1, 117, 6, 0xa10, 29, 0xa90, 29),
1946};
1947
1948static struct atlas7_grp_mux audio_uart1_urfs_grp0_mux = {
1949 .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp0_pad_mux),
1950 .pad_mux_list = audio_uart1_urfs_grp0_pad_mux,
1951};
1952
1953static struct atlas7_pad_mux audio_uart1_urfs_grp1_pad_mux[] = {
1954 MUX(1, 140, 3, 0xa10, 29, 0xa90, 29),
1955};
1956
1957static struct atlas7_grp_mux audio_uart1_urfs_grp1_mux = {
1958 .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp1_pad_mux),
1959 .pad_mux_list = audio_uart1_urfs_grp1_pad_mux,
1960};
1961
1962static struct atlas7_pad_mux audio_uart1_urfs_grp2_pad_mux[] = {
1963 MUX(1, 163, 4, 0xa10, 29, 0xa90, 29),
1964};
1965
1966static struct atlas7_grp_mux audio_uart1_urfs_grp2_mux = {
1967 .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp2_pad_mux),
1968 .pad_mux_list = audio_uart1_urfs_grp2_pad_mux,
1969};
1970
1971static struct atlas7_pad_mux audio_uart2_urfs_grp0_pad_mux[] = {
1972 MUX(1, 139, 4, 0xa10, 30, 0xa90, 30),
1973};
1974
1975static struct atlas7_grp_mux audio_uart2_urfs_grp0_mux = {
1976 .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp0_pad_mux),
1977 .pad_mux_list = audio_uart2_urfs_grp0_pad_mux,
1978};
1979
1980static struct atlas7_pad_mux audio_uart2_urfs_grp1_pad_mux[] = {
1981 MUX(1, 163, 6, 0xa10, 30, 0xa90, 30),
1982};
1983
1984static struct atlas7_grp_mux audio_uart2_urfs_grp1_mux = {
1985 .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp1_pad_mux),
1986 .pad_mux_list = audio_uart2_urfs_grp1_pad_mux,
1987};
1988
1989static struct atlas7_pad_mux audio_uart2_urfs_grp2_pad_mux[] = {
1990 MUX(1, 96, 3, 0xa10, 30, 0xa90, 30),
1991};
1992
1993static struct atlas7_grp_mux audio_uart2_urfs_grp2_mux = {
1994 .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp2_pad_mux),
1995 .pad_mux_list = audio_uart2_urfs_grp2_pad_mux,
1996};
1997
1998static struct atlas7_pad_mux audio_uart2_urxd_grp0_pad_mux[] = {
1540 MUX(1, 20, 2, 0xa00, 24, 0xa80, 24), 1999 MUX(1, 20, 2, 0xa00, 24, 0xa80, 24),
1541 MUX(1, 21, 2, 0xa00, 25, 0xa80, 25),
1542 MUX(1, 19, 2, 0xa00, 23, 0xa80, 23),
1543 MUX(1, 18, 2, 0xa00, 22, 0xa80, 22),
1544}; 2000};
1545 2001
1546static struct atlas7_grp_mux audio_uart2_grp0_mux = { 2002static struct atlas7_grp_mux audio_uart2_urxd_grp0_mux = {
1547 .pad_mux_count = ARRAY_SIZE(audio_uart2_grp0_pad_mux), 2003 .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp0_pad_mux),
1548 .pad_mux_list = audio_uart2_grp0_pad_mux, 2004 .pad_mux_list = audio_uart2_urxd_grp0_pad_mux,
1549}; 2005};
1550 2006
1551static struct atlas7_pad_mux audio_uart2_grp1_pad_mux[] = { 2007static struct atlas7_pad_mux audio_uart2_urxd_grp1_pad_mux[] = {
1552 MUX(1, 109, 2, 0xa00, 24, 0xa80, 24), 2008 MUX(1, 109, 2, 0xa00, 24, 0xa80, 24),
1553 MUX(1, 110, 2, 0xa00, 25, 0xa80, 25), 2009};
2010
2011static struct atlas7_grp_mux audio_uart2_urxd_grp1_mux = {
2012 .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp1_pad_mux),
2013 .pad_mux_list = audio_uart2_urxd_grp1_pad_mux,
2014};
2015
2016static struct atlas7_pad_mux audio_uart2_urxd_grp2_pad_mux[] = {
2017 MUX(1, 93, 3, 0xa00, 24, 0xa80, 24),
2018};
2019
2020static struct atlas7_grp_mux audio_uart2_urxd_grp2_mux = {
2021 .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp2_pad_mux),
2022 .pad_mux_list = audio_uart2_urxd_grp2_pad_mux,
2023};
2024
2025static struct atlas7_pad_mux audio_uart2_usclk_grp0_pad_mux[] = {
2026 MUX(1, 19, 2, 0xa00, 23, 0xa80, 23),
2027};
2028
2029static struct atlas7_grp_mux audio_uart2_usclk_grp0_mux = {
2030 .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp0_pad_mux),
2031 .pad_mux_list = audio_uart2_usclk_grp0_pad_mux,
2032};
2033
2034static struct atlas7_pad_mux audio_uart2_usclk_grp1_pad_mux[] = {
1554 MUX(1, 101, 2, 0xa00, 23, 0xa80, 23), 2035 MUX(1, 101, 2, 0xa00, 23, 0xa80, 23),
2036};
2037
2038static struct atlas7_grp_mux audio_uart2_usclk_grp1_mux = {
2039 .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp1_pad_mux),
2040 .pad_mux_list = audio_uart2_usclk_grp1_pad_mux,
2041};
2042
2043static struct atlas7_pad_mux audio_uart2_usclk_grp2_pad_mux[] = {
2044 MUX(1, 91, 3, 0xa00, 23, 0xa80, 23),
2045};
2046
2047static struct atlas7_grp_mux audio_uart2_usclk_grp2_mux = {
2048 .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp2_pad_mux),
2049 .pad_mux_list = audio_uart2_usclk_grp2_pad_mux,
2050};
2051
2052static struct atlas7_pad_mux audio_uart2_utfs_grp0_pad_mux[] = {
2053 MUX(1, 18, 2, 0xa00, 22, 0xa80, 22),
2054};
2055
2056static struct atlas7_grp_mux audio_uart2_utfs_grp0_mux = {
2057 .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp0_pad_mux),
2058 .pad_mux_list = audio_uart2_utfs_grp0_pad_mux,
2059};
2060
2061static struct atlas7_pad_mux audio_uart2_utfs_grp1_pad_mux[] = {
1555 MUX(1, 111, 2, 0xa00, 22, 0xa80, 22), 2062 MUX(1, 111, 2, 0xa00, 22, 0xa80, 22),
1556}; 2063};
1557 2064
1558static struct atlas7_grp_mux audio_uart2_grp1_mux = { 2065static struct atlas7_grp_mux audio_uart2_utfs_grp1_mux = {
1559 .pad_mux_count = ARRAY_SIZE(audio_uart2_grp1_pad_mux), 2066 .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp1_pad_mux),
1560 .pad_mux_list = audio_uart2_grp1_pad_mux, 2067 .pad_mux_list = audio_uart2_utfs_grp1_pad_mux,
2068};
2069
2070static struct atlas7_pad_mux audio_uart2_utfs_grp2_pad_mux[] = {
2071 MUX(1, 94, 3, 0xa00, 22, 0xa80, 22),
2072};
2073
2074static struct atlas7_grp_mux audio_uart2_utfs_grp2_mux = {
2075 .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp2_pad_mux),
2076 .pad_mux_list = audio_uart2_utfs_grp2_pad_mux,
2077};
2078
2079static struct atlas7_pad_mux audio_uart2_utxd_grp0_pad_mux[] = {
2080 MUX(1, 21, 2, 0xa00, 25, 0xa80, 25),
2081};
2082
2083static struct atlas7_grp_mux audio_uart2_utxd_grp0_mux = {
2084 .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp0_pad_mux),
2085 .pad_mux_list = audio_uart2_utxd_grp0_pad_mux,
2086};
2087
2088static struct atlas7_pad_mux audio_uart2_utxd_grp1_pad_mux[] = {
2089 MUX(1, 110, 2, 0xa00, 25, 0xa80, 25),
2090};
2091
2092static struct atlas7_grp_mux audio_uart2_utxd_grp1_mux = {
2093 .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp1_pad_mux),
2094 .pad_mux_list = audio_uart2_utxd_grp1_pad_mux,
2095};
2096
2097static struct atlas7_pad_mux audio_uart2_utxd_grp2_pad_mux[] = {
2098 MUX(1, 92, 3, 0xa00, 25, 0xa80, 25),
2099};
2100
2101static struct atlas7_grp_mux audio_uart2_utxd_grp2_mux = {
2102 .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp2_pad_mux),
2103 .pad_mux_list = audio_uart2_utxd_grp2_pad_mux,
2104};
2105
2106static struct atlas7_pad_mux c_can_trnsvr_en_grp0_pad_mux[] = {
2107 MUX(0, 2, 6, N, N, N, N),
1561}; 2108};
1562 2109
1563static struct atlas7_pad_mux c_can_trnsvr_grp_pad_mux[] = { 2110static struct atlas7_grp_mux c_can_trnsvr_en_grp0_mux = {
2111 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp0_pad_mux),
2112 .pad_mux_list = c_can_trnsvr_en_grp0_pad_mux,
2113};
2114
2115static struct atlas7_pad_mux c_can_trnsvr_en_grp1_pad_mux[] = {
2116 MUX(0, 0, 2, N, N, N, N),
2117};
2118
2119static struct atlas7_grp_mux c_can_trnsvr_en_grp1_mux = {
2120 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp1_pad_mux),
2121 .pad_mux_list = c_can_trnsvr_en_grp1_pad_mux,
2122};
2123
2124static struct atlas7_pad_mux c_can_trnsvr_intr_grp_pad_mux[] = {
1564 MUX(0, 1, 2, N, N, N, N), 2125 MUX(0, 1, 2, N, N, N, N),
1565}; 2126};
1566 2127
1567static struct atlas7_grp_mux c_can_trnsvr_grp_mux = { 2128static struct atlas7_grp_mux c_can_trnsvr_intr_grp_mux = {
1568 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_grp_pad_mux), 2129 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_intr_grp_pad_mux),
1569 .pad_mux_list = c_can_trnsvr_grp_pad_mux, 2130 .pad_mux_list = c_can_trnsvr_intr_grp_pad_mux,
1570}; 2131};
1571 2132
1572static struct atlas7_pad_mux c0_can_grp0_pad_mux[] = { 2133static struct atlas7_pad_mux c_can_trnsvr_stb_n_grp_pad_mux[] = {
2134 MUX(0, 3, 6, N, N, N, N),
2135};
2136
2137static struct atlas7_grp_mux c_can_trnsvr_stb_n_grp_mux = {
2138 .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_stb_n_grp_pad_mux),
2139 .pad_mux_list = c_can_trnsvr_stb_n_grp_pad_mux,
2140};
2141
2142static struct atlas7_pad_mux c0_can_rxd_trnsv0_grp_pad_mux[] = {
1573 MUX(0, 11, 1, 0xa08, 9, 0xa88, 9), 2143 MUX(0, 11, 1, 0xa08, 9, 0xa88, 9),
2144};
2145
2146static struct atlas7_grp_mux c0_can_rxd_trnsv0_grp_mux = {
2147 .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv0_grp_pad_mux),
2148 .pad_mux_list = c0_can_rxd_trnsv0_grp_pad_mux,
2149};
2150
2151static struct atlas7_pad_mux c0_can_rxd_trnsv1_grp_pad_mux[] = {
2152 MUX(0, 2, 5, 0xa10, 9, 0xa90, 9),
2153};
2154
2155static struct atlas7_grp_mux c0_can_rxd_trnsv1_grp_mux = {
2156 .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv1_grp_pad_mux),
2157 .pad_mux_list = c0_can_rxd_trnsv1_grp_pad_mux,
2158};
2159
2160static struct atlas7_pad_mux c0_can_txd_trnsv0_grp_pad_mux[] = {
1574 MUX(0, 10, 1, N, N, N, N), 2161 MUX(0, 10, 1, N, N, N, N),
1575}; 2162};
1576 2163
1577static struct atlas7_grp_mux c0_can_grp0_mux = { 2164static struct atlas7_grp_mux c0_can_txd_trnsv0_grp_mux = {
1578 .pad_mux_count = ARRAY_SIZE(c0_can_grp0_pad_mux), 2165 .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv0_grp_pad_mux),
1579 .pad_mux_list = c0_can_grp0_pad_mux, 2166 .pad_mux_list = c0_can_txd_trnsv0_grp_pad_mux,
1580}; 2167};
1581 2168
1582static struct atlas7_pad_mux c0_can_grp1_pad_mux[] = { 2169static struct atlas7_pad_mux c0_can_txd_trnsv1_grp_pad_mux[] = {
1583 MUX(0, 2, 5, 0xa08, 9, 0xa88, 9),
1584 MUX(0, 3, 5, N, N, N, N), 2170 MUX(0, 3, 5, N, N, N, N),
1585}; 2171};
1586 2172
1587static struct atlas7_grp_mux c0_can_grp1_mux = { 2173static struct atlas7_grp_mux c0_can_txd_trnsv1_grp_mux = {
1588 .pad_mux_count = ARRAY_SIZE(c0_can_grp1_pad_mux), 2174 .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv1_grp_pad_mux),
1589 .pad_mux_list = c0_can_grp1_pad_mux, 2175 .pad_mux_list = c0_can_txd_trnsv1_grp_pad_mux,
1590}; 2176};
1591 2177
1592static struct atlas7_pad_mux c1_can_grp0_pad_mux[] = { 2178static struct atlas7_pad_mux c1_can_rxd_grp0_pad_mux[] = {
1593 MUX(1, 138, 2, 0xa00, 4, 0xa80, 4), 2179 MUX(1, 138, 2, 0xa00, 4, 0xa80, 4),
1594 MUX(1, 137, 2, N, N, N, N),
1595}; 2180};
1596 2181
1597static struct atlas7_grp_mux c1_can_grp0_mux = { 2182static struct atlas7_grp_mux c1_can_rxd_grp0_mux = {
1598 .pad_mux_count = ARRAY_SIZE(c1_can_grp0_pad_mux), 2183 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp0_pad_mux),
1599 .pad_mux_list = c1_can_grp0_pad_mux, 2184 .pad_mux_list = c1_can_rxd_grp0_pad_mux,
1600}; 2185};
1601 2186
1602static struct atlas7_pad_mux c1_can_grp1_pad_mux[] = { 2187static struct atlas7_pad_mux c1_can_rxd_grp1_pad_mux[] = {
1603 MUX(1, 147, 2, 0xa00, 4, 0xa80, 4), 2188 MUX(1, 147, 2, 0xa00, 4, 0xa80, 4),
1604 MUX(1, 146, 2, N, N, N, N),
1605}; 2189};
1606 2190
1607static struct atlas7_grp_mux c1_can_grp1_mux = { 2191static struct atlas7_grp_mux c1_can_rxd_grp1_mux = {
1608 .pad_mux_count = ARRAY_SIZE(c1_can_grp1_pad_mux), 2192 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp1_pad_mux),
1609 .pad_mux_list = c1_can_grp1_pad_mux, 2193 .pad_mux_list = c1_can_rxd_grp1_pad_mux,
1610}; 2194};
1611 2195
1612static struct atlas7_pad_mux c1_can_grp2_pad_mux[] = { 2196static struct atlas7_pad_mux c1_can_rxd_grp2_pad_mux[] = {
1613 MUX(0, 2, 2, 0xa00, 4, 0xa80, 4), 2197 MUX(0, 2, 2, 0xa00, 4, 0xa80, 4),
2198};
2199
2200static struct atlas7_grp_mux c1_can_rxd_grp2_mux = {
2201 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp2_pad_mux),
2202 .pad_mux_list = c1_can_rxd_grp2_pad_mux,
2203};
2204
2205static struct atlas7_pad_mux c1_can_rxd_grp3_pad_mux[] = {
2206 MUX(1, 162, 4, 0xa00, 4, 0xa80, 4),
2207};
2208
2209static struct atlas7_grp_mux c1_can_rxd_grp3_mux = {
2210 .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp3_pad_mux),
2211 .pad_mux_list = c1_can_rxd_grp3_pad_mux,
2212};
2213
2214static struct atlas7_pad_mux c1_can_txd_grp0_pad_mux[] = {
2215 MUX(1, 137, 2, N, N, N, N),
2216};
2217
2218static struct atlas7_grp_mux c1_can_txd_grp0_mux = {
2219 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp0_pad_mux),
2220 .pad_mux_list = c1_can_txd_grp0_pad_mux,
2221};
2222
2223static struct atlas7_pad_mux c1_can_txd_grp1_pad_mux[] = {
2224 MUX(1, 146, 2, N, N, N, N),
2225};
2226
2227static struct atlas7_grp_mux c1_can_txd_grp1_mux = {
2228 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp1_pad_mux),
2229 .pad_mux_list = c1_can_txd_grp1_pad_mux,
2230};
2231
2232static struct atlas7_pad_mux c1_can_txd_grp2_pad_mux[] = {
1614 MUX(0, 3, 2, N, N, N, N), 2233 MUX(0, 3, 2, N, N, N, N),
1615}; 2234};
1616 2235
1617static struct atlas7_grp_mux c1_can_grp2_mux = { 2236static struct atlas7_grp_mux c1_can_txd_grp2_mux = {
1618 .pad_mux_count = ARRAY_SIZE(c1_can_grp2_pad_mux), 2237 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp2_pad_mux),
1619 .pad_mux_list = c1_can_grp2_pad_mux, 2238 .pad_mux_list = c1_can_txd_grp2_pad_mux,
2239};
2240
2241static struct atlas7_pad_mux c1_can_txd_grp3_pad_mux[] = {
2242 MUX(1, 161, 4, N, N, N, N),
2243};
2244
2245static struct atlas7_grp_mux c1_can_txd_grp3_mux = {
2246 .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp3_pad_mux),
2247 .pad_mux_list = c1_can_txd_grp3_pad_mux,
1620}; 2248};
1621 2249
1622static struct atlas7_pad_mux ca_audio_lpc_grp_pad_mux[] = { 2250static struct atlas7_pad_mux ca_audio_lpc_grp_pad_mux[] = {
@@ -2198,18 +2826,215 @@ static struct atlas7_grp_mux i2c1_grp_mux = {
2198 .pad_mux_list = i2c1_grp_pad_mux, 2826 .pad_mux_list = i2c1_grp_pad_mux,
2199}; 2827};
2200 2828
2201static struct atlas7_pad_mux jtag_grp0_pad_mux[] = { 2829static struct atlas7_pad_mux i2s0_grp_pad_mux[] = {
2830 MUX(1, 91, 2, 0xa10, 12, 0xa90, 12),
2831 MUX(1, 93, 2, 0xa10, 13, 0xa90, 13),
2832 MUX(1, 94, 2, 0xa10, 14, 0xa90, 14),
2833 MUX(1, 92, 2, 0xa10, 15, 0xa90, 15),
2834};
2835
2836static struct atlas7_grp_mux i2s0_grp_mux = {
2837 .pad_mux_count = ARRAY_SIZE(i2s0_grp_pad_mux),
2838 .pad_mux_list = i2s0_grp_pad_mux,
2839};
2840
2841static struct atlas7_pad_mux i2s1_basic_grp_pad_mux[] = {
2842 MUX(1, 95, 2, 0xa10, 16, 0xa90, 16),
2843 MUX(1, 96, 2, 0xa10, 19, 0xa90, 19),
2844};
2845
2846static struct atlas7_grp_mux i2s1_basic_grp_mux = {
2847 .pad_mux_count = ARRAY_SIZE(i2s1_basic_grp_pad_mux),
2848 .pad_mux_list = i2s1_basic_grp_pad_mux,
2849};
2850
2851static struct atlas7_pad_mux i2s1_rxd0_grp0_pad_mux[] = {
2852 MUX(1, 61, 4, 0xa10, 17, 0xa90, 17),
2853};
2854
2855static struct atlas7_grp_mux i2s1_rxd0_grp0_mux = {
2856 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp0_pad_mux),
2857 .pad_mux_list = i2s1_rxd0_grp0_pad_mux,
2858};
2859
2860static struct atlas7_pad_mux i2s1_rxd0_grp1_pad_mux[] = {
2861 MUX(1, 131, 4, 0xa10, 17, 0xa90, 17),
2862};
2863
2864static struct atlas7_grp_mux i2s1_rxd0_grp1_mux = {
2865 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp1_pad_mux),
2866 .pad_mux_list = i2s1_rxd0_grp1_pad_mux,
2867};
2868
2869static struct atlas7_pad_mux i2s1_rxd0_grp2_pad_mux[] = {
2870 MUX(1, 129, 2, 0xa10, 17, 0xa90, 17),
2871};
2872
2873static struct atlas7_grp_mux i2s1_rxd0_grp2_mux = {
2874 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp2_pad_mux),
2875 .pad_mux_list = i2s1_rxd0_grp2_pad_mux,
2876};
2877
2878static struct atlas7_pad_mux i2s1_rxd0_grp3_pad_mux[] = {
2879 MUX(1, 117, 7, 0xa10, 17, 0xa90, 17),
2880};
2881
2882static struct atlas7_grp_mux i2s1_rxd0_grp3_mux = {
2883 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp3_pad_mux),
2884 .pad_mux_list = i2s1_rxd0_grp3_pad_mux,
2885};
2886
2887static struct atlas7_pad_mux i2s1_rxd0_grp4_pad_mux[] = {
2888 MUX(1, 83, 4, 0xa10, 17, 0xa90, 17),
2889};
2890
2891static struct atlas7_grp_mux i2s1_rxd0_grp4_mux = {
2892 .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp4_pad_mux),
2893 .pad_mux_list = i2s1_rxd0_grp4_pad_mux,
2894};
2895
2896static struct atlas7_pad_mux i2s1_rxd1_grp0_pad_mux[] = {
2897 MUX(1, 72, 4, 0xa10, 18, 0xa90, 18),
2898};
2899
2900static struct atlas7_grp_mux i2s1_rxd1_grp0_mux = {
2901 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp0_pad_mux),
2902 .pad_mux_list = i2s1_rxd1_grp0_pad_mux,
2903};
2904
2905static struct atlas7_pad_mux i2s1_rxd1_grp1_pad_mux[] = {
2906 MUX(1, 132, 4, 0xa10, 18, 0xa90, 18),
2907};
2908
2909static struct atlas7_grp_mux i2s1_rxd1_grp1_mux = {
2910 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp1_pad_mux),
2911 .pad_mux_list = i2s1_rxd1_grp1_pad_mux,
2912};
2913
2914static struct atlas7_pad_mux i2s1_rxd1_grp2_pad_mux[] = {
2915 MUX(1, 130, 2, 0xa10, 18, 0xa90, 18),
2916};
2917
2918static struct atlas7_grp_mux i2s1_rxd1_grp2_mux = {
2919 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp2_pad_mux),
2920 .pad_mux_list = i2s1_rxd1_grp2_pad_mux,
2921};
2922
2923static struct atlas7_pad_mux i2s1_rxd1_grp3_pad_mux[] = {
2924 MUX(1, 118, 7, 0xa10, 18, 0xa90, 18),
2925};
2926
2927static struct atlas7_grp_mux i2s1_rxd1_grp3_mux = {
2928 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp3_pad_mux),
2929 .pad_mux_list = i2s1_rxd1_grp3_pad_mux,
2930};
2931
2932static struct atlas7_pad_mux i2s1_rxd1_grp4_pad_mux[] = {
2933 MUX(1, 84, 4, 0xa10, 18, 0xa90, 18),
2934};
2935
2936static struct atlas7_grp_mux i2s1_rxd1_grp4_mux = {
2937 .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp4_pad_mux),
2938 .pad_mux_list = i2s1_rxd1_grp4_pad_mux,
2939};
2940
2941static struct atlas7_pad_mux jtag_jt_dbg_nsrst_grp_pad_mux[] = {
2202 MUX(1, 125, 5, 0xa08, 2, 0xa88, 2), 2942 MUX(1, 125, 5, 0xa08, 2, 0xa88, 2),
2943};
2944
2945static struct atlas7_grp_mux jtag_jt_dbg_nsrst_grp_mux = {
2946 .pad_mux_count = ARRAY_SIZE(jtag_jt_dbg_nsrst_grp_pad_mux),
2947 .pad_mux_list = jtag_jt_dbg_nsrst_grp_pad_mux,
2948};
2949
2950static struct atlas7_pad_mux jtag_ntrst_grp0_pad_mux[] = {
2203 MUX(0, 4, 3, 0xa08, 3, 0xa88, 3), 2951 MUX(0, 4, 3, 0xa08, 3, 0xa88, 3),
2204 MUX(0, 2, 3, N, N, N, N), 2952};
2205 MUX(0, 0, 3, N, N, N, N), 2953
2206 MUX(0, 1, 3, N, N, N, N), 2954static struct atlas7_grp_mux jtag_ntrst_grp0_mux = {
2955 .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp0_pad_mux),
2956 .pad_mux_list = jtag_ntrst_grp0_pad_mux,
2957};
2958
2959static struct atlas7_pad_mux jtag_ntrst_grp1_pad_mux[] = {
2960 MUX(1, 163, 1, 0xa08, 3, 0xa88, 3),
2961};
2962
2963static struct atlas7_grp_mux jtag_ntrst_grp1_mux = {
2964 .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp1_pad_mux),
2965 .pad_mux_list = jtag_ntrst_grp1_pad_mux,
2966};
2967
2968static struct atlas7_pad_mux jtag_swdiotms_grp0_pad_mux[] = {
2969 MUX(0, 2, 3, 0xa10, 10, 0xa90, 10),
2970};
2971
2972static struct atlas7_grp_mux jtag_swdiotms_grp0_mux = {
2973 .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp0_pad_mux),
2974 .pad_mux_list = jtag_swdiotms_grp0_pad_mux,
2975};
2976
2977static struct atlas7_pad_mux jtag_swdiotms_grp1_pad_mux[] = {
2978 MUX(1, 160, 1, 0xa10, 10, 0xa90, 10),
2979};
2980
2981static struct atlas7_grp_mux jtag_swdiotms_grp1_mux = {
2982 .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp1_pad_mux),
2983 .pad_mux_list = jtag_swdiotms_grp1_pad_mux,
2984};
2985
2986static struct atlas7_pad_mux jtag_tck_grp0_pad_mux[] = {
2987 MUX(0, 0, 3, 0xa10, 11, 0xa90, 11),
2988};
2989
2990static struct atlas7_grp_mux jtag_tck_grp0_mux = {
2991 .pad_mux_count = ARRAY_SIZE(jtag_tck_grp0_pad_mux),
2992 .pad_mux_list = jtag_tck_grp0_pad_mux,
2993};
2994
2995static struct atlas7_pad_mux jtag_tck_grp1_pad_mux[] = {
2996 MUX(1, 161, 1, 0xa10, 11, 0xa90, 11),
2997};
2998
2999static struct atlas7_grp_mux jtag_tck_grp1_mux = {
3000 .pad_mux_count = ARRAY_SIZE(jtag_tck_grp1_pad_mux),
3001 .pad_mux_list = jtag_tck_grp1_pad_mux,
3002};
3003
3004static struct atlas7_pad_mux jtag_tdi_grp0_pad_mux[] = {
3005 MUX(0, 1, 3, 0xa10, 31, 0xa90, 31),
3006};
3007
3008static struct atlas7_grp_mux jtag_tdi_grp0_mux = {
3009 .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp0_pad_mux),
3010 .pad_mux_list = jtag_tdi_grp0_pad_mux,
3011};
3012
3013static struct atlas7_pad_mux jtag_tdi_grp1_pad_mux[] = {
3014 MUX(1, 162, 1, 0xa10, 31, 0xa90, 31),
3015};
3016
3017static struct atlas7_grp_mux jtag_tdi_grp1_mux = {
3018 .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp1_pad_mux),
3019 .pad_mux_list = jtag_tdi_grp1_pad_mux,
3020};
3021
3022static struct atlas7_pad_mux jtag_tdo_grp0_pad_mux[] = {
2207 MUX(0, 3, 3, N, N, N, N), 3023 MUX(0, 3, 3, N, N, N, N),
2208}; 3024};
2209 3025
2210static struct atlas7_grp_mux jtag_grp0_mux = { 3026static struct atlas7_grp_mux jtag_tdo_grp0_mux = {
2211 .pad_mux_count = ARRAY_SIZE(jtag_grp0_pad_mux), 3027 .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp0_pad_mux),
2212 .pad_mux_list = jtag_grp0_pad_mux, 3028 .pad_mux_list = jtag_tdo_grp0_pad_mux,
3029};
3030
3031static struct atlas7_pad_mux jtag_tdo_grp1_pad_mux[] = {
3032 MUX(1, 159, 1, N, N, N, N),
3033};
3034
3035static struct atlas7_grp_mux jtag_tdo_grp1_mux = {
3036 .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp1_pad_mux),
3037 .pad_mux_list = jtag_tdo_grp1_pad_mux,
2213}; 3038};
2214 3039
2215static struct atlas7_pad_mux ks_kas_spi_grp0_pad_mux[] = { 3040static struct atlas7_pad_mux ks_kas_spi_grp0_pad_mux[] = {
@@ -2401,6 +3226,7 @@ static struct atlas7_grp_mux nd_df_nowp_grp_mux = {
2401static struct atlas7_pad_mux ps_grp_pad_mux[] = { 3226static struct atlas7_pad_mux ps_grp_pad_mux[] = {
2402 MUX(1, 120, 2, N, N, N, N), 3227 MUX(1, 120, 2, N, N, N, N),
2403 MUX(1, 119, 2, N, N, N, N), 3228 MUX(1, 119, 2, N, N, N, N),
3229 MUX(1, 121, 5, N, N, N, N),
2404}; 3230};
2405 3231
2406static struct atlas7_grp_mux ps_grp_mux = { 3232static struct atlas7_grp_mux ps_grp_mux = {
@@ -2534,6 +3360,15 @@ static struct atlas7_grp_mux pw_cko0_grp2_mux = {
2534 .pad_mux_list = pw_cko0_grp2_pad_mux, 3360 .pad_mux_list = pw_cko0_grp2_pad_mux,
2535}; 3361};
2536 3362
3363static struct atlas7_pad_mux pw_cko0_grp3_pad_mux[] = {
3364 MUX(1, 162, 5, N, N, N, N),
3365};
3366
3367static struct atlas7_grp_mux pw_cko0_grp3_mux = {
3368 .pad_mux_count = ARRAY_SIZE(pw_cko0_grp3_pad_mux),
3369 .pad_mux_list = pw_cko0_grp3_pad_mux,
3370};
3371
2537static struct atlas7_pad_mux pw_cko1_grp0_pad_mux[] = { 3372static struct atlas7_pad_mux pw_cko1_grp0_pad_mux[] = {
2538 MUX(1, 124, 3, N, N, N, N), 3373 MUX(1, 124, 3, N, N, N, N),
2539}; 3374};
@@ -2552,6 +3387,15 @@ static struct atlas7_grp_mux pw_cko1_grp1_mux = {
2552 .pad_mux_list = pw_cko1_grp1_pad_mux, 3387 .pad_mux_list = pw_cko1_grp1_pad_mux,
2553}; 3388};
2554 3389
3390static struct atlas7_pad_mux pw_cko1_grp2_pad_mux[] = {
3391 MUX(1, 163, 5, N, N, N, N),
3392};
3393
3394static struct atlas7_grp_mux pw_cko1_grp2_mux = {
3395 .pad_mux_count = ARRAY_SIZE(pw_cko1_grp2_pad_mux),
3396 .pad_mux_list = pw_cko1_grp2_pad_mux,
3397};
3398
2555static struct atlas7_pad_mux pw_i2s01_clk_grp0_pad_mux[] = { 3399static struct atlas7_pad_mux pw_i2s01_clk_grp0_pad_mux[] = {
2556 MUX(1, 125, 3, N, N, N, N), 3400 MUX(1, 125, 3, N, N, N, N),
2557}; 3401};
@@ -2570,22 +3414,58 @@ static struct atlas7_grp_mux pw_i2s01_clk_grp1_mux = {
2570 .pad_mux_list = pw_i2s01_clk_grp1_pad_mux, 3414 .pad_mux_list = pw_i2s01_clk_grp1_pad_mux,
2571}; 3415};
2572 3416
2573static struct atlas7_pad_mux pw_pwm0_grp_pad_mux[] = { 3417static struct atlas7_pad_mux pw_i2s01_clk_grp2_pad_mux[] = {
3418 MUX(1, 132, 2, N, N, N, N),
3419};
3420
3421static struct atlas7_grp_mux pw_i2s01_clk_grp2_mux = {
3422 .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp2_pad_mux),
3423 .pad_mux_list = pw_i2s01_clk_grp2_pad_mux,
3424};
3425
3426static struct atlas7_pad_mux pw_pwm0_grp0_pad_mux[] = {
2574 MUX(1, 119, 3, N, N, N, N), 3427 MUX(1, 119, 3, N, N, N, N),
2575}; 3428};
2576 3429
2577static struct atlas7_grp_mux pw_pwm0_grp_mux = { 3430static struct atlas7_grp_mux pw_pwm0_grp0_mux = {
2578 .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp_pad_mux), 3431 .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp0_pad_mux),
2579 .pad_mux_list = pw_pwm0_grp_pad_mux, 3432 .pad_mux_list = pw_pwm0_grp0_pad_mux,
3433};
3434
3435static struct atlas7_pad_mux pw_pwm0_grp1_pad_mux[] = {
3436 MUX(1, 159, 5, N, N, N, N),
3437};
3438
3439static struct atlas7_grp_mux pw_pwm0_grp1_mux = {
3440 .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp1_pad_mux),
3441 .pad_mux_list = pw_pwm0_grp1_pad_mux,
2580}; 3442};
2581 3443
2582static struct atlas7_pad_mux pw_pwm1_grp_pad_mux[] = { 3444static struct atlas7_pad_mux pw_pwm1_grp0_pad_mux[] = {
2583 MUX(1, 120, 3, N, N, N, N), 3445 MUX(1, 120, 3, N, N, N, N),
2584}; 3446};
2585 3447
2586static struct atlas7_grp_mux pw_pwm1_grp_mux = { 3448static struct atlas7_grp_mux pw_pwm1_grp0_mux = {
2587 .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp_pad_mux), 3449 .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp0_pad_mux),
2588 .pad_mux_list = pw_pwm1_grp_pad_mux, 3450 .pad_mux_list = pw_pwm1_grp0_pad_mux,
3451};
3452
3453static struct atlas7_pad_mux pw_pwm1_grp1_pad_mux[] = {
3454 MUX(1, 160, 5, N, N, N, N),
3455};
3456
3457static struct atlas7_grp_mux pw_pwm1_grp1_mux = {
3458 .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp1_pad_mux),
3459 .pad_mux_list = pw_pwm1_grp1_pad_mux,
3460};
3461
3462static struct atlas7_pad_mux pw_pwm1_grp2_pad_mux[] = {
3463 MUX(1, 131, 2, N, N, N, N),
3464};
3465
3466static struct atlas7_grp_mux pw_pwm1_grp2_mux = {
3467 .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp2_pad_mux),
3468 .pad_mux_list = pw_pwm1_grp2_pad_mux,
2589}; 3469};
2590 3470
2591static struct atlas7_pad_mux pw_pwm2_grp0_pad_mux[] = { 3471static struct atlas7_pad_mux pw_pwm2_grp0_pad_mux[] = {
@@ -2606,6 +3486,15 @@ static struct atlas7_grp_mux pw_pwm2_grp1_mux = {
2606 .pad_mux_list = pw_pwm2_grp1_pad_mux, 3486 .pad_mux_list = pw_pwm2_grp1_pad_mux,
2607}; 3487};
2608 3488
3489static struct atlas7_pad_mux pw_pwm2_grp2_pad_mux[] = {
3490 MUX(1, 161, 5, N, N, N, N),
3491};
3492
3493static struct atlas7_grp_mux pw_pwm2_grp2_mux = {
3494 .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp2_pad_mux),
3495 .pad_mux_list = pw_pwm2_grp2_pad_mux,
3496};
3497
2609static struct atlas7_pad_mux pw_pwm3_grp0_pad_mux[] = { 3498static struct atlas7_pad_mux pw_pwm3_grp0_pad_mux[] = {
2610 MUX(1, 122, 3, N, N, N, N), 3499 MUX(1, 122, 3, N, N, N, N),
2611}; 3500};
@@ -2642,6 +3531,15 @@ static struct atlas7_grp_mux pw_pwm_cpu_vol_grp1_mux = {
2642 .pad_mux_list = pw_pwm_cpu_vol_grp1_pad_mux, 3531 .pad_mux_list = pw_pwm_cpu_vol_grp1_pad_mux,
2643}; 3532};
2644 3533
3534static struct atlas7_pad_mux pw_pwm_cpu_vol_grp2_pad_mux[] = {
3535 MUX(1, 161, 5, N, N, N, N),
3536};
3537
3538static struct atlas7_grp_mux pw_pwm_cpu_vol_grp2_mux = {
3539 .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp2_pad_mux),
3540 .pad_mux_list = pw_pwm_cpu_vol_grp2_pad_mux,
3541};
3542
2645static struct atlas7_pad_mux pw_backlight_grp0_pad_mux[] = { 3543static struct atlas7_pad_mux pw_backlight_grp0_pad_mux[] = {
2646 MUX(1, 122, 3, N, N, N, N), 3544 MUX(1, 122, 3, N, N, N, N),
2647}; 3545};
@@ -2795,35 +3693,54 @@ static struct atlas7_grp_mux sd1_4bit_grp1_mux = {
2795 .pad_mux_list = sd1_4bit_grp1_pad_mux, 3693 .pad_mux_list = sd1_4bit_grp1_pad_mux,
2796}; 3694};
2797 3695
2798static struct atlas7_pad_mux sd2_grp0_pad_mux[] = { 3696static struct atlas7_pad_mux sd2_basic_grp_pad_mux[] = {
2799 MUX(1, 124, 2, 0xa08, 7, 0xa88, 7),
2800 MUX(1, 31, 1, N, N, N, N), 3697 MUX(1, 31, 1, N, N, N, N),
2801 MUX(1, 32, 1, N, N, N, N), 3698 MUX(1, 32, 1, N, N, N, N),
2802 MUX(1, 33, 1, N, N, N, N), 3699 MUX(1, 33, 1, N, N, N, N),
2803 MUX(1, 34, 1, N, N, N, N), 3700 MUX(1, 34, 1, N, N, N, N),
2804 MUX(1, 35, 1, N, N, N, N), 3701 MUX(1, 35, 1, N, N, N, N),
2805 MUX(1, 36, 1, N, N, N, N), 3702 MUX(1, 36, 1, N, N, N, N),
2806 MUX(1, 123, 2, N, N, N, N),
2807}; 3703};
2808 3704
2809static struct atlas7_grp_mux sd2_grp0_mux = { 3705static struct atlas7_grp_mux sd2_basic_grp_mux = {
2810 .pad_mux_count = ARRAY_SIZE(sd2_grp0_pad_mux), 3706 .pad_mux_count = ARRAY_SIZE(sd2_basic_grp_pad_mux),
2811 .pad_mux_list = sd2_grp0_pad_mux, 3707 .pad_mux_list = sd2_basic_grp_pad_mux,
2812}; 3708};
2813 3709
2814static struct atlas7_pad_mux sd2_no_cdb_grp0_pad_mux[] = { 3710static struct atlas7_pad_mux sd2_cdb_grp0_pad_mux[] = {
2815 MUX(1, 31, 1, N, N, N, N), 3711 MUX(1, 124, 2, 0xa08, 7, 0xa88, 7),
2816 MUX(1, 32, 1, N, N, N, N),
2817 MUX(1, 33, 1, N, N, N, N),
2818 MUX(1, 34, 1, N, N, N, N),
2819 MUX(1, 35, 1, N, N, N, N),
2820 MUX(1, 36, 1, N, N, N, N),
2821 MUX(1, 123, 2, N, N, N, N),
2822}; 3712};
2823 3713
2824static struct atlas7_grp_mux sd2_no_cdb_grp0_mux = { 3714static struct atlas7_grp_mux sd2_cdb_grp0_mux = {
2825 .pad_mux_count = ARRAY_SIZE(sd2_no_cdb_grp0_pad_mux), 3715 .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp0_pad_mux),
2826 .pad_mux_list = sd2_no_cdb_grp0_pad_mux, 3716 .pad_mux_list = sd2_cdb_grp0_pad_mux,
3717};
3718
3719static struct atlas7_pad_mux sd2_cdb_grp1_pad_mux[] = {
3720 MUX(1, 161, 6, 0xa08, 7, 0xa88, 7),
3721};
3722
3723static struct atlas7_grp_mux sd2_cdb_grp1_mux = {
3724 .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp1_pad_mux),
3725 .pad_mux_list = sd2_cdb_grp1_pad_mux,
3726};
3727
3728static struct atlas7_pad_mux sd2_wpb_grp0_pad_mux[] = {
3729 MUX(1, 123, 2, 0xa10, 6, 0xa90, 6),
3730};
3731
3732static struct atlas7_grp_mux sd2_wpb_grp0_mux = {
3733 .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp0_pad_mux),
3734 .pad_mux_list = sd2_wpb_grp0_pad_mux,
3735};
3736
3737static struct atlas7_pad_mux sd2_wpb_grp1_pad_mux[] = {
3738 MUX(1, 163, 7, 0xa10, 6, 0xa90, 6),
3739};
3740
3741static struct atlas7_grp_mux sd2_wpb_grp1_mux = {
3742 .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp1_pad_mux),
3743 .pad_mux_list = sd2_wpb_grp1_pad_mux,
2827}; 3744};
2828 3745
2829static struct atlas7_pad_mux sd3_grp_pad_mux[] = { 3746static struct atlas7_pad_mux sd3_grp_pad_mux[] = {
@@ -2975,146 +3892,302 @@ static struct atlas7_grp_mux uart1_grp_mux = {
2975 .pad_mux_list = uart1_grp_pad_mux, 3892 .pad_mux_list = uart1_grp_pad_mux,
2976}; 3893};
2977 3894
2978static struct atlas7_pad_mux uart2_grp_pad_mux[] = { 3895static struct atlas7_pad_mux uart2_cts_grp0_pad_mux[] = {
2979 MUX(0, 11, 2, N, N, N, N), 3896 MUX(1, 132, 3, 0xa10, 2, 0xa90, 2),
3897};
3898
3899static struct atlas7_grp_mux uart2_cts_grp0_mux = {
3900 .pad_mux_count = ARRAY_SIZE(uart2_cts_grp0_pad_mux),
3901 .pad_mux_list = uart2_cts_grp0_pad_mux,
3902};
3903
3904static struct atlas7_pad_mux uart2_cts_grp1_pad_mux[] = {
3905 MUX(1, 162, 2, 0xa10, 2, 0xa90, 2),
3906};
3907
3908static struct atlas7_grp_mux uart2_cts_grp1_mux = {
3909 .pad_mux_count = ARRAY_SIZE(uart2_cts_grp1_pad_mux),
3910 .pad_mux_list = uart2_cts_grp1_pad_mux,
3911};
3912
3913static struct atlas7_pad_mux uart2_rts_grp0_pad_mux[] = {
3914 MUX(1, 131, 3, N, N, N, N),
3915};
3916
3917static struct atlas7_grp_mux uart2_rts_grp0_mux = {
3918 .pad_mux_count = ARRAY_SIZE(uart2_rts_grp0_pad_mux),
3919 .pad_mux_list = uart2_rts_grp0_pad_mux,
3920};
3921
3922static struct atlas7_pad_mux uart2_rts_grp1_pad_mux[] = {
3923 MUX(1, 161, 2, N, N, N, N),
3924};
3925
3926static struct atlas7_grp_mux uart2_rts_grp1_mux = {
3927 .pad_mux_count = ARRAY_SIZE(uart2_rts_grp1_pad_mux),
3928 .pad_mux_list = uart2_rts_grp1_pad_mux,
3929};
3930
3931static struct atlas7_pad_mux uart2_rxd_grp0_pad_mux[] = {
3932 MUX(0, 11, 2, 0xa10, 5, 0xa90, 5),
3933};
3934
3935static struct atlas7_grp_mux uart2_rxd_grp0_mux = {
3936 .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp0_pad_mux),
3937 .pad_mux_list = uart2_rxd_grp0_pad_mux,
3938};
3939
3940static struct atlas7_pad_mux uart2_rxd_grp1_pad_mux[] = {
3941 MUX(1, 160, 2, 0xa10, 5, 0xa90, 5),
3942};
3943
3944static struct atlas7_grp_mux uart2_rxd_grp1_mux = {
3945 .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp1_pad_mux),
3946 .pad_mux_list = uart2_rxd_grp1_pad_mux,
3947};
3948
3949static struct atlas7_pad_mux uart2_rxd_grp2_pad_mux[] = {
3950 MUX(1, 130, 3, 0xa10, 5, 0xa90, 5),
3951};
3952
3953static struct atlas7_grp_mux uart2_rxd_grp2_mux = {
3954 .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp2_pad_mux),
3955 .pad_mux_list = uart2_rxd_grp2_pad_mux,
3956};
3957
3958static struct atlas7_pad_mux uart2_txd_grp0_pad_mux[] = {
2980 MUX(0, 10, 2, N, N, N, N), 3959 MUX(0, 10, 2, N, N, N, N),
2981}; 3960};
2982 3961
2983static struct atlas7_grp_mux uart2_grp_mux = { 3962static struct atlas7_grp_mux uart2_txd_grp0_mux = {
2984 .pad_mux_count = ARRAY_SIZE(uart2_grp_pad_mux), 3963 .pad_mux_count = ARRAY_SIZE(uart2_txd_grp0_pad_mux),
2985 .pad_mux_list = uart2_grp_pad_mux, 3964 .pad_mux_list = uart2_txd_grp0_pad_mux,
3965};
3966
3967static struct atlas7_pad_mux uart2_txd_grp1_pad_mux[] = {
3968 MUX(1, 159, 2, N, N, N, N),
2986}; 3969};
2987 3970
2988static struct atlas7_pad_mux uart3_grp0_pad_mux[] = { 3971static struct atlas7_grp_mux uart2_txd_grp1_mux = {
3972 .pad_mux_count = ARRAY_SIZE(uart2_txd_grp1_pad_mux),
3973 .pad_mux_list = uart2_txd_grp1_pad_mux,
3974};
3975
3976static struct atlas7_pad_mux uart2_txd_grp2_pad_mux[] = {
3977 MUX(1, 129, 3, N, N, N, N),
3978};
3979
3980static struct atlas7_grp_mux uart2_txd_grp2_mux = {
3981 .pad_mux_count = ARRAY_SIZE(uart2_txd_grp2_pad_mux),
3982 .pad_mux_list = uart2_txd_grp2_pad_mux,
3983};
3984
3985static struct atlas7_pad_mux uart3_cts_grp0_pad_mux[] = {
2989 MUX(1, 125, 2, 0xa08, 0, 0xa88, 0), 3986 MUX(1, 125, 2, 0xa08, 0, 0xa88, 0),
2990 MUX(1, 126, 2, N, N, N, N),
2991 MUX(1, 138, 1, 0xa00, 5, 0xa80, 5),
2992 MUX(1, 137, 1, N, N, N, N),
2993}; 3987};
2994 3988
2995static struct atlas7_grp_mux uart3_grp0_mux = { 3989static struct atlas7_grp_mux uart3_cts_grp0_mux = {
2996 .pad_mux_count = ARRAY_SIZE(uart3_grp0_pad_mux), 3990 .pad_mux_count = ARRAY_SIZE(uart3_cts_grp0_pad_mux),
2997 .pad_mux_list = uart3_grp0_pad_mux, 3991 .pad_mux_list = uart3_cts_grp0_pad_mux,
2998}; 3992};
2999 3993
3000static struct atlas7_pad_mux uart3_grp1_pad_mux[] = { 3994static struct atlas7_pad_mux uart3_cts_grp1_pad_mux[] = {
3001 MUX(1, 111, 4, 0xa08, 0, 0xa88, 0), 3995 MUX(1, 111, 4, 0xa08, 0, 0xa88, 0),
3002 MUX(1, 109, 4, N, N, N, N),
3003 MUX(1, 84, 2, 0xa00, 5, 0xa80, 5),
3004 MUX(1, 83, 2, N, N, N, N),
3005}; 3996};
3006 3997
3007static struct atlas7_grp_mux uart3_grp1_mux = { 3998static struct atlas7_grp_mux uart3_cts_grp1_mux = {
3008 .pad_mux_count = ARRAY_SIZE(uart3_grp1_pad_mux), 3999 .pad_mux_count = ARRAY_SIZE(uart3_cts_grp1_pad_mux),
3009 .pad_mux_list = uart3_grp1_pad_mux, 4000 .pad_mux_list = uart3_cts_grp1_pad_mux,
3010}; 4001};
3011 4002
3012static struct atlas7_pad_mux uart3_grp2_pad_mux[] = { 4003static struct atlas7_pad_mux uart3_cts_grp2_pad_mux[] = {
3013 MUX(1, 140, 2, 0xa08, 0, 0xa88, 0), 4004 MUX(1, 140, 2, 0xa08, 0, 0xa88, 0),
4005};
4006
4007static struct atlas7_grp_mux uart3_cts_grp2_mux = {
4008 .pad_mux_count = ARRAY_SIZE(uart3_cts_grp2_pad_mux),
4009 .pad_mux_list = uart3_cts_grp2_pad_mux,
4010};
4011
4012static struct atlas7_pad_mux uart3_rts_grp0_pad_mux[] = {
4013 MUX(1, 126, 2, N, N, N, N),
4014};
4015
4016static struct atlas7_grp_mux uart3_rts_grp0_mux = {
4017 .pad_mux_count = ARRAY_SIZE(uart3_rts_grp0_pad_mux),
4018 .pad_mux_list = uart3_rts_grp0_pad_mux,
4019};
4020
4021static struct atlas7_pad_mux uart3_rts_grp1_pad_mux[] = {
4022 MUX(1, 109, 4, N, N, N, N),
4023};
4024
4025static struct atlas7_grp_mux uart3_rts_grp1_mux = {
4026 .pad_mux_count = ARRAY_SIZE(uart3_rts_grp1_pad_mux),
4027 .pad_mux_list = uart3_rts_grp1_pad_mux,
4028};
4029
4030static struct atlas7_pad_mux uart3_rts_grp2_pad_mux[] = {
3014 MUX(1, 139, 2, N, N, N, N), 4031 MUX(1, 139, 2, N, N, N, N),
4032};
4033
4034static struct atlas7_grp_mux uart3_rts_grp2_mux = {
4035 .pad_mux_count = ARRAY_SIZE(uart3_rts_grp2_pad_mux),
4036 .pad_mux_list = uart3_rts_grp2_pad_mux,
4037};
4038
4039static struct atlas7_pad_mux uart3_rxd_grp0_pad_mux[] = {
3015 MUX(1, 138, 1, 0xa00, 5, 0xa80, 5), 4040 MUX(1, 138, 1, 0xa00, 5, 0xa80, 5),
3016 MUX(1, 137, 1, N, N, N, N),
3017}; 4041};
3018 4042
3019static struct atlas7_grp_mux uart3_grp2_mux = { 4043static struct atlas7_grp_mux uart3_rxd_grp0_mux = {
3020 .pad_mux_count = ARRAY_SIZE(uart3_grp2_pad_mux), 4044 .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp0_pad_mux),
3021 .pad_mux_list = uart3_grp2_pad_mux, 4045 .pad_mux_list = uart3_rxd_grp0_pad_mux,
3022}; 4046};
3023 4047
3024static struct atlas7_pad_mux uart3_grp3_pad_mux[] = { 4048static struct atlas7_pad_mux uart3_rxd_grp1_pad_mux[] = {
3025 MUX(1, 139, 2, N, N, N, N),
3026 MUX(1, 140, 2, 0xa08, 0, 0xa88, 0),
3027 MUX(1, 84, 2, 0xa00, 5, 0xa80, 5), 4049 MUX(1, 84, 2, 0xa00, 5, 0xa80, 5),
3028 MUX(1, 83, 2, N, N, N, N),
3029}; 4050};
3030 4051
3031static struct atlas7_grp_mux uart3_grp3_mux = { 4052static struct atlas7_grp_mux uart3_rxd_grp1_mux = {
3032 .pad_mux_count = ARRAY_SIZE(uart3_grp3_pad_mux), 4053 .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp1_pad_mux),
3033 .pad_mux_list = uart3_grp3_pad_mux, 4054 .pad_mux_list = uart3_rxd_grp1_pad_mux,
3034}; 4055};
3035 4056
3036static struct atlas7_pad_mux uart3_nopause_grp0_pad_mux[] = { 4057static struct atlas7_pad_mux uart3_rxd_grp2_pad_mux[] = {
3037 MUX(1, 138, 1, 0xa00, 5, 0xa80, 5), 4058 MUX(1, 162, 3, 0xa00, 5, 0xa80, 5),
4059};
4060
4061static struct atlas7_grp_mux uart3_rxd_grp2_mux = {
4062 .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp2_pad_mux),
4063 .pad_mux_list = uart3_rxd_grp2_pad_mux,
4064};
4065
4066static struct atlas7_pad_mux uart3_txd_grp0_pad_mux[] = {
3038 MUX(1, 137, 1, N, N, N, N), 4067 MUX(1, 137, 1, N, N, N, N),
3039}; 4068};
3040 4069
3041static struct atlas7_grp_mux uart3_nopause_grp0_mux = { 4070static struct atlas7_grp_mux uart3_txd_grp0_mux = {
3042 .pad_mux_count = ARRAY_SIZE(uart3_nopause_grp0_pad_mux), 4071 .pad_mux_count = ARRAY_SIZE(uart3_txd_grp0_pad_mux),
3043 .pad_mux_list = uart3_nopause_grp0_pad_mux, 4072 .pad_mux_list = uart3_txd_grp0_pad_mux,
3044}; 4073};
3045 4074
3046static struct atlas7_pad_mux uart3_nopause_grp1_pad_mux[] = { 4075static struct atlas7_pad_mux uart3_txd_grp1_pad_mux[] = {
3047 MUX(1, 84, 2, 0xa00, 5, 0xa80, 5),
3048 MUX(1, 83, 2, N, N, N, N), 4076 MUX(1, 83, 2, N, N, N, N),
3049}; 4077};
3050 4078
3051static struct atlas7_grp_mux uart3_nopause_grp1_mux = { 4079static struct atlas7_grp_mux uart3_txd_grp1_mux = {
3052 .pad_mux_count = ARRAY_SIZE(uart3_nopause_grp1_pad_mux), 4080 .pad_mux_count = ARRAY_SIZE(uart3_txd_grp1_pad_mux),
3053 .pad_mux_list = uart3_nopause_grp1_pad_mux, 4081 .pad_mux_list = uart3_txd_grp1_pad_mux,
3054}; 4082};
3055 4083
3056static struct atlas7_pad_mux uart4_grp0_pad_mux[] = { 4084static struct atlas7_pad_mux uart3_txd_grp2_pad_mux[] = {
3057 MUX(1, 122, 4, 0xa08, 1, 0xa88, 1), 4085 MUX(1, 161, 3, N, N, N, N),
3058 MUX(1, 123, 4, N, N, N, N), 4086};
4087
4088static struct atlas7_grp_mux uart3_txd_grp2_mux = {
4089 .pad_mux_count = ARRAY_SIZE(uart3_txd_grp2_pad_mux),
4090 .pad_mux_list = uart3_txd_grp2_pad_mux,
4091};
4092
4093static struct atlas7_pad_mux uart4_basic_grp_pad_mux[] = {
3059 MUX(1, 140, 1, N, N, N, N), 4094 MUX(1, 140, 1, N, N, N, N),
3060 MUX(1, 139, 1, N, N, N, N), 4095 MUX(1, 139, 1, N, N, N, N),
3061}; 4096};
3062 4097
3063static struct atlas7_grp_mux uart4_grp0_mux = { 4098static struct atlas7_grp_mux uart4_basic_grp_mux = {
3064 .pad_mux_count = ARRAY_SIZE(uart4_grp0_pad_mux), 4099 .pad_mux_count = ARRAY_SIZE(uart4_basic_grp_pad_mux),
3065 .pad_mux_list = uart4_grp0_pad_mux, 4100 .pad_mux_list = uart4_basic_grp_pad_mux,
4101};
4102
4103static struct atlas7_pad_mux uart4_cts_grp0_pad_mux[] = {
4104 MUX(1, 122, 4, 0xa08, 1, 0xa88, 1),
4105};
4106
4107static struct atlas7_grp_mux uart4_cts_grp0_mux = {
4108 .pad_mux_count = ARRAY_SIZE(uart4_cts_grp0_pad_mux),
4109 .pad_mux_list = uart4_cts_grp0_pad_mux,
3066}; 4110};
3067 4111
3068static struct atlas7_pad_mux uart4_grp1_pad_mux[] = { 4112static struct atlas7_pad_mux uart4_cts_grp1_pad_mux[] = {
3069 MUX(1, 100, 4, 0xa08, 1, 0xa88, 1), 4113 MUX(1, 100, 4, 0xa08, 1, 0xa88, 1),
3070 MUX(1, 99, 4, N, N, N, N),
3071 MUX(1, 140, 1, N, N, N, N),
3072 MUX(1, 139, 1, N, N, N, N),
3073}; 4114};
3074 4115
3075static struct atlas7_grp_mux uart4_grp1_mux = { 4116static struct atlas7_grp_mux uart4_cts_grp1_mux = {
3076 .pad_mux_count = ARRAY_SIZE(uart4_grp1_pad_mux), 4117 .pad_mux_count = ARRAY_SIZE(uart4_cts_grp1_pad_mux),
3077 .pad_mux_list = uart4_grp1_pad_mux, 4118 .pad_mux_list = uart4_cts_grp1_pad_mux,
3078}; 4119};
3079 4120
3080static struct atlas7_pad_mux uart4_grp2_pad_mux[] = { 4121static struct atlas7_pad_mux uart4_cts_grp2_pad_mux[] = {
3081 MUX(1, 117, 2, 0xa08, 1, 0xa88, 1), 4122 MUX(1, 117, 2, 0xa08, 1, 0xa88, 1),
3082 MUX(1, 116, 2, N, N, N, N),
3083 MUX(1, 140, 1, N, N, N, N),
3084 MUX(1, 139, 1, N, N, N, N),
3085}; 4123};
3086 4124
3087static struct atlas7_grp_mux uart4_grp2_mux = { 4125static struct atlas7_grp_mux uart4_cts_grp2_mux = {
3088 .pad_mux_count = ARRAY_SIZE(uart4_grp2_pad_mux), 4126 .pad_mux_count = ARRAY_SIZE(uart4_cts_grp2_pad_mux),
3089 .pad_mux_list = uart4_grp2_pad_mux, 4127 .pad_mux_list = uart4_cts_grp2_pad_mux,
3090}; 4128};
3091 4129
3092static struct atlas7_pad_mux uart4_nopause_grp_pad_mux[] = { 4130static struct atlas7_pad_mux uart4_rts_grp0_pad_mux[] = {
3093 MUX(1, 140, 1, N, N, N, N), 4131 MUX(1, 123, 4, N, N, N, N),
3094 MUX(1, 139, 1, N, N, N, N),
3095}; 4132};
3096 4133
3097static struct atlas7_grp_mux uart4_nopause_grp_mux = { 4134static struct atlas7_grp_mux uart4_rts_grp0_mux = {
3098 .pad_mux_count = ARRAY_SIZE(uart4_nopause_grp_pad_mux), 4135 .pad_mux_count = ARRAY_SIZE(uart4_rts_grp0_pad_mux),
3099 .pad_mux_list = uart4_nopause_grp_pad_mux, 4136 .pad_mux_list = uart4_rts_grp0_pad_mux,
3100}; 4137};
3101 4138
3102static struct atlas7_pad_mux usb0_drvvbus_grp_pad_mux[] = { 4139static struct atlas7_pad_mux uart4_rts_grp1_pad_mux[] = {
4140 MUX(1, 99, 4, N, N, N, N),
4141};
4142
4143static struct atlas7_grp_mux uart4_rts_grp1_mux = {
4144 .pad_mux_count = ARRAY_SIZE(uart4_rts_grp1_pad_mux),
4145 .pad_mux_list = uart4_rts_grp1_pad_mux,
4146};
4147
4148static struct atlas7_pad_mux uart4_rts_grp2_pad_mux[] = {
4149 MUX(1, 116, 2, N, N, N, N),
4150};
4151
4152static struct atlas7_grp_mux uart4_rts_grp2_mux = {
4153 .pad_mux_count = ARRAY_SIZE(uart4_rts_grp2_pad_mux),
4154 .pad_mux_list = uart4_rts_grp2_pad_mux,
4155};
4156
4157static struct atlas7_pad_mux usb0_drvvbus_grp0_pad_mux[] = {
3103 MUX(1, 51, 2, N, N, N, N), 4158 MUX(1, 51, 2, N, N, N, N),
3104}; 4159};
3105 4160
3106static struct atlas7_grp_mux usb0_drvvbus_grp_mux = { 4161static struct atlas7_grp_mux usb0_drvvbus_grp0_mux = {
3107 .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp_pad_mux), 4162 .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp0_pad_mux),
3108 .pad_mux_list = usb0_drvvbus_grp_pad_mux, 4163 .pad_mux_list = usb0_drvvbus_grp0_pad_mux,
4164};
4165
4166static struct atlas7_pad_mux usb0_drvvbus_grp1_pad_mux[] = {
4167 MUX(1, 162, 7, N, N, N, N),
3109}; 4168};
3110 4169
3111static struct atlas7_pad_mux usb1_drvvbus_grp_pad_mux[] = { 4170static struct atlas7_grp_mux usb0_drvvbus_grp1_mux = {
4171 .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp1_pad_mux),
4172 .pad_mux_list = usb0_drvvbus_grp1_pad_mux,
4173};
4174
4175static struct atlas7_pad_mux usb1_drvvbus_grp0_pad_mux[] = {
3112 MUX(1, 134, 2, N, N, N, N), 4176 MUX(1, 134, 2, N, N, N, N),
3113}; 4177};
3114 4178
3115static struct atlas7_grp_mux usb1_drvvbus_grp_mux = { 4179static struct atlas7_grp_mux usb1_drvvbus_grp0_mux = {
3116 .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp_pad_mux), 4180 .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp0_pad_mux),
3117 .pad_mux_list = usb1_drvvbus_grp_pad_mux, 4181 .pad_mux_list = usb1_drvvbus_grp0_pad_mux,
4182};
4183
4184static struct atlas7_pad_mux usb1_drvvbus_grp1_pad_mux[] = {
4185 MUX(1, 163, 2, N, N, N, N),
4186};
4187
4188static struct atlas7_grp_mux usb1_drvvbus_grp1_mux = {
4189 .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp1_pad_mux),
4190 .pad_mux_list = usb1_drvvbus_grp1_pad_mux,
3118}; 4191};
3119 4192
3120static struct atlas7_pad_mux visbus_dout_grp_pad_mux[] = { 4193static struct atlas7_pad_mux visbus_dout_grp_pad_mux[] = {
@@ -3252,11 +4325,20 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = {
3252 FUNCTION("sdio_i2s_gpio", sdio_i2s_gpio_grp, &sdio_i2s_gpio_grp_mux), 4325 FUNCTION("sdio_i2s_gpio", sdio_i2s_gpio_grp, &sdio_i2s_gpio_grp_mux),
3253 FUNCTION("sp_rgmii_gpio", sp_rgmii_gpio_grp, &sp_rgmii_gpio_grp_mux), 4326 FUNCTION("sp_rgmii_gpio", sp_rgmii_gpio_grp, &sp_rgmii_gpio_grp_mux),
3254 FUNCTION("lvds_gpio", lvds_gpio_grp, &lvds_gpio_grp_mux), 4327 FUNCTION("lvds_gpio", lvds_gpio_grp, &lvds_gpio_grp_mux),
3255 FUNCTION("uart_nand_gpio", 4328 FUNCTION("jtag_uart_nand_gpio",
3256 uart_nand_gpio_grp, 4329 jtag_uart_nand_gpio_grp,
3257 &uart_nand_gpio_grp_mux), 4330 &jtag_uart_nand_gpio_grp_mux),
3258 FUNCTION("rtc_gpio", rtc_gpio_grp, &rtc_gpio_grp_mux), 4331 FUNCTION("rtc_gpio", rtc_gpio_grp, &rtc_gpio_grp_mux),
3259 FUNCTION("audio_ac97", audio_ac97_grp, &audio_ac97_grp_mux), 4332 FUNCTION("audio_ac97", audio_ac97_grp, &audio_ac97_grp_mux),
4333 FUNCTION("audio_digmic_m0",
4334 audio_digmic_grp0,
4335 &audio_digmic_grp0_mux),
4336 FUNCTION("audio_digmic_m1",
4337 audio_digmic_grp1,
4338 &audio_digmic_grp1_mux),
4339 FUNCTION("audio_digmic_m2",
4340 audio_digmic_grp2,
4341 &audio_digmic_grp2_mux),
3260 FUNCTION("audio_func_dbg", 4342 FUNCTION("audio_func_dbg",
3261 audio_func_dbg_grp, 4343 audio_func_dbg_grp,
3262 &audio_func_dbg_grp_mux), 4344 &audio_func_dbg_grp_mux),
@@ -3265,16 +4347,119 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = {
3265 FUNCTION("audio_i2s_extclk", 4347 FUNCTION("audio_i2s_extclk",
3266 audio_i2s_extclk_grp, 4348 audio_i2s_extclk_grp,
3267 &audio_i2s_extclk_grp_mux), 4349 &audio_i2s_extclk_grp_mux),
3268 FUNCTION("audio_uart0", audio_uart0_grp, &audio_uart0_grp_mux), 4350 FUNCTION("audio_spdif_out_m0",
3269 FUNCTION("audio_uart1", audio_uart1_grp, &audio_uart1_grp_mux), 4351 audio_spdif_out_grp0,
3270 FUNCTION("audio_uart2_m0", audio_uart2_grp0, &audio_uart2_grp0_mux), 4352 &audio_spdif_out_grp0_mux),
3271 FUNCTION("audio_uart2_m1", audio_uart2_grp1, &audio_uart2_grp1_mux), 4353 FUNCTION("audio_spdif_out_m1",
3272 FUNCTION("c_can_trnsvr", c_can_trnsvr_grp, &c_can_trnsvr_grp_mux), 4354 audio_spdif_out_grp1,
3273 FUNCTION("c0_can_m0", c0_can_grp0, &c0_can_grp0_mux), 4355 &audio_spdif_out_grp1_mux),
3274 FUNCTION("c0_can_m1", c0_can_grp1, &c0_can_grp1_mux), 4356 FUNCTION("audio_spdif_out_m2",
3275 FUNCTION("c1_can_m0", c1_can_grp0, &c1_can_grp0_mux), 4357 audio_spdif_out_grp2,
3276 FUNCTION("c1_can_m1", c1_can_grp1, &c1_can_grp1_mux), 4358 &audio_spdif_out_grp2_mux),
3277 FUNCTION("c1_can_m2", c1_can_grp2, &c1_can_grp2_mux), 4359 FUNCTION("audio_uart0_basic",
4360 audio_uart0_basic_grp,
4361 &audio_uart0_basic_grp_mux),
4362 FUNCTION("audio_uart0_urfs_m0",
4363 audio_uart0_urfs_grp0,
4364 &audio_uart0_urfs_grp0_mux),
4365 FUNCTION("audio_uart0_urfs_m1",
4366 audio_uart0_urfs_grp1,
4367 &audio_uart0_urfs_grp1_mux),
4368 FUNCTION("audio_uart0_urfs_m2",
4369 audio_uart0_urfs_grp2,
4370 &audio_uart0_urfs_grp2_mux),
4371 FUNCTION("audio_uart0_urfs_m3",
4372 audio_uart0_urfs_grp3,
4373 &audio_uart0_urfs_grp3_mux),
4374 FUNCTION("audio_uart1_basic",
4375 audio_uart1_basic_grp,
4376 &audio_uart1_basic_grp_mux),
4377 FUNCTION("audio_uart1_urfs_m0",
4378 audio_uart1_urfs_grp0,
4379 &audio_uart1_urfs_grp0_mux),
4380 FUNCTION("audio_uart1_urfs_m1",
4381 audio_uart1_urfs_grp1,
4382 &audio_uart1_urfs_grp1_mux),
4383 FUNCTION("audio_uart1_urfs_m2",
4384 audio_uart1_urfs_grp2,
4385 &audio_uart1_urfs_grp2_mux),
4386 FUNCTION("audio_uart2_urfs_m0",
4387 audio_uart2_urfs_grp0,
4388 &audio_uart2_urfs_grp0_mux),
4389 FUNCTION("audio_uart2_urfs_m1",
4390 audio_uart2_urfs_grp1,
4391 &audio_uart2_urfs_grp1_mux),
4392 FUNCTION("audio_uart2_urfs_m2",
4393 audio_uart2_urfs_grp2,
4394 &audio_uart2_urfs_grp2_mux),
4395 FUNCTION("audio_uart2_urxd_m0",
4396 audio_uart2_urxd_grp0,
4397 &audio_uart2_urxd_grp0_mux),
4398 FUNCTION("audio_uart2_urxd_m1",
4399 audio_uart2_urxd_grp1,
4400 &audio_uart2_urxd_grp1_mux),
4401 FUNCTION("audio_uart2_urxd_m2",
4402 audio_uart2_urxd_grp2,
4403 &audio_uart2_urxd_grp2_mux),
4404 FUNCTION("audio_uart2_usclk_m0",
4405 audio_uart2_usclk_grp0,
4406 &audio_uart2_usclk_grp0_mux),
4407 FUNCTION("audio_uart2_usclk_m1",
4408 audio_uart2_usclk_grp1,
4409 &audio_uart2_usclk_grp1_mux),
4410 FUNCTION("audio_uart2_usclk_m2",
4411 audio_uart2_usclk_grp2,
4412 &audio_uart2_usclk_grp2_mux),
4413 FUNCTION("audio_uart2_utfs_m0",
4414 audio_uart2_utfs_grp0,
4415 &audio_uart2_utfs_grp0_mux),
4416 FUNCTION("audio_uart2_utfs_m1",
4417 audio_uart2_utfs_grp1,
4418 &audio_uart2_utfs_grp1_mux),
4419 FUNCTION("audio_uart2_utfs_m2",
4420 audio_uart2_utfs_grp2,
4421 &audio_uart2_utfs_grp2_mux),
4422 FUNCTION("audio_uart2_utxd_m0",
4423 audio_uart2_utxd_grp0,
4424 &audio_uart2_utxd_grp0_mux),
4425 FUNCTION("audio_uart2_utxd_m1",
4426 audio_uart2_utxd_grp1,
4427 &audio_uart2_utxd_grp1_mux),
4428 FUNCTION("audio_uart2_utxd_m2",
4429 audio_uart2_utxd_grp2,
4430 &audio_uart2_utxd_grp2_mux),
4431 FUNCTION("c_can_trnsvr_en_m0",
4432 c_can_trnsvr_en_grp0,
4433 &c_can_trnsvr_en_grp0_mux),
4434 FUNCTION("c_can_trnsvr_en_m1",
4435 c_can_trnsvr_en_grp1,
4436 &c_can_trnsvr_en_grp1_mux),
4437 FUNCTION("c_can_trnsvr_intr",
4438 c_can_trnsvr_intr_grp,
4439 &c_can_trnsvr_intr_grp_mux),
4440 FUNCTION("c_can_trnsvr_stb_n",
4441 c_can_trnsvr_stb_n_grp,
4442 &c_can_trnsvr_stb_n_grp_mux),
4443 FUNCTION("c0_can_rxd_trnsv0",
4444 c0_can_rxd_trnsv0_grp,
4445 &c0_can_rxd_trnsv0_grp_mux),
4446 FUNCTION("c0_can_rxd_trnsv1",
4447 c0_can_rxd_trnsv1_grp,
4448 &c0_can_rxd_trnsv1_grp_mux),
4449 FUNCTION("c0_can_txd_trnsv0",
4450 c0_can_txd_trnsv0_grp,
4451 &c0_can_txd_trnsv0_grp_mux),
4452 FUNCTION("c0_can_txd_trnsv1",
4453 c0_can_txd_trnsv1_grp,
4454 &c0_can_txd_trnsv1_grp_mux),
4455 FUNCTION("c1_can_rxd_m0", c1_can_rxd_grp0, &c1_can_rxd_grp0_mux),
4456 FUNCTION("c1_can_rxd_m1", c1_can_rxd_grp1, &c1_can_rxd_grp1_mux),
4457 FUNCTION("c1_can_rxd_m2", c1_can_rxd_grp2, &c1_can_rxd_grp2_mux),
4458 FUNCTION("c1_can_rxd_m3", c1_can_rxd_grp3, &c1_can_rxd_grp3_mux),
4459 FUNCTION("c1_can_txd_m0", c1_can_txd_grp0, &c1_can_txd_grp0_mux),
4460 FUNCTION("c1_can_txd_m1", c1_can_txd_grp1, &c1_can_txd_grp1_mux),
4461 FUNCTION("c1_can_txd_m2", c1_can_txd_grp2, &c1_can_txd_grp2_mux),
4462 FUNCTION("c1_can_txd_m3", c1_can_txd_grp3, &c1_can_txd_grp3_mux),
3278 FUNCTION("ca_audio_lpc", ca_audio_lpc_grp, &ca_audio_lpc_grp_mux), 4463 FUNCTION("ca_audio_lpc", ca_audio_lpc_grp, &ca_audio_lpc_grp_mux),
3279 FUNCTION("ca_bt_lpc", ca_bt_lpc_grp, &ca_bt_lpc_grp_mux), 4464 FUNCTION("ca_bt_lpc", ca_bt_lpc_grp, &ca_bt_lpc_grp_mux),
3280 FUNCTION("ca_coex", ca_coex_grp, &ca_coex_grp_mux), 4465 FUNCTION("ca_coex", ca_coex_grp, &ca_coex_grp_mux),
@@ -3377,7 +4562,35 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = {
3377 &gn_trg_shutdown_grp3_mux), 4562 &gn_trg_shutdown_grp3_mux),
3378 FUNCTION("i2c0", i2c0_grp, &i2c0_grp_mux), 4563 FUNCTION("i2c0", i2c0_grp, &i2c0_grp_mux),
3379 FUNCTION("i2c1", i2c1_grp, &i2c1_grp_mux), 4564 FUNCTION("i2c1", i2c1_grp, &i2c1_grp_mux),
3380 FUNCTION("jtag_m0", jtag_grp0, &jtag_grp0_mux), 4565 FUNCTION("i2s0", i2s0_grp, &i2s0_grp_mux),
4566 FUNCTION("i2s1_basic", i2s1_basic_grp, &i2s1_basic_grp_mux),
4567 FUNCTION("i2s1_rxd0_m0", i2s1_rxd0_grp0, &i2s1_rxd0_grp0_mux),
4568 FUNCTION("i2s1_rxd0_m1", i2s1_rxd0_grp1, &i2s1_rxd0_grp1_mux),
4569 FUNCTION("i2s1_rxd0_m2", i2s1_rxd0_grp2, &i2s1_rxd0_grp2_mux),
4570 FUNCTION("i2s1_rxd0_m3", i2s1_rxd0_grp3, &i2s1_rxd0_grp3_mux),
4571 FUNCTION("i2s1_rxd0_m4", i2s1_rxd0_grp4, &i2s1_rxd0_grp4_mux),
4572 FUNCTION("i2s1_rxd1_m0", i2s1_rxd1_grp0, &i2s1_rxd1_grp0_mux),
4573 FUNCTION("i2s1_rxd1_m1", i2s1_rxd1_grp1, &i2s1_rxd1_grp1_mux),
4574 FUNCTION("i2s1_rxd1_m2", i2s1_rxd1_grp2, &i2s1_rxd1_grp2_mux),
4575 FUNCTION("i2s1_rxd1_m3", i2s1_rxd1_grp3, &i2s1_rxd1_grp3_mux),
4576 FUNCTION("i2s1_rxd1_m4", i2s1_rxd1_grp4, &i2s1_rxd1_grp4_mux),
4577 FUNCTION("jtag_jt_dbg_nsrst",
4578 jtag_jt_dbg_nsrst_grp,
4579 &jtag_jt_dbg_nsrst_grp_mux),
4580 FUNCTION("jtag_ntrst_m0", jtag_ntrst_grp0, &jtag_ntrst_grp0_mux),
4581 FUNCTION("jtag_ntrst_m1", jtag_ntrst_grp1, &jtag_ntrst_grp1_mux),
4582 FUNCTION("jtag_swdiotms_m0",
4583 jtag_swdiotms_grp0,
4584 &jtag_swdiotms_grp0_mux),
4585 FUNCTION("jtag_swdiotms_m1",
4586 jtag_swdiotms_grp1,
4587 &jtag_swdiotms_grp1_mux),
4588 FUNCTION("jtag_tck_m0", jtag_tck_grp0, &jtag_tck_grp0_mux),
4589 FUNCTION("jtag_tck_m1", jtag_tck_grp1, &jtag_tck_grp1_mux),
4590 FUNCTION("jtag_tdi_m0", jtag_tdi_grp0, &jtag_tdi_grp0_mux),
4591 FUNCTION("jtag_tdi_m1", jtag_tdi_grp1, &jtag_tdi_grp1_mux),
4592 FUNCTION("jtag_tdo_m0", jtag_tdo_grp0, &jtag_tdo_grp0_mux),
4593 FUNCTION("jtag_tdo_m1", jtag_tdo_grp1, &jtag_tdo_grp1_mux),
3381 FUNCTION("ks_kas_spi_m0", ks_kas_spi_grp0, &ks_kas_spi_grp0_mux), 4594 FUNCTION("ks_kas_spi_m0", ks_kas_spi_grp0, &ks_kas_spi_grp0_mux),
3382 FUNCTION("ld_ldd", ld_ldd_grp, &ld_ldd_grp_mux), 4595 FUNCTION("ld_ldd", ld_ldd_grp, &ld_ldd_grp_mux),
3383 FUNCTION("ld_ldd_16bit", ld_ldd_16bit_grp, &ld_ldd_16bit_grp_mux), 4596 FUNCTION("ld_ldd_16bit", ld_ldd_16bit_grp, &ld_ldd_16bit_grp_mux),
@@ -3414,18 +4627,27 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = {
3414 FUNCTION("pw_cko0_m0", pw_cko0_grp0, &pw_cko0_grp0_mux), 4627 FUNCTION("pw_cko0_m0", pw_cko0_grp0, &pw_cko0_grp0_mux),
3415 FUNCTION("pw_cko0_m1", pw_cko0_grp1, &pw_cko0_grp1_mux), 4628 FUNCTION("pw_cko0_m1", pw_cko0_grp1, &pw_cko0_grp1_mux),
3416 FUNCTION("pw_cko0_m2", pw_cko0_grp2, &pw_cko0_grp2_mux), 4629 FUNCTION("pw_cko0_m2", pw_cko0_grp2, &pw_cko0_grp2_mux),
4630 FUNCTION("pw_cko0_m3", pw_cko0_grp3, &pw_cko0_grp3_mux),
3417 FUNCTION("pw_cko1_m0", pw_cko1_grp0, &pw_cko1_grp0_mux), 4631 FUNCTION("pw_cko1_m0", pw_cko1_grp0, &pw_cko1_grp0_mux),
3418 FUNCTION("pw_cko1_m1", pw_cko1_grp1, &pw_cko1_grp1_mux), 4632 FUNCTION("pw_cko1_m1", pw_cko1_grp1, &pw_cko1_grp1_mux),
4633 FUNCTION("pw_cko1_m2", pw_cko1_grp2, &pw_cko1_grp2_mux),
3419 FUNCTION("pw_i2s01_clk_m0", 4634 FUNCTION("pw_i2s01_clk_m0",
3420 pw_i2s01_clk_grp0, 4635 pw_i2s01_clk_grp0,
3421 &pw_i2s01_clk_grp0_mux), 4636 &pw_i2s01_clk_grp0_mux),
3422 FUNCTION("pw_i2s01_clk_m1", 4637 FUNCTION("pw_i2s01_clk_m1",
3423 pw_i2s01_clk_grp1, 4638 pw_i2s01_clk_grp1,
3424 &pw_i2s01_clk_grp1_mux), 4639 &pw_i2s01_clk_grp1_mux),
3425 FUNCTION("pw_pwm0", pw_pwm0_grp, &pw_pwm0_grp_mux), 4640 FUNCTION("pw_i2s01_clk_m2",
3426 FUNCTION("pw_pwm1", pw_pwm1_grp, &pw_pwm1_grp_mux), 4641 pw_i2s01_clk_grp2,
4642 &pw_i2s01_clk_grp2_mux),
4643 FUNCTION("pw_pwm0_m0", pw_pwm0_grp0, &pw_pwm0_grp0_mux),
4644 FUNCTION("pw_pwm0_m1", pw_pwm0_grp1, &pw_pwm0_grp1_mux),
4645 FUNCTION("pw_pwm1_m0", pw_pwm1_grp0, &pw_pwm1_grp0_mux),
4646 FUNCTION("pw_pwm1_m1", pw_pwm1_grp1, &pw_pwm1_grp1_mux),
4647 FUNCTION("pw_pwm1_m2", pw_pwm1_grp2, &pw_pwm1_grp2_mux),
3427 FUNCTION("pw_pwm2_m0", pw_pwm2_grp0, &pw_pwm2_grp0_mux), 4648 FUNCTION("pw_pwm2_m0", pw_pwm2_grp0, &pw_pwm2_grp0_mux),
3428 FUNCTION("pw_pwm2_m1", pw_pwm2_grp1, &pw_pwm2_grp1_mux), 4649 FUNCTION("pw_pwm2_m1", pw_pwm2_grp1, &pw_pwm2_grp1_mux),
4650 FUNCTION("pw_pwm2_m2", pw_pwm2_grp2, &pw_pwm2_grp2_mux),
3429 FUNCTION("pw_pwm3_m0", pw_pwm3_grp0, &pw_pwm3_grp0_mux), 4651 FUNCTION("pw_pwm3_m0", pw_pwm3_grp0, &pw_pwm3_grp0_mux),
3430 FUNCTION("pw_pwm3_m1", pw_pwm3_grp1, &pw_pwm3_grp1_mux), 4652 FUNCTION("pw_pwm3_m1", pw_pwm3_grp1, &pw_pwm3_grp1_mux),
3431 FUNCTION("pw_pwm_cpu_vol_m0", 4653 FUNCTION("pw_pwm_cpu_vol_m0",
@@ -3434,6 +4656,9 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = {
3434 FUNCTION("pw_pwm_cpu_vol_m1", 4656 FUNCTION("pw_pwm_cpu_vol_m1",
3435 pw_pwm_cpu_vol_grp1, 4657 pw_pwm_cpu_vol_grp1,
3436 &pw_pwm_cpu_vol_grp1_mux), 4658 &pw_pwm_cpu_vol_grp1_mux),
4659 FUNCTION("pw_pwm_cpu_vol_m2",
4660 pw_pwm_cpu_vol_grp2,
4661 &pw_pwm_cpu_vol_grp2_mux),
3437 FUNCTION("pw_backlight_m0", 4662 FUNCTION("pw_backlight_m0",
3438 pw_backlight_grp0, 4663 pw_backlight_grp0,
3439 &pw_backlight_grp0_mux), 4664 &pw_backlight_grp0_mux),
@@ -3456,8 +4681,11 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = {
3456 FUNCTION("sd1", sd1_grp, &sd1_grp_mux), 4681 FUNCTION("sd1", sd1_grp, &sd1_grp_mux),
3457 FUNCTION("sd1_4bit_m0", sd1_4bit_grp0, &sd1_4bit_grp0_mux), 4682 FUNCTION("sd1_4bit_m0", sd1_4bit_grp0, &sd1_4bit_grp0_mux),
3458 FUNCTION("sd1_4bit_m1", sd1_4bit_grp1, &sd1_4bit_grp1_mux), 4683 FUNCTION("sd1_4bit_m1", sd1_4bit_grp1, &sd1_4bit_grp1_mux),
3459 FUNCTION("sd2_m0", sd2_grp0, &sd2_grp0_mux), 4684 FUNCTION("sd2_basic", sd2_basic_grp, &sd2_basic_grp_mux),
3460 FUNCTION("sd2_no_cdb_m0", sd2_no_cdb_grp0, &sd2_no_cdb_grp0_mux), 4685 FUNCTION("sd2_cdb_m0", sd2_cdb_grp0, &sd2_cdb_grp0_mux),
4686 FUNCTION("sd2_cdb_m1", sd2_cdb_grp1, &sd2_cdb_grp1_mux),
4687 FUNCTION("sd2_wpb_m0", sd2_wpb_grp0, &sd2_wpb_grp0_mux),
4688 FUNCTION("sd2_wpb_m1", sd2_wpb_grp1, &sd2_wpb_grp1_mux),
3461 FUNCTION("sd3", sd3_grp, &sd3_grp_mux), 4689 FUNCTION("sd3", sd3_grp, &sd3_grp_mux),
3462 FUNCTION("sd5", sd5_grp, &sd5_grp_mux), 4690 FUNCTION("sd5", sd5_grp, &sd5_grp_mux),
3463 FUNCTION("sd6_m0", sd6_grp0, &sd6_grp0_mux), 4691 FUNCTION("sd6_m0", sd6_grp0, &sd6_grp0_mux),
@@ -3471,23 +4699,47 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = {
3471 FUNCTION("uart0", uart0_grp, &uart0_grp_mux), 4699 FUNCTION("uart0", uart0_grp, &uart0_grp_mux),
3472 FUNCTION("uart0_nopause", uart0_nopause_grp, &uart0_nopause_grp_mux), 4700 FUNCTION("uart0_nopause", uart0_nopause_grp, &uart0_nopause_grp_mux),
3473 FUNCTION("uart1", uart1_grp, &uart1_grp_mux), 4701 FUNCTION("uart1", uart1_grp, &uart1_grp_mux),
3474 FUNCTION("uart2", uart2_grp, &uart2_grp_mux), 4702 FUNCTION("uart2_cts_m0", uart2_cts_grp0, &uart2_cts_grp0_mux),
3475 FUNCTION("uart3_m0", uart3_grp0, &uart3_grp0_mux), 4703 FUNCTION("uart2_cts_m1", uart2_cts_grp1, &uart2_cts_grp1_mux),
3476 FUNCTION("uart3_m1", uart3_grp1, &uart3_grp1_mux), 4704 FUNCTION("uart2_rts_m0", uart2_rts_grp0, &uart2_rts_grp0_mux),
3477 FUNCTION("uart3_m2", uart3_grp2, &uart3_grp2_mux), 4705 FUNCTION("uart2_rts_m1", uart2_rts_grp1, &uart2_rts_grp1_mux),
3478 FUNCTION("uart3_m3", uart3_grp3, &uart3_grp3_mux), 4706 FUNCTION("uart2_rxd_m0", uart2_rxd_grp0, &uart2_rxd_grp0_mux),
3479 FUNCTION("uart3_nopause_m0", 4707 FUNCTION("uart2_rxd_m1", uart2_rxd_grp1, &uart2_rxd_grp1_mux),
3480 uart3_nopause_grp0, 4708 FUNCTION("uart2_rxd_m2", uart2_rxd_grp2, &uart2_rxd_grp2_mux),
3481 &uart3_nopause_grp0_mux), 4709 FUNCTION("uart2_txd_m0", uart2_txd_grp0, &uart2_txd_grp0_mux),
3482 FUNCTION("uart3_nopause_m1", 4710 FUNCTION("uart2_txd_m1", uart2_txd_grp1, &uart2_txd_grp1_mux),
3483 uart3_nopause_grp1, 4711 FUNCTION("uart2_txd_m2", uart2_txd_grp2, &uart2_txd_grp2_mux),
3484 &uart3_nopause_grp1_mux), 4712 FUNCTION("uart3_cts_m0", uart3_cts_grp0, &uart3_cts_grp0_mux),
3485 FUNCTION("uart4_m0", uart4_grp0, &uart4_grp0_mux), 4713 FUNCTION("uart3_cts_m1", uart3_cts_grp1, &uart3_cts_grp1_mux),
3486 FUNCTION("uart4_m1", uart4_grp1, &uart4_grp1_mux), 4714 FUNCTION("uart3_cts_m2", uart3_cts_grp2, &uart3_cts_grp2_mux),
3487 FUNCTION("uart4_m2", uart4_grp2, &uart4_grp2_mux), 4715 FUNCTION("uart3_rts_m0", uart3_rts_grp0, &uart3_rts_grp0_mux),
3488 FUNCTION("uart4_nopause", uart4_nopause_grp, &uart4_nopause_grp_mux), 4716 FUNCTION("uart3_rts_m1", uart3_rts_grp1, &uart3_rts_grp1_mux),
3489 FUNCTION("usb0_drvvbus", usb0_drvvbus_grp, &usb0_drvvbus_grp_mux), 4717 FUNCTION("uart3_rts_m2", uart3_rts_grp2, &uart3_rts_grp2_mux),
3490 FUNCTION("usb1_drvvbus", usb1_drvvbus_grp, &usb1_drvvbus_grp_mux), 4718 FUNCTION("uart3_rxd_m0", uart3_rxd_grp0, &uart3_rxd_grp0_mux),
4719 FUNCTION("uart3_rxd_m1", uart3_rxd_grp1, &uart3_rxd_grp1_mux),
4720 FUNCTION("uart3_rxd_m2", uart3_rxd_grp2, &uart3_rxd_grp2_mux),
4721 FUNCTION("uart3_txd_m0", uart3_txd_grp0, &uart3_txd_grp0_mux),
4722 FUNCTION("uart3_txd_m1", uart3_txd_grp1, &uart3_txd_grp1_mux),
4723 FUNCTION("uart3_txd_m2", uart3_txd_grp2, &uart3_txd_grp2_mux),
4724 FUNCTION("uart4_basic", uart4_basic_grp, &uart4_basic_grp_mux),
4725 FUNCTION("uart4_cts_m0", uart4_cts_grp0, &uart4_cts_grp0_mux),
4726 FUNCTION("uart4_cts_m1", uart4_cts_grp1, &uart4_cts_grp1_mux),
4727 FUNCTION("uart4_cts_m2", uart4_cts_grp2, &uart4_cts_grp2_mux),
4728 FUNCTION("uart4_rts_m0", uart4_rts_grp0, &uart4_rts_grp0_mux),
4729 FUNCTION("uart4_rts_m1", uart4_rts_grp1, &uart4_rts_grp1_mux),
4730 FUNCTION("uart4_rts_m2", uart4_rts_grp2, &uart4_rts_grp2_mux),
4731 FUNCTION("usb0_drvvbus_m0",
4732 usb0_drvvbus_grp0,
4733 &usb0_drvvbus_grp0_mux),
4734 FUNCTION("usb0_drvvbus_m1",
4735 usb0_drvvbus_grp1,
4736 &usb0_drvvbus_grp1_mux),
4737 FUNCTION("usb1_drvvbus_m0",
4738 usb1_drvvbus_grp0,
4739 &usb1_drvvbus_grp0_mux),
4740 FUNCTION("usb1_drvvbus_m1",
4741 usb1_drvvbus_grp1,
4742 &usb1_drvvbus_grp1_mux),
3491 FUNCTION("visbus_dout", visbus_dout_grp, &visbus_dout_grp_mux), 4743 FUNCTION("visbus_dout", visbus_dout_grp, &visbus_dout_grp_mux),
3492 FUNCTION("vi_vip1", vi_vip1_grp, &vi_vip1_grp_mux), 4744 FUNCTION("vi_vip1", vi_vip1_grp, &vi_vip1_grp_mux),
3493 FUNCTION("vi_vip1_ext", vi_vip1_ext_grp, &vi_vip1_ext_grp_mux), 4745 FUNCTION("vi_vip1_ext", vi_vip1_ext_grp, &vi_vip1_ext_grp_mux),
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index ae27872ff3a6..e68fd951129a 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -42,6 +42,10 @@ config PINCTRL_SUN8I_A33
42 def_bool MACH_SUN8I 42 def_bool MACH_SUN8I
43 select PINCTRL_SUNXI_COMMON 43 select PINCTRL_SUNXI_COMMON
44 44
45config PINCTRL_SUN8I_A83T
46 def_bool MACH_SUN8I
47 select PINCTRL_SUNXI_COMMON
48
45config PINCTRL_SUN8I_A23_R 49config PINCTRL_SUN8I_A23_R
46 def_bool MACH_SUN8I 50 def_bool MACH_SUN8I
47 depends on RESET_CONTROLLER 51 depends on RESET_CONTROLLER
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 227a1213947c..e08029034510 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -12,4 +12,5 @@ obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
12obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o 12obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
13obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o 13obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
14obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o 14obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o
15obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o
15obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o 16obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
index 9596b0a3df6b..d4bc4f0e8be0 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
@@ -47,45 +47,57 @@ static const struct sunxi_desc_pin sun6i_a31_r_pins[] = {
47 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5), 47 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
48 SUNXI_FUNCTION(0x0, "gpio_in"), 48 SUNXI_FUNCTION(0x0, "gpio_in"),
49 SUNXI_FUNCTION(0x1, "gpio_out"), 49 SUNXI_FUNCTION(0x1, "gpio_out"),
50 SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 0), /* PL_EINT0 */
50 SUNXI_FUNCTION(0x3, "s_jtag")), /* MS */ 51 SUNXI_FUNCTION(0x3, "s_jtag")), /* MS */
51 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6), 52 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
52 SUNXI_FUNCTION(0x0, "gpio_in"), 53 SUNXI_FUNCTION(0x0, "gpio_in"),
53 SUNXI_FUNCTION(0x1, "gpio_out"), 54 SUNXI_FUNCTION(0x1, "gpio_out"),
55 SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 1), /* PL_EINT1 */
54 SUNXI_FUNCTION(0x3, "s_jtag")), /* CK */ 56 SUNXI_FUNCTION(0x3, "s_jtag")), /* CK */
55 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7), 57 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
56 SUNXI_FUNCTION(0x0, "gpio_in"), 58 SUNXI_FUNCTION(0x0, "gpio_in"),
57 SUNXI_FUNCTION(0x1, "gpio_out"), 59 SUNXI_FUNCTION(0x1, "gpio_out"),
60 SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 2), /* PL_EINT2 */
58 SUNXI_FUNCTION(0x3, "s_jtag")), /* DO */ 61 SUNXI_FUNCTION(0x3, "s_jtag")), /* DO */
59 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8), 62 SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
60 SUNXI_FUNCTION(0x0, "gpio_in"), 63 SUNXI_FUNCTION(0x0, "gpio_in"),
61 SUNXI_FUNCTION(0x1, "gpio_out"), 64 SUNXI_FUNCTION(0x1, "gpio_out"),
65 SUNXI_FUNCTION_IRQ_BANK(0x2, 0, 3), /* PL_EINT3 */
62 SUNXI_FUNCTION(0x3, "s_jtag")), /* DI */ 66 SUNXI_FUNCTION(0x3, "s_jtag")), /* DI */
63 /* Hole */ 67 /* Hole */
64 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0), 68 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
65 SUNXI_FUNCTION(0x0, "gpio_in"), 69 SUNXI_FUNCTION(0x0, "gpio_in"),
66 SUNXI_FUNCTION(0x1, "gpio_out")), 70 SUNXI_FUNCTION(0x1, "gpio_out"),
71 SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 0)), /* PM_EINT0 */
67 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1), 72 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
68 SUNXI_FUNCTION(0x0, "gpio_in"), 73 SUNXI_FUNCTION(0x0, "gpio_in"),
69 SUNXI_FUNCTION(0x1, "gpio_out")), 74 SUNXI_FUNCTION(0x1, "gpio_out"),
75 SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 1)), /* PM_EINT1 */
70 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2), 76 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
71 SUNXI_FUNCTION(0x0, "gpio_in"), 77 SUNXI_FUNCTION(0x0, "gpio_in"),
72 SUNXI_FUNCTION(0x1, "gpio_out"), 78 SUNXI_FUNCTION(0x1, "gpio_out"),
79 SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 2), /* PM_EINT2 */
73 SUNXI_FUNCTION(0x3, "1wire")), 80 SUNXI_FUNCTION(0x3, "1wire")),
74 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3), 81 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
75 SUNXI_FUNCTION(0x0, "gpio_in"), 82 SUNXI_FUNCTION(0x0, "gpio_in"),
76 SUNXI_FUNCTION(0x1, "gpio_out")), 83 SUNXI_FUNCTION(0x1, "gpio_out"),
84 SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 3)), /* PM_EINT3 */
77 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4), 85 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
78 SUNXI_FUNCTION(0x0, "gpio_in"), 86 SUNXI_FUNCTION(0x0, "gpio_in"),
79 SUNXI_FUNCTION(0x1, "gpio_out")), 87 SUNXI_FUNCTION(0x1, "gpio_out"),
88 SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 4)), /* PM_EINT4 */
80 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 5), 89 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 5),
81 SUNXI_FUNCTION(0x0, "gpio_in"), 90 SUNXI_FUNCTION(0x0, "gpio_in"),
82 SUNXI_FUNCTION(0x1, "gpio_out")), 91 SUNXI_FUNCTION(0x1, "gpio_out"),
92 SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 5)), /* PM_EINT5 */
83 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 6), 93 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 6),
84 SUNXI_FUNCTION(0x0, "gpio_in"), 94 SUNXI_FUNCTION(0x0, "gpio_in"),
85 SUNXI_FUNCTION(0x1, "gpio_out")), 95 SUNXI_FUNCTION(0x1, "gpio_out"),
96 SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 6)), /* PM_EINT6 */
86 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 7), 97 SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 7),
87 SUNXI_FUNCTION(0x0, "gpio_in"), 98 SUNXI_FUNCTION(0x0, "gpio_in"),
88 SUNXI_FUNCTION(0x1, "gpio_out"), 99 SUNXI_FUNCTION(0x1, "gpio_out"),
100 SUNXI_FUNCTION_IRQ_BANK(0x2, 1, 7), /* PM_EINT7 */
89 SUNXI_FUNCTION(0x3, "rtc")), /* CLKO */ 101 SUNXI_FUNCTION(0x3, "rtc")), /* CLKO */
90}; 102};
91 103
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
new file mode 100644
index 000000000000..90b973e15982
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
@@ -0,0 +1,603 @@
1/*
2 * Allwinner a83t SoCs pinctrl driver.
3 *
4 * Copyright (C) 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
5 *
6 * Based on pinctrl-sun8i-a23.c, which is:
7 * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
8 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/of.h>
18#include <linux/of_device.h>
19#include <linux/pinctrl/pinctrl.h>
20
21#include "pinctrl-sunxi.h"
22
23static const struct sunxi_desc_pin sun8i_a83t_pins[] = {
24 /* Hole */
25 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
26 SUNXI_FUNCTION(0x0, "gpio_in"),
27 SUNXI_FUNCTION(0x1, "gpio_out"),
28 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
29 SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
30 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */
31 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
32 SUNXI_FUNCTION(0x0, "gpio_in"),
33 SUNXI_FUNCTION(0x1, "gpio_out"),
34 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
35 SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
36 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PB_EINT1 */
37 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
38 SUNXI_FUNCTION(0x0, "gpio_in"),
39 SUNXI_FUNCTION(0x1, "gpio_out"),
40 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
41 SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
42 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PB_EINT2 */
43 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
44 SUNXI_FUNCTION(0x0, "gpio_in"),
45 SUNXI_FUNCTION(0x1, "gpio_out"),
46 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
47 SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
48 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PB_EINT3 */
49 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
50 SUNXI_FUNCTION(0x0, "gpio_in"),
51 SUNXI_FUNCTION(0x1, "gpio_out"),
52 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
53 SUNXI_FUNCTION(0x3, "tdm"), /* LRCK */
54 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PB_EINT4 */
55 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
56 SUNXI_FUNCTION(0x0, "gpio_in"),
57 SUNXI_FUNCTION(0x1, "gpio_out"),
58 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
59 SUNXI_FUNCTION(0x3, "tdm"), /* BCLK */
60 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PB_EINT5 */
61 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
62 SUNXI_FUNCTION(0x0, "gpio_in"),
63 SUNXI_FUNCTION(0x1, "gpio_out"),
64 SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
65 SUNXI_FUNCTION(0x3, "tdm"), /* DOUT */
66 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PB_EINT6 */
67 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
68 SUNXI_FUNCTION(0x0, "gpio_in"),
69 SUNXI_FUNCTION(0x1, "gpio_out"),
70 SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
71 SUNXI_FUNCTION(0x3, "tdm"), /* DIN */
72 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PB_EINT7 */
73 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
74 SUNXI_FUNCTION(0x0, "gpio_in"),
75 SUNXI_FUNCTION(0x1, "gpio_out"),
76 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
77 SUNXI_FUNCTION(0x3, "tdm"), /* MCLK */
78 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PB_EINT8 */
79 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
80 SUNXI_FUNCTION(0x0, "gpio_in"),
81 SUNXI_FUNCTION(0x1, "gpio_out"),
82 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
83 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PB_EINT9 */
84 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
85 SUNXI_FUNCTION(0x0, "gpio_in"),
86 SUNXI_FUNCTION(0x1, "gpio_out"),
87 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
88 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PB_EINT10 */
89 /* Hole */
90 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
91 SUNXI_FUNCTION(0x0, "gpio_in"),
92 SUNXI_FUNCTION(0x1, "gpio_out"),
93 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
94 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
95 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
96 SUNXI_FUNCTION(0x0, "gpio_in"),
97 SUNXI_FUNCTION(0x1, "gpio_out"),
98 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
99 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
100 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
101 SUNXI_FUNCTION(0x0, "gpio_in"),
102 SUNXI_FUNCTION(0x1, "gpio_out"),
103 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
104 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
105 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
106 SUNXI_FUNCTION(0x0, "gpio_in"),
107 SUNXI_FUNCTION(0x1, "gpio_out"),
108 SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
109 SUNXI_FUNCTION(0x3, "spi0")), /* CS */
110 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
111 SUNXI_FUNCTION(0x0, "gpio_in"),
112 SUNXI_FUNCTION(0x1, "gpio_out"),
113 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
114 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
115 SUNXI_FUNCTION(0x0, "gpio_in"),
116 SUNXI_FUNCTION(0x1, "gpio_out"),
117 SUNXI_FUNCTION(0x2, "nand0"), /* RE */
118 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
119 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
120 SUNXI_FUNCTION(0x0, "gpio_in"),
121 SUNXI_FUNCTION(0x1, "gpio_out"),
122 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
123 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
124 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
125 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out"),
127 SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
128 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
129 SUNXI_FUNCTION(0x0, "gpio_in"),
130 SUNXI_FUNCTION(0x1, "gpio_out"),
131 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
132 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
133 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
134 SUNXI_FUNCTION(0x0, "gpio_in"),
135 SUNXI_FUNCTION(0x1, "gpio_out"),
136 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
137 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
138 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
139 SUNXI_FUNCTION(0x0, "gpio_in"),
140 SUNXI_FUNCTION(0x1, "gpio_out"),
141 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
142 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
143 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
144 SUNXI_FUNCTION(0x0, "gpio_in"),
145 SUNXI_FUNCTION(0x1, "gpio_out"),
146 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
147 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
148 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
149 SUNXI_FUNCTION(0x0, "gpio_in"),
150 SUNXI_FUNCTION(0x1, "gpio_out"),
151 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
152 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
153 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
154 SUNXI_FUNCTION(0x0, "gpio_in"),
155 SUNXI_FUNCTION(0x1, "gpio_out"),
156 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
157 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
158 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
159 SUNXI_FUNCTION(0x0, "gpio_in"),
160 SUNXI_FUNCTION(0x1, "gpio_out"),
161 SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */
162 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
163 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
164 SUNXI_FUNCTION(0x0, "gpio_in"),
165 SUNXI_FUNCTION(0x1, "gpio_out"),
166 SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */
167 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
168 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
169 SUNXI_FUNCTION(0x0, "gpio_in"),
170 SUNXI_FUNCTION(0x1, "gpio_out"),
171 SUNXI_FUNCTION(0x2, "nand"), /* DQS */
172 SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
173 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
174 SUNXI_FUNCTION(0x0, "gpio_in"),
175 SUNXI_FUNCTION(0x1, "gpio_out"),
176 SUNXI_FUNCTION(0x2, "nand")), /* CE2 */
177 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
178 SUNXI_FUNCTION(0x0, "gpio_in"),
179 SUNXI_FUNCTION(0x1, "gpio_out"),
180 SUNXI_FUNCTION(0x2, "nand")), /* CE3 */
181 /* Hole */
182 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
183 SUNXI_FUNCTION(0x0, "gpio_in"),
184 SUNXI_FUNCTION(0x1, "gpio_out"),
185 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
186 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD3 */
187 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
188 SUNXI_FUNCTION(0x0, "gpio_in"),
189 SUNXI_FUNCTION(0x1, "gpio_out"),
190 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
191 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD2 */
192 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
193 SUNXI_FUNCTION(0x0, "gpio_in"),
194 SUNXI_FUNCTION(0x1, "gpio_out"),
195 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
196 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD1 */
197 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
198 SUNXI_FUNCTION(0x0, "gpio_in"),
199 SUNXI_FUNCTION(0x1, "gpio_out"),
200 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
201 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXD0 */
202 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
203 SUNXI_FUNCTION(0x0, "gpio_in"),
204 SUNXI_FUNCTION(0x1, "gpio_out"),
205 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
206 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXCK */
207 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
208 SUNXI_FUNCTION(0x0, "gpio_in"),
209 SUNXI_FUNCTION(0x1, "gpio_out"),
210 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
211 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXDV */
212 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
213 SUNXI_FUNCTION(0x0, "gpio_in"),
214 SUNXI_FUNCTION(0x1, "gpio_out"),
215 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
216 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII RXERR */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
218 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
221 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD3 */
222 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
223 SUNXI_FUNCTION(0x0, "gpio_in"),
224 SUNXI_FUNCTION(0x1, "gpio_out"),
225 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
226 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD2 */
227 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
228 SUNXI_FUNCTION(0x0, "gpio_in"),
229 SUNXI_FUNCTION(0x1, "gpio_out"),
230 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
231 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD1 */
232 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
233 SUNXI_FUNCTION(0x0, "gpio_in"),
234 SUNXI_FUNCTION(0x1, "gpio_out"),
235 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
236 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII / MII TXD0 */
237 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
238 SUNXI_FUNCTION(0x0, "gpio_in"),
239 SUNXI_FUNCTION(0x1, "gpio_out"),
240 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
241 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII-NULL / MII-CRS */
242 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
243 SUNXI_FUNCTION(0x0, "gpio_in"),
244 SUNXI_FUNCTION(0x1, "gpio_out"),
245 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
246 SUNXI_FUNCTION(0x3, "lvds0"), /* VP0 */
247 SUNXI_FUNCTION(0x4, "gmac")), /* GTXCK / ETXCK */
248 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
249 SUNXI_FUNCTION(0x0, "gpio_in"),
250 SUNXI_FUNCTION(0x1, "gpio_out"),
251 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
252 SUNXI_FUNCTION(0x3, "lvds0"), /* VN0 */
253 SUNXI_FUNCTION(0x4, "gmac")), /* GTXCTL / ETXEL */
254 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
255 SUNXI_FUNCTION(0x0, "gpio_in"),
256 SUNXI_FUNCTION(0x1, "gpio_out"),
257 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
258 SUNXI_FUNCTION(0x3, "lvds0"), /* VP1 */
259 SUNXI_FUNCTION(0x4, "gmac")), /* GNULL / ETXERR */
260 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
261 SUNXI_FUNCTION(0x0, "gpio_in"),
262 SUNXI_FUNCTION(0x1, "gpio_out"),
263 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
264 SUNXI_FUNCTION(0x3, "lvds0"), /* VN1 */
265 SUNXI_FUNCTION(0x4, "gmac")), /* GCLKIN / ECOL */
266 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
267 SUNXI_FUNCTION(0x0, "gpio_in"),
268 SUNXI_FUNCTION(0x1, "gpio_out"),
269 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
270 SUNXI_FUNCTION(0x3, "lvds0"), /* VP2 */
271 SUNXI_FUNCTION(0x4, "gmac")), /* GMDC */
272 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
273 SUNXI_FUNCTION(0x0, "gpio_in"),
274 SUNXI_FUNCTION(0x1, "gpio_out"),
275 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
276 SUNXI_FUNCTION(0x3, "lvds0"), /* VN2 */
277 SUNXI_FUNCTION(0x4, "gmac")), /* GMDIO */
278 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
279 SUNXI_FUNCTION(0x0, "gpio_in"),
280 SUNXI_FUNCTION(0x1, "gpio_out"),
281 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
282 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
283 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
284 SUNXI_FUNCTION(0x0, "gpio_in"),
285 SUNXI_FUNCTION(0x1, "gpio_out"),
286 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
287 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
288 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
289 SUNXI_FUNCTION(0x0, "gpio_in"),
290 SUNXI_FUNCTION(0x1, "gpio_out"),
291 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
292 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
293 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
294 SUNXI_FUNCTION(0x0, "gpio_in"),
295 SUNXI_FUNCTION(0x1, "gpio_out"),
296 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
297 SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
298 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28),
299 SUNXI_FUNCTION(0x0, "gpio_in"),
300 SUNXI_FUNCTION(0x1, "gpio_out"),
301 SUNXI_FUNCTION(0x2, "pwm")), /* PWM */
302 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 29),
303 SUNXI_FUNCTION(0x0, "gpio_in"),
304 SUNXI_FUNCTION(0x1, "gpio_out")),
305 /* Hole */
306 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
307 SUNXI_FUNCTION(0x0, "gpio_in"),
308 SUNXI_FUNCTION(0x1, "gpio_out"),
309 SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
310 SUNXI_FUNCTION(0x4, "ccir")), /* CLK */
311 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
312 SUNXI_FUNCTION(0x0, "gpio_in"),
313 SUNXI_FUNCTION(0x1, "gpio_out"),
314 SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
315 SUNXI_FUNCTION(0x4, "ccir")), /* DE */
316 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
317 SUNXI_FUNCTION(0x0, "gpio_in"),
318 SUNXI_FUNCTION(0x1, "gpio_out"),
319 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
320 SUNXI_FUNCTION(0x4, "ccir")), /* HSYNC */
321 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
322 SUNXI_FUNCTION(0x0, "gpio_in"),
323 SUNXI_FUNCTION(0x1, "gpio_out"),
324 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
325 SUNXI_FUNCTION(0x4, "ccir")), /* VSYNC */
326 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
327 SUNXI_FUNCTION(0x0, "gpio_in"),
328 SUNXI_FUNCTION(0x1, "gpio_out"),
329 SUNXI_FUNCTION(0x2, "csi")), /* D0 */
330 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
331 SUNXI_FUNCTION(0x0, "gpio_in"),
332 SUNXI_FUNCTION(0x1, "gpio_out"),
333 SUNXI_FUNCTION(0x2, "csi")), /* D1 */
334 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
335 SUNXI_FUNCTION(0x0, "gpio_in"),
336 SUNXI_FUNCTION(0x1, "gpio_out"),
337 SUNXI_FUNCTION(0x2, "csi"), /* D2 */
338 SUNXI_FUNCTION(0x4, "ccir")), /* D0 */
339 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
340 SUNXI_FUNCTION(0x0, "gpio_in"),
341 SUNXI_FUNCTION(0x1, "gpio_out"),
342 SUNXI_FUNCTION(0x2, "csi"), /* D3 */
343 SUNXI_FUNCTION(0x4, "ccir")), /* D1 */
344 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
345 SUNXI_FUNCTION(0x0, "gpio_in"),
346 SUNXI_FUNCTION(0x1, "gpio_out"),
347 SUNXI_FUNCTION(0x2, "csi"), /* D4 */
348 SUNXI_FUNCTION(0x4, "ccir")), /* D2 */
349 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
350 SUNXI_FUNCTION(0x0, "gpio_in"),
351 SUNXI_FUNCTION(0x1, "gpio_out"),
352 SUNXI_FUNCTION(0x2, "csi"), /* D5 */
353 SUNXI_FUNCTION(0x4, "ccir")), /* D3 */
354 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
355 SUNXI_FUNCTION(0x0, "gpio_in"),
356 SUNXI_FUNCTION(0x1, "gpio_out"),
357 SUNXI_FUNCTION(0x2, "csi"), /* D6 */
358 SUNXI_FUNCTION(0x3, "uart4"), /* TX */
359 SUNXI_FUNCTION(0x4, "ccir")), /* D4 */
360 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
361 SUNXI_FUNCTION(0x0, "gpio_in"),
362 SUNXI_FUNCTION(0x1, "gpio_out"),
363 SUNXI_FUNCTION(0x2, "csi"), /* D7 */
364 SUNXI_FUNCTION(0x3, "uart4"), /* RX */
365 SUNXI_FUNCTION(0x4, "ccir")), /* D5 */
366 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
367 SUNXI_FUNCTION(0x0, "gpio_in"),
368 SUNXI_FUNCTION(0x1, "gpio_out"),
369 SUNXI_FUNCTION(0x2, "csi"), /* D8 */
370 SUNXI_FUNCTION(0x3, "uart4"), /* RTS */
371 SUNXI_FUNCTION(0x4, "ccir")), /* D6 */
372 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
373 SUNXI_FUNCTION(0x0, "gpio_in"),
374 SUNXI_FUNCTION(0x1, "gpio_out"),
375 SUNXI_FUNCTION(0x2, "csi"), /* D9 */
376 SUNXI_FUNCTION(0x3, "uart4"), /* CTS */
377 SUNXI_FUNCTION(0x4, "ccir")), /* D7 */
378 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
379 SUNXI_FUNCTION(0x0, "gpio_in"),
380 SUNXI_FUNCTION(0x1, "gpio_out"),
381 SUNXI_FUNCTION(0x2, "csi"), /* SCK */
382 SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
383 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
384 SUNXI_FUNCTION(0x0, "gpio_in"),
385 SUNXI_FUNCTION(0x1, "gpio_out"),
386 SUNXI_FUNCTION(0x2, "csi"), /* SDA */
387 SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
388 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
389 SUNXI_FUNCTION(0x0, "gpio_in"),
390 SUNXI_FUNCTION(0x1, "gpio_out")),
391 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
392 SUNXI_FUNCTION(0x0, "gpio_in"),
393 SUNXI_FUNCTION(0x1, "gpio_out")),
394 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18),
395 SUNXI_FUNCTION(0x0, "gpio_in"),
396 SUNXI_FUNCTION(0x1, "gpio_out"),
397 SUNXI_FUNCTION(0x3, "owa")), /* DOUT */
398 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19),
399 SUNXI_FUNCTION(0x0, "gpio_in"),
400 SUNXI_FUNCTION(0x1, "gpio_out")),
401 /* Hole */
402 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
403 SUNXI_FUNCTION(0x0, "gpio_in"),
404 SUNXI_FUNCTION(0x1, "gpio_out"),
405 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
406 SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */
407 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
408 SUNXI_FUNCTION(0x0, "gpio_in"),
409 SUNXI_FUNCTION(0x1, "gpio_out"),
410 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
411 SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */
412 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
413 SUNXI_FUNCTION(0x0, "gpio_in"),
414 SUNXI_FUNCTION(0x1, "gpio_out"),
415 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
416 SUNXI_FUNCTION(0x3, "uart0")), /* TX */
417 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
418 SUNXI_FUNCTION(0x0, "gpio_in"),
419 SUNXI_FUNCTION(0x1, "gpio_out"),
420 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
421 SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */
422 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
423 SUNXI_FUNCTION(0x0, "gpio_in"),
424 SUNXI_FUNCTION(0x1, "gpio_out"),
425 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
426 SUNXI_FUNCTION(0x3, "uart0")), /* RX */
427 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
428 SUNXI_FUNCTION(0x0, "gpio_in"),
429 SUNXI_FUNCTION(0x1, "gpio_out"),
430 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
431 SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */
432 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
433 SUNXI_FUNCTION(0x0, "gpio_in"),
434 SUNXI_FUNCTION(0x1, "gpio_out")),
435 /* Hole */
436 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
437 SUNXI_FUNCTION(0x0, "gpio_in"),
438 SUNXI_FUNCTION(0x1, "gpio_out"),
439 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
440 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PG_EINT0 */
441 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
442 SUNXI_FUNCTION(0x0, "gpio_in"),
443 SUNXI_FUNCTION(0x1, "gpio_out"),
444 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
445 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PG_EINT1 */
446 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
447 SUNXI_FUNCTION(0x0, "gpio_in"),
448 SUNXI_FUNCTION(0x1, "gpio_out"),
449 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
450 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PG_EINT2 */
451 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
452 SUNXI_FUNCTION(0x0, "gpio_in"),
453 SUNXI_FUNCTION(0x1, "gpio_out"),
454 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
455 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PG_EINT3 */
456 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
457 SUNXI_FUNCTION(0x0, "gpio_in"),
458 SUNXI_FUNCTION(0x1, "gpio_out"),
459 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
460 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PG_EINT4 */
461 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
462 SUNXI_FUNCTION(0x0, "gpio_in"),
463 SUNXI_FUNCTION(0x1, "gpio_out"),
464 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
465 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */
466 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
467 SUNXI_FUNCTION(0x0, "gpio_in"),
468 SUNXI_FUNCTION(0x1, "gpio_out"),
469 SUNXI_FUNCTION(0x2, "uart1"), /* TX */
470 SUNXI_FUNCTION(0x3, "spi1"), /* CS */
471 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */
472 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
473 SUNXI_FUNCTION(0x0, "gpio_in"),
474 SUNXI_FUNCTION(0x1, "gpio_out"),
475 SUNXI_FUNCTION(0x2, "uart1"), /* RX */
476 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
477 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */
478 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
479 SUNXI_FUNCTION(0x0, "gpio_in"),
480 SUNXI_FUNCTION(0x1, "gpio_out"),
481 SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
482 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
483 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */
484 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
485 SUNXI_FUNCTION(0x0, "gpio_in"),
486 SUNXI_FUNCTION(0x1, "gpio_out"),
487 SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
488 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
489 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */
490 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
491 SUNXI_FUNCTION(0x0, "gpio_in"),
492 SUNXI_FUNCTION(0x1, "gpio_out"),
493 SUNXI_FUNCTION(0x2, "i2s1"), /* BCLK */
494 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
495 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */
496 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
497 SUNXI_FUNCTION(0x0, "gpio_in"),
498 SUNXI_FUNCTION(0x1, "gpio_out"),
499 SUNXI_FUNCTION(0x2, "i2s1"), /* LRCK */
500 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
501 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */
502 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
503 SUNXI_FUNCTION(0x0, "gpio_in"),
504 SUNXI_FUNCTION(0x1, "gpio_out"),
505 SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
506 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
507 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */
508 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
509 SUNXI_FUNCTION(0x0, "gpio_in"),
510 SUNXI_FUNCTION(0x1, "gpio_out"),
511 SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
512 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
513 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */
514 /* Hole */
515 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
516 SUNXI_FUNCTION(0x0, "gpio_in"),
517 SUNXI_FUNCTION(0x1, "gpio_out"),
518 SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
519 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PH_EINT0 */
520 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
521 SUNXI_FUNCTION(0x0, "gpio_in"),
522 SUNXI_FUNCTION(0x1, "gpio_out"),
523 SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
524 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PH_EINT1 */
525 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
526 SUNXI_FUNCTION(0x0, "gpio_in"),
527 SUNXI_FUNCTION(0x1, "gpio_out"),
528 SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */
529 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PH_EINT2 */
530 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
531 SUNXI_FUNCTION(0x0, "gpio_in"),
532 SUNXI_FUNCTION(0x1, "gpio_out"),
533 SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */
534 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PH_EINT3 */
535 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
536 SUNXI_FUNCTION(0x0, "gpio_in"),
537 SUNXI_FUNCTION(0x1, "gpio_out"),
538 SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */
539 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PH_EINT4 */
540 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
541 SUNXI_FUNCTION(0x0, "gpio_in"),
542 SUNXI_FUNCTION(0x1, "gpio_out"),
543 SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */
544 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PH_EINT5 */
545 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
546 SUNXI_FUNCTION(0x0, "gpio_in"),
547 SUNXI_FUNCTION(0x1, "gpio_out"),
548 SUNXI_FUNCTION(0x2, "hdmi"), /* HSCL */
549 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PH_EINT6 */
550 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
551 SUNXI_FUNCTION(0x0, "gpio_in"),
552 SUNXI_FUNCTION(0x1, "gpio_out"),
553 SUNXI_FUNCTION(0x2, "hdmi"), /* HSDA */
554 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PH_EINT7 */
555 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
556 SUNXI_FUNCTION(0x0, "gpio_in"),
557 SUNXI_FUNCTION(0x1, "gpio_out"),
558 SUNXI_FUNCTION(0x2, "hdmi"), /* HCEC */
559 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PH_EINT8 */
560 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
561 SUNXI_FUNCTION(0x0, "gpio_in"),
562 SUNXI_FUNCTION(0x1, "gpio_out"),
563 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PH_EINT9 */
564 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
565 SUNXI_FUNCTION(0x0, "gpio_in"),
566 SUNXI_FUNCTION(0x1, "gpio_out"),
567 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PH_EINT10 */
568 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
569 SUNXI_FUNCTION(0x0, "gpio_in"),
570 SUNXI_FUNCTION(0x1, "gpio_out"),
571 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PH_EINT11 */
572};
573
574static const struct sunxi_pinctrl_desc sun8i_a83t_pinctrl_data = {
575 .pins = sun8i_a83t_pins,
576 .npins = ARRAY_SIZE(sun8i_a83t_pins),
577 .irq_banks = 3,
578};
579
580static int sun8i_a83t_pinctrl_probe(struct platform_device *pdev)
581{
582 return sunxi_pinctrl_init(pdev,
583 &sun8i_a83t_pinctrl_data);
584}
585
586static const struct of_device_id sun8i_a83t_pinctrl_match[] = {
587 { .compatible = "allwinner,sun8i-a83t-pinctrl", },
588 {}
589};
590MODULE_DEVICE_TABLE(of, sun8i_a83t_pinctrl_match);
591
592static struct platform_driver sun8i_a83t_pinctrl_driver = {
593 .probe = sun8i_a83t_pinctrl_probe,
594 .driver = {
595 .name = "sun8i-a83t-pinctrl",
596 .of_match_table = sun8i_a83t_pinctrl_match,
597 },
598};
599module_platform_driver(sun8i_a83t_pinctrl_driver);
600
601MODULE_AUTHOR("Vishnu Patekar <vishnupatekar0510@gmail.com>");
602MODULE_DESCRIPTION("Allwinner a83t pinctrl driver");
603MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 38e0c7bdd2ac..21fd638171f9 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -716,6 +716,7 @@ static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
716 unsigned long *out_hwirq, 716 unsigned long *out_hwirq,
717 unsigned int *out_type) 717 unsigned int *out_type)
718{ 718{
719 struct sunxi_pinctrl *pctl = d->host_data;
719 struct sunxi_desc_function *desc; 720 struct sunxi_desc_function *desc;
720 int pin, base; 721 int pin, base;
721 722
@@ -723,10 +724,9 @@ static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
723 return -EINVAL; 724 return -EINVAL;
724 725
725 base = PINS_PER_BANK * intspec[0]; 726 base = PINS_PER_BANK * intspec[0];
726 pin = base + intspec[1]; 727 pin = pctl->desc->pin_base + base + intspec[1];
727 728
728 desc = sunxi_pinctrl_desc_find_function_by_pin(d->host_data, 729 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
729 pin, "irq");
730 if (!desc) 730 if (!desc)
731 return -EINVAL; 731 return -EINVAL;
732 732
@@ -1029,7 +1029,7 @@ int sunxi_pinctrl_init(struct platform_device *pdev,
1029 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip, 1029 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
1030 handle_edge_irq); 1030 handle_edge_irq);
1031 irq_set_chip_data(irqno, pctl); 1031 irq_set_chip_data(irqno, pctl);
1032 }; 1032 }
1033 1033
1034 for (i = 0; i < pctl->desc->irq_banks; i++) { 1034 for (i = 0; i < pctl->desc->irq_banks; i++) {
1035 /* Mask and clear all IRQs before registering a handler */ 1035 /* Mask and clear all IRQs before registering a handler */
diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
index eab23ef9ddbf..ad907072e09f 100644
--- a/drivers/pinctrl/uniphier/Kconfig
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -1,32 +1,32 @@
1if ARCH_UNIPHIER 1if ARCH_UNIPHIER
2 2
3config PINCTRL_UNIPHIER_CORE 3config PINCTRL_UNIPHIER
4 bool 4 bool
5 select PINMUX 5 select PINMUX
6 select GENERIC_PINCONF 6 select GENERIC_PINCONF
7 7
8config PINCTRL_UNIPHIER_PH1_LD4 8config PINCTRL_UNIPHIER_PH1_LD4
9 tristate "UniPhier PH1-LD4 SoC pinctrl driver" 9 tristate "UniPhier PH1-LD4 SoC pinctrl driver"
10 select PINCTRL_UNIPHIER_CORE 10 select PINCTRL_UNIPHIER
11 11
12config PINCTRL_UNIPHIER_PH1_PRO4 12config PINCTRL_UNIPHIER_PH1_PRO4
13 tristate "UniPhier PH1-Pro4 SoC pinctrl driver" 13 tristate "UniPhier PH1-Pro4 SoC pinctrl driver"
14 select PINCTRL_UNIPHIER_CORE 14 select PINCTRL_UNIPHIER
15 15
16config PINCTRL_UNIPHIER_PH1_SLD8 16config PINCTRL_UNIPHIER_PH1_SLD8
17 tristate "UniPhier PH1-sLD8 SoC pinctrl driver" 17 tristate "UniPhier PH1-sLD8 SoC pinctrl driver"
18 select PINCTRL_UNIPHIER_CORE 18 select PINCTRL_UNIPHIER
19 19
20config PINCTRL_UNIPHIER_PH1_PRO5 20config PINCTRL_UNIPHIER_PH1_PRO5
21 tristate "UniPhier PH1-Pro5 SoC pinctrl driver" 21 tristate "UniPhier PH1-Pro5 SoC pinctrl driver"
22 select PINCTRL_UNIPHIER_CORE 22 select PINCTRL_UNIPHIER
23 23
24config PINCTRL_UNIPHIER_PROXSTREAM2 24config PINCTRL_UNIPHIER_PROXSTREAM2
25 tristate "UniPhier ProXstream2 SoC pinctrl driver" 25 tristate "UniPhier ProXstream2 SoC pinctrl driver"
26 select PINCTRL_UNIPHIER_CORE 26 select PINCTRL_UNIPHIER
27 27
28config PINCTRL_UNIPHIER_PH1_LD6B 28config PINCTRL_UNIPHIER_PH1_LD6B
29 tristate "UniPhier PH1-LD6b SoC pinctrl driver" 29 tristate "UniPhier PH1-LD6b SoC pinctrl driver"
30 select PINCTRL_UNIPHIER_CORE 30 select PINCTRL_UNIPHIER
31 31
32endif 32endif
diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile
index e215b1097297..e7ce9670306c 100644
--- a/drivers/pinctrl/uniphier/Makefile
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -1,4 +1,4 @@
1obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o 1obj-y += pinctrl-uniphier-core.o
2 2
3obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o 3obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o
4obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o 4obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o
diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c b/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c
index 7beb87e8f499..a7056dccfa53 100644
--- a/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c
@@ -537,6 +537,8 @@ static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
537 0, 0}; 537 0, 0};
538static const unsigned nand_cs1_pins[] = {22, 23}; 538static const unsigned nand_cs1_pins[] = {22, 23};
539static const unsigned nand_cs1_muxvals[] = {0, 0}; 539static const unsigned nand_cs1_muxvals[] = {0, 0};
540static const unsigned sd_pins[] = {44, 45, 46, 47, 48, 49, 50, 51, 52};
541static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
540static const unsigned uart0_pins[] = {85, 88}; 542static const unsigned uart0_pins[] = {85, 88};
541static const unsigned uart0_muxvals[] = {1, 1}; 543static const unsigned uart0_muxvals[] = {1, 1};
542static const unsigned uart1_pins[] = {155, 156}; 544static const unsigned uart1_pins[] = {155, 156};
@@ -619,6 +621,7 @@ static const struct uniphier_pinctrl_group ph1_ld4_groups[] = {
619 UNIPHIER_PINCTRL_GROUP(i2c3), 621 UNIPHIER_PINCTRL_GROUP(i2c3),
620 UNIPHIER_PINCTRL_GROUP(nand), 622 UNIPHIER_PINCTRL_GROUP(nand),
621 UNIPHIER_PINCTRL_GROUP(nand_cs1), 623 UNIPHIER_PINCTRL_GROUP(nand_cs1),
624 UNIPHIER_PINCTRL_GROUP(sd),
622 UNIPHIER_PINCTRL_GROUP(uart0), 625 UNIPHIER_PINCTRL_GROUP(uart0),
623 UNIPHIER_PINCTRL_GROUP(uart1), 626 UNIPHIER_PINCTRL_GROUP(uart1),
624 UNIPHIER_PINCTRL_GROUP(uart1b), 627 UNIPHIER_PINCTRL_GROUP(uart1b),
@@ -776,6 +779,7 @@ static const char * const i2c1_groups[] = {"i2c1"};
776static const char * const i2c2_groups[] = {"i2c2"}; 779static const char * const i2c2_groups[] = {"i2c2"};
777static const char * const i2c3_groups[] = {"i2c3"}; 780static const char * const i2c3_groups[] = {"i2c3"};
778static const char * const nand_groups[] = {"nand", "nand_cs1"}; 781static const char * const nand_groups[] = {"nand", "nand_cs1"};
782static const char * const sd_groups[] = {"sd"};
779static const char * const uart0_groups[] = {"uart0"}; 783static const char * const uart0_groups[] = {"uart0"};
780static const char * const uart1_groups[] = {"uart1", "uart1b"}; 784static const char * const uart1_groups[] = {"uart1", "uart1b"};
781static const char * const uart2_groups[] = {"uart2"}; 785static const char * const uart2_groups[] = {"uart2"};
@@ -831,6 +835,7 @@ static const struct uniphier_pinmux_function ph1_ld4_functions[] = {
831 UNIPHIER_PINMUX_FUNCTION(i2c2), 835 UNIPHIER_PINMUX_FUNCTION(i2c2),
832 UNIPHIER_PINMUX_FUNCTION(i2c3), 836 UNIPHIER_PINMUX_FUNCTION(i2c3),
833 UNIPHIER_PINMUX_FUNCTION(nand), 837 UNIPHIER_PINMUX_FUNCTION(nand),
838 UNIPHIER_PINMUX_FUNCTION(sd),
834 UNIPHIER_PINMUX_FUNCTION(uart0), 839 UNIPHIER_PINMUX_FUNCTION(uart0),
835 UNIPHIER_PINMUX_FUNCTION(uart1), 840 UNIPHIER_PINMUX_FUNCTION(uart1),
836 UNIPHIER_PINMUX_FUNCTION(uart2), 841 UNIPHIER_PINMUX_FUNCTION(uart2),
diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c
index 9720e697fbc1..1824831bb4da 100644
--- a/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c
+++ b/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c
@@ -761,6 +761,8 @@ static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
761 0, 0}; 761 0, 0};
762static const unsigned nand_cs1_pins[] = {37, 38}; 762static const unsigned nand_cs1_pins[] = {37, 38};
763static const unsigned nand_cs1_muxvals[] = {0, 0}; 763static const unsigned nand_cs1_muxvals[] = {0, 0};
764static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
765static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
764static const unsigned uart0_pins[] = {135, 136}; 766static const unsigned uart0_pins[] = {135, 136};
765static const unsigned uart0_muxvals[] = {3, 3}; 767static const unsigned uart0_muxvals[] = {3, 3};
766static const unsigned uart0b_pins[] = {11, 12}; 768static const unsigned uart0b_pins[] = {11, 12};
@@ -866,6 +868,7 @@ static const struct uniphier_pinctrl_group ph1_ld6b_groups[] = {
866 UNIPHIER_PINCTRL_GROUP(i2c3), 868 UNIPHIER_PINCTRL_GROUP(i2c3),
867 UNIPHIER_PINCTRL_GROUP(nand), 869 UNIPHIER_PINCTRL_GROUP(nand),
868 UNIPHIER_PINCTRL_GROUP(nand_cs1), 870 UNIPHIER_PINCTRL_GROUP(nand_cs1),
871 UNIPHIER_PINCTRL_GROUP(sd),
869 UNIPHIER_PINCTRL_GROUP(uart0), 872 UNIPHIER_PINCTRL_GROUP(uart0),
870 UNIPHIER_PINCTRL_GROUP(uart0b), 873 UNIPHIER_PINCTRL_GROUP(uart0b),
871 UNIPHIER_PINCTRL_GROUP(uart1), 874 UNIPHIER_PINCTRL_GROUP(uart1),
@@ -1136,6 +1139,7 @@ static const char * const i2c1_groups[] = {"i2c1"};
1136static const char * const i2c2_groups[] = {"i2c2"}; 1139static const char * const i2c2_groups[] = {"i2c2"};
1137static const char * const i2c3_groups[] = {"i2c3"}; 1140static const char * const i2c3_groups[] = {"i2c3"};
1138static const char * const nand_groups[] = {"nand", "nand_cs1"}; 1141static const char * const nand_groups[] = {"nand", "nand_cs1"};
1142static const char * const sd_groups[] = {"sd"};
1139static const char * const uart0_groups[] = {"uart0", "uart0b"}; 1143static const char * const uart0_groups[] = {"uart0", "uart0b"};
1140static const char * const uart1_groups[] = {"uart1", "uart1b"}; 1144static const char * const uart1_groups[] = {"uart1", "uart1b"};
1141static const char * const uart2_groups[] = {"uart2", "uart2b"}; 1145static const char * const uart2_groups[] = {"uart2", "uart2b"};
@@ -1219,6 +1223,7 @@ static const struct uniphier_pinmux_function ph1_ld6b_functions[] = {
1219 UNIPHIER_PINMUX_FUNCTION(i2c2), 1223 UNIPHIER_PINMUX_FUNCTION(i2c2),
1220 UNIPHIER_PINMUX_FUNCTION(i2c3), 1224 UNIPHIER_PINMUX_FUNCTION(i2c3),
1221 UNIPHIER_PINMUX_FUNCTION(nand), 1225 UNIPHIER_PINMUX_FUNCTION(nand),
1226 UNIPHIER_PINMUX_FUNCTION(sd),
1222 UNIPHIER_PINMUX_FUNCTION(uart0), 1227 UNIPHIER_PINMUX_FUNCTION(uart0),
1223 UNIPHIER_PINMUX_FUNCTION(uart1), 1228 UNIPHIER_PINMUX_FUNCTION(uart1),
1224 UNIPHIER_PINMUX_FUNCTION(uart2), 1229 UNIPHIER_PINMUX_FUNCTION(uart2),
diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c b/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c
index 96921e40da5f..ec8e92dfaf8c 100644
--- a/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c
@@ -1031,6 +1031,11 @@ static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1031 0, 0}; 1031 0, 0};
1032static const unsigned nand_cs1_pins[] = {131, 132}; 1032static const unsigned nand_cs1_pins[] = {131, 132};
1033static const unsigned nand_cs1_muxvals[] = {1, 1}; 1033static const unsigned nand_cs1_muxvals[] = {1, 1};
1034static const unsigned sd_pins[] = {150, 151, 152, 153, 154, 155, 156, 157, 158};
1035static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
1036static const unsigned sd1_pins[] = {319, 320, 321, 322, 323, 324, 325, 326,
1037 327};
1038static const unsigned sd1_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
1034static const unsigned uart0_pins[] = {127, 128}; 1039static const unsigned uart0_pins[] = {127, 128};
1035static const unsigned uart0_muxvals[] = {0, 0}; 1040static const unsigned uart0_muxvals[] = {0, 0};
1036static const unsigned uart1_pins[] = {129, 130}; 1041static const unsigned uart1_pins[] = {129, 130};
@@ -1140,6 +1145,8 @@ static const struct uniphier_pinctrl_group ph1_pro4_groups[] = {
1140 UNIPHIER_PINCTRL_GROUP(i2c6), 1145 UNIPHIER_PINCTRL_GROUP(i2c6),
1141 UNIPHIER_PINCTRL_GROUP(nand), 1146 UNIPHIER_PINCTRL_GROUP(nand),
1142 UNIPHIER_PINCTRL_GROUP(nand_cs1), 1147 UNIPHIER_PINCTRL_GROUP(nand_cs1),
1148 UNIPHIER_PINCTRL_GROUP(sd),
1149 UNIPHIER_PINCTRL_GROUP(sd1),
1143 UNIPHIER_PINCTRL_GROUP(uart0), 1150 UNIPHIER_PINCTRL_GROUP(uart0),
1144 UNIPHIER_PINCTRL_GROUP(uart1), 1151 UNIPHIER_PINCTRL_GROUP(uart1),
1145 UNIPHIER_PINCTRL_GROUP(uart2), 1152 UNIPHIER_PINCTRL_GROUP(uart2),
@@ -1412,6 +1419,8 @@ static const char * const i2c2_groups[] = {"i2c2"};
1412static const char * const i2c3_groups[] = {"i2c3"}; 1419static const char * const i2c3_groups[] = {"i2c3"};
1413static const char * const i2c6_groups[] = {"i2c6"}; 1420static const char * const i2c6_groups[] = {"i2c6"};
1414static const char * const nand_groups[] = {"nand", "nand_cs1"}; 1421static const char * const nand_groups[] = {"nand", "nand_cs1"};
1422static const char * const sd_groups[] = {"sd"};
1423static const char * const sd1_groups[] = {"sd1"};
1415static const char * const uart0_groups[] = {"uart0"}; 1424static const char * const uart0_groups[] = {"uart0"};
1416static const char * const uart1_groups[] = {"uart1"}; 1425static const char * const uart1_groups[] = {"uart1"};
1417static const char * const uart2_groups[] = {"uart2"}; 1426static const char * const uart2_groups[] = {"uart2"};
@@ -1498,6 +1507,8 @@ static const struct uniphier_pinmux_function ph1_pro4_functions[] = {
1498 UNIPHIER_PINMUX_FUNCTION(i2c3), 1507 UNIPHIER_PINMUX_FUNCTION(i2c3),
1499 UNIPHIER_PINMUX_FUNCTION(i2c6), 1508 UNIPHIER_PINMUX_FUNCTION(i2c6),
1500 UNIPHIER_PINMUX_FUNCTION(nand), 1509 UNIPHIER_PINMUX_FUNCTION(nand),
1510 UNIPHIER_PINMUX_FUNCTION(sd),
1511 UNIPHIER_PINMUX_FUNCTION(sd1),
1501 UNIPHIER_PINMUX_FUNCTION(uart0), 1512 UNIPHIER_PINMUX_FUNCTION(uart0),
1502 UNIPHIER_PINMUX_FUNCTION(uart1), 1513 UNIPHIER_PINMUX_FUNCTION(uart1),
1503 UNIPHIER_PINMUX_FUNCTION(uart2), 1514 UNIPHIER_PINMUX_FUNCTION(uart2),
diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c b/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c
index 9af455978058..e3d648eae85a 100644
--- a/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c
+++ b/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c
@@ -818,6 +818,8 @@ static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
818 0, 0}; 818 0, 0};
819static const unsigned nand_cs1_pins[] = {26, 27}; 819static const unsigned nand_cs1_pins[] = {26, 27};
820static const unsigned nand_cs1_muxvals[] = {0, 0}; 820static const unsigned nand_cs1_muxvals[] = {0, 0};
821static const unsigned sd_pins[] = {250, 251, 252, 253, 254, 255, 256, 257, 258};
822static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
821static const unsigned uart0_pins[] = {47, 48}; 823static const unsigned uart0_pins[] = {47, 48};
822static const unsigned uart0_muxvals[] = {0, 0}; 824static const unsigned uart0_muxvals[] = {0, 0};
823static const unsigned uart0b_pins[] = {227, 228}; 825static const unsigned uart0b_pins[] = {227, 228};
@@ -930,6 +932,7 @@ static const struct uniphier_pinctrl_group ph1_pro5_groups[] = {
930 UNIPHIER_PINCTRL_GROUP(i2c5b), 932 UNIPHIER_PINCTRL_GROUP(i2c5b),
931 UNIPHIER_PINCTRL_GROUP(i2c5c), 933 UNIPHIER_PINCTRL_GROUP(i2c5c),
932 UNIPHIER_PINCTRL_GROUP(i2c6), 934 UNIPHIER_PINCTRL_GROUP(i2c6),
935 UNIPHIER_PINCTRL_GROUP(sd),
933 UNIPHIER_PINCTRL_GROUP(uart0), 936 UNIPHIER_PINCTRL_GROUP(uart0),
934 UNIPHIER_PINCTRL_GROUP(uart0b), 937 UNIPHIER_PINCTRL_GROUP(uart0b),
935 UNIPHIER_PINCTRL_GROUP(uart1), 938 UNIPHIER_PINCTRL_GROUP(uart1),
@@ -1209,6 +1212,7 @@ static const char * const i2c3_groups[] = {"i2c3"};
1209static const char * const i2c5_groups[] = {"i2c5", "i2c5b", "i2c5c"}; 1212static const char * const i2c5_groups[] = {"i2c5", "i2c5b", "i2c5c"};
1210static const char * const i2c6_groups[] = {"i2c6"}; 1213static const char * const i2c6_groups[] = {"i2c6"};
1211static const char * const nand_groups[] = {"nand", "nand_cs1"}; 1214static const char * const nand_groups[] = {"nand", "nand_cs1"};
1215static const char * const sd_groups[] = {"sd"};
1212static const char * const uart0_groups[] = {"uart0", "uart0b"}; 1216static const char * const uart0_groups[] = {"uart0", "uart0b"};
1213static const char * const uart1_groups[] = {"uart1"}; 1217static const char * const uart1_groups[] = {"uart1"};
1214static const char * const uart2_groups[] = {"uart2"}; 1218static const char * const uart2_groups[] = {"uart2"};
@@ -1296,6 +1300,7 @@ static const struct uniphier_pinmux_function ph1_pro5_functions[] = {
1296 UNIPHIER_PINMUX_FUNCTION(i2c5), 1300 UNIPHIER_PINMUX_FUNCTION(i2c5),
1297 UNIPHIER_PINMUX_FUNCTION(i2c6), 1301 UNIPHIER_PINMUX_FUNCTION(i2c6),
1298 UNIPHIER_PINMUX_FUNCTION(nand), 1302 UNIPHIER_PINMUX_FUNCTION(nand),
1303 UNIPHIER_PINMUX_FUNCTION(sd),
1299 UNIPHIER_PINMUX_FUNCTION(uart0), 1304 UNIPHIER_PINMUX_FUNCTION(uart0),
1300 UNIPHIER_PINMUX_FUNCTION(uart1), 1305 UNIPHIER_PINMUX_FUNCTION(uart1),
1301 UNIPHIER_PINMUX_FUNCTION(uart2), 1306 UNIPHIER_PINMUX_FUNCTION(uart2),
diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c b/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c
index 2df8bbecebfc..c3700a33a5da 100644
--- a/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c
+++ b/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c
@@ -450,6 +450,8 @@ static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
450 0, 0}; 450 0, 0};
451static const unsigned nand_cs1_pins[] = {22, 23}; 451static const unsigned nand_cs1_pins[] = {22, 23};
452static const unsigned nand_cs1_muxvals[] = {0, 0}; 452static const unsigned nand_cs1_muxvals[] = {0, 0};
453static const unsigned sd_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40};
454static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
453static const unsigned uart0_pins[] = {70, 71}; 455static const unsigned uart0_pins[] = {70, 71};
454static const unsigned uart0_muxvals[] = {3, 3}; 456static const unsigned uart0_muxvals[] = {3, 3};
455static const unsigned uart1_pins[] = {114, 115}; 457static const unsigned uart1_pins[] = {114, 115};
@@ -536,6 +538,7 @@ static const struct uniphier_pinctrl_group ph1_sld8_groups[] = {
536 UNIPHIER_PINCTRL_GROUP(i2c3), 538 UNIPHIER_PINCTRL_GROUP(i2c3),
537 UNIPHIER_PINCTRL_GROUP(nand), 539 UNIPHIER_PINCTRL_GROUP(nand),
538 UNIPHIER_PINCTRL_GROUP(nand_cs1), 540 UNIPHIER_PINCTRL_GROUP(nand_cs1),
541 UNIPHIER_PINCTRL_GROUP(sd),
539 UNIPHIER_PINCTRL_GROUP(uart0), 542 UNIPHIER_PINCTRL_GROUP(uart0),
540 UNIPHIER_PINCTRL_GROUP(uart1), 543 UNIPHIER_PINCTRL_GROUP(uart1),
541 UNIPHIER_PINCTRL_GROUP(uart2), 544 UNIPHIER_PINCTRL_GROUP(uart2),
@@ -684,6 +687,7 @@ static const char * const i2c1_groups[] = {"i2c1"};
684static const char * const i2c2_groups[] = {"i2c2"}; 687static const char * const i2c2_groups[] = {"i2c2"};
685static const char * const i2c3_groups[] = {"i2c3"}; 688static const char * const i2c3_groups[] = {"i2c3"};
686static const char * const nand_groups[] = {"nand", "nand_cs1"}; 689static const char * const nand_groups[] = {"nand", "nand_cs1"};
690static const char * const sd_groups[] = {"sd"};
687static const char * const uart0_groups[] = {"uart0"}; 691static const char * const uart0_groups[] = {"uart0"};
688static const char * const uart1_groups[] = {"uart1"}; 692static const char * const uart1_groups[] = {"uart1"};
689static const char * const uart2_groups[] = {"uart2"}; 693static const char * const uart2_groups[] = {"uart2"};
@@ -739,6 +743,7 @@ static const struct uniphier_pinmux_function ph1_sld8_functions[] = {
739 UNIPHIER_PINMUX_FUNCTION(i2c2), 743 UNIPHIER_PINMUX_FUNCTION(i2c2),
740 UNIPHIER_PINMUX_FUNCTION(i2c3), 744 UNIPHIER_PINMUX_FUNCTION(i2c3),
741 UNIPHIER_PINMUX_FUNCTION(nand), 745 UNIPHIER_PINMUX_FUNCTION(nand),
746 UNIPHIER_PINMUX_FUNCTION(sd),
742 UNIPHIER_PINMUX_FUNCTION(uart0), 747 UNIPHIER_PINMUX_FUNCTION(uart0),
743 UNIPHIER_PINMUX_FUNCTION(uart1), 748 UNIPHIER_PINMUX_FUNCTION(uart1),
744 UNIPHIER_PINMUX_FUNCTION(uart2), 749 UNIPHIER_PINMUX_FUNCTION(uart2),
diff --git a/drivers/pinctrl/uniphier/pinctrl-proxstream2.c b/drivers/pinctrl/uniphier/pinctrl-proxstream2.c
index 3f036e236ad9..bc00d7591c59 100644
--- a/drivers/pinctrl/uniphier/pinctrl-proxstream2.c
+++ b/drivers/pinctrl/uniphier/pinctrl-proxstream2.c
@@ -751,6 +751,8 @@ static const unsigned nand_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
751 8, 8}; 751 8, 8};
752static const unsigned nand_cs1_pins[] = {37, 38}; 752static const unsigned nand_cs1_pins[] = {37, 38};
753static const unsigned nand_cs1_muxvals[] = {8, 8}; 753static const unsigned nand_cs1_muxvals[] = {8, 8};
754static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
755static const unsigned sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8};
754static const unsigned uart0_pins[] = {217, 218}; 756static const unsigned uart0_pins[] = {217, 218};
755static const unsigned uart0_muxvals[] = {8, 8}; 757static const unsigned uart0_muxvals[] = {8, 8};
756static const unsigned uart0b_pins[] = {179, 180}; 758static const unsigned uart0b_pins[] = {179, 180};
@@ -857,6 +859,7 @@ static const struct uniphier_pinctrl_group proxstream2_groups[] = {
857 UNIPHIER_PINCTRL_GROUP(i2c6), 859 UNIPHIER_PINCTRL_GROUP(i2c6),
858 UNIPHIER_PINCTRL_GROUP(nand), 860 UNIPHIER_PINCTRL_GROUP(nand),
859 UNIPHIER_PINCTRL_GROUP(nand_cs1), 861 UNIPHIER_PINCTRL_GROUP(nand_cs1),
862 UNIPHIER_PINCTRL_GROUP(sd),
860 UNIPHIER_PINCTRL_GROUP(uart0), 863 UNIPHIER_PINCTRL_GROUP(uart0),
861 UNIPHIER_PINCTRL_GROUP(uart0b), 864 UNIPHIER_PINCTRL_GROUP(uart0b),
862 UNIPHIER_PINCTRL_GROUP(uart1), 865 UNIPHIER_PINCTRL_GROUP(uart1),
@@ -1128,6 +1131,7 @@ static const char * const i2c3_groups[] = {"i2c3"};
1128static const char * const i2c5_groups[] = {"i2c5"}; 1131static const char * const i2c5_groups[] = {"i2c5"};
1129static const char * const i2c6_groups[] = {"i2c6"}; 1132static const char * const i2c6_groups[] = {"i2c6"};
1130static const char * const nand_groups[] = {"nand", "nand_cs1"}; 1133static const char * const nand_groups[] = {"nand", "nand_cs1"};
1134static const char * const sd_groups[] = {"sd"};
1131static const char * const uart0_groups[] = {"uart0", "uart0b"}; 1135static const char * const uart0_groups[] = {"uart0", "uart0b"};
1132static const char * const uart1_groups[] = {"uart1"}; 1136static const char * const uart1_groups[] = {"uart1"};
1133static const char * const uart2_groups[] = {"uart2"}; 1137static const char * const uart2_groups[] = {"uart2"};
@@ -1213,6 +1217,7 @@ static const struct uniphier_pinmux_function proxstream2_functions[] = {
1213 UNIPHIER_PINMUX_FUNCTION(i2c5), 1217 UNIPHIER_PINMUX_FUNCTION(i2c5),
1214 UNIPHIER_PINMUX_FUNCTION(i2c6), 1218 UNIPHIER_PINMUX_FUNCTION(i2c6),
1215 UNIPHIER_PINMUX_FUNCTION(nand), 1219 UNIPHIER_PINMUX_FUNCTION(nand),
1220 UNIPHIER_PINMUX_FUNCTION(sd),
1216 UNIPHIER_PINMUX_FUNCTION(uart0), 1221 UNIPHIER_PINMUX_FUNCTION(uart0),
1217 UNIPHIER_PINMUX_FUNCTION(uart1), 1222 UNIPHIER_PINMUX_FUNCTION(uart1),
1218 UNIPHIER_PINMUX_FUNCTION(uart2), 1223 UNIPHIER_PINMUX_FUNCTION(uart2),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index 918f3b643f1b..589872cc8adb 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -539,6 +539,12 @@ static int uniphier_pmx_set_one_mux(struct pinctrl_dev *pctldev, unsigned pin,
539 unsigned reg, reg_end, shift, mask; 539 unsigned reg, reg_end, shift, mask;
540 int ret; 540 int ret;
541 541
542 /* some pins need input-enabling */
543 ret = uniphier_conf_pin_input_enable(pctldev,
544 &pctldev->desc->pins[pin], 1);
545 if (ret)
546 return ret;
547
542 reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride; 548 reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride;
543 reg_end = reg + reg_stride; 549 reg_end = reg + reg_stride;
544 shift = pin * mux_bits % 32; 550 shift = pin * mux_bits % 32;
@@ -563,9 +569,7 @@ static int uniphier_pmx_set_one_mux(struct pinctrl_dev *pctldev, unsigned pin,
563 return ret; 569 return ret;
564 } 570 }
565 571
566 /* some pins need input-enabling */ 572 return 0;
567 return uniphier_conf_pin_input_enable(pctldev,
568 &pctldev->desc->pins[pin], 1);
569} 573}
570 574
571static int uniphier_pmx_set_mux(struct pinctrl_dev *pctldev, 575static int uniphier_pmx_set_mux(struct pinctrl_dev *pctldev,
diff --git a/drivers/usb/renesas_usbhs/rcar2.c b/drivers/usb/renesas_usbhs/rcar2.c
index 8fc15c0ba339..277160bc6f25 100644
--- a/drivers/usb/renesas_usbhs/rcar2.c
+++ b/drivers/usb/renesas_usbhs/rcar2.c
@@ -13,7 +13,6 @@
13#include <linux/gpio.h> 13#include <linux/gpio.h>
14#include <linux/of_gpio.h> 14#include <linux/of_gpio.h>
15#include <linux/phy/phy.h> 15#include <linux/phy/phy.h>
16#include <linux/platform_data/gpio-rcar.h>
17#include <linux/usb/phy.h> 16#include <linux/usb/phy.h>
18#include "common.h" 17#include "common.h"
19#include "rcar2.h" 18#include "rcar2.h"
diff --git a/include/linux/pinctrl/devinfo.h b/include/linux/pinctrl/devinfo.h
index 281cb91ddcf5..05082e407c4a 100644
--- a/include/linux/pinctrl/devinfo.h
+++ b/include/linux/pinctrl/devinfo.h
@@ -24,10 +24,14 @@
24 * struct dev_pin_info - pin state container for devices 24 * struct dev_pin_info - pin state container for devices
25 * @p: pinctrl handle for the containing device 25 * @p: pinctrl handle for the containing device
26 * @default_state: the default state for the handle, if found 26 * @default_state: the default state for the handle, if found
27 * @init_state: the state at probe time, if found
28 * @sleep_state: the state at suspend time, if found
29 * @idle_state: the state at idle (runtime suspend) time, if found
27 */ 30 */
28struct dev_pin_info { 31struct dev_pin_info {
29 struct pinctrl *p; 32 struct pinctrl *p;
30 struct pinctrl_state *default_state; 33 struct pinctrl_state *default_state;
34 struct pinctrl_state *init_state;
31#ifdef CONFIG_PM 35#ifdef CONFIG_PM
32 struct pinctrl_state *sleep_state; 36 struct pinctrl_state *sleep_state;
33 struct pinctrl_state *idle_state; 37 struct pinctrl_state *idle_state;
@@ -35,6 +39,7 @@ struct dev_pin_info {
35}; 39};
36 40
37extern int pinctrl_bind_pins(struct device *dev); 41extern int pinctrl_bind_pins(struct device *dev);
42extern int pinctrl_init_done(struct device *dev);
38 43
39#else 44#else
40 45
@@ -45,5 +50,10 @@ static inline int pinctrl_bind_pins(struct device *dev)
45 return 0; 50 return 0;
46} 51}
47 52
53static inline int pinctrl_init_done(struct device *dev)
54{
55 return 0;
56}
57
48#endif /* CONFIG_PINCTRL */ 58#endif /* CONFIG_PINCTRL */
49#endif /* PINCTRL_DEVINFO_H */ 59#endif /* PINCTRL_DEVINFO_H */
diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h
index fe65962b264f..d921afd5f109 100644
--- a/include/linux/pinctrl/pinconf-generic.h
+++ b/include/linux/pinctrl/pinconf-generic.h
@@ -20,6 +20,11 @@
20 20
21/** 21/**
22 * enum pin_config_param - possible pin configuration parameters 22 * enum pin_config_param - possible pin configuration parameters
23 * @PIN_CONFIG_BIAS_BUS_HOLD: the pin will be set to weakly latch so that it
24 * weakly drives the last value on a tristate bus, also known as a "bus
25 * holder", "bus keeper" or "repeater". This allows another device on the
26 * bus to change the value by driving the bus high or low and switching to
27 * tristate. The argument is ignored.
23 * @PIN_CONFIG_BIAS_DISABLE: disable any pin bias on the pin, a 28 * @PIN_CONFIG_BIAS_DISABLE: disable any pin bias on the pin, a
24 * transition from say pull-up to pull-down implies that you disable 29 * transition from say pull-up to pull-down implies that you disable
25 * pull-up in the process, this setting disables all biasing. 30 * pull-up in the process, this setting disables all biasing.
@@ -29,14 +34,6 @@
29 * if for example some other pin is going to drive the signal connected 34 * if for example some other pin is going to drive the signal connected
30 * to it for a while. Pins used for input are usually always high 35 * to it for a while. Pins used for input are usually always high
31 * impedance. 36 * impedance.
32 * @PIN_CONFIG_BIAS_BUS_HOLD: the pin will be set to weakly latch so that it
33 * weakly drives the last value on a tristate bus, also known as a "bus
34 * holder", "bus keeper" or "repeater". This allows another device on the
35 * bus to change the value by driving the bus high or low and switching to
36 * tristate. The argument is ignored.
37 * @PIN_CONFIG_BIAS_PULL_UP: the pin will be pulled up (usually with high
38 * impedance to VDD). If the argument is != 0 pull-up is enabled,
39 * if it is 0, pull-up is total, i.e. the pin is connected to VDD.
40 * @PIN_CONFIG_BIAS_PULL_DOWN: the pin will be pulled down (usually with high 37 * @PIN_CONFIG_BIAS_PULL_DOWN: the pin will be pulled down (usually with high
41 * impedance to GROUND). If the argument is != 0 pull-down is enabled, 38 * impedance to GROUND). If the argument is != 0 pull-down is enabled,
42 * if it is 0, pull-down is total, i.e. the pin is connected to GROUND. 39 * if it is 0, pull-down is total, i.e. the pin is connected to GROUND.
@@ -48,10 +45,9 @@
48 * If the argument is != 0 pull up/down is enabled, if it is 0, the 45 * If the argument is != 0 pull up/down is enabled, if it is 0, the
49 * configuration is ignored. The proper way to disable it is to use 46 * configuration is ignored. The proper way to disable it is to use
50 * @PIN_CONFIG_BIAS_DISABLE. 47 * @PIN_CONFIG_BIAS_DISABLE.
51 * @PIN_CONFIG_DRIVE_PUSH_PULL: the pin will be driven actively high and 48 * @PIN_CONFIG_BIAS_PULL_UP: the pin will be pulled up (usually with high
52 * low, this is the most typical case and is typically achieved with two 49 * impedance to VDD). If the argument is != 0 pull-up is enabled,
53 * active transistors on the output. Setting this config will enable 50 * if it is 0, pull-up is total, i.e. the pin is connected to VDD.
54 * push-pull mode, the argument is ignored.
55 * @PIN_CONFIG_DRIVE_OPEN_DRAIN: the pin will be driven with open drain (open 51 * @PIN_CONFIG_DRIVE_OPEN_DRAIN: the pin will be driven with open drain (open
56 * collector) which means it is usually wired with other output ports 52 * collector) which means it is usually wired with other output ports
57 * which are then pulled up with an external resistor. Setting this 53 * which are then pulled up with an external resistor. Setting this
@@ -59,28 +55,26 @@
59 * @PIN_CONFIG_DRIVE_OPEN_SOURCE: the pin will be driven with open source 55 * @PIN_CONFIG_DRIVE_OPEN_SOURCE: the pin will be driven with open source
60 * (open emitter). Setting this config will enable open source mode, the 56 * (open emitter). Setting this config will enable open source mode, the
61 * argument is ignored. 57 * argument is ignored.
58 * @PIN_CONFIG_DRIVE_PUSH_PULL: the pin will be driven actively high and
59 * low, this is the most typical case and is typically achieved with two
60 * active transistors on the output. Setting this config will enable
61 * push-pull mode, the argument is ignored.
62 * @PIN_CONFIG_DRIVE_STRENGTH: the pin will sink or source at most the current 62 * @PIN_CONFIG_DRIVE_STRENGTH: the pin will sink or source at most the current
63 * passed as argument. The argument is in mA. 63 * passed as argument. The argument is in mA.
64 * @PIN_CONFIG_INPUT_DEBOUNCE: this will configure the pin to debounce mode,
65 * which means it will wait for signals to settle when reading inputs. The
66 * argument gives the debounce time in usecs. Setting the
67 * argument to zero turns debouncing off.
64 * @PIN_CONFIG_INPUT_ENABLE: enable the pin's input. Note that this does not 68 * @PIN_CONFIG_INPUT_ENABLE: enable the pin's input. Note that this does not
65 * affect the pin's ability to drive output. 1 enables input, 0 disables 69 * affect the pin's ability to drive output. 1 enables input, 0 disables
66 * input. 70 * input.
67 * @PIN_CONFIG_INPUT_SCHMITT_ENABLE: control schmitt-trigger mode on the pin.
68 * If the argument != 0, schmitt-trigger mode is enabled. If it's 0,
69 * schmitt-trigger mode is disabled.
70 * @PIN_CONFIG_INPUT_SCHMITT: this will configure an input pin to run in 71 * @PIN_CONFIG_INPUT_SCHMITT: this will configure an input pin to run in
71 * schmitt-trigger mode. If the schmitt-trigger has adjustable hysteresis, 72 * schmitt-trigger mode. If the schmitt-trigger has adjustable hysteresis,
72 * the threshold value is given on a custom format as argument when 73 * the threshold value is given on a custom format as argument when
73 * setting pins to this mode. 74 * setting pins to this mode.
74 * @PIN_CONFIG_INPUT_DEBOUNCE: this will configure the pin to debounce mode, 75 * @PIN_CONFIG_INPUT_SCHMITT_ENABLE: control schmitt-trigger mode on the pin.
75 * which means it will wait for signals to settle when reading inputs. The 76 * If the argument != 0, schmitt-trigger mode is enabled. If it's 0,
76 * argument gives the debounce time in usecs. Setting the 77 * schmitt-trigger mode is disabled.
77 * argument to zero turns debouncing off.
78 * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power
79 * supplies, the argument to this parameter (on a custom format) tells
80 * the driver which alternative power source to use.
81 * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to
82 * this parameter (on a custom format) tells the driver which alternative
83 * slew rate to use.
84 * @PIN_CONFIG_LOW_POWER_MODE: this will configure the pin for low power 78 * @PIN_CONFIG_LOW_POWER_MODE: this will configure the pin for low power
85 * operation, if several modes of operation are supported these can be 79 * operation, if several modes of operation are supported these can be
86 * passed in the argument on a custom form, else just use argument 1 80 * passed in the argument on a custom form, else just use argument 1
@@ -89,29 +83,35 @@
89 * 1 to indicate high level, argument 0 to indicate low level. (Please 83 * 1 to indicate high level, argument 0 to indicate low level. (Please
90 * see Documentation/pinctrl.txt, section "GPIO mode pitfalls" for a 84 * see Documentation/pinctrl.txt, section "GPIO mode pitfalls" for a
91 * discussion around this parameter.) 85 * discussion around this parameter.)
86 * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power
87 * supplies, the argument to this parameter (on a custom format) tells
88 * the driver which alternative power source to use.
89 * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to
90 * this parameter (on a custom format) tells the driver which alternative
91 * slew rate to use.
92 * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if 92 * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if
93 * you need to pass in custom configurations to the pin controller, use 93 * you need to pass in custom configurations to the pin controller, use
94 * PIN_CONFIG_END+1 as the base offset. 94 * PIN_CONFIG_END+1 as the base offset.
95 */ 95 */
96enum pin_config_param { 96enum pin_config_param {
97 PIN_CONFIG_BIAS_BUS_HOLD,
97 PIN_CONFIG_BIAS_DISABLE, 98 PIN_CONFIG_BIAS_DISABLE,
98 PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 99 PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
99 PIN_CONFIG_BIAS_BUS_HOLD,
100 PIN_CONFIG_BIAS_PULL_UP,
101 PIN_CONFIG_BIAS_PULL_DOWN, 100 PIN_CONFIG_BIAS_PULL_DOWN,
102 PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 101 PIN_CONFIG_BIAS_PULL_PIN_DEFAULT,
103 PIN_CONFIG_DRIVE_PUSH_PULL, 102 PIN_CONFIG_BIAS_PULL_UP,
104 PIN_CONFIG_DRIVE_OPEN_DRAIN, 103 PIN_CONFIG_DRIVE_OPEN_DRAIN,
105 PIN_CONFIG_DRIVE_OPEN_SOURCE, 104 PIN_CONFIG_DRIVE_OPEN_SOURCE,
105 PIN_CONFIG_DRIVE_PUSH_PULL,
106 PIN_CONFIG_DRIVE_STRENGTH, 106 PIN_CONFIG_DRIVE_STRENGTH,
107 PIN_CONFIG_INPUT_DEBOUNCE,
107 PIN_CONFIG_INPUT_ENABLE, 108 PIN_CONFIG_INPUT_ENABLE,
108 PIN_CONFIG_INPUT_SCHMITT_ENABLE,
109 PIN_CONFIG_INPUT_SCHMITT, 109 PIN_CONFIG_INPUT_SCHMITT,
110 PIN_CONFIG_INPUT_DEBOUNCE, 110 PIN_CONFIG_INPUT_SCHMITT_ENABLE,
111 PIN_CONFIG_POWER_SOURCE,
112 PIN_CONFIG_SLEW_RATE,
113 PIN_CONFIG_LOW_POWER_MODE, 111 PIN_CONFIG_LOW_POWER_MODE,
114 PIN_CONFIG_OUTPUT, 112 PIN_CONFIG_OUTPUT,
113 PIN_CONFIG_POWER_SOURCE,
114 PIN_CONFIG_SLEW_RATE,
115 PIN_CONFIG_END = 0x7FFF, 115 PIN_CONFIG_END = 0x7FFF,
116}; 116};
117 117
diff --git a/include/linux/pinctrl/pinctrl-state.h b/include/linux/pinctrl/pinctrl-state.h
index b5919f8e6d1a..23073519339f 100644
--- a/include/linux/pinctrl/pinctrl-state.h
+++ b/include/linux/pinctrl/pinctrl-state.h
@@ -9,6 +9,13 @@
9 * hogs to configure muxing and pins at boot, and also as a state 9 * hogs to configure muxing and pins at boot, and also as a state
10 * to go into when returning from sleep and idle in 10 * to go into when returning from sleep and idle in
11 * .pm_runtime_resume() or ordinary .resume() for example. 11 * .pm_runtime_resume() or ordinary .resume() for example.
12 * @PINCTRL_STATE_INIT: normally the pinctrl will be set to "default"
13 * before the driver's probe() function is called. There are some
14 * drivers where that is not appropriate becausing doing so would
15 * glitch the pins. In those cases you can add an "init" pinctrl
16 * which is the state of the pins before drive probe. After probe
17 * if the pins are still in "init" state they'll be moved to
18 * "default".
12 * @PINCTRL_STATE_IDLE: the state the pinctrl handle shall be put into 19 * @PINCTRL_STATE_IDLE: the state the pinctrl handle shall be put into
13 * when the pins are idle. This is a state where the system is relaxed 20 * when the pins are idle. This is a state where the system is relaxed
14 * but not fully sleeping - some power may be on but clocks gated for 21 * but not fully sleeping - some power may be on but clocks gated for
@@ -20,5 +27,6 @@
20 * ordinary .suspend() function. 27 * ordinary .suspend() function.
21 */ 28 */
22#define PINCTRL_STATE_DEFAULT "default" 29#define PINCTRL_STATE_DEFAULT "default"
30#define PINCTRL_STATE_INIT "init"
23#define PINCTRL_STATE_IDLE "idle" 31#define PINCTRL_STATE_IDLE "idle"
24#define PINCTRL_STATE_SLEEP "sleep" 32#define PINCTRL_STATE_SLEEP "sleep"
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-14 14:33:10 -0400