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-rw-r--r--drivers/clk/meson/axg-audio.h20
-rw-r--r--drivers/clk/meson/clk-pll.c26
-rw-r--r--drivers/clk/meson/clk-pll.h1
-rw-r--r--drivers/clk/meson/g12a-aoclk.h2
-rw-r--r--drivers/clk/meson/g12a.c631
-rw-r--r--drivers/clk/meson/g12a.h31
-rw-r--r--drivers/clk/meson/meson8b.c734
-rw-r--r--drivers/clk/meson/meson8b.h27
-rw-r--r--include/dt-bindings/clock/axg-audio-clkc.h20
-rw-r--r--include/dt-bindings/clock/g12a-aoclkc.h2
-rw-r--r--include/dt-bindings/clock/g12a-clkc.h5
-rw-r--r--include/dt-bindings/clock/meson8b-clkc.h6
12 files changed, 1479 insertions, 26 deletions
diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h
index 7191b39c9d65..644f0b0fddf2 100644
--- a/drivers/clk/meson/axg-audio.h
+++ b/drivers/clk/meson/axg-audio.h
@@ -60,6 +60,26 @@
60#define AUD_CLKID_MST5 6 60#define AUD_CLKID_MST5 6
61#define AUD_CLKID_MST6 7 61#define AUD_CLKID_MST6 7
62#define AUD_CLKID_MST7 8 62#define AUD_CLKID_MST7 8
63#define AUD_CLKID_SLV_SCLK0 9
64#define AUD_CLKID_SLV_SCLK1 10
65#define AUD_CLKID_SLV_SCLK2 11
66#define AUD_CLKID_SLV_SCLK3 12
67#define AUD_CLKID_SLV_SCLK4 13
68#define AUD_CLKID_SLV_SCLK5 14
69#define AUD_CLKID_SLV_SCLK6 15
70#define AUD_CLKID_SLV_SCLK7 16
71#define AUD_CLKID_SLV_SCLK8 17
72#define AUD_CLKID_SLV_SCLK9 18
73#define AUD_CLKID_SLV_LRCLK0 19
74#define AUD_CLKID_SLV_LRCLK1 20
75#define AUD_CLKID_SLV_LRCLK2 21
76#define AUD_CLKID_SLV_LRCLK3 22
77#define AUD_CLKID_SLV_LRCLK4 23
78#define AUD_CLKID_SLV_LRCLK5 24
79#define AUD_CLKID_SLV_LRCLK6 25
80#define AUD_CLKID_SLV_LRCLK7 26
81#define AUD_CLKID_SLV_LRCLK8 27
82#define AUD_CLKID_SLV_LRCLK9 28
63#define AUD_CLKID_MST_A_MCLK_SEL 59 83#define AUD_CLKID_MST_A_MCLK_SEL 59
64#define AUD_CLKID_MST_B_MCLK_SEL 60 84#define AUD_CLKID_MST_B_MCLK_SEL 60
65#define AUD_CLKID_MST_C_MCLK_SEL 61 85#define AUD_CLKID_MST_C_MCLK_SEL 61
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 41e16dd7272a..6a88dd75ccf0 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -303,6 +303,16 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw)
303 return 1; 303 return 1;
304} 304}
305 305
306static int meson_clk_pcie_pll_enable(struct clk_hw *hw)
307{
308 meson_clk_pll_init(hw);
309
310 if (meson_clk_pll_wait_lock(hw))
311 return -EIO;
312
313 return 0;
314}
315
306static int meson_clk_pll_enable(struct clk_hw *hw) 316static int meson_clk_pll_enable(struct clk_hw *hw)
307{ 317{
308 struct clk_regmap *clk = to_clk_regmap(hw); 318 struct clk_regmap *clk = to_clk_regmap(hw);
@@ -387,6 +397,22 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
387 return 0; 397 return 0;
388} 398}
389 399
400/*
401 * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
402 * 100MHz reference clock for the PCIe Analog PHY, and thus requires
403 * a strict register sequence to enable the PLL.
404 * To simplify, re-use the _init() op to enable the PLL and keep
405 * the other ops except set_rate since the rate is fixed.
406 */
407const struct clk_ops meson_clk_pcie_pll_ops = {
408 .recalc_rate = meson_clk_pll_recalc_rate,
409 .round_rate = meson_clk_pll_round_rate,
410 .is_enabled = meson_clk_pll_is_enabled,
411 .enable = meson_clk_pcie_pll_enable,
412 .disable = meson_clk_pll_disable
413};
414EXPORT_SYMBOL_GPL(meson_clk_pcie_pll_ops);
415
390const struct clk_ops meson_clk_pll_ops = { 416const struct clk_ops meson_clk_pll_ops = {
391 .init = meson_clk_pll_init, 417 .init = meson_clk_pll_init,
392 .recalc_rate = meson_clk_pll_recalc_rate, 418 .recalc_rate = meson_clk_pll_recalc_rate,
diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h
index 55af2e285b1b..367efd0f6410 100644
--- a/drivers/clk/meson/clk-pll.h
+++ b/drivers/clk/meson/clk-pll.h
@@ -45,5 +45,6 @@ struct meson_clk_pll_data {
45 45
46extern const struct clk_ops meson_clk_pll_ro_ops; 46extern const struct clk_ops meson_clk_pll_ro_ops;
47extern const struct clk_ops meson_clk_pll_ops; 47extern const struct clk_ops meson_clk_pll_ops;
48extern const struct clk_ops meson_clk_pcie_pll_ops;
48 49
49#endif /* __MESON_CLK_PLL_H */ 50#endif /* __MESON_CLK_PLL_H */
diff --git a/drivers/clk/meson/g12a-aoclk.h b/drivers/clk/meson/g12a-aoclk.h
index 04b0d5506641..a67c8a7cd7c4 100644
--- a/drivers/clk/meson/g12a-aoclk.h
+++ b/drivers/clk/meson/g12a-aoclk.h
@@ -16,9 +16,7 @@
16 * to expose, such as the internal muxes and dividers of composite clocks, 16 * to expose, such as the internal muxes and dividers of composite clocks,
17 * will remain defined here. 17 * will remain defined here.
18 */ 18 */
19#define CLKID_AO_SAR_ADC_SEL 16
20#define CLKID_AO_SAR_ADC_DIV 17 19#define CLKID_AO_SAR_ADC_DIV 17
21#define CLKID_AO_CTS_OSCIN 19
22#define CLKID_AO_32K_PRE 20 20#define CLKID_AO_32K_PRE 20
23#define CLKID_AO_32K_DIV 21 21#define CLKID_AO_32K_DIV 21
24#define CLKID_AO_32K_SEL 22 22#define CLKID_AO_32K_SEL 22
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 0e1ce8c03259..86a7c1b5bd42 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -150,6 +150,318 @@ static struct clk_regmap g12a_sys_pll = {
150 }, 150 },
151}; 151};
152 152
153static struct clk_regmap g12a_sys_pll_div16_en = {
154 .data = &(struct clk_regmap_gate_data){
155 .offset = HHI_SYS_CPU_CLK_CNTL1,
156 .bit_idx = 24,
157 },
158 .hw.init = &(struct clk_init_data) {
159 .name = "sys_pll_div16_en",
160 .ops = &clk_regmap_gate_ro_ops,
161 .parent_names = (const char *[]){ "sys_pll" },
162 .num_parents = 1,
163 /*
164 * This clock is used to debug the sys_pll range
165 * Linux should not change it at runtime
166 */
167 },
168};
169
170static struct clk_fixed_factor g12a_sys_pll_div16 = {
171 .mult = 1,
172 .div = 16,
173 .hw.init = &(struct clk_init_data){
174 .name = "sys_pll_div16",
175 .ops = &clk_fixed_factor_ops,
176 .parent_names = (const char *[]){ "sys_pll_div16_en" },
177 .num_parents = 1,
178 },
179};
180
181/* Datasheet names this field as "premux0" */
182static struct clk_regmap g12a_cpu_clk_premux0 = {
183 .data = &(struct clk_regmap_mux_data){
184 .offset = HHI_SYS_CPU_CLK_CNTL0,
185 .mask = 0x3,
186 .shift = 0,
187 },
188 .hw.init = &(struct clk_init_data){
189 .name = "cpu_clk_dyn0_sel",
190 .ops = &clk_regmap_mux_ro_ops,
191 .parent_names = (const char *[]){ IN_PREFIX "xtal",
192 "fclk_div2",
193 "fclk_div3" },
194 .num_parents = 3,
195 },
196};
197
198/* Datasheet names this field as "mux0_divn_tcnt" */
199static struct clk_regmap g12a_cpu_clk_mux0_div = {
200 .data = &(struct clk_regmap_div_data){
201 .offset = HHI_SYS_CPU_CLK_CNTL0,
202 .shift = 4,
203 .width = 6,
204 },
205 .hw.init = &(struct clk_init_data){
206 .name = "cpu_clk_dyn0_div",
207 .ops = &clk_regmap_divider_ro_ops,
208 .parent_names = (const char *[]){ "cpu_clk_dyn0_sel" },
209 .num_parents = 1,
210 },
211};
212
213/* Datasheet names this field as "postmux0" */
214static struct clk_regmap g12a_cpu_clk_postmux0 = {
215 .data = &(struct clk_regmap_mux_data){
216 .offset = HHI_SYS_CPU_CLK_CNTL0,
217 .mask = 0x1,
218 .shift = 2,
219 },
220 .hw.init = &(struct clk_init_data){
221 .name = "cpu_clk_dyn0",
222 .ops = &clk_regmap_mux_ro_ops,
223 .parent_names = (const char *[]){ "cpu_clk_dyn0_sel",
224 "cpu_clk_dyn0_div" },
225 .num_parents = 2,
226 },
227};
228
229/* Datasheet names this field as "premux1" */
230static struct clk_regmap g12a_cpu_clk_premux1 = {
231 .data = &(struct clk_regmap_mux_data){
232 .offset = HHI_SYS_CPU_CLK_CNTL0,
233 .mask = 0x3,
234 .shift = 16,
235 },
236 .hw.init = &(struct clk_init_data){
237 .name = "cpu_clk_dyn1_sel",
238 .ops = &clk_regmap_mux_ro_ops,
239 .parent_names = (const char *[]){ IN_PREFIX "xtal",
240 "fclk_div2",
241 "fclk_div3" },
242 .num_parents = 3,
243 },
244};
245
246/* Datasheet names this field as "Mux1_divn_tcnt" */
247static struct clk_regmap g12a_cpu_clk_mux1_div = {
248 .data = &(struct clk_regmap_div_data){
249 .offset = HHI_SYS_CPU_CLK_CNTL0,
250 .shift = 20,
251 .width = 6,
252 },
253 .hw.init = &(struct clk_init_data){
254 .name = "cpu_clk_dyn1_div",
255 .ops = &clk_regmap_divider_ro_ops,
256 .parent_names = (const char *[]){ "cpu_clk_dyn1_sel" },
257 .num_parents = 1,
258 },
259};
260
261/* Datasheet names this field as "postmux1" */
262static struct clk_regmap g12a_cpu_clk_postmux1 = {
263 .data = &(struct clk_regmap_mux_data){
264 .offset = HHI_SYS_CPU_CLK_CNTL0,
265 .mask = 0x1,
266 .shift = 18,
267 },
268 .hw.init = &(struct clk_init_data){
269 .name = "cpu_clk_dyn1",
270 .ops = &clk_regmap_mux_ro_ops,
271 .parent_names = (const char *[]){ "cpu_clk_dyn1_sel",
272 "cpu_clk_dyn1_div" },
273 .num_parents = 2,
274 },
275};
276
277/* Datasheet names this field as "Final_dyn_mux_sel" */
278static struct clk_regmap g12a_cpu_clk_dyn = {
279 .data = &(struct clk_regmap_mux_data){
280 .offset = HHI_SYS_CPU_CLK_CNTL0,
281 .mask = 0x1,
282 .shift = 10,
283 },
284 .hw.init = &(struct clk_init_data){
285 .name = "cpu_clk_dyn",
286 .ops = &clk_regmap_mux_ro_ops,
287 .parent_names = (const char *[]){ "cpu_clk_dyn0",
288 "cpu_clk_dyn1" },
289 .num_parents = 2,
290 },
291};
292
293/* Datasheet names this field as "Final_mux_sel" */
294static struct clk_regmap g12a_cpu_clk = {
295 .data = &(struct clk_regmap_mux_data){
296 .offset = HHI_SYS_CPU_CLK_CNTL0,
297 .mask = 0x1,
298 .shift = 11,
299 },
300 .hw.init = &(struct clk_init_data){
301 .name = "cpu_clk",
302 .ops = &clk_regmap_mux_ro_ops,
303 .parent_names = (const char *[]){ "cpu_clk_dyn",
304 "sys_pll" },
305 .num_parents = 2,
306 },
307};
308
309static struct clk_regmap g12a_cpu_clk_div16_en = {
310 .data = &(struct clk_regmap_gate_data){
311 .offset = HHI_SYS_CPU_CLK_CNTL1,
312 .bit_idx = 1,
313 },
314 .hw.init = &(struct clk_init_data) {
315 .name = "cpu_clk_div16_en",
316 .ops = &clk_regmap_gate_ro_ops,
317 .parent_names = (const char *[]){ "cpu_clk" },
318 .num_parents = 1,
319 /*
320 * This clock is used to debug the cpu_clk range
321 * Linux should not change it at runtime
322 */
323 },
324};
325
326static struct clk_fixed_factor g12a_cpu_clk_div16 = {
327 .mult = 1,
328 .div = 16,
329 .hw.init = &(struct clk_init_data){
330 .name = "cpu_clk_div16",
331 .ops = &clk_fixed_factor_ops,
332 .parent_names = (const char *[]){ "cpu_clk_div16_en" },
333 .num_parents = 1,
334 },
335};
336
337static struct clk_regmap g12a_cpu_clk_apb_div = {
338 .data = &(struct clk_regmap_div_data){
339 .offset = HHI_SYS_CPU_CLK_CNTL1,
340 .shift = 3,
341 .width = 3,
342 .flags = CLK_DIVIDER_POWER_OF_TWO,
343 },
344 .hw.init = &(struct clk_init_data){
345 .name = "cpu_clk_apb_div",
346 .ops = &clk_regmap_divider_ro_ops,
347 .parent_names = (const char *[]){ "cpu_clk" },
348 .num_parents = 1,
349 },
350};
351
352static struct clk_regmap g12a_cpu_clk_apb = {
353 .data = &(struct clk_regmap_gate_data){
354 .offset = HHI_SYS_CPU_CLK_CNTL1,
355 .bit_idx = 1,
356 },
357 .hw.init = &(struct clk_init_data) {
358 .name = "cpu_clk_apb",
359 .ops = &clk_regmap_gate_ro_ops,
360 .parent_names = (const char *[]){ "cpu_clk_apb_div" },
361 .num_parents = 1,
362 /*
363 * This clock is set by the ROM monitor code,
364 * Linux should not change it at runtime
365 */
366 },
367};
368
369static struct clk_regmap g12a_cpu_clk_atb_div = {
370 .data = &(struct clk_regmap_div_data){
371 .offset = HHI_SYS_CPU_CLK_CNTL1,
372 .shift = 6,
373 .width = 3,
374 .flags = CLK_DIVIDER_POWER_OF_TWO,
375 },
376 .hw.init = &(struct clk_init_data){
377 .name = "cpu_clk_atb_div",
378 .ops = &clk_regmap_divider_ro_ops,
379 .parent_names = (const char *[]){ "cpu_clk" },
380 .num_parents = 1,
381 },
382};
383
384static struct clk_regmap g12a_cpu_clk_atb = {
385 .data = &(struct clk_regmap_gate_data){
386 .offset = HHI_SYS_CPU_CLK_CNTL1,
387 .bit_idx = 17,
388 },
389 .hw.init = &(struct clk_init_data) {
390 .name = "cpu_clk_atb",
391 .ops = &clk_regmap_gate_ro_ops,
392 .parent_names = (const char *[]){ "cpu_clk_atb_div" },
393 .num_parents = 1,
394 /*
395 * This clock is set by the ROM monitor code,
396 * Linux should not change it at runtime
397 */
398 },
399};
400
401static struct clk_regmap g12a_cpu_clk_axi_div = {
402 .data = &(struct clk_regmap_div_data){
403 .offset = HHI_SYS_CPU_CLK_CNTL1,
404 .shift = 9,
405 .width = 3,
406 .flags = CLK_DIVIDER_POWER_OF_TWO,
407 },
408 .hw.init = &(struct clk_init_data){
409 .name = "cpu_clk_axi_div",
410 .ops = &clk_regmap_divider_ro_ops,
411 .parent_names = (const char *[]){ "cpu_clk" },
412 .num_parents = 1,
413 },
414};
415
416static struct clk_regmap g12a_cpu_clk_axi = {
417 .data = &(struct clk_regmap_gate_data){
418 .offset = HHI_SYS_CPU_CLK_CNTL1,
419 .bit_idx = 18,
420 },
421 .hw.init = &(struct clk_init_data) {
422 .name = "cpu_clk_axi",
423 .ops = &clk_regmap_gate_ro_ops,
424 .parent_names = (const char *[]){ "cpu_clk_axi_div" },
425 .num_parents = 1,
426 /*
427 * This clock is set by the ROM monitor code,
428 * Linux should not change it at runtime
429 */
430 },
431};
432
433static struct clk_regmap g12a_cpu_clk_trace_div = {
434 .data = &(struct clk_regmap_div_data){
435 .offset = HHI_SYS_CPU_CLK_CNTL1,
436 .shift = 20,
437 .width = 3,
438 .flags = CLK_DIVIDER_POWER_OF_TWO,
439 },
440 .hw.init = &(struct clk_init_data){
441 .name = "cpu_clk_trace_div",
442 .ops = &clk_regmap_divider_ro_ops,
443 .parent_names = (const char *[]){ "cpu_clk" },
444 .num_parents = 1,
445 },
446};
447
448static struct clk_regmap g12a_cpu_clk_trace = {
449 .data = &(struct clk_regmap_gate_data){
450 .offset = HHI_SYS_CPU_CLK_CNTL1,
451 .bit_idx = 23,
452 },
453 .hw.init = &(struct clk_init_data) {
454 .name = "cpu_clk_trace",
455 .ops = &clk_regmap_gate_ro_ops,
456 .parent_names = (const char *[]){ "cpu_clk_trace_div" },
457 .num_parents = 1,
458 /*
459 * This clock is set by the ROM monitor code,
460 * Linux should not change it at runtime
461 */
462 },
463};
464
153static const struct pll_mult_range g12a_gp0_pll_mult_range = { 465static const struct pll_mult_range g12a_gp0_pll_mult_range = {
154 .min = 55, 466 .min = 55,
155 .max = 255, 467 .max = 255,
@@ -302,6 +614,118 @@ static struct clk_regmap g12a_hifi_pll = {
302 }, 614 },
303}; 615};
304 616
617/*
618 * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
619 * 100MHz reference clock for the PCIe Analog PHY, and thus requires
620 * a strict register sequence to enable the PLL.
621 */
622static const struct reg_sequence g12a_pcie_pll_init_regs[] = {
623 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x20090496 },
624 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x30090496 },
625 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x00000000 },
626 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001100 },
627 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x10058e00 },
628 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x000100c0 },
629 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000048 },
630 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000068, .delay_us = 20 },
631 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x008100c0, .delay_us = 10 },
632 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x34090496 },
633 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x14090496, .delay_us = 10 },
634 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001000 },
635};
636
637/* Keep a single entry table for recalc/round_rate() ops */
638static const struct pll_params_table g12a_pcie_pll_table[] = {
639 PLL_PARAMS(150, 1),
640 {0, 0},
641};
642
643static struct clk_regmap g12a_pcie_pll_dco = {
644 .data = &(struct meson_clk_pll_data){
645 .en = {
646 .reg_off = HHI_PCIE_PLL_CNTL0,
647 .shift = 28,
648 .width = 1,
649 },
650 .m = {
651 .reg_off = HHI_PCIE_PLL_CNTL0,
652 .shift = 0,
653 .width = 8,
654 },
655 .n = {
656 .reg_off = HHI_PCIE_PLL_CNTL0,
657 .shift = 10,
658 .width = 5,
659 },
660 .frac = {
661 .reg_off = HHI_PCIE_PLL_CNTL1,
662 .shift = 0,
663 .width = 12,
664 },
665 .l = {
666 .reg_off = HHI_PCIE_PLL_CNTL0,
667 .shift = 31,
668 .width = 1,
669 },
670 .rst = {
671 .reg_off = HHI_PCIE_PLL_CNTL0,
672 .shift = 29,
673 .width = 1,
674 },
675 .table = g12a_pcie_pll_table,
676 .init_regs = g12a_pcie_pll_init_regs,
677 .init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs),
678 },
679 .hw.init = &(struct clk_init_data){
680 .name = "pcie_pll_dco",
681 .ops = &meson_clk_pcie_pll_ops,
682 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
683 .num_parents = 1,
684 },
685};
686
687static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {
688 .mult = 1,
689 .div = 2,
690 .hw.init = &(struct clk_init_data){
691 .name = "pcie_pll_dco_div2",
692 .ops = &clk_fixed_factor_ops,
693 .parent_names = (const char *[]){ "pcie_pll_dco" },
694 .num_parents = 1,
695 .flags = CLK_SET_RATE_PARENT,
696 },
697};
698
699static struct clk_regmap g12a_pcie_pll_od = {
700 .data = &(struct clk_regmap_div_data){
701 .offset = HHI_PCIE_PLL_CNTL0,
702 .shift = 16,
703 .width = 5,
704 .flags = CLK_DIVIDER_ROUND_CLOSEST |
705 CLK_DIVIDER_ONE_BASED |
706 CLK_DIVIDER_ALLOW_ZERO,
707 },
708 .hw.init = &(struct clk_init_data){
709 .name = "pcie_pll_od",
710 .ops = &clk_regmap_divider_ops,
711 .parent_names = (const char *[]){ "pcie_pll_dco_div2" },
712 .num_parents = 1,
713 .flags = CLK_SET_RATE_PARENT,
714 },
715};
716
717static struct clk_fixed_factor g12a_pcie_pll = {
718 .mult = 1,
719 .div = 2,
720 .hw.init = &(struct clk_init_data){
721 .name = "pcie_pll_pll",
722 .ops = &clk_fixed_factor_ops,
723 .parent_names = (const char *[]){ "pcie_pll_od" },
724 .num_parents = 1,
725 .flags = CLK_SET_RATE_PARENT,
726 },
727};
728
305static struct clk_regmap g12a_hdmi_pll_dco = { 729static struct clk_regmap g12a_hdmi_pll_dco = {
306 .data = &(struct meson_clk_pll_data){ 730 .data = &(struct meson_clk_pll_data){
307 .en = { 731 .en = {
@@ -1071,6 +1495,151 @@ static struct clk_regmap g12a_vpu = {
1071 }, 1495 },
1072}; 1496};
1073 1497
1498/* VDEC clocks */
1499
1500static const char * const g12a_vdec_parent_names[] = {
1501 "fclk_div2p5", "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7",
1502 "hifi_pll", "gp0_pll",
1503};
1504
1505static struct clk_regmap g12a_vdec_1_sel = {
1506 .data = &(struct clk_regmap_mux_data){
1507 .offset = HHI_VDEC_CLK_CNTL,
1508 .mask = 0x7,
1509 .shift = 9,
1510 .flags = CLK_MUX_ROUND_CLOSEST,
1511 },
1512 .hw.init = &(struct clk_init_data){
1513 .name = "vdec_1_sel",
1514 .ops = &clk_regmap_mux_ops,
1515 .parent_names = g12a_vdec_parent_names,
1516 .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
1517 .flags = CLK_SET_RATE_PARENT,
1518 },
1519};
1520
1521static struct clk_regmap g12a_vdec_1_div = {
1522 .data = &(struct clk_regmap_div_data){
1523 .offset = HHI_VDEC_CLK_CNTL,
1524 .shift = 0,
1525 .width = 7,
1526 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1527 },
1528 .hw.init = &(struct clk_init_data){
1529 .name = "vdec_1_div",
1530 .ops = &clk_regmap_divider_ops,
1531 .parent_names = (const char *[]){ "vdec_1_sel" },
1532 .num_parents = 1,
1533 .flags = CLK_SET_RATE_PARENT,
1534 },
1535};
1536
1537static struct clk_regmap g12a_vdec_1 = {
1538 .data = &(struct clk_regmap_gate_data){
1539 .offset = HHI_VDEC_CLK_CNTL,
1540 .bit_idx = 8,
1541 },
1542 .hw.init = &(struct clk_init_data) {
1543 .name = "vdec_1",
1544 .ops = &clk_regmap_gate_ops,
1545 .parent_names = (const char *[]){ "vdec_1_div" },
1546 .num_parents = 1,
1547 .flags = CLK_SET_RATE_PARENT,
1548 },
1549};
1550
1551static struct clk_regmap g12a_vdec_hevcf_sel = {
1552 .data = &(struct clk_regmap_mux_data){
1553 .offset = HHI_VDEC2_CLK_CNTL,
1554 .mask = 0x7,
1555 .shift = 9,
1556 .flags = CLK_MUX_ROUND_CLOSEST,
1557 },
1558 .hw.init = &(struct clk_init_data){
1559 .name = "vdec_hevcf_sel",
1560 .ops = &clk_regmap_mux_ops,
1561 .parent_names = g12a_vdec_parent_names,
1562 .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
1563 .flags = CLK_SET_RATE_PARENT,
1564 },
1565};
1566
1567static struct clk_regmap g12a_vdec_hevcf_div = {
1568 .data = &(struct clk_regmap_div_data){
1569 .offset = HHI_VDEC2_CLK_CNTL,
1570 .shift = 0,
1571 .width = 7,
1572 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1573 },
1574 .hw.init = &(struct clk_init_data){
1575 .name = "vdec_hevcf_div",
1576 .ops = &clk_regmap_divider_ops,
1577 .parent_names = (const char *[]){ "vdec_hevcf_sel" },
1578 .num_parents = 1,
1579 .flags = CLK_SET_RATE_PARENT,
1580 },
1581};
1582
1583static struct clk_regmap g12a_vdec_hevcf = {
1584 .data = &(struct clk_regmap_gate_data){
1585 .offset = HHI_VDEC2_CLK_CNTL,
1586 .bit_idx = 8,
1587 },
1588 .hw.init = &(struct clk_init_data) {
1589 .name = "vdec_hevcf",
1590 .ops = &clk_regmap_gate_ops,
1591 .parent_names = (const char *[]){ "vdec_hevcf_div" },
1592 .num_parents = 1,
1593 .flags = CLK_SET_RATE_PARENT,
1594 },
1595};
1596
1597static struct clk_regmap g12a_vdec_hevc_sel = {
1598 .data = &(struct clk_regmap_mux_data){
1599 .offset = HHI_VDEC2_CLK_CNTL,
1600 .mask = 0x7,
1601 .shift = 25,
1602 .flags = CLK_MUX_ROUND_CLOSEST,
1603 },
1604 .hw.init = &(struct clk_init_data){
1605 .name = "vdec_hevc_sel",
1606 .ops = &clk_regmap_mux_ops,
1607 .parent_names = g12a_vdec_parent_names,
1608 .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
1609 .flags = CLK_SET_RATE_PARENT,
1610 },
1611};
1612
1613static struct clk_regmap g12a_vdec_hevc_div = {
1614 .data = &(struct clk_regmap_div_data){
1615 .offset = HHI_VDEC2_CLK_CNTL,
1616 .shift = 16,
1617 .width = 7,
1618 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1619 },
1620 .hw.init = &(struct clk_init_data){
1621 .name = "vdec_hevc_div",
1622 .ops = &clk_regmap_divider_ops,
1623 .parent_names = (const char *[]){ "vdec_hevc_sel" },
1624 .num_parents = 1,
1625 .flags = CLK_SET_RATE_PARENT,
1626 },
1627};
1628
1629static struct clk_regmap g12a_vdec_hevc = {
1630 .data = &(struct clk_regmap_gate_data){
1631 .offset = HHI_VDEC2_CLK_CNTL,
1632 .bit_idx = 24,
1633 },
1634 .hw.init = &(struct clk_init_data) {
1635 .name = "vdec_hevc",
1636 .ops = &clk_regmap_gate_ops,
1637 .parent_names = (const char *[]){ "vdec_hevc_div" },
1638 .num_parents = 1,
1639 .flags = CLK_SET_RATE_PARENT,
1640 },
1641};
1642
1074/* VAPB Clock */ 1643/* VAPB Clock */
1075 1644
1076static const char * const g12a_vapb_parent_names[] = { 1645static const char * const g12a_vapb_parent_names[] = {
@@ -2167,6 +2736,39 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
2167 [CLKID_MALI] = &g12a_mali.hw, 2736 [CLKID_MALI] = &g12a_mali.hw,
2168 [CLKID_MPLL_5OM_DIV] = &g12a_mpll_50m_div.hw, 2737 [CLKID_MPLL_5OM_DIV] = &g12a_mpll_50m_div.hw,
2169 [CLKID_MPLL_5OM] = &g12a_mpll_50m.hw, 2738 [CLKID_MPLL_5OM] = &g12a_mpll_50m.hw,
2739 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
2740 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
2741 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
2742 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
2743 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
2744 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
2745 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
2746 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
2747 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
2748 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
2749 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
2750 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
2751 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
2752 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
2753 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
2754 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
2755 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
2756 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
2757 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
2758 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
2759 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
2760 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
2761 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
2762 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
2763 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
2764 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
2765 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
2766 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
2767 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
2768 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
2769 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
2770 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
2771 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
2170 [NR_CLKS] = NULL, 2772 [NR_CLKS] = NULL,
2171 }, 2773 },
2172 .num = NR_CLKS, 2774 .num = NR_CLKS,
@@ -2335,6 +2937,35 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
2335 &g12a_mali_1, 2937 &g12a_mali_1,
2336 &g12a_mali, 2938 &g12a_mali,
2337 &g12a_mpll_50m, 2939 &g12a_mpll_50m,
2940 &g12a_sys_pll_div16_en,
2941 &g12a_cpu_clk_premux0,
2942 &g12a_cpu_clk_mux0_div,
2943 &g12a_cpu_clk_postmux0,
2944 &g12a_cpu_clk_premux1,
2945 &g12a_cpu_clk_mux1_div,
2946 &g12a_cpu_clk_postmux1,
2947 &g12a_cpu_clk_dyn,
2948 &g12a_cpu_clk,
2949 &g12a_cpu_clk_div16_en,
2950 &g12a_cpu_clk_apb_div,
2951 &g12a_cpu_clk_apb,
2952 &g12a_cpu_clk_atb_div,
2953 &g12a_cpu_clk_atb,
2954 &g12a_cpu_clk_axi_div,
2955 &g12a_cpu_clk_axi,
2956 &g12a_cpu_clk_trace_div,
2957 &g12a_cpu_clk_trace,
2958 &g12a_pcie_pll_od,
2959 &g12a_pcie_pll_dco,
2960 &g12a_vdec_1_sel,
2961 &g12a_vdec_1_div,
2962 &g12a_vdec_1,
2963 &g12a_vdec_hevc_sel,
2964 &g12a_vdec_hevc_div,
2965 &g12a_vdec_hevc,
2966 &g12a_vdec_hevcf_sel,
2967 &g12a_vdec_hevcf_div,
2968 &g12a_vdec_hevcf,
2338}; 2969};
2339 2970
2340static const struct meson_eeclkc_data g12a_clkc_data = { 2971static const struct meson_eeclkc_data g12a_clkc_data = {
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index f399dfe1401c..39c41af70804 100644
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -50,6 +50,7 @@
50#define HHI_GCLK_MPEG2 0x148 50#define HHI_GCLK_MPEG2 0x148
51#define HHI_GCLK_OTHER 0x150 51#define HHI_GCLK_OTHER 0x150
52#define HHI_GCLK_OTHER2 0x154 52#define HHI_GCLK_OTHER2 0x154
53#define HHI_SYS_CPU_CLK_CNTL1 0x15c
53#define HHI_VID_CLK_DIV 0x164 54#define HHI_VID_CLK_DIV 0x164
54#define HHI_MPEG_CLK_CNTL 0x174 55#define HHI_MPEG_CLK_CNTL 0x174
55#define HHI_AUD_CLK_CNTL 0x178 56#define HHI_AUD_CLK_CNTL 0x178
@@ -166,8 +167,36 @@
166#define CLKID_MALI_0_DIV 170 167#define CLKID_MALI_0_DIV 170
167#define CLKID_MALI_1_DIV 173 168#define CLKID_MALI_1_DIV 173
168#define CLKID_MPLL_5OM_DIV 176 169#define CLKID_MPLL_5OM_DIV 176
170#define CLKID_SYS_PLL_DIV16_EN 178
171#define CLKID_SYS_PLL_DIV16 179
172#define CLKID_CPU_CLK_DYN0_SEL 180
173#define CLKID_CPU_CLK_DYN0_DIV 181
174#define CLKID_CPU_CLK_DYN0 182
175#define CLKID_CPU_CLK_DYN1_SEL 183
176#define CLKID_CPU_CLK_DYN1_DIV 184
177#define CLKID_CPU_CLK_DYN1 185
178#define CLKID_CPU_CLK_DYN 186
179#define CLKID_CPU_CLK_DIV16_EN 188
180#define CLKID_CPU_CLK_DIV16 189
181#define CLKID_CPU_CLK_APB_DIV 190
182#define CLKID_CPU_CLK_APB 191
183#define CLKID_CPU_CLK_ATB_DIV 192
184#define CLKID_CPU_CLK_ATB 193
185#define CLKID_CPU_CLK_AXI_DIV 194
186#define CLKID_CPU_CLK_AXI 195
187#define CLKID_CPU_CLK_TRACE_DIV 196
188#define CLKID_CPU_CLK_TRACE 197
189#define CLKID_PCIE_PLL_DCO 198
190#define CLKID_PCIE_PLL_DCO_DIV2 199
191#define CLKID_PCIE_PLL_OD 200
192#define CLKID_VDEC_1_SEL 202
193#define CLKID_VDEC_1_DIV 203
194#define CLKID_VDEC_HEVC_SEL 205
195#define CLKID_VDEC_HEVC_DIV 206
196#define CLKID_VDEC_HEVCF_SEL 208
197#define CLKID_VDEC_HEVCF_DIV 209
169 198
170#define NR_CLKS 178 199#define NR_CLKS 211
171 200
172/* include the CLKIDs that have been made part of the DT binding */ 201/* include the CLKIDs that have been made part of the DT binding */
173#include <dt-bindings/clock/g12a-clkc.h> 202#include <dt-bindings/clock/g12a-clkc.h>
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 576ad42252d0..37cf0f01bb5d 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -1703,6 +1703,456 @@ static struct clk_regmap meson8b_mali = {
1703 }, 1703 },
1704}; 1704};
1705 1705
1706static const struct pll_params_table meson8m2_gp_pll_params_table[] = {
1707 PLL_PARAMS(182, 3),
1708 { /* sentinel */ },
1709};
1710
1711static struct clk_regmap meson8m2_gp_pll_dco = {
1712 .data = &(struct meson_clk_pll_data){
1713 .en = {
1714 .reg_off = HHI_GP_PLL_CNTL,
1715 .shift = 30,
1716 .width = 1,
1717 },
1718 .m = {
1719 .reg_off = HHI_GP_PLL_CNTL,
1720 .shift = 0,
1721 .width = 9,
1722 },
1723 .n = {
1724 .reg_off = HHI_GP_PLL_CNTL,
1725 .shift = 9,
1726 .width = 5,
1727 },
1728 .l = {
1729 .reg_off = HHI_GP_PLL_CNTL,
1730 .shift = 31,
1731 .width = 1,
1732 },
1733 .rst = {
1734 .reg_off = HHI_GP_PLL_CNTL,
1735 .shift = 29,
1736 .width = 1,
1737 },
1738 .table = meson8m2_gp_pll_params_table,
1739 },
1740 .hw.init = &(struct clk_init_data){
1741 .name = "gp_pll_dco",
1742 .ops = &meson_clk_pll_ops,
1743 .parent_names = (const char *[]){ "xtal" },
1744 .num_parents = 1,
1745 },
1746};
1747
1748static struct clk_regmap meson8m2_gp_pll = {
1749 .data = &(struct clk_regmap_div_data){
1750 .offset = HHI_GP_PLL_CNTL,
1751 .shift = 16,
1752 .width = 2,
1753 .flags = CLK_DIVIDER_POWER_OF_TWO,
1754 },
1755 .hw.init = &(struct clk_init_data){
1756 .name = "gp_pll",
1757 .ops = &clk_regmap_divider_ops,
1758 .parent_names = (const char *[]){ "gp_pll_dco" },
1759 .num_parents = 1,
1760 .flags = CLK_SET_RATE_PARENT,
1761 },
1762};
1763
1764static const char * const mmeson8b_vpu_0_1_parent_names[] = {
1765 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1766};
1767
1768static const char * const mmeson8m2_vpu_0_1_parent_names[] = {
1769 "fclk_div4", "fclk_div3", "fclk_div5", "gp_pll"
1770};
1771
1772static struct clk_regmap meson8b_vpu_0_sel = {
1773 .data = &(struct clk_regmap_mux_data){
1774 .offset = HHI_VPU_CLK_CNTL,
1775 .mask = 0x3,
1776 .shift = 9,
1777 },
1778 .hw.init = &(struct clk_init_data){
1779 .name = "vpu_0_sel",
1780 .ops = &clk_regmap_mux_ops,
1781 .parent_names = mmeson8b_vpu_0_1_parent_names,
1782 .num_parents = ARRAY_SIZE(mmeson8b_vpu_0_1_parent_names),
1783 .flags = CLK_SET_RATE_PARENT,
1784 },
1785};
1786
1787static struct clk_regmap meson8m2_vpu_0_sel = {
1788 .data = &(struct clk_regmap_mux_data){
1789 .offset = HHI_VPU_CLK_CNTL,
1790 .mask = 0x3,
1791 .shift = 9,
1792 },
1793 .hw.init = &(struct clk_init_data){
1794 .name = "vpu_0_sel",
1795 .ops = &clk_regmap_mux_ops,
1796 .parent_names = mmeson8m2_vpu_0_1_parent_names,
1797 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_names),
1798 .flags = CLK_SET_RATE_PARENT,
1799 },
1800};
1801
1802static struct clk_regmap meson8b_vpu_0_div = {
1803 .data = &(struct clk_regmap_div_data){
1804 .offset = HHI_VPU_CLK_CNTL,
1805 .shift = 0,
1806 .width = 7,
1807 },
1808 .hw.init = &(struct clk_init_data){
1809 .name = "vpu_0_div",
1810 .ops = &clk_regmap_divider_ops,
1811 .parent_names = (const char *[]){ "vpu_0_sel" },
1812 .num_parents = 1,
1813 .flags = CLK_SET_RATE_PARENT,
1814 },
1815};
1816
1817static struct clk_regmap meson8b_vpu_0 = {
1818 .data = &(struct clk_regmap_gate_data){
1819 .offset = HHI_VPU_CLK_CNTL,
1820 .bit_idx = 8,
1821 },
1822 .hw.init = &(struct clk_init_data) {
1823 .name = "vpu_0",
1824 .ops = &clk_regmap_gate_ops,
1825 .parent_names = (const char *[]){ "vpu_0_div" },
1826 .num_parents = 1,
1827 .flags = CLK_SET_RATE_PARENT,
1828 },
1829};
1830
1831static struct clk_regmap meson8b_vpu_1_sel = {
1832 .data = &(struct clk_regmap_mux_data){
1833 .offset = HHI_VPU_CLK_CNTL,
1834 .mask = 0x3,
1835 .shift = 25,
1836 },
1837 .hw.init = &(struct clk_init_data){
1838 .name = "vpu_1_sel",
1839 .ops = &clk_regmap_mux_ops,
1840 .parent_names = mmeson8b_vpu_0_1_parent_names,
1841 .num_parents = ARRAY_SIZE(mmeson8b_vpu_0_1_parent_names),
1842 .flags = CLK_SET_RATE_PARENT,
1843 },
1844};
1845
1846static struct clk_regmap meson8m2_vpu_1_sel = {
1847 .data = &(struct clk_regmap_mux_data){
1848 .offset = HHI_VPU_CLK_CNTL,
1849 .mask = 0x3,
1850 .shift = 25,
1851 },
1852 .hw.init = &(struct clk_init_data){
1853 .name = "vpu_1_sel",
1854 .ops = &clk_regmap_mux_ops,
1855 .parent_names = mmeson8m2_vpu_0_1_parent_names,
1856 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_names),
1857 .flags = CLK_SET_RATE_PARENT,
1858 },
1859};
1860
1861static struct clk_regmap meson8b_vpu_1_div = {
1862 .data = &(struct clk_regmap_div_data){
1863 .offset = HHI_VPU_CLK_CNTL,
1864 .shift = 16,
1865 .width = 7,
1866 },
1867 .hw.init = &(struct clk_init_data){
1868 .name = "vpu_1_div",
1869 .ops = &clk_regmap_divider_ops,
1870 .parent_names = (const char *[]){ "vpu_1_sel" },
1871 .num_parents = 1,
1872 .flags = CLK_SET_RATE_PARENT,
1873 },
1874};
1875
1876static struct clk_regmap meson8b_vpu_1 = {
1877 .data = &(struct clk_regmap_gate_data){
1878 .offset = HHI_VPU_CLK_CNTL,
1879 .bit_idx = 24,
1880 },
1881 .hw.init = &(struct clk_init_data) {
1882 .name = "vpu_1",
1883 .ops = &clk_regmap_gate_ops,
1884 .parent_names = (const char *[]){ "vpu_1_div" },
1885 .num_parents = 1,
1886 .flags = CLK_SET_RATE_PARENT,
1887 },
1888};
1889
1890static struct clk_regmap meson8b_vpu = {
1891 .data = &(struct clk_regmap_mux_data){
1892 .offset = HHI_VPU_CLK_CNTL,
1893 .mask = 1,
1894 .shift = 31,
1895 },
1896 .hw.init = &(struct clk_init_data){
1897 .name = "vpu",
1898 .ops = &clk_regmap_mux_ops,
1899 .parent_names = (const char *[]){ "vpu_0", "vpu_1" },
1900 .num_parents = 2,
1901 .flags = CLK_SET_RATE_NO_REPARENT,
1902 },
1903};
1904
1905static const char * const meson8b_vdec_parent_names[] = {
1906 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "mpll2", "mpll1"
1907};
1908
1909static struct clk_regmap meson8b_vdec_1_sel = {
1910 .data = &(struct clk_regmap_mux_data){
1911 .offset = HHI_VDEC_CLK_CNTL,
1912 .mask = 0x3,
1913 .shift = 9,
1914 .flags = CLK_MUX_ROUND_CLOSEST,
1915 },
1916 .hw.init = &(struct clk_init_data){
1917 .name = "vdec_1_sel",
1918 .ops = &clk_regmap_mux_ops,
1919 .parent_names = meson8b_vdec_parent_names,
1920 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
1921 .flags = CLK_SET_RATE_PARENT,
1922 },
1923};
1924
1925static struct clk_regmap meson8b_vdec_1_1_div = {
1926 .data = &(struct clk_regmap_div_data){
1927 .offset = HHI_VDEC_CLK_CNTL,
1928 .shift = 0,
1929 .width = 7,
1930 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1931 },
1932 .hw.init = &(struct clk_init_data){
1933 .name = "vdec_1_1_div",
1934 .ops = &clk_regmap_divider_ops,
1935 .parent_names = (const char *[]){ "vdec_1_sel" },
1936 .num_parents = 1,
1937 .flags = CLK_SET_RATE_PARENT,
1938 },
1939};
1940
1941static struct clk_regmap meson8b_vdec_1_1 = {
1942 .data = &(struct clk_regmap_gate_data){
1943 .offset = HHI_VDEC_CLK_CNTL,
1944 .bit_idx = 8,
1945 },
1946 .hw.init = &(struct clk_init_data) {
1947 .name = "vdec_1_1",
1948 .ops = &clk_regmap_gate_ops,
1949 .parent_names = (const char *[]){ "vdec_1_1_div" },
1950 .num_parents = 1,
1951 .flags = CLK_SET_RATE_PARENT,
1952 },
1953};
1954
1955static struct clk_regmap meson8b_vdec_1_2_div = {
1956 .data = &(struct clk_regmap_div_data){
1957 .offset = HHI_VDEC3_CLK_CNTL,
1958 .shift = 0,
1959 .width = 7,
1960 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1961 },
1962 .hw.init = &(struct clk_init_data){
1963 .name = "vdec_1_2_div",
1964 .ops = &clk_regmap_divider_ops,
1965 .parent_names = (const char *[]){ "vdec_1_sel" },
1966 .num_parents = 1,
1967 .flags = CLK_SET_RATE_PARENT,
1968 },
1969};
1970
1971static struct clk_regmap meson8b_vdec_1_2 = {
1972 .data = &(struct clk_regmap_gate_data){
1973 .offset = HHI_VDEC3_CLK_CNTL,
1974 .bit_idx = 8,
1975 },
1976 .hw.init = &(struct clk_init_data) {
1977 .name = "vdec_1_2",
1978 .ops = &clk_regmap_gate_ops,
1979 .parent_names = (const char *[]){ "vdec_1_2_div" },
1980 .num_parents = 1,
1981 .flags = CLK_SET_RATE_PARENT,
1982 },
1983};
1984
1985static struct clk_regmap meson8b_vdec_1 = {
1986 .data = &(struct clk_regmap_mux_data){
1987 .offset = HHI_VDEC3_CLK_CNTL,
1988 .mask = 0x1,
1989 .shift = 15,
1990 .flags = CLK_MUX_ROUND_CLOSEST,
1991 },
1992 .hw.init = &(struct clk_init_data){
1993 .name = "vdec_1",
1994 .ops = &clk_regmap_mux_ops,
1995 .parent_names = (const char *[]){ "vdec_1_1", "vdec_1_2" },
1996 .num_parents = 2,
1997 .flags = CLK_SET_RATE_PARENT,
1998 },
1999};
2000
2001static struct clk_regmap meson8b_vdec_hcodec_sel = {
2002 .data = &(struct clk_regmap_mux_data){
2003 .offset = HHI_VDEC_CLK_CNTL,
2004 .mask = 0x3,
2005 .shift = 25,
2006 .flags = CLK_MUX_ROUND_CLOSEST,
2007 },
2008 .hw.init = &(struct clk_init_data){
2009 .name = "vdec_hcodec_sel",
2010 .ops = &clk_regmap_mux_ops,
2011 .parent_names = meson8b_vdec_parent_names,
2012 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
2013 .flags = CLK_SET_RATE_PARENT,
2014 },
2015};
2016
2017static struct clk_regmap meson8b_vdec_hcodec_div = {
2018 .data = &(struct clk_regmap_div_data){
2019 .offset = HHI_VDEC_CLK_CNTL,
2020 .shift = 16,
2021 .width = 7,
2022 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2023 },
2024 .hw.init = &(struct clk_init_data){
2025 .name = "vdec_hcodec_div",
2026 .ops = &clk_regmap_divider_ops,
2027 .parent_names = (const char *[]){ "vdec_hcodec_sel" },
2028 .num_parents = 1,
2029 .flags = CLK_SET_RATE_PARENT,
2030 },
2031};
2032
2033static struct clk_regmap meson8b_vdec_hcodec = {
2034 .data = &(struct clk_regmap_gate_data){
2035 .offset = HHI_VDEC_CLK_CNTL,
2036 .bit_idx = 24,
2037 },
2038 .hw.init = &(struct clk_init_data) {
2039 .name = "vdec_hcodec",
2040 .ops = &clk_regmap_gate_ops,
2041 .parent_names = (const char *[]){ "vdec_hcodec_div" },
2042 .num_parents = 1,
2043 .flags = CLK_SET_RATE_PARENT,
2044 },
2045};
2046
2047static struct clk_regmap meson8b_vdec_2_sel = {
2048 .data = &(struct clk_regmap_mux_data){
2049 .offset = HHI_VDEC2_CLK_CNTL,
2050 .mask = 0x3,
2051 .shift = 9,
2052 .flags = CLK_MUX_ROUND_CLOSEST,
2053 },
2054 .hw.init = &(struct clk_init_data){
2055 .name = "vdec_2_sel",
2056 .ops = &clk_regmap_mux_ops,
2057 .parent_names = meson8b_vdec_parent_names,
2058 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
2059 .flags = CLK_SET_RATE_PARENT,
2060 },
2061};
2062
2063static struct clk_regmap meson8b_vdec_2_div = {
2064 .data = &(struct clk_regmap_div_data){
2065 .offset = HHI_VDEC2_CLK_CNTL,
2066 .shift = 0,
2067 .width = 7,
2068 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2069 },
2070 .hw.init = &(struct clk_init_data){
2071 .name = "vdec_2_div",
2072 .ops = &clk_regmap_divider_ops,
2073 .parent_names = (const char *[]){ "vdec_2_sel" },
2074 .num_parents = 1,
2075 .flags = CLK_SET_RATE_PARENT,
2076 },
2077};
2078
2079static struct clk_regmap meson8b_vdec_2 = {
2080 .data = &(struct clk_regmap_gate_data){
2081 .offset = HHI_VDEC2_CLK_CNTL,
2082 .bit_idx = 8,
2083 },
2084 .hw.init = &(struct clk_init_data) {
2085 .name = "vdec_2",
2086 .ops = &clk_regmap_gate_ops,
2087 .parent_names = (const char *[]){ "vdec_2_div" },
2088 .num_parents = 1,
2089 .flags = CLK_SET_RATE_PARENT,
2090 },
2091};
2092
2093static struct clk_regmap meson8b_vdec_hevc_sel = {
2094 .data = &(struct clk_regmap_mux_data){
2095 .offset = HHI_VDEC2_CLK_CNTL,
2096 .mask = 0x3,
2097 .shift = 25,
2098 .flags = CLK_MUX_ROUND_CLOSEST,
2099 },
2100 .hw.init = &(struct clk_init_data){
2101 .name = "vdec_hevc_sel",
2102 .ops = &clk_regmap_mux_ops,
2103 .parent_names = meson8b_vdec_parent_names,
2104 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
2105 .flags = CLK_SET_RATE_PARENT,
2106 },
2107};
2108
2109static struct clk_regmap meson8b_vdec_hevc_div = {
2110 .data = &(struct clk_regmap_div_data){
2111 .offset = HHI_VDEC2_CLK_CNTL,
2112 .shift = 16,
2113 .width = 7,
2114 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2115 },
2116 .hw.init = &(struct clk_init_data){
2117 .name = "vdec_hevc_div",
2118 .ops = &clk_regmap_divider_ops,
2119 .parent_names = (const char *[]){ "vdec_hevc_sel" },
2120 .num_parents = 1,
2121 .flags = CLK_SET_RATE_PARENT,
2122 },
2123};
2124
2125static struct clk_regmap meson8b_vdec_hevc_en = {
2126 .data = &(struct clk_regmap_gate_data){
2127 .offset = HHI_VDEC2_CLK_CNTL,
2128 .bit_idx = 24,
2129 },
2130 .hw.init = &(struct clk_init_data) {
2131 .name = "vdec_hevc_en",
2132 .ops = &clk_regmap_gate_ops,
2133 .parent_names = (const char *[]){ "vdec_hevc_div" },
2134 .num_parents = 1,
2135 .flags = CLK_SET_RATE_PARENT,
2136 },
2137};
2138
2139static struct clk_regmap meson8b_vdec_hevc = {
2140 .data = &(struct clk_regmap_mux_data){
2141 .offset = HHI_VDEC2_CLK_CNTL,
2142 .mask = 0x1,
2143 .shift = 31,
2144 .flags = CLK_MUX_ROUND_CLOSEST,
2145 },
2146 .hw.init = &(struct clk_init_data){
2147 .name = "vdec_hevc",
2148 .ops = &clk_regmap_mux_ops,
2149 /* TODO: The second parent is currently unknown */
2150 .parent_names = (const char *[]){ "vdec_hevc_en" },
2151 .num_parents = 1,
2152 .flags = CLK_SET_RATE_PARENT,
2153 },
2154};
2155
1706/* Everything Else (EE) domain gates */ 2156/* Everything Else (EE) domain gates */
1707 2157
1708static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0); 2158static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
@@ -1966,6 +2416,22 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
1966 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw, 2416 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
1967 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw, 2417 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
1968 [CLKID_MALI] = &meson8b_mali_0.hw, 2418 [CLKID_MALI] = &meson8b_mali_0.hw,
2419 [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
2420 [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
2421 [CLKID_VPU] = &meson8b_vpu_0.hw,
2422 [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
2423 [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
2424 [CLKID_VDEC_1] = &meson8b_vdec_1_1.hw,
2425 [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
2426 [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
2427 [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
2428 [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
2429 [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
2430 [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
2431 [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
2432 [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
2433 [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
2434 [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
1969 [CLK_NR_CLKS] = NULL, 2435 [CLK_NR_CLKS] = NULL,
1970 }, 2436 },
1971 .num = CLK_NR_CLKS, 2437 .num = CLK_NR_CLKS,
@@ -2152,6 +2618,240 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
2152 [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw, 2618 [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
2153 [CLKID_MALI_1] = &meson8b_mali_1.hw, 2619 [CLKID_MALI_1] = &meson8b_mali_1.hw,
2154 [CLKID_MALI] = &meson8b_mali.hw, 2620 [CLKID_MALI] = &meson8b_mali.hw,
2621 [CLKID_VPU_0_SEL] = &meson8b_vpu_0_sel.hw,
2622 [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
2623 [CLKID_VPU_0] = &meson8b_vpu_0.hw,
2624 [CLKID_VPU_1_SEL] = &meson8b_vpu_1_sel.hw,
2625 [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
2626 [CLKID_VPU_1] = &meson8b_vpu_1.hw,
2627 [CLKID_VPU] = &meson8b_vpu.hw,
2628 [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
2629 [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
2630 [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
2631 [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
2632 [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
2633 [CLKID_VDEC_1] = &meson8b_vdec_1.hw,
2634 [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
2635 [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
2636 [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
2637 [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
2638 [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
2639 [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
2640 [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
2641 [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
2642 [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
2643 [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
2644 [CLK_NR_CLKS] = NULL,
2645 },
2646 .num = CLK_NR_CLKS,
2647};
2648
2649static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
2650 .hws = {
2651 [CLKID_XTAL] = &meson8b_xtal.hw,
2652 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
2653 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
2654 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
2655 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
2656 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
2657 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
2658 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2659 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
2660 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
2661 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
2662 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
2663 [CLKID_CLK81] = &meson8b_clk81.hw,
2664 [CLKID_DDR] = &meson8b_ddr.hw,
2665 [CLKID_DOS] = &meson8b_dos.hw,
2666 [CLKID_ISA] = &meson8b_isa.hw,
2667 [CLKID_PL301] = &meson8b_pl301.hw,
2668 [CLKID_PERIPHS] = &meson8b_periphs.hw,
2669 [CLKID_SPICC] = &meson8b_spicc.hw,
2670 [CLKID_I2C] = &meson8b_i2c.hw,
2671 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
2672 [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
2673 [CLKID_RNG0] = &meson8b_rng0.hw,
2674 [CLKID_UART0] = &meson8b_uart0.hw,
2675 [CLKID_SDHC] = &meson8b_sdhc.hw,
2676 [CLKID_STREAM] = &meson8b_stream.hw,
2677 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
2678 [CLKID_SDIO] = &meson8b_sdio.hw,
2679 [CLKID_ABUF] = &meson8b_abuf.hw,
2680 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
2681 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
2682 [CLKID_SPI] = &meson8b_spi.hw,
2683 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
2684 [CLKID_ETH] = &meson8b_eth.hw,
2685 [CLKID_DEMUX] = &meson8b_demux.hw,
2686 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
2687 [CLKID_IEC958] = &meson8b_iec958.hw,
2688 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
2689 [CLKID_AMCLK] = &meson8b_amclk.hw,
2690 [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
2691 [CLKID_MIXER] = &meson8b_mixer.hw,
2692 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
2693 [CLKID_ADC] = &meson8b_adc.hw,
2694 [CLKID_BLKMV] = &meson8b_blkmv.hw,
2695 [CLKID_AIU] = &meson8b_aiu.hw,
2696 [CLKID_UART1] = &meson8b_uart1.hw,
2697 [CLKID_G2D] = &meson8b_g2d.hw,
2698 [CLKID_USB0] = &meson8b_usb0.hw,
2699 [CLKID_USB1] = &meson8b_usb1.hw,
2700 [CLKID_RESET] = &meson8b_reset.hw,
2701 [CLKID_NAND] = &meson8b_nand.hw,
2702 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
2703 [CLKID_USB] = &meson8b_usb.hw,
2704 [CLKID_VDIN1] = &meson8b_vdin1.hw,
2705 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
2706 [CLKID_EFUSE] = &meson8b_efuse.hw,
2707 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
2708 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
2709 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
2710 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
2711 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
2712 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
2713 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
2714 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
2715 [CLKID_DVIN] = &meson8b_dvin.hw,
2716 [CLKID_UART2] = &meson8b_uart2.hw,
2717 [CLKID_SANA] = &meson8b_sana.hw,
2718 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
2719 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
2720 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
2721 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
2722 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
2723 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
2724 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
2725 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
2726 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
2727 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
2728 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
2729 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
2730 [CLKID_ENC480P] = &meson8b_enc480p.hw,
2731 [CLKID_RNG1] = &meson8b_rng1.hw,
2732 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
2733 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
2734 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
2735 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
2736 [CLKID_EDP] = &meson8b_edp.hw,
2737 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
2738 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
2739 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
2740 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
2741 [CLKID_MPLL0] = &meson8b_mpll0.hw,
2742 [CLKID_MPLL1] = &meson8b_mpll1.hw,
2743 [CLKID_MPLL2] = &meson8b_mpll2.hw,
2744 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
2745 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
2746 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
2747 [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
2748 [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
2749 [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
2750 [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
2751 [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
2752 [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
2753 [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
2754 [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
2755 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
2756 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
2757 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
2758 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
2759 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
2760 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
2761 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
2762 [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
2763 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
2764 [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
2765 [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
2766 [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
2767 [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
2768 [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
2769 [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
2770 [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
2771 [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
2772 [CLKID_APB] = &meson8b_apb_clk_gate.hw,
2773 [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
2774 [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
2775 [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
2776 [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
2777 [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
2778 [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
2779 [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
2780 [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
2781 [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
2782 [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
2783 [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
2784 [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
2785 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
2786 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
2787 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
2788 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
2789 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
2790 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
2791 [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
2792 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
2793 [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
2794 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
2795 [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
2796 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
2797 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
2798 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
2799 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
2800 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
2801 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
2802 [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
2803 [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
2804 [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
2805 [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
2806 [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
2807 [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
2808 [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
2809 [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
2810 [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
2811 [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
2812 [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
2813 [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
2814 [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
2815 [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
2816 [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
2817 [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
2818 [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
2819 [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
2820 [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
2821 [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
2822 [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
2823 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
2824 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
2825 [CLKID_MALI_0] = &meson8b_mali_0.hw,
2826 [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
2827 [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
2828 [CLKID_MALI_1] = &meson8b_mali_1.hw,
2829 [CLKID_MALI] = &meson8b_mali.hw,
2830 [CLKID_GP_PLL_DCO] = &meson8m2_gp_pll_dco.hw,
2831 [CLKID_GP_PLL] = &meson8m2_gp_pll.hw,
2832 [CLKID_VPU_0_SEL] = &meson8m2_vpu_0_sel.hw,
2833 [CLKID_VPU_0_DIV] = &meson8b_vpu_0_div.hw,
2834 [CLKID_VPU_0] = &meson8b_vpu_0.hw,
2835 [CLKID_VPU_1_SEL] = &meson8m2_vpu_1_sel.hw,
2836 [CLKID_VPU_1_DIV] = &meson8b_vpu_1_div.hw,
2837 [CLKID_VPU_1] = &meson8b_vpu_1.hw,
2838 [CLKID_VPU] = &meson8b_vpu.hw,
2839 [CLKID_VDEC_1_SEL] = &meson8b_vdec_1_sel.hw,
2840 [CLKID_VDEC_1_1_DIV] = &meson8b_vdec_1_1_div.hw,
2841 [CLKID_VDEC_1_1] = &meson8b_vdec_1_1.hw,
2842 [CLKID_VDEC_1_2_DIV] = &meson8b_vdec_1_2_div.hw,
2843 [CLKID_VDEC_1_2] = &meson8b_vdec_1_2.hw,
2844 [CLKID_VDEC_1] = &meson8b_vdec_1.hw,
2845 [CLKID_VDEC_HCODEC_SEL] = &meson8b_vdec_hcodec_sel.hw,
2846 [CLKID_VDEC_HCODEC_DIV] = &meson8b_vdec_hcodec_div.hw,
2847 [CLKID_VDEC_HCODEC] = &meson8b_vdec_hcodec.hw,
2848 [CLKID_VDEC_2_SEL] = &meson8b_vdec_2_sel.hw,
2849 [CLKID_VDEC_2_DIV] = &meson8b_vdec_2_div.hw,
2850 [CLKID_VDEC_2] = &meson8b_vdec_2.hw,
2851 [CLKID_VDEC_HEVC_SEL] = &meson8b_vdec_hevc_sel.hw,
2852 [CLKID_VDEC_HEVC_DIV] = &meson8b_vdec_hevc_div.hw,
2853 [CLKID_VDEC_HEVC_EN] = &meson8b_vdec_hevc_en.hw,
2854 [CLKID_VDEC_HEVC] = &meson8b_vdec_hevc.hw,
2155 [CLK_NR_CLKS] = NULL, 2855 [CLK_NR_CLKS] = NULL,
2156 }, 2856 },
2157 .num = CLK_NR_CLKS, 2857 .num = CLK_NR_CLKS,
@@ -2314,6 +3014,33 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = {
2314 &meson8b_mali_1_div, 3014 &meson8b_mali_1_div,
2315 &meson8b_mali_1, 3015 &meson8b_mali_1,
2316 &meson8b_mali, 3016 &meson8b_mali,
3017 &meson8m2_gp_pll_dco,
3018 &meson8m2_gp_pll,
3019 &meson8b_vpu_0_sel,
3020 &meson8m2_vpu_0_sel,
3021 &meson8b_vpu_0_div,
3022 &meson8b_vpu_0,
3023 &meson8b_vpu_1_sel,
3024 &meson8m2_vpu_1_sel,
3025 &meson8b_vpu_1_div,
3026 &meson8b_vpu_1,
3027 &meson8b_vpu,
3028 &meson8b_vdec_1_sel,
3029 &meson8b_vdec_1_1_div,
3030 &meson8b_vdec_1_1,
3031 &meson8b_vdec_1_2_div,
3032 &meson8b_vdec_1_2,
3033 &meson8b_vdec_1,
3034 &meson8b_vdec_hcodec_sel,
3035 &meson8b_vdec_hcodec_div,
3036 &meson8b_vdec_hcodec,
3037 &meson8b_vdec_2_sel,
3038 &meson8b_vdec_2_div,
3039 &meson8b_vdec_2,
3040 &meson8b_vdec_hevc_sel,
3041 &meson8b_vdec_hevc_div,
3042 &meson8b_vdec_hevc_en,
3043 &meson8b_vdec_hevc,
2317}; 3044};
2318 3045
2319static const struct meson8b_clk_reset_line { 3046static const struct meson8b_clk_reset_line {
@@ -2558,9 +3285,14 @@ static void __init meson8b_clkc_init(struct device_node *np)
2558 return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data); 3285 return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data);
2559} 3286}
2560 3287
3288static void __init meson8m2_clkc_init(struct device_node *np)
3289{
3290 return meson8b_clkc_init_common(np, &meson8m2_hw_onecell_data);
3291}
3292
2561CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc", 3293CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
2562 meson8_clkc_init); 3294 meson8_clkc_init);
2563CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc", 3295CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
2564 meson8b_clkc_init); 3296 meson8b_clkc_init);
2565CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc", 3297CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
2566 meson8b_clkc_init); 3298 meson8m2_clkc_init);
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index b8c58faeae52..ed37196187e6 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -19,6 +19,7 @@
19 * 19 *
20 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf 20 * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
21 */ 21 */
22#define HHI_GP_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
22#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ 23#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
23#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ 24#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
24#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */ 25#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
@@ -34,7 +35,11 @@
34#define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */ 35#define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */
35#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */ 36#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
36#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */ 37#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */
38#define HHI_VPU_CLK_CNTL 0x1bc /* 0x6f offset in data sheet */
37#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */ 39#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */
40#define HHI_VDEC_CLK_CNTL 0x1e0 /* 0x78 offset in data sheet */
41#define HHI_VDEC2_CLK_CNTL 0x1e4 /* 0x79 offset in data sheet */
42#define HHI_VDEC3_CLK_CNTL 0x1e8 /* 0x7a offset in data sheet */
38#define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet */ 43#define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet */
39#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */ 44#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
40#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ 45#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
@@ -146,8 +151,28 @@
146#define CLKID_MALI_1_SEL 178 151#define CLKID_MALI_1_SEL 178
147#define CLKID_MALI_1_DIV 179 152#define CLKID_MALI_1_DIV 179
148#define CLKID_MALI_1 180 153#define CLKID_MALI_1 180
154#define CLKID_GP_PLL_DCO 181
155#define CLKID_GP_PLL 182
156#define CLKID_VPU_0_SEL 183
157#define CLKID_VPU_0_DIV 184
158#define CLKID_VPU_0 185
159#define CLKID_VPU_1_SEL 186
160#define CLKID_VPU_1_DIV 187
161#define CLKID_VPU_1 189
162#define CLKID_VDEC_1_SEL 191
163#define CLKID_VDEC_1_1_DIV 192
164#define CLKID_VDEC_1_1 193
165#define CLKID_VDEC_1_2_DIV 194
166#define CLKID_VDEC_1_2 195
167#define CLKID_VDEC_HCODEC_SEL 197
168#define CLKID_VDEC_HCODEC_DIV 198
169#define CLKID_VDEC_2_SEL 200
170#define CLKID_VDEC_2_DIV 201
171#define CLKID_VDEC_HEVC_SEL 203
172#define CLKID_VDEC_HEVC_DIV 204
173#define CLKID_VDEC_HEVC_EN 205
149 174
150#define CLK_NR_CLKS 181 175#define CLK_NR_CLKS 207
151 176
152/* 177/*
153 * include the CLKID and RESETID that have 178 * include the CLKID and RESETID that have
diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h
index fd9c362099d9..eafb0de8466b 100644
--- a/include/dt-bindings/clock/axg-audio-clkc.h
+++ b/include/dt-bindings/clock/axg-audio-clkc.h
@@ -7,26 +7,6 @@
7#ifndef __AXG_AUDIO_CLKC_BINDINGS_H 7#ifndef __AXG_AUDIO_CLKC_BINDINGS_H
8#define __AXG_AUDIO_CLKC_BINDINGS_H 8#define __AXG_AUDIO_CLKC_BINDINGS_H
9 9
10#define AUD_CLKID_SLV_SCLK0 9
11#define AUD_CLKID_SLV_SCLK1 10
12#define AUD_CLKID_SLV_SCLK2 11
13#define AUD_CLKID_SLV_SCLK3 12
14#define AUD_CLKID_SLV_SCLK4 13
15#define AUD_CLKID_SLV_SCLK5 14
16#define AUD_CLKID_SLV_SCLK6 15
17#define AUD_CLKID_SLV_SCLK7 16
18#define AUD_CLKID_SLV_SCLK8 17
19#define AUD_CLKID_SLV_SCLK9 18
20#define AUD_CLKID_SLV_LRCLK0 19
21#define AUD_CLKID_SLV_LRCLK1 20
22#define AUD_CLKID_SLV_LRCLK2 21
23#define AUD_CLKID_SLV_LRCLK3 22
24#define AUD_CLKID_SLV_LRCLK4 23
25#define AUD_CLKID_SLV_LRCLK5 24
26#define AUD_CLKID_SLV_LRCLK6 25
27#define AUD_CLKID_SLV_LRCLK7 26
28#define AUD_CLKID_SLV_LRCLK8 27
29#define AUD_CLKID_SLV_LRCLK9 28
30#define AUD_CLKID_DDR_ARB 29 10#define AUD_CLKID_DDR_ARB 29
31#define AUD_CLKID_PDM 30 11#define AUD_CLKID_PDM 30
32#define AUD_CLKID_TDMIN_A 31 12#define AUD_CLKID_TDMIN_A 31
diff --git a/include/dt-bindings/clock/g12a-aoclkc.h b/include/dt-bindings/clock/g12a-aoclkc.h
index 8db01ffbeb06..e916e49ff288 100644
--- a/include/dt-bindings/clock/g12a-aoclkc.h
+++ b/include/dt-bindings/clock/g12a-aoclkc.h
@@ -26,7 +26,9 @@
26#define CLKID_AO_M4_FCLK 13 26#define CLKID_AO_M4_FCLK 13
27#define CLKID_AO_M4_HCLK 14 27#define CLKID_AO_M4_HCLK 14
28#define CLKID_AO_CLK81 15 28#define CLKID_AO_CLK81 15
29#define CLKID_AO_SAR_ADC_SEL 16
29#define CLKID_AO_SAR_ADC_CLK 18 30#define CLKID_AO_SAR_ADC_CLK 18
31#define CLKID_AO_CTS_OSCIN 19
30#define CLKID_AO_32K 23 32#define CLKID_AO_32K 23
31#define CLKID_AO_CEC 27 33#define CLKID_AO_CEC 27
32#define CLKID_AO_CTS_RTC_OSCIN 28 34#define CLKID_AO_CTS_RTC_OSCIN 28
diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h
index 83b657038d1e..82c9e0c020b2 100644
--- a/include/dt-bindings/clock/g12a-clkc.h
+++ b/include/dt-bindings/clock/g12a-clkc.h
@@ -131,5 +131,10 @@
131#define CLKID_MALI_1 174 131#define CLKID_MALI_1 174
132#define CLKID_MALI 175 132#define CLKID_MALI 175
133#define CLKID_MPLL_5OM 177 133#define CLKID_MPLL_5OM 177
134#define CLKID_CPU_CLK 187
135#define CLKID_PCIE_PLL 201
136#define CLKID_VDEC_1 204
137#define CLKID_VDEC_HEVC 207
138#define CLKID_VDEC_HEVCF 210
134 139
135#endif /* __G12A_CLKC_H */ 140#endif /* __G12A_CLKC_H */
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index 8067077a62ca..47556539f0ee 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -103,10 +103,14 @@
103#define CLKID_MPLL1 94 103#define CLKID_MPLL1 94
104#define CLKID_MPLL2 95 104#define CLKID_MPLL2 95
105#define CLKID_NAND_CLK 112 105#define CLKID_NAND_CLK 112
106#define CLKID_ABP 124
107#define CLKID_APB 124 106#define CLKID_APB 124
108#define CLKID_PERIPH 126 107#define CLKID_PERIPH 126
109#define CLKID_AXI 128 108#define CLKID_AXI 128
110#define CLKID_L2_DRAM 130 109#define CLKID_L2_DRAM 130
110#define CLKID_VPU 190
111#define CLKID_VDEC_1 196
112#define CLKID_VDEC_HCODEC 199
113#define CLKID_VDEC_2 202
114#define CLKID_VDEC_HEVC 206
111 115
112#endif /* __MESON8B_CLKC_H */ 116#endif /* __MESON8B_CLKC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-05 00:11:23 -0400