diff options
-rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/en.h | 16 | ||||
-rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c | 34 | ||||
-rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 43 | ||||
-rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/en_rep.c | 9 | ||||
-rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/en_tc.c | 5 | ||||
-rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c | 2 |
6 files changed, 62 insertions, 47 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h index 8539ea9a67ca..330c476c1df2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h | |||
@@ -244,9 +244,6 @@ struct mlx5e_params { | |||
244 | bool lro_en; | 244 | bool lro_en; |
245 | u32 lro_wqe_sz; | 245 | u32 lro_wqe_sz; |
246 | u8 tx_min_inline_mode; | 246 | u8 tx_min_inline_mode; |
247 | u8 rss_hfunc; | ||
248 | u8 toeplitz_hash_key[40]; | ||
249 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | ||
250 | bool vlan_strip_disable; | 247 | bool vlan_strip_disable; |
251 | bool scatter_fcs_en; | 248 | bool scatter_fcs_en; |
252 | bool rx_dim_enabled; | 249 | bool rx_dim_enabled; |
@@ -651,6 +648,12 @@ enum { | |||
651 | MLX5E_NIC_PRIO | 648 | MLX5E_NIC_PRIO |
652 | }; | 649 | }; |
653 | 650 | ||
651 | struct mlx5e_rss_params { | ||
652 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | ||
653 | u8 toeplitz_hash_key[40]; | ||
654 | u8 hfunc; | ||
655 | }; | ||
656 | |||
654 | struct mlx5e_priv { | 657 | struct mlx5e_priv { |
655 | /* priv data path fields - start */ | 658 | /* priv data path fields - start */ |
656 | struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC]; | 659 | struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC]; |
@@ -671,6 +674,7 @@ struct mlx5e_priv { | |||
671 | struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; | 674 | struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; |
672 | struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS]; | 675 | struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS]; |
673 | struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; | 676 | struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; |
677 | struct mlx5e_rss_params rss_params; | ||
674 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; | 678 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; |
675 | 679 | ||
676 | struct mlx5e_flow_steering fs; | 680 | struct mlx5e_flow_steering fs; |
@@ -796,7 +800,7 @@ struct mlx5e_redirect_rqt_param { | |||
796 | 800 | ||
797 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, | 801 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, |
798 | struct mlx5e_redirect_rqt_param rrp); | 802 | struct mlx5e_redirect_rqt_param rrp); |
799 | void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params, | 803 | void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params, |
800 | const struct mlx5e_tirc_config *ttconfig, | 804 | const struct mlx5e_tirc_config *ttconfig, |
801 | void *tirc, bool inner); | 805 | void *tirc, bool inner); |
802 | void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen); | 806 | void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen); |
@@ -982,11 +986,13 @@ int mlx5e_attach_netdev(struct mlx5e_priv *priv); | |||
982 | void mlx5e_detach_netdev(struct mlx5e_priv *priv); | 986 | void mlx5e_detach_netdev(struct mlx5e_priv *priv); |
983 | void mlx5e_destroy_netdev(struct mlx5e_priv *priv); | 987 | void mlx5e_destroy_netdev(struct mlx5e_priv *priv); |
984 | void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, | 988 | void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, |
989 | struct mlx5e_rss_params *rss_params, | ||
985 | struct mlx5e_params *params, | 990 | struct mlx5e_params *params, |
986 | u16 max_channels, u16 mtu); | 991 | u16 max_channels, u16 mtu); |
987 | void mlx5e_build_rq_params(struct mlx5_core_dev *mdev, | 992 | void mlx5e_build_rq_params(struct mlx5_core_dev *mdev, |
988 | struct mlx5e_params *params); | 993 | struct mlx5e_params *params); |
989 | void mlx5e_build_rss_params(struct mlx5e_params *params); | 994 | void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params, |
995 | u16 num_channels); | ||
990 | u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev); | 996 | u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev); |
991 | void mlx5e_rx_dim_work(struct work_struct *work); | 997 | void mlx5e_rx_dim_work(struct work_struct *work); |
992 | void mlx5e_tx_dim_work(struct work_struct *work); | 998 | void mlx5e_tx_dim_work(struct work_struct *work); |
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c index 2d5b00751a6d..e868d42c83cb 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c | |||
@@ -353,7 +353,7 @@ int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, | |||
353 | new_channels.params = priv->channels.params; | 353 | new_channels.params = priv->channels.params; |
354 | new_channels.params.num_channels = count; | 354 | new_channels.params.num_channels = count; |
355 | if (!netif_is_rxfh_configured(priv->netdev)) | 355 | if (!netif_is_rxfh_configured(priv->netdev)) |
356 | mlx5e_build_default_indir_rqt(new_channels.params.indirection_rqt, | 356 | mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt, |
357 | MLX5E_INDIR_RQT_SIZE, count); | 357 | MLX5E_INDIR_RQT_SIZE, count); |
358 | 358 | ||
359 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { | 359 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { |
@@ -931,7 +931,7 @@ out: | |||
931 | 931 | ||
932 | u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv) | 932 | u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv) |
933 | { | 933 | { |
934 | return sizeof(priv->channels.params.toeplitz_hash_key); | 934 | return sizeof(priv->rss_params.toeplitz_hash_key); |
935 | } | 935 | } |
936 | 936 | ||
937 | static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev) | 937 | static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev) |
@@ -957,17 +957,18 @@ static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, | |||
957 | u8 *hfunc) | 957 | u8 *hfunc) |
958 | { | 958 | { |
959 | struct mlx5e_priv *priv = netdev_priv(netdev); | 959 | struct mlx5e_priv *priv = netdev_priv(netdev); |
960 | struct mlx5e_rss_params *rss = &priv->rss_params; | ||
960 | 961 | ||
961 | if (indir) | 962 | if (indir) |
962 | memcpy(indir, priv->channels.params.indirection_rqt, | 963 | memcpy(indir, rss->indirection_rqt, |
963 | sizeof(priv->channels.params.indirection_rqt)); | 964 | sizeof(rss->indirection_rqt)); |
964 | 965 | ||
965 | if (key) | 966 | if (key) |
966 | memcpy(key, priv->channels.params.toeplitz_hash_key, | 967 | memcpy(key, rss->toeplitz_hash_key, |
967 | sizeof(priv->channels.params.toeplitz_hash_key)); | 968 | sizeof(rss->toeplitz_hash_key)); |
968 | 969 | ||
969 | if (hfunc) | 970 | if (hfunc) |
970 | *hfunc = priv->channels.params.rss_hfunc; | 971 | *hfunc = rss->hfunc; |
971 | 972 | ||
972 | return 0; | 973 | return 0; |
973 | } | 974 | } |
@@ -976,6 +977,7 @@ static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, | |||
976 | const u8 *key, const u8 hfunc) | 977 | const u8 *key, const u8 hfunc) |
977 | { | 978 | { |
978 | struct mlx5e_priv *priv = netdev_priv(dev); | 979 | struct mlx5e_priv *priv = netdev_priv(dev); |
980 | struct mlx5e_rss_params *rss = &priv->rss_params; | ||
979 | int inlen = MLX5_ST_SZ_BYTES(modify_tir_in); | 981 | int inlen = MLX5_ST_SZ_BYTES(modify_tir_in); |
980 | bool hash_changed = false; | 982 | bool hash_changed = false; |
981 | void *in; | 983 | void *in; |
@@ -991,15 +993,14 @@ static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, | |||
991 | 993 | ||
992 | mutex_lock(&priv->state_lock); | 994 | mutex_lock(&priv->state_lock); |
993 | 995 | ||
994 | if (hfunc != ETH_RSS_HASH_NO_CHANGE && | 996 | if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != rss->hfunc) { |
995 | hfunc != priv->channels.params.rss_hfunc) { | 997 | rss->hfunc = hfunc; |
996 | priv->channels.params.rss_hfunc = hfunc; | ||
997 | hash_changed = true; | 998 | hash_changed = true; |
998 | } | 999 | } |
999 | 1000 | ||
1000 | if (indir) { | 1001 | if (indir) { |
1001 | memcpy(priv->channels.params.indirection_rqt, indir, | 1002 | memcpy(rss->indirection_rqt, indir, |
1002 | sizeof(priv->channels.params.indirection_rqt)); | 1003 | sizeof(rss->indirection_rqt)); |
1003 | 1004 | ||
1004 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) { | 1005 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) { |
1005 | u32 rqtn = priv->indir_rqt.rqtn; | 1006 | u32 rqtn = priv->indir_rqt.rqtn; |
@@ -1007,7 +1008,7 @@ static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, | |||
1007 | .is_rss = true, | 1008 | .is_rss = true, |
1008 | { | 1009 | { |
1009 | .rss = { | 1010 | .rss = { |
1010 | .hfunc = priv->channels.params.rss_hfunc, | 1011 | .hfunc = rss->hfunc, |
1011 | .channels = &priv->channels, | 1012 | .channels = &priv->channels, |
1012 | }, | 1013 | }, |
1013 | }, | 1014 | }, |
@@ -1018,10 +1019,9 @@ static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, | |||
1018 | } | 1019 | } |
1019 | 1020 | ||
1020 | if (key) { | 1021 | if (key) { |
1021 | memcpy(priv->channels.params.toeplitz_hash_key, key, | 1022 | memcpy(rss->toeplitz_hash_key, key, |
1022 | sizeof(priv->channels.params.toeplitz_hash_key)); | 1023 | sizeof(rss->toeplitz_hash_key)); |
1023 | hash_changed = hash_changed || | 1024 | hash_changed = hash_changed || rss->hfunc == ETH_RSS_HASH_TOP; |
1024 | priv->channels.params.rss_hfunc == ETH_RSS_HASH_TOP; | ||
1025 | } | 1025 | } |
1026 | 1026 | ||
1027 | if (hash_changed) | 1027 | if (hash_changed) |
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index 01828efe905d..be782c508f3a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c | |||
@@ -2504,7 +2504,7 @@ static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz, | |||
2504 | if (rrp.rss.hfunc == ETH_RSS_HASH_XOR) | 2504 | if (rrp.rss.hfunc == ETH_RSS_HASH_XOR) |
2505 | ix = mlx5e_bits_invert(i, ilog2(sz)); | 2505 | ix = mlx5e_bits_invert(i, ilog2(sz)); |
2506 | 2506 | ||
2507 | ix = priv->channels.params.indirection_rqt[ix]; | 2507 | ix = priv->rss_params.indirection_rqt[ix]; |
2508 | rqn = rrp.rss.channels->c[ix]->rq.rqn; | 2508 | rqn = rrp.rss.channels->c[ix]->rq.rqn; |
2509 | } else { | 2509 | } else { |
2510 | rqn = rrp.rqn; | 2510 | rqn = rrp.rqn; |
@@ -2587,7 +2587,7 @@ static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv, | |||
2587 | { | 2587 | { |
2588 | .rss = { | 2588 | .rss = { |
2589 | .channels = chs, | 2589 | .channels = chs, |
2590 | .hfunc = chs->params.rss_hfunc, | 2590 | .hfunc = priv->rss_params.hfunc, |
2591 | } | 2591 | } |
2592 | }, | 2592 | }, |
2593 | }; | 2593 | }; |
@@ -2670,22 +2670,22 @@ static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc) | |||
2670 | MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout); | 2670 | MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout); |
2671 | } | 2671 | } |
2672 | 2672 | ||
2673 | void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params, | 2673 | void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params, |
2674 | const struct mlx5e_tirc_config *ttconfig, | 2674 | const struct mlx5e_tirc_config *ttconfig, |
2675 | void *tirc, bool inner) | 2675 | void *tirc, bool inner) |
2676 | { | 2676 | { |
2677 | void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) : | 2677 | void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) : |
2678 | MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); | 2678 | MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); |
2679 | 2679 | ||
2680 | MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc)); | 2680 | MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc)); |
2681 | if (params->rss_hfunc == ETH_RSS_HASH_TOP) { | 2681 | if (rss_params->hfunc == ETH_RSS_HASH_TOP) { |
2682 | void *rss_key = MLX5_ADDR_OF(tirc, tirc, | 2682 | void *rss_key = MLX5_ADDR_OF(tirc, tirc, |
2683 | rx_hash_toeplitz_key); | 2683 | rx_hash_toeplitz_key); |
2684 | size_t len = MLX5_FLD_SZ_BYTES(tirc, | 2684 | size_t len = MLX5_FLD_SZ_BYTES(tirc, |
2685 | rx_hash_toeplitz_key); | 2685 | rx_hash_toeplitz_key); |
2686 | 2686 | ||
2687 | MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); | 2687 | MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); |
2688 | memcpy(rss_key, params->toeplitz_hash_key, len); | 2688 | memcpy(rss_key, rss_params->toeplitz_hash_key, len); |
2689 | } | 2689 | } |
2690 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | 2690 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, |
2691 | ttconfig->l3_prot_type); | 2691 | ttconfig->l3_prot_type); |
@@ -2706,7 +2706,7 @@ void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen) | |||
2706 | 2706 | ||
2707 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { | 2707 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { |
2708 | memset(tirc, 0, ctxlen); | 2708 | memset(tirc, 0, ctxlen); |
2709 | mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, | 2709 | mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, |
2710 | &tirc_default_config[tt], | 2710 | &tirc_default_config[tt], |
2711 | tirc, false); | 2711 | tirc, false); |
2712 | mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen); | 2712 | mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen); |
@@ -2717,7 +2717,7 @@ void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen) | |||
2717 | 2717 | ||
2718 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { | 2718 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { |
2719 | memset(tirc, 0, ctxlen); | 2719 | memset(tirc, 0, ctxlen); |
2720 | mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, | 2720 | mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, |
2721 | &tirc_default_config[tt], | 2721 | &tirc_default_config[tt], |
2722 | tirc, true); | 2722 | tirc, true); |
2723 | mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in, | 2723 | mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in, |
@@ -2778,7 +2778,7 @@ static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv, | |||
2778 | MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn); | 2778 | MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn); |
2779 | MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1); | 2779 | MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1); |
2780 | 2780 | ||
2781 | mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, | 2781 | mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, |
2782 | &tirc_default_config[tt], tirc, true); | 2782 | &tirc_default_config[tt], tirc, true); |
2783 | } | 2783 | } |
2784 | 2784 | ||
@@ -3172,7 +3172,7 @@ static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, | |||
3172 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); | 3172 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); |
3173 | MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn); | 3173 | MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn); |
3174 | 3174 | ||
3175 | mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, | 3175 | mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, |
3176 | &tirc_default_config[tt], tirc, false); | 3176 | &tirc_default_config[tt], tirc, false); |
3177 | } | 3177 | } |
3178 | 3178 | ||
@@ -4511,15 +4511,18 @@ void mlx5e_build_rq_params(struct mlx5_core_dev *mdev, | |||
4511 | mlx5e_init_rq_type_params(mdev, params); | 4511 | mlx5e_init_rq_type_params(mdev, params); |
4512 | } | 4512 | } |
4513 | 4513 | ||
4514 | void mlx5e_build_rss_params(struct mlx5e_params *params) | 4514 | void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params, |
4515 | u16 num_channels) | ||
4515 | { | 4516 | { |
4516 | params->rss_hfunc = ETH_RSS_HASH_XOR; | 4517 | rss_params->hfunc = ETH_RSS_HASH_XOR; |
4517 | netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key)); | 4518 | netdev_rss_key_fill(rss_params->toeplitz_hash_key, |
4518 | mlx5e_build_default_indir_rqt(params->indirection_rqt, | 4519 | sizeof(rss_params->toeplitz_hash_key)); |
4519 | MLX5E_INDIR_RQT_SIZE, params->num_channels); | 4520 | mlx5e_build_default_indir_rqt(rss_params->indirection_rqt, |
4521 | MLX5E_INDIR_RQT_SIZE, num_channels); | ||
4520 | } | 4522 | } |
4521 | 4523 | ||
4522 | void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, | 4524 | void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, |
4525 | struct mlx5e_rss_params *rss_params, | ||
4523 | struct mlx5e_params *params, | 4526 | struct mlx5e_params *params, |
4524 | u16 max_channels, u16 mtu) | 4527 | u16 max_channels, u16 mtu) |
4525 | { | 4528 | { |
@@ -4568,7 +4571,7 @@ void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, | |||
4568 | params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev); | 4571 | params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev); |
4569 | 4572 | ||
4570 | /* RSS */ | 4573 | /* RSS */ |
4571 | mlx5e_build_rss_params(params); | 4574 | mlx5e_build_rss_params(rss_params, params->num_channels); |
4572 | } | 4575 | } |
4573 | 4576 | ||
4574 | static void mlx5e_set_netdev_dev_addr(struct net_device *netdev) | 4577 | static void mlx5e_set_netdev_dev_addr(struct net_device *netdev) |
@@ -4741,14 +4744,16 @@ static int mlx5e_nic_init(struct mlx5_core_dev *mdev, | |||
4741 | void *ppriv) | 4744 | void *ppriv) |
4742 | { | 4745 | { |
4743 | struct mlx5e_priv *priv = netdev_priv(netdev); | 4746 | struct mlx5e_priv *priv = netdev_priv(netdev); |
4747 | struct mlx5e_rss_params *rss = &priv->rss_params; | ||
4744 | int err; | 4748 | int err; |
4745 | 4749 | ||
4746 | err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv); | 4750 | err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv); |
4747 | if (err) | 4751 | if (err) |
4748 | return err; | 4752 | return err; |
4749 | 4753 | ||
4750 | mlx5e_build_nic_params(mdev, &priv->channels.params, | 4754 | mlx5e_build_nic_params(mdev, rss, &priv->channels.params, |
4751 | mlx5e_get_netdev_max_channels(netdev), netdev->mtu); | 4755 | mlx5e_get_netdev_max_channels(netdev), |
4756 | netdev->mtu); | ||
4752 | 4757 | ||
4753 | mlx5e_timestamp_init(priv); | 4758 | mlx5e_timestamp_init(priv); |
4754 | 4759 | ||
@@ -5023,7 +5028,7 @@ int mlx5e_attach_netdev(struct mlx5e_priv *priv) | |||
5023 | if (priv->channels.params.num_channels > max_nch) { | 5028 | if (priv->channels.params.num_channels > max_nch) { |
5024 | mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch); | 5029 | mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch); |
5025 | priv->channels.params.num_channels = max_nch; | 5030 | priv->channels.params.num_channels = max_nch; |
5026 | mlx5e_build_default_indir_rqt(priv->channels.params.indirection_rqt, | 5031 | mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt, |
5027 | MLX5E_INDIR_RQT_SIZE, max_nch); | 5032 | MLX5E_INDIR_RQT_SIZE, max_nch); |
5028 | } | 5033 | } |
5029 | 5034 | ||
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c index c3c657548824..a137540b84bf 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rep.c | |||
@@ -1012,7 +1012,9 @@ static const struct net_device_ops mlx5e_netdev_ops_rep = { | |||
1012 | }; | 1012 | }; |
1013 | 1013 | ||
1014 | static void mlx5e_build_rep_params(struct mlx5_core_dev *mdev, | 1014 | static void mlx5e_build_rep_params(struct mlx5_core_dev *mdev, |
1015 | struct mlx5e_params *params, u16 mtu) | 1015 | struct mlx5e_params *params, |
1016 | struct mlx5e_rss_params *rss_params, | ||
1017 | u16 mtu) | ||
1016 | { | 1018 | { |
1017 | u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? | 1019 | u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? |
1018 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE : | 1020 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE : |
@@ -1034,7 +1036,7 @@ static void mlx5e_build_rep_params(struct mlx5_core_dev *mdev, | |||
1034 | mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode); | 1036 | mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode); |
1035 | 1037 | ||
1036 | /* RSS */ | 1038 | /* RSS */ |
1037 | mlx5e_build_rss_params(params); | 1039 | mlx5e_build_rss_params(rss_params, params->num_channels); |
1038 | } | 1040 | } |
1039 | 1041 | ||
1040 | static void mlx5e_build_rep_netdev(struct net_device *netdev) | 1042 | static void mlx5e_build_rep_netdev(struct net_device *netdev) |
@@ -1087,7 +1089,8 @@ static int mlx5e_init_rep(struct mlx5_core_dev *mdev, | |||
1087 | priv->channels.params.num_channels = | 1089 | priv->channels.params.num_channels = |
1088 | mlx5e_get_netdev_max_channels(netdev); | 1090 | mlx5e_get_netdev_max_channels(netdev); |
1089 | 1091 | ||
1090 | mlx5e_build_rep_params(mdev, &priv->channels.params, netdev->mtu); | 1092 | mlx5e_build_rep_params(mdev, &priv->channels.params, |
1093 | &priv->rss_params, netdev->mtu); | ||
1091 | mlx5e_build_rep_netdev(netdev); | 1094 | mlx5e_build_rep_netdev(netdev); |
1092 | 1095 | ||
1093 | mlx5e_timestamp_init(priv); | 1096 | mlx5e_timestamp_init(priv); |
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c index 1025afc80f42..a3ff2492646d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c | |||
@@ -316,7 +316,7 @@ static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc) | |||
316 | 316 | ||
317 | for (i = 0; i < sz; i++) { | 317 | for (i = 0; i < sz; i++) { |
318 | ix = i; | 318 | ix = i; |
319 | if (priv->channels.params.rss_hfunc == ETH_RSS_HASH_XOR) | 319 | if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR) |
320 | ix = mlx5e_bits_invert(i, ilog2(sz)); | 320 | ix = mlx5e_bits_invert(i, ilog2(sz)); |
321 | ix = indirection_rqt[ix]; | 321 | ix = indirection_rqt[ix]; |
322 | rqn = hp->pair->rqn[ix]; | 322 | rqn = hp->pair->rqn[ix]; |
@@ -368,7 +368,8 @@ static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp) | |||
368 | MLX5_SET(tirc, tirc, transport_domain, hp->tdn); | 368 | MLX5_SET(tirc, tirc, transport_domain, hp->tdn); |
369 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); | 369 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); |
370 | MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn); | 370 | MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn); |
371 | mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, &ttconfig, tirc, false); | 371 | mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false); |
372 | |||
372 | err = mlx5_core_create_tir(hp->func_mdev, in, | 373 | err = mlx5_core_create_tir(hp->func_mdev, in, |
373 | MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]); | 374 | MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]); |
374 | if (err) { | 375 | if (err) { |
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c b/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c index 11dabd62e2c7..bfc0f6581729 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c | |||
@@ -87,7 +87,7 @@ int mlx5i_init(struct mlx5_core_dev *mdev, | |||
87 | mlx5_query_port_max_mtu(mdev, &max_mtu, 1); | 87 | mlx5_query_port_max_mtu(mdev, &max_mtu, 1); |
88 | netdev->mtu = max_mtu; | 88 | netdev->mtu = max_mtu; |
89 | 89 | ||
90 | mlx5e_build_nic_params(mdev, &priv->channels.params, | 90 | mlx5e_build_nic_params(mdev, &priv->rss_params, &priv->channels.params, |
91 | mlx5e_get_netdev_max_channels(netdev), | 91 | mlx5e_get_netdev_max_channels(netdev), |
92 | netdev->mtu); | 92 | netdev->mtu); |
93 | mlx5i_build_nic_params(mdev, &priv->channels.params); | 93 | mlx5i_build_nic_params(mdev, &priv->channels.params); |