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-rw-r--r--Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt1
-rw-r--r--Documentation/devicetree/bindings/spi/sh-msiof.txt1
-rw-r--r--Documentation/devicetree/bindings/spi/spi-rockchip.txt1
-rw-r--r--drivers/spi/Kconfig5
-rw-r--r--drivers/spi/spi-altera.c163
-rw-r--r--drivers/spi/spi-ath79.c13
-rw-r--r--drivers/spi/spi-bcm-qspi.c89
-rw-r--r--drivers/spi/spi-bcm63xx-hsspi.c10
-rw-r--r--drivers/spi/spi-bcm63xx.c4
-rw-r--r--drivers/spi/spi-cadence.c4
-rw-r--r--drivers/spi/spi-ep93xx.c501
-rw-r--r--drivers/spi/spi-falcon.c5
-rw-r--r--drivers/spi/spi-imx.c218
-rw-r--r--drivers/spi/spi-loopback-test.c34
-rw-r--r--drivers/spi/spi-omap2-mcspi.c4
-rw-r--r--drivers/spi/spi-orion.c4
-rw-r--r--drivers/spi/spi-pic32.c4
-rw-r--r--drivers/spi/spi-pl022.c2
-rw-r--r--drivers/spi/spi-pxa2xx.c35
-rw-r--r--drivers/spi/spi-pxa2xx.h2
-rw-r--r--drivers/spi/spi-qup.c564
-rw-r--r--drivers/spi/spi-rockchip.c60
-rw-r--r--drivers/spi/spi-sh-msiof.c32
-rw-r--r--drivers/spi/spi-sh.c4
-rw-r--r--drivers/spi/spi-stm32.c2
-rw-r--r--drivers/spi/spi-sun6i.c2
-rw-r--r--drivers/spi/spi-tegra114.c2
-rw-r--r--drivers/spi/spi-tegra20-sflash.c2
-rw-r--r--drivers/spi/spi-tegra20-slink.c2
-rw-r--r--drivers/spi/spi-xlp.c4
-rw-r--r--drivers/spi/spi.c110
-rw-r--r--tools/Makefile4
-rw-r--r--tools/spi/Build2
-rw-r--r--tools/spi/Makefile64
34 files changed, 1126 insertions, 828 deletions
diff --git a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
index 31b5b21598ff..5bf13960f7f4 100644
--- a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
+++ b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
@@ -9,6 +9,7 @@ Required properties:
9 - "fsl,imx31-cspi" for SPI compatible with the one integrated on i.MX31 9 - "fsl,imx31-cspi" for SPI compatible with the one integrated on i.MX31
10 - "fsl,imx35-cspi" for SPI compatible with the one integrated on i.MX35 10 - "fsl,imx35-cspi" for SPI compatible with the one integrated on i.MX35
11 - "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51 11 - "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51
12 - "fsl,imx53-ecspi" for SPI compatible with the one integrated on i.MX53 and later Soc
12- reg : Offset and length of the register set for the device 13- reg : Offset and length of the register set for the device
13- interrupts : Should contain CSPI/eCSPI interrupt 14- interrupts : Should contain CSPI/eCSPI interrupt
14- cs-gpios : Specifies the gpio pins to be used for chipselects. 15- cs-gpios : Specifies the gpio pins to be used for chipselects.
diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt
index 64ee489571c4..39e5ef7c5e71 100644
--- a/Documentation/devicetree/bindings/spi/sh-msiof.txt
+++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt
@@ -6,6 +6,7 @@ Required properties:
6 "renesas,msiof-r8a7792" (R-Car V2H) 6 "renesas,msiof-r8a7792" (R-Car V2H)
7 "renesas,msiof-r8a7793" (R-Car M2-N) 7 "renesas,msiof-r8a7793" (R-Car M2-N)
8 "renesas,msiof-r8a7794" (R-Car E2) 8 "renesas,msiof-r8a7794" (R-Car E2)
9 "renesas,msiof-r8a7795" (R-Car H3)
9 "renesas,msiof-r8a7796" (R-Car M3-W) 10 "renesas,msiof-r8a7796" (R-Car M3-W)
10 "renesas,msiof-sh73a0" (SH-Mobile AG5) 11 "renesas,msiof-sh73a0" (SH-Mobile AG5)
11 "renesas,sh-mobile-msiof" (generic SH-Mobile compatibile device) 12 "renesas,sh-mobile-msiof" (generic SH-Mobile compatibile device)
diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.txt b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
index 83da4931d832..6e3ffacbba32 100644
--- a/Documentation/devicetree/bindings/spi/spi-rockchip.txt
+++ b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
@@ -6,6 +6,7 @@ and display controllers using the SPI communication interface.
6Required Properties: 6Required Properties:
7 7
8- compatible: should be one of the following. 8- compatible: should be one of the following.
9 "rockchip,rv1108-spi" for rv1108 SoCs.
9 "rockchip,rk3036-spi" for rk3036 SoCS. 10 "rockchip,rk3036-spi" for rk3036 SoCS.
10 "rockchip,rk3066-spi" for rk3066 SoCs. 11 "rockchip,rk3066-spi" for rk3066 SoCs.
11 "rockchip,rk3188-spi" for rk3188 SoCs. 12 "rockchip,rk3188-spi" for rk3188 SoCs.
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 9b31351fe429..a75f2a2cf780 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -55,7 +55,6 @@ comment "SPI Master Controller Drivers"
55 55
56config SPI_ALTERA 56config SPI_ALTERA
57 tristate "Altera SPI Controller" 57 tristate "Altera SPI Controller"
58 select SPI_BITBANG
59 help 58 help
60 This is the driver for the Altera SPI Controller. 59 This is the driver for the Altera SPI Controller.
61 60
@@ -518,8 +517,8 @@ config SPI_PPC4xx
518 517
519config SPI_PXA2XX 518config SPI_PXA2XX
520 tristate "PXA2xx SSP SPI master" 519 tristate "PXA2xx SSP SPI master"
521 depends on (ARCH_PXA || PCI || ACPI) 520 depends on (ARCH_PXA || ARCH_MMP || PCI || ACPI)
522 select PXA_SSP if ARCH_PXA 521 select PXA_SSP if ARCH_PXA || ARCH_MMP
523 help 522 help
524 This enables using a PXA2xx or Sodaville SSP port as a SPI master 523 This enables using a PXA2xx or Sodaville SSP port as a SPI master
525 controller. The driver can be configured to use any SSP port and 524 controller. The driver can be configured to use any SSP port and
diff --git a/drivers/spi/spi-altera.c b/drivers/spi/spi-altera.c
index b95010e72452..a5adf0d868fc 100644
--- a/drivers/spi/spi-altera.c
+++ b/drivers/spi/spi-altera.c
@@ -18,7 +18,6 @@
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/platform_device.h> 19#include <linux/platform_device.h>
20#include <linux/spi/spi.h> 20#include <linux/spi/spi.h>
21#include <linux/spi/spi_bitbang.h>
22#include <linux/io.h> 21#include <linux/io.h>
23#include <linux/of.h> 22#include <linux/of.h>
24 23
@@ -45,10 +44,6 @@
45#define ALTERA_SPI_CONTROL_SSO_MSK 0x400 44#define ALTERA_SPI_CONTROL_SSO_MSK 0x400
46 45
47struct altera_spi { 46struct altera_spi {
48 /* bitbang has to be first */
49 struct spi_bitbang bitbang;
50 struct completion done;
51
52 void __iomem *base; 47 void __iomem *base;
53 int irq; 48 int irq;
54 int len; 49 int len;
@@ -66,59 +61,64 @@ static inline struct altera_spi *altera_spi_to_hw(struct spi_device *sdev)
66 return spi_master_get_devdata(sdev->master); 61 return spi_master_get_devdata(sdev->master);
67} 62}
68 63
69static void altera_spi_chipsel(struct spi_device *spi, int value) 64static void altera_spi_set_cs(struct spi_device *spi, bool is_high)
70{ 65{
71 struct altera_spi *hw = altera_spi_to_hw(spi); 66 struct altera_spi *hw = altera_spi_to_hw(spi);
72 67
73 if (spi->mode & SPI_CS_HIGH) { 68 if (is_high) {
74 switch (value) { 69 hw->imr &= ~ALTERA_SPI_CONTROL_SSO_MSK;
75 case BITBANG_CS_INACTIVE: 70 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL);
76 writel(1 << spi->chip_select, 71 writel(0, hw->base + ALTERA_SPI_SLAVE_SEL);
77 hw->base + ALTERA_SPI_SLAVE_SEL);
78 hw->imr |= ALTERA_SPI_CONTROL_SSO_MSK;
79 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL);
80 break;
81
82 case BITBANG_CS_ACTIVE:
83 hw->imr &= ~ALTERA_SPI_CONTROL_SSO_MSK;
84 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL);
85 writel(0, hw->base + ALTERA_SPI_SLAVE_SEL);
86 break;
87 }
88 } else { 72 } else {
89 switch (value) { 73 writel(BIT(spi->chip_select), hw->base + ALTERA_SPI_SLAVE_SEL);
90 case BITBANG_CS_INACTIVE: 74 hw->imr |= ALTERA_SPI_CONTROL_SSO_MSK;
91 hw->imr &= ~ALTERA_SPI_CONTROL_SSO_MSK; 75 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL);
92 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); 76 }
93 break; 77}
78
79static void altera_spi_tx_word(struct altera_spi *hw)
80{
81 unsigned int txd = 0;
94 82
95 case BITBANG_CS_ACTIVE: 83 if (hw->tx) {
96 writel(1 << spi->chip_select, 84 switch (hw->bytes_per_word) {
97 hw->base + ALTERA_SPI_SLAVE_SEL); 85 case 1:
98 hw->imr |= ALTERA_SPI_CONTROL_SSO_MSK; 86 txd = hw->tx[hw->count];
99 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); 87 break;
88 case 2:
89 txd = (hw->tx[hw->count * 2]
90 | (hw->tx[hw->count * 2 + 1] << 8));
100 break; 91 break;
101 } 92 }
102 } 93 }
94
95 writel(txd, hw->base + ALTERA_SPI_TXDATA);
103} 96}
104 97
105static inline unsigned int hw_txbyte(struct altera_spi *hw, int count) 98static void altera_spi_rx_word(struct altera_spi *hw)
106{ 99{
107 if (hw->tx) { 100 unsigned int rxd;
101
102 rxd = readl(hw->base + ALTERA_SPI_RXDATA);
103 if (hw->rx) {
108 switch (hw->bytes_per_word) { 104 switch (hw->bytes_per_word) {
109 case 1: 105 case 1:
110 return hw->tx[count]; 106 hw->rx[hw->count] = rxd;
107 break;
111 case 2: 108 case 2:
112 return (hw->tx[count * 2] 109 hw->rx[hw->count * 2] = rxd;
113 | (hw->tx[count * 2 + 1] << 8)); 110 hw->rx[hw->count * 2 + 1] = rxd >> 8;
111 break;
114 } 112 }
115 } 113 }
116 return 0; 114
115 hw->count++;
117} 116}
118 117
119static int altera_spi_txrx(struct spi_device *spi, struct spi_transfer *t) 118static int altera_spi_txrx(struct spi_master *master,
119 struct spi_device *spi, struct spi_transfer *t)
120{ 120{
121 struct altera_spi *hw = altera_spi_to_hw(spi); 121 struct altera_spi *hw = spi_master_get_devdata(master);
122 122
123 hw->tx = t->tx_buf; 123 hw->tx = t->tx_buf;
124 hw->rx = t->rx_buf; 124 hw->rx = t->rx_buf;
@@ -132,67 +132,39 @@ static int altera_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
132 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); 132 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL);
133 133
134 /* send the first byte */ 134 /* send the first byte */
135 writel(hw_txbyte(hw, 0), hw->base + ALTERA_SPI_TXDATA); 135 altera_spi_tx_word(hw);
136
137 wait_for_completion(&hw->done);
138 /* disable receive interrupt */
139 hw->imr &= ~ALTERA_SPI_CONTROL_IRRDY_MSK;
140 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL);
141 } else { 136 } else {
142 while (hw->count < hw->len) { 137 while (hw->count < hw->len) {
143 unsigned int rxd; 138 altera_spi_tx_word(hw);
144
145 writel(hw_txbyte(hw, hw->count),
146 hw->base + ALTERA_SPI_TXDATA);
147 139
148 while (!(readl(hw->base + ALTERA_SPI_STATUS) & 140 while (!(readl(hw->base + ALTERA_SPI_STATUS) &
149 ALTERA_SPI_STATUS_RRDY_MSK)) 141 ALTERA_SPI_STATUS_RRDY_MSK))
150 cpu_relax(); 142 cpu_relax();
151 143
152 rxd = readl(hw->base + ALTERA_SPI_RXDATA); 144 altera_spi_rx_word(hw);
153 if (hw->rx) {
154 switch (hw->bytes_per_word) {
155 case 1:
156 hw->rx[hw->count] = rxd;
157 break;
158 case 2:
159 hw->rx[hw->count * 2] = rxd;
160 hw->rx[hw->count * 2 + 1] = rxd >> 8;
161 break;
162 }
163 }
164
165 hw->count++;
166 } 145 }
146 spi_finalize_current_transfer(master);
167 } 147 }
168 148
169 return hw->count * hw->bytes_per_word; 149 return t->len;
170} 150}
171 151
172static irqreturn_t altera_spi_irq(int irq, void *dev) 152static irqreturn_t altera_spi_irq(int irq, void *dev)
173{ 153{
174 struct altera_spi *hw = dev; 154 struct spi_master *master = dev;
175 unsigned int rxd; 155 struct altera_spi *hw = spi_master_get_devdata(master);
176 156
177 rxd = readl(hw->base + ALTERA_SPI_RXDATA); 157 altera_spi_rx_word(hw);
178 if (hw->rx) {
179 switch (hw->bytes_per_word) {
180 case 1:
181 hw->rx[hw->count] = rxd;
182 break;
183 case 2:
184 hw->rx[hw->count * 2] = rxd;
185 hw->rx[hw->count * 2 + 1] = rxd >> 8;
186 break;
187 }
188 }
189 158
190 hw->count++; 159 if (hw->count < hw->len) {
160 altera_spi_tx_word(hw);
161 } else {
162 /* disable receive interrupt */
163 hw->imr &= ~ALTERA_SPI_CONTROL_IRRDY_MSK;
164 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL);
191 165
192 if (hw->count < hw->len) 166 spi_finalize_current_transfer(master);
193 writel(hw_txbyte(hw, hw->count), hw->base + ALTERA_SPI_TXDATA); 167 }
194 else
195 complete(&hw->done);
196 168
197 return IRQ_HANDLED; 169 return IRQ_HANDLED;
198} 170}
@@ -214,14 +186,10 @@ static int altera_spi_probe(struct platform_device *pdev)
214 master->mode_bits = SPI_CS_HIGH; 186 master->mode_bits = SPI_CS_HIGH;
215 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16); 187 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
216 master->dev.of_node = pdev->dev.of_node; 188 master->dev.of_node = pdev->dev.of_node;
189 master->transfer_one = altera_spi_txrx;
190 master->set_cs = altera_spi_set_cs;
217 191
218 hw = spi_master_get_devdata(master); 192 hw = spi_master_get_devdata(master);
219 platform_set_drvdata(pdev, hw);
220
221 /* setup the state for the bitbang driver */
222 hw->bitbang.master = master;
223 hw->bitbang.chipselect = altera_spi_chipsel;
224 hw->bitbang.txrx_bufs = altera_spi_txrx;
225 193
226 /* find and map our resources */ 194 /* find and map our resources */
227 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 195 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -239,15 +207,13 @@ static int altera_spi_probe(struct platform_device *pdev)
239 /* irq is optional */ 207 /* irq is optional */
240 hw->irq = platform_get_irq(pdev, 0); 208 hw->irq = platform_get_irq(pdev, 0);
241 if (hw->irq >= 0) { 209 if (hw->irq >= 0) {
242 init_completion(&hw->done);
243 err = devm_request_irq(&pdev->dev, hw->irq, altera_spi_irq, 0, 210 err = devm_request_irq(&pdev->dev, hw->irq, altera_spi_irq, 0,
244 pdev->name, hw); 211 pdev->name, master);
245 if (err) 212 if (err)
246 goto exit; 213 goto exit;
247 } 214 }
248 215
249 /* register our spi controller */ 216 err = devm_spi_register_master(&pdev->dev, master);
250 err = spi_bitbang_start(&hw->bitbang);
251 if (err) 217 if (err)
252 goto exit; 218 goto exit;
253 dev_info(&pdev->dev, "base %p, irq %d\n", hw->base, hw->irq); 219 dev_info(&pdev->dev, "base %p, irq %d\n", hw->base, hw->irq);
@@ -258,16 +224,6 @@ exit:
258 return err; 224 return err;
259} 225}
260 226
261static int altera_spi_remove(struct platform_device *dev)
262{
263 struct altera_spi *hw = platform_get_drvdata(dev);
264 struct spi_master *master = hw->bitbang.master;
265
266 spi_bitbang_stop(&hw->bitbang);
267 spi_master_put(master);
268 return 0;
269}
270
271#ifdef CONFIG_OF 227#ifdef CONFIG_OF
272static const struct of_device_id altera_spi_match[] = { 228static const struct of_device_id altera_spi_match[] = {
273 { .compatible = "ALTR,spi-1.0", }, 229 { .compatible = "ALTR,spi-1.0", },
@@ -279,7 +235,6 @@ MODULE_DEVICE_TABLE(of, altera_spi_match);
279 235
280static struct platform_driver altera_spi_driver = { 236static struct platform_driver altera_spi_driver = {
281 .probe = altera_spi_probe, 237 .probe = altera_spi_probe,
282 .remove = altera_spi_remove,
283 .driver = { 238 .driver = {
284 .name = DRV_NAME, 239 .name = DRV_NAME,
285 .pm = NULL, 240 .pm = NULL,
diff --git a/drivers/spi/spi-ath79.c b/drivers/spi/spi-ath79.c
index b89cee11f418..0719bd484891 100644
--- a/drivers/spi/spi-ath79.c
+++ b/drivers/spi/spi-ath79.c
@@ -39,15 +39,15 @@ struct ath79_spi {
39 u32 reg_ctrl; 39 u32 reg_ctrl;
40 void __iomem *base; 40 void __iomem *base;
41 struct clk *clk; 41 struct clk *clk;
42 unsigned rrw_delay; 42 unsigned int rrw_delay;
43}; 43};
44 44
45static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg) 45static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned int reg)
46{ 46{
47 return ioread32(sp->base + reg); 47 return ioread32(sp->base + reg);
48} 48}
49 49
50static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val) 50static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val)
51{ 51{
52 iowrite32(val, sp->base + reg); 52 iowrite32(val, sp->base + reg);
53} 53}
@@ -57,7 +57,7 @@ static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
57 return spi_master_get_devdata(spi->master); 57 return spi_master_get_devdata(spi->master);
58} 58}
59 59
60static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs) 60static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned int nsecs)
61{ 61{
62 if (nsecs > sp->rrw_delay) 62 if (nsecs > sp->rrw_delay)
63 ndelay(nsecs - sp->rrw_delay); 63 ndelay(nsecs - sp->rrw_delay);
@@ -148,9 +148,8 @@ static int ath79_spi_setup_cs(struct spi_device *spi)
148 148
149static void ath79_spi_cleanup_cs(struct spi_device *spi) 149static void ath79_spi_cleanup_cs(struct spi_device *spi)
150{ 150{
151 if (gpio_is_valid(spi->cs_gpio)) { 151 if (gpio_is_valid(spi->cs_gpio))
152 gpio_free(spi->cs_gpio); 152 gpio_free(spi->cs_gpio);
153 }
154} 153}
155 154
156static int ath79_spi_setup(struct spi_device *spi) 155static int ath79_spi_setup(struct spi_device *spi)
@@ -176,7 +175,7 @@ static void ath79_spi_cleanup(struct spi_device *spi)
176 spi_bitbang_cleanup(spi); 175 spi_bitbang_cleanup(spi);
177} 176}
178 177
179static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, 178static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs,
180 u32 word, u8 bits) 179 u32 word, u8 bits)
181{ 180{
182 struct ath79_spi *sp = ath79_spidev_to_sp(spi); 181 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c
index b19722ba908c..6ef6c44f39f5 100644
--- a/drivers/spi/spi-bcm-qspi.c
+++ b/drivers/spi/spi-bcm-qspi.c
@@ -25,7 +25,6 @@
25#include <linux/ioport.h> 25#include <linux/ioport.h>
26#include <linux/kernel.h> 26#include <linux/kernel.h>
27#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/mtd/spi-nor.h>
29#include <linux/of.h> 28#include <linux/of.h>
30#include <linux/of_irq.h> 29#include <linux/of_irq.h>
31#include <linux/platform_device.h> 30#include <linux/platform_device.h>
@@ -349,76 +348,60 @@ static void bcm_qspi_bspi_set_xfer_params(struct bcm_qspi *qspi, u8 cmd_byte,
349 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, flex_mode); 348 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, flex_mode);
350} 349}
351 350
352static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi, int width, 351static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi,
353 int addrlen, int hp) 352 struct spi_flash_read_message *msg,
353 int hp)
354{ 354{
355 int bpc = 0, bpp = 0; 355 int bpc = 0, bpp = 0;
356 u8 command = SPINOR_OP_READ_FAST; 356 u8 command = msg->read_opcode;
357 int flex_mode = 1, rv = 0; 357 int width = msg->data_nbits ? msg->data_nbits : SPI_NBITS_SINGLE;
358 bool spans_4byte = false; 358 int addrlen = msg->addr_width;
359 int addr_nbits = msg->addr_nbits ? msg->addr_nbits : SPI_NBITS_SINGLE;
360 int flex_mode = 1;
359 361
360 dev_dbg(&qspi->pdev->dev, "set flex mode w %x addrlen %x hp %d\n", 362 dev_dbg(&qspi->pdev->dev, "set flex mode w %x addrlen %x hp %d\n",
361 width, addrlen, hp); 363 width, addrlen, hp);
362 364
363 if (addrlen == BSPI_ADDRLEN_4BYTES) { 365 if (addrlen == BSPI_ADDRLEN_4BYTES)
364 bpp = BSPI_BPP_ADDR_SELECT_MASK; 366 bpp = BSPI_BPP_ADDR_SELECT_MASK;
365 spans_4byte = true;
366 }
367 367
368 bpp |= 8; 368 bpp |= msg->dummy_bytes * (8/addr_nbits);
369 369
370 switch (width) { 370 switch (width) {
371 case SPI_NBITS_SINGLE: 371 case SPI_NBITS_SINGLE:
372 if (addrlen == BSPI_ADDRLEN_3BYTES) 372 if (addrlen == BSPI_ADDRLEN_3BYTES)
373 /* default mode, does not need flex_cmd */ 373 /* default mode, does not need flex_cmd */
374 flex_mode = 0; 374 flex_mode = 0;
375 else
376 command = SPINOR_OP_READ_FAST_4B;
377 break; 375 break;
378 case SPI_NBITS_DUAL: 376 case SPI_NBITS_DUAL:
379 bpc = 0x00000001; 377 bpc = 0x00000001;
380 if (hp) { 378 if (hp) {
381 bpc |= 0x00010100; /* address and mode are 2-bit */ 379 bpc |= 0x00010100; /* address and mode are 2-bit */
382 bpp = BSPI_BPP_MODE_SELECT_MASK; 380 bpp = BSPI_BPP_MODE_SELECT_MASK;
383 command = OPCODE_DIOR;
384 if (spans_4byte)
385 command = OPCODE_DIOR_4B;
386 } else {
387 command = SPINOR_OP_READ_1_1_2;
388 if (spans_4byte)
389 command = SPINOR_OP_READ_1_1_2_4B;
390 } 381 }
391 break; 382 break;
392 case SPI_NBITS_QUAD: 383 case SPI_NBITS_QUAD:
393 bpc = 0x00000002; 384 bpc = 0x00000002;
394 if (hp) { 385 if (hp) {
395 bpc |= 0x00020200; /* address and mode are 4-bit */ 386 bpc |= 0x00020200; /* address and mode are 4-bit */
396 bpp = 4; /* dummy cycles */ 387 bpp |= BSPI_BPP_MODE_SELECT_MASK;
397 bpp |= BSPI_BPP_ADDR_SELECT_MASK;
398 command = OPCODE_QIOR;
399 if (spans_4byte)
400 command = OPCODE_QIOR_4B;
401 } else {
402 command = SPINOR_OP_READ_1_1_4;
403 if (spans_4byte)
404 command = SPINOR_OP_READ_1_1_4_4B;
405 } 388 }
406 break; 389 break;
407 default: 390 default:
408 rv = -EINVAL; 391 return -EINVAL;
409 break;
410 } 392 }
411 393
412 if (rv == 0) 394 bcm_qspi_bspi_set_xfer_params(qspi, command, bpp, bpc, flex_mode);
413 bcm_qspi_bspi_set_xfer_params(qspi, command, bpp, bpc,
414 flex_mode);
415 395
416 return rv; 396 return 0;
417} 397}
418 398
419static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi, int width, 399static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi,
420 int addrlen, int hp) 400 struct spi_flash_read_message *msg,
401 int hp)
421{ 402{
403 int width = msg->data_nbits ? msg->data_nbits : SPI_NBITS_SINGLE;
404 int addrlen = msg->addr_width;
422 u32 data = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL); 405 u32 data = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
423 406
424 dev_dbg(&qspi->pdev->dev, "set override mode w %x addrlen %x hp %d\n", 407 dev_dbg(&qspi->pdev->dev, "set override mode w %x addrlen %x hp %d\n",
@@ -430,7 +413,6 @@ static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi, int width,
430 data &= ~(BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD | 413 data &= ~(BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD |
431 BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL); 414 BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL);
432 break; 415 break;
433
434 case SPI_NBITS_QUAD: 416 case SPI_NBITS_QUAD:
435 /* clear dual mode and set quad mode */ 417 /* clear dual mode and set quad mode */
436 data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL; 418 data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL;
@@ -455,15 +437,17 @@ static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi, int width,
455 /* set the override mode */ 437 /* set the override mode */
456 data |= BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE; 438 data |= BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
457 bcm_qspi_write(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL, data); 439 bcm_qspi_write(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL, data);
458 bcm_qspi_bspi_set_xfer_params(qspi, SPINOR_OP_READ_FAST, 0, 0, 0); 440 bcm_qspi_bspi_set_xfer_params(qspi, msg->read_opcode, 0, 0, 0);
459 441
460 return 0; 442 return 0;
461} 443}
462 444
463static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi, 445static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi,
464 int width, int addrlen, int hp) 446 struct spi_flash_read_message *msg, int hp)
465{ 447{
466 int error = 0; 448 int error = 0;
449 int width = msg->data_nbits ? msg->data_nbits : SPI_NBITS_SINGLE;
450 int addrlen = msg->addr_width;
467 451
468 /* default mode */ 452 /* default mode */
469 qspi->xfer_mode.flex_mode = true; 453 qspi->xfer_mode.flex_mode = true;
@@ -475,23 +459,13 @@ static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi,
475 mask = BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE; 459 mask = BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
476 if (val & mask || qspi->s3_strap_override_ctrl & mask) { 460 if (val & mask || qspi->s3_strap_override_ctrl & mask) {
477 qspi->xfer_mode.flex_mode = false; 461 qspi->xfer_mode.flex_mode = false;
478 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 462 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
479 0); 463 error = bcm_qspi_bspi_set_override(qspi, msg, hp);
480
481 if ((val | qspi->s3_strap_override_ctrl) &
482 BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL)
483 width = SPI_NBITS_DUAL;
484 else if ((val | qspi->s3_strap_override_ctrl) &
485 BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD)
486 width = SPI_NBITS_QUAD;
487
488 error = bcm_qspi_bspi_set_override(qspi, width, addrlen,
489 hp);
490 } 464 }
491 } 465 }
492 466
493 if (qspi->xfer_mode.flex_mode) 467 if (qspi->xfer_mode.flex_mode)
494 error = bcm_qspi_bspi_set_flex_mode(qspi, width, addrlen, hp); 468 error = bcm_qspi_bspi_set_flex_mode(qspi, msg, hp);
495 469
496 if (error) { 470 if (error) {
497 dev_warn(&qspi->pdev->dev, 471 dev_warn(&qspi->pdev->dev,
@@ -981,7 +955,7 @@ static int bcm_qspi_flash_read(struct spi_device *spi,
981 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master); 955 struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
982 int ret = 0; 956 int ret = 0;
983 bool mspi_read = false; 957 bool mspi_read = false;
984 u32 io_width, addrlen, addr, len; 958 u32 addr, len;
985 u_char *buf; 959 u_char *buf;
986 960
987 buf = msg->buf; 961 buf = msg->buf;
@@ -1010,9 +984,7 @@ static int bcm_qspi_flash_read(struct spi_device *spi,
1010 if (mspi_read) 984 if (mspi_read)
1011 return bcm_qspi_mspi_flash_read(spi, msg); 985 return bcm_qspi_mspi_flash_read(spi, msg);
1012 986
1013 io_width = msg->data_nbits ? msg->data_nbits : SPI_NBITS_SINGLE; 987 ret = bcm_qspi_bspi_set_mode(qspi, msg, -1);
1014 addrlen = msg->addr_width;
1015 ret = bcm_qspi_bspi_set_mode(qspi, io_width, addrlen, -1);
1016 988
1017 if (!ret) 989 if (!ret)
1018 ret = bcm_qspi_bspi_flash_read(spi, msg); 990 ret = bcm_qspi_bspi_flash_read(spi, msg);
@@ -1422,6 +1394,11 @@ static int __maybe_unused bcm_qspi_suspend(struct device *dev)
1422{ 1394{
1423 struct bcm_qspi *qspi = dev_get_drvdata(dev); 1395 struct bcm_qspi *qspi = dev_get_drvdata(dev);
1424 1396
1397 /* store the override strap value */
1398 if (!bcm_qspi_bspi_ver_three(qspi))
1399 qspi->s3_strap_override_ctrl =
1400 bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
1401
1425 spi_master_suspend(qspi->master); 1402 spi_master_suspend(qspi->master);
1426 clk_disable(qspi->clk); 1403 clk_disable(qspi->clk);
1427 bcm_qspi_hw_uninit(qspi); 1404 bcm_qspi_hw_uninit(qspi);
diff --git a/drivers/spi/spi-bcm63xx-hsspi.c b/drivers/spi/spi-bcm63xx-hsspi.c
index 4da2d4a524ca..cbcba614b253 100644
--- a/drivers/spi/spi-bcm63xx-hsspi.c
+++ b/drivers/spi/spi-bcm63xx-hsspi.c
@@ -108,7 +108,7 @@ struct bcm63xx_hsspi {
108 u8 cs_polarity; 108 u8 cs_polarity;
109}; 109};
110 110
111static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned cs, 111static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs,
112 bool active) 112 bool active)
113{ 113{
114 u32 reg; 114 u32 reg;
@@ -127,7 +127,7 @@ static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned cs,
127static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs, 127static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
128 struct spi_device *spi, int hz) 128 struct spi_device *spi, int hz)
129{ 129{
130 unsigned profile = spi->chip_select; 130 unsigned int profile = spi->chip_select;
131 u32 reg; 131 u32 reg;
132 132
133 reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz)); 133 reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
@@ -154,7 +154,7 @@ static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
154static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) 154static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
155{ 155{
156 struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master); 156 struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
157 unsigned chip_select = spi->chip_select; 157 unsigned int chip_select = spi->chip_select;
158 u16 opcode = 0; 158 u16 opcode = 0;
159 int pending = t->len; 159 int pending = t->len;
160 int step_size = HSSPI_BUFFER_LEN; 160 int step_size = HSSPI_BUFFER_LEN;
@@ -338,8 +338,8 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev)
338 338
339 irq = platform_get_irq(pdev, 0); 339 irq = platform_get_irq(pdev, 0);
340 if (irq < 0) { 340 if (irq < 0) {
341 dev_err(dev, "no irq\n"); 341 dev_err(dev, "no irq: %d\n", irq);
342 return -ENXIO; 342 return irq;
343 } 343 }
344 344
345 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 345 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c
index 84c7356ce5b4..bfe5754768f9 100644
--- a/drivers/spi/spi-bcm63xx.c
+++ b/drivers/spi/spi-bcm63xx.c
@@ -530,8 +530,8 @@ static int bcm63xx_spi_probe(struct platform_device *pdev)
530 530
531 irq = platform_get_irq(pdev, 0); 531 irq = platform_get_irq(pdev, 0);
532 if (irq < 0) { 532 if (irq < 0) {
533 dev_err(dev, "no irq\n"); 533 dev_err(dev, "no irq: %d\n", irq);
534 return -ENXIO; 534 return irq;
535 } 535 }
536 536
537 clk = devm_clk_get(dev, "spi"); 537 clk = devm_clk_get(dev, "spi");
diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c
index f0b5c7b91f37..5c9516ae4942 100644
--- a/drivers/spi/spi-cadence.c
+++ b/drivers/spi/spi-cadence.c
@@ -576,10 +576,10 @@ static int cdns_spi_probe(struct platform_device *pdev)
576 goto clk_dis_apb; 576 goto clk_dis_apb;
577 } 577 }
578 578
579 pm_runtime_enable(&pdev->dev);
580 pm_runtime_use_autosuspend(&pdev->dev); 579 pm_runtime_use_autosuspend(&pdev->dev);
581 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); 580 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
582 pm_runtime_set_active(&pdev->dev); 581 pm_runtime_set_active(&pdev->dev);
582 pm_runtime_enable(&pdev->dev);
583 583
584 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs); 584 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
585 if (ret < 0) 585 if (ret < 0)
@@ -704,7 +704,9 @@ static int __maybe_unused cdns_spi_resume(struct device *dev)
704{ 704{
705 struct platform_device *pdev = to_platform_device(dev); 705 struct platform_device *pdev = to_platform_device(dev);
706 struct spi_master *master = platform_get_drvdata(pdev); 706 struct spi_master *master = platform_get_drvdata(pdev);
707 struct cdns_spi *xspi = spi_master_get_devdata(master);
707 708
709 cdns_spi_init_hw(xspi);
708 return spi_master_resume(master); 710 return spi_master_resume(master);
709} 711}
710 712
diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c
index b5d766064b7b..e5cc07357746 100644
--- a/drivers/spi/spi-ep93xx.c
+++ b/drivers/spi/spi-ep93xx.c
@@ -70,12 +70,9 @@
70 70
71/** 71/**
72 * struct ep93xx_spi - EP93xx SPI controller structure 72 * struct ep93xx_spi - EP93xx SPI controller structure
73 * @pdev: pointer to platform device
74 * @clk: clock for the controller 73 * @clk: clock for the controller
75 * @regs_base: pointer to ioremap()'d registers 74 * @mmio: pointer to ioremap()'d registers
76 * @sspdr_phys: physical address of the SSPDR register 75 * @sspdr_phys: physical address of the SSPDR register
77 * @wait: wait here until given transfer is completed
78 * @current_msg: message that is currently processed (or %NULL if none)
79 * @tx: current byte in transfer to transmit 76 * @tx: current byte in transfer to transmit
80 * @rx: current byte in transfer to receive 77 * @rx: current byte in transfer to receive
81 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one 78 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
@@ -90,12 +87,9 @@
90 * the client 87 * the client
91 */ 88 */
92struct ep93xx_spi { 89struct ep93xx_spi {
93 const struct platform_device *pdev;
94 struct clk *clk; 90 struct clk *clk;
95 void __iomem *regs_base; 91 void __iomem *mmio;
96 unsigned long sspdr_phys; 92 unsigned long sspdr_phys;
97 struct completion wait;
98 struct spi_message *current_msg;
99 size_t tx; 93 size_t tx;
100 size_t rx; 94 size_t rx;
101 size_t fifo_level; 95 size_t fifo_level;
@@ -111,91 +105,23 @@ struct ep93xx_spi {
111/* converts bits per word to CR0.DSS value */ 105/* converts bits per word to CR0.DSS value */
112#define bits_per_word_to_dss(bpw) ((bpw) - 1) 106#define bits_per_word_to_dss(bpw) ((bpw) - 1)
113 107
114static void ep93xx_spi_write_u8(const struct ep93xx_spi *espi,
115 u16 reg, u8 value)
116{
117 writeb(value, espi->regs_base + reg);
118}
119
120static u8 ep93xx_spi_read_u8(const struct ep93xx_spi *spi, u16 reg)
121{
122 return readb(spi->regs_base + reg);
123}
124
125static void ep93xx_spi_write_u16(const struct ep93xx_spi *espi,
126 u16 reg, u16 value)
127{
128 writew(value, espi->regs_base + reg);
129}
130
131static u16 ep93xx_spi_read_u16(const struct ep93xx_spi *spi, u16 reg)
132{
133 return readw(spi->regs_base + reg);
134}
135
136static int ep93xx_spi_enable(const struct ep93xx_spi *espi)
137{
138 u8 regval;
139 int err;
140
141 err = clk_enable(espi->clk);
142 if (err)
143 return err;
144
145 regval = ep93xx_spi_read_u8(espi, SSPCR1);
146 regval |= SSPCR1_SSE;
147 ep93xx_spi_write_u8(espi, SSPCR1, regval);
148
149 return 0;
150}
151
152static void ep93xx_spi_disable(const struct ep93xx_spi *espi)
153{
154 u8 regval;
155
156 regval = ep93xx_spi_read_u8(espi, SSPCR1);
157 regval &= ~SSPCR1_SSE;
158 ep93xx_spi_write_u8(espi, SSPCR1, regval);
159
160 clk_disable(espi->clk);
161}
162
163static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi)
164{
165 u8 regval;
166
167 regval = ep93xx_spi_read_u8(espi, SSPCR1);
168 regval |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
169 ep93xx_spi_write_u8(espi, SSPCR1, regval);
170}
171
172static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi)
173{
174 u8 regval;
175
176 regval = ep93xx_spi_read_u8(espi, SSPCR1);
177 regval &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
178 ep93xx_spi_write_u8(espi, SSPCR1, regval);
179}
180
181/** 108/**
182 * ep93xx_spi_calc_divisors() - calculates SPI clock divisors 109 * ep93xx_spi_calc_divisors() - calculates SPI clock divisors
183 * @espi: ep93xx SPI controller struct 110 * @master: SPI master
184 * @rate: desired SPI output clock rate 111 * @rate: desired SPI output clock rate
185 * @div_cpsr: pointer to return the cpsr (pre-scaler) divider 112 * @div_cpsr: pointer to return the cpsr (pre-scaler) divider
186 * @div_scr: pointer to return the scr divider 113 * @div_scr: pointer to return the scr divider
187 */ 114 */
188static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi, 115static int ep93xx_spi_calc_divisors(struct spi_master *master,
189 u32 rate, u8 *div_cpsr, u8 *div_scr) 116 u32 rate, u8 *div_cpsr, u8 *div_scr)
190{ 117{
191 struct spi_master *master = platform_get_drvdata(espi->pdev); 118 struct ep93xx_spi *espi = spi_master_get_devdata(master);
192 unsigned long spi_clk_rate = clk_get_rate(espi->clk); 119 unsigned long spi_clk_rate = clk_get_rate(espi->clk);
193 int cpsr, scr; 120 int cpsr, scr;
194 121
195 /* 122 /*
196 * Make sure that max value is between values supported by the 123 * Make sure that max value is between values supported by the
197 * controller. Note that minimum value is already checked in 124 * controller.
198 * ep93xx_spi_transfer_one_message().
199 */ 125 */
200 rate = clamp(rate, master->min_speed_hz, master->max_speed_hz); 126 rate = clamp(rate, master->min_speed_hz, master->max_speed_hz);
201 127
@@ -220,26 +146,18 @@ static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi,
220 return -EINVAL; 146 return -EINVAL;
221} 147}
222 148
223static void ep93xx_spi_cs_control(struct spi_device *spi, bool enable) 149static int ep93xx_spi_chip_setup(struct spi_master *master,
224{
225 if (spi->mode & SPI_CS_HIGH)
226 enable = !enable;
227
228 if (gpio_is_valid(spi->cs_gpio))
229 gpio_set_value(spi->cs_gpio, !enable);
230}
231
232static int ep93xx_spi_chip_setup(const struct ep93xx_spi *espi,
233 struct spi_device *spi, 150 struct spi_device *spi,
234 struct spi_transfer *xfer) 151 struct spi_transfer *xfer)
235{ 152{
153 struct ep93xx_spi *espi = spi_master_get_devdata(master);
236 u8 dss = bits_per_word_to_dss(xfer->bits_per_word); 154 u8 dss = bits_per_word_to_dss(xfer->bits_per_word);
237 u8 div_cpsr = 0; 155 u8 div_cpsr = 0;
238 u8 div_scr = 0; 156 u8 div_scr = 0;
239 u16 cr0; 157 u16 cr0;
240 int err; 158 int err;
241 159
242 err = ep93xx_spi_calc_divisors(espi, xfer->speed_hz, 160 err = ep93xx_spi_calc_divisors(master, xfer->speed_hz,
243 &div_cpsr, &div_scr); 161 &div_cpsr, &div_scr);
244 if (err) 162 if (err)
245 return err; 163 return err;
@@ -248,51 +166,49 @@ static int ep93xx_spi_chip_setup(const struct ep93xx_spi *espi,
248 cr0 |= (spi->mode & (SPI_CPHA | SPI_CPOL)) << SSPCR0_MODE_SHIFT; 166 cr0 |= (spi->mode & (SPI_CPHA | SPI_CPOL)) << SSPCR0_MODE_SHIFT;
249 cr0 |= dss; 167 cr0 |= dss;
250 168
251 dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n", 169 dev_dbg(&master->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n",
252 spi->mode, div_cpsr, div_scr, dss); 170 spi->mode, div_cpsr, div_scr, dss);
253 dev_dbg(&espi->pdev->dev, "setup: cr0 %#x\n", cr0); 171 dev_dbg(&master->dev, "setup: cr0 %#x\n", cr0);
254 172
255 ep93xx_spi_write_u8(espi, SSPCPSR, div_cpsr); 173 writel(div_cpsr, espi->mmio + SSPCPSR);
256 ep93xx_spi_write_u16(espi, SSPCR0, cr0); 174 writel(cr0, espi->mmio + SSPCR0);
257 175
258 return 0; 176 return 0;
259} 177}
260 178
261static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t) 179static void ep93xx_do_write(struct spi_master *master)
262{ 180{
263 if (t->bits_per_word > 8) { 181 struct ep93xx_spi *espi = spi_master_get_devdata(master);
264 u16 tx_val = 0; 182 struct spi_transfer *xfer = master->cur_msg->state;
183 u32 val = 0;
265 184
266 if (t->tx_buf) 185 if (xfer->bits_per_word > 8) {
267 tx_val = ((u16 *)t->tx_buf)[espi->tx]; 186 if (xfer->tx_buf)
268 ep93xx_spi_write_u16(espi, SSPDR, tx_val); 187 val = ((u16 *)xfer->tx_buf)[espi->tx];
269 espi->tx += sizeof(tx_val); 188 espi->tx += 2;
270 } else { 189 } else {
271 u8 tx_val = 0; 190 if (xfer->tx_buf)
272 191 val = ((u8 *)xfer->tx_buf)[espi->tx];
273 if (t->tx_buf) 192 espi->tx += 1;
274 tx_val = ((u8 *)t->tx_buf)[espi->tx];
275 ep93xx_spi_write_u8(espi, SSPDR, tx_val);
276 espi->tx += sizeof(tx_val);
277 } 193 }
194 writel(val, espi->mmio + SSPDR);
278} 195}
279 196
280static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t) 197static void ep93xx_do_read(struct spi_master *master)
281{ 198{
282 if (t->bits_per_word > 8) { 199 struct ep93xx_spi *espi = spi_master_get_devdata(master);
283 u16 rx_val; 200 struct spi_transfer *xfer = master->cur_msg->state;
284 201 u32 val;
285 rx_val = ep93xx_spi_read_u16(espi, SSPDR); 202
286 if (t->rx_buf) 203 val = readl(espi->mmio + SSPDR);
287 ((u16 *)t->rx_buf)[espi->rx] = rx_val; 204 if (xfer->bits_per_word > 8) {
288 espi->rx += sizeof(rx_val); 205 if (xfer->rx_buf)
206 ((u16 *)xfer->rx_buf)[espi->rx] = val;
207 espi->rx += 2;
289 } else { 208 } else {
290 u8 rx_val; 209 if (xfer->rx_buf)
291 210 ((u8 *)xfer->rx_buf)[espi->rx] = val;
292 rx_val = ep93xx_spi_read_u8(espi, SSPDR); 211 espi->rx += 1;
293 if (t->rx_buf)
294 ((u8 *)t->rx_buf)[espi->rx] = rx_val;
295 espi->rx += sizeof(rx_val);
296 } 212 }
297} 213}
298 214
@@ -307,44 +223,32 @@ static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t)
307 * When this function is finished, RX FIFO should be empty and TX FIFO should be 223 * When this function is finished, RX FIFO should be empty and TX FIFO should be
308 * full. 224 * full.
309 */ 225 */
310static int ep93xx_spi_read_write(struct ep93xx_spi *espi) 226static int ep93xx_spi_read_write(struct spi_master *master)
311{ 227{
312 struct spi_message *msg = espi->current_msg; 228 struct ep93xx_spi *espi = spi_master_get_devdata(master);
313 struct spi_transfer *t = msg->state; 229 struct spi_transfer *xfer = master->cur_msg->state;
314 230
315 /* read as long as RX FIFO has frames in it */ 231 /* read as long as RX FIFO has frames in it */
316 while ((ep93xx_spi_read_u8(espi, SSPSR) & SSPSR_RNE)) { 232 while ((readl(espi->mmio + SSPSR) & SSPSR_RNE)) {
317 ep93xx_do_read(espi, t); 233 ep93xx_do_read(master);
318 espi->fifo_level--; 234 espi->fifo_level--;
319 } 235 }
320 236
321 /* write as long as TX FIFO has room */ 237 /* write as long as TX FIFO has room */
322 while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < t->len) { 238 while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < xfer->len) {
323 ep93xx_do_write(espi, t); 239 ep93xx_do_write(master);
324 espi->fifo_level++; 240 espi->fifo_level++;
325 } 241 }
326 242
327 if (espi->rx == t->len) 243 if (espi->rx == xfer->len)
328 return 0; 244 return 0;
329 245
330 return -EINPROGRESS; 246 return -EINPROGRESS;
331} 247}
332 248
333static void ep93xx_spi_pio_transfer(struct ep93xx_spi *espi)
334{
335 /*
336 * Now everything is set up for the current transfer. We prime the TX
337 * FIFO, enable interrupts, and wait for the transfer to complete.
338 */
339 if (ep93xx_spi_read_write(espi)) {
340 ep93xx_spi_enable_interrupts(espi);
341 wait_for_completion(&espi->wait);
342 }
343}
344
345/** 249/**
346 * ep93xx_spi_dma_prepare() - prepares a DMA transfer 250 * ep93xx_spi_dma_prepare() - prepares a DMA transfer
347 * @espi: ep93xx SPI controller struct 251 * @master: SPI master
348 * @dir: DMA transfer direction 252 * @dir: DMA transfer direction
349 * 253 *
350 * Function configures the DMA, maps the buffer and prepares the DMA 254 * Function configures the DMA, maps the buffer and prepares the DMA
@@ -352,9 +256,11 @@ static void ep93xx_spi_pio_transfer(struct ep93xx_spi *espi)
352 * in case of failure. 256 * in case of failure.
353 */ 257 */
354static struct dma_async_tx_descriptor * 258static struct dma_async_tx_descriptor *
355ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir) 259ep93xx_spi_dma_prepare(struct spi_master *master,
260 enum dma_transfer_direction dir)
356{ 261{
357 struct spi_transfer *t = espi->current_msg->state; 262 struct ep93xx_spi *espi = spi_master_get_devdata(master);
263 struct spi_transfer *xfer = master->cur_msg->state;
358 struct dma_async_tx_descriptor *txd; 264 struct dma_async_tx_descriptor *txd;
359 enum dma_slave_buswidth buswidth; 265 enum dma_slave_buswidth buswidth;
360 struct dma_slave_config conf; 266 struct dma_slave_config conf;
@@ -362,10 +268,10 @@ ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir)
362 struct sg_table *sgt; 268 struct sg_table *sgt;
363 struct dma_chan *chan; 269 struct dma_chan *chan;
364 const void *buf, *pbuf; 270 const void *buf, *pbuf;
365 size_t len = t->len; 271 size_t len = xfer->len;
366 int i, ret, nents; 272 int i, ret, nents;
367 273
368 if (t->bits_per_word > 8) 274 if (xfer->bits_per_word > 8)
369 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; 275 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
370 else 276 else
371 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; 277 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
@@ -375,14 +281,14 @@ ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir)
375 281
376 if (dir == DMA_DEV_TO_MEM) { 282 if (dir == DMA_DEV_TO_MEM) {
377 chan = espi->dma_rx; 283 chan = espi->dma_rx;
378 buf = t->rx_buf; 284 buf = xfer->rx_buf;
379 sgt = &espi->rx_sgt; 285 sgt = &espi->rx_sgt;
380 286
381 conf.src_addr = espi->sspdr_phys; 287 conf.src_addr = espi->sspdr_phys;
382 conf.src_addr_width = buswidth; 288 conf.src_addr_width = buswidth;
383 } else { 289 } else {
384 chan = espi->dma_tx; 290 chan = espi->dma_tx;
385 buf = t->tx_buf; 291 buf = xfer->tx_buf;
386 sgt = &espi->tx_sgt; 292 sgt = &espi->tx_sgt;
387 293
388 conf.dst_addr = espi->sspdr_phys; 294 conf.dst_addr = espi->sspdr_phys;
@@ -429,7 +335,7 @@ ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir)
429 } 335 }
430 336
431 if (WARN_ON(len)) { 337 if (WARN_ON(len)) {
432 dev_warn(&espi->pdev->dev, "len = %zu expected 0!\n", len); 338 dev_warn(&master->dev, "len = %zu expected 0!\n", len);
433 return ERR_PTR(-EINVAL); 339 return ERR_PTR(-EINVAL);
434 } 340 }
435 341
@@ -447,15 +353,16 @@ ep93xx_spi_dma_prepare(struct ep93xx_spi *espi, enum dma_transfer_direction dir)
447 353
448/** 354/**
449 * ep93xx_spi_dma_finish() - finishes with a DMA transfer 355 * ep93xx_spi_dma_finish() - finishes with a DMA transfer
450 * @espi: ep93xx SPI controller struct 356 * @master: SPI master
451 * @dir: DMA transfer direction 357 * @dir: DMA transfer direction
452 * 358 *
453 * Function finishes with the DMA transfer. After this, the DMA buffer is 359 * Function finishes with the DMA transfer. After this, the DMA buffer is
454 * unmapped. 360 * unmapped.
455 */ 361 */
456static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi, 362static void ep93xx_spi_dma_finish(struct spi_master *master,
457 enum dma_transfer_direction dir) 363 enum dma_transfer_direction dir)
458{ 364{
365 struct ep93xx_spi *espi = spi_master_get_devdata(master);
459 struct dma_chan *chan; 366 struct dma_chan *chan;
460 struct sg_table *sgt; 367 struct sg_table *sgt;
461 368
@@ -472,72 +379,107 @@ static void ep93xx_spi_dma_finish(struct ep93xx_spi *espi,
472 379
473static void ep93xx_spi_dma_callback(void *callback_param) 380static void ep93xx_spi_dma_callback(void *callback_param)
474{ 381{
475 complete(callback_param); 382 struct spi_master *master = callback_param;
383
384 ep93xx_spi_dma_finish(master, DMA_MEM_TO_DEV);
385 ep93xx_spi_dma_finish(master, DMA_DEV_TO_MEM);
386
387 spi_finalize_current_transfer(master);
476} 388}
477 389
478static void ep93xx_spi_dma_transfer(struct ep93xx_spi *espi) 390static int ep93xx_spi_dma_transfer(struct spi_master *master)
479{ 391{
480 struct spi_message *msg = espi->current_msg; 392 struct ep93xx_spi *espi = spi_master_get_devdata(master);
481 struct dma_async_tx_descriptor *rxd, *txd; 393 struct dma_async_tx_descriptor *rxd, *txd;
482 394
483 rxd = ep93xx_spi_dma_prepare(espi, DMA_DEV_TO_MEM); 395 rxd = ep93xx_spi_dma_prepare(master, DMA_DEV_TO_MEM);
484 if (IS_ERR(rxd)) { 396 if (IS_ERR(rxd)) {
485 dev_err(&espi->pdev->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd)); 397 dev_err(&master->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd));
486 msg->status = PTR_ERR(rxd); 398 return PTR_ERR(rxd);
487 return;
488 } 399 }
489 400
490 txd = ep93xx_spi_dma_prepare(espi, DMA_MEM_TO_DEV); 401 txd = ep93xx_spi_dma_prepare(master, DMA_MEM_TO_DEV);
491 if (IS_ERR(txd)) { 402 if (IS_ERR(txd)) {
492 ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM); 403 ep93xx_spi_dma_finish(master, DMA_DEV_TO_MEM);
493 dev_err(&espi->pdev->dev, "DMA TX failed: %ld\n", PTR_ERR(txd)); 404 dev_err(&master->dev, "DMA TX failed: %ld\n", PTR_ERR(txd));
494 msg->status = PTR_ERR(txd); 405 return PTR_ERR(txd);
495 return;
496 } 406 }
497 407
498 /* We are ready when RX is done */ 408 /* We are ready when RX is done */
499 rxd->callback = ep93xx_spi_dma_callback; 409 rxd->callback = ep93xx_spi_dma_callback;
500 rxd->callback_param = &espi->wait; 410 rxd->callback_param = master;
501 411
502 /* Now submit both descriptors and wait while they finish */ 412 /* Now submit both descriptors and start DMA */
503 dmaengine_submit(rxd); 413 dmaengine_submit(rxd);
504 dmaengine_submit(txd); 414 dmaengine_submit(txd);
505 415
506 dma_async_issue_pending(espi->dma_rx); 416 dma_async_issue_pending(espi->dma_rx);
507 dma_async_issue_pending(espi->dma_tx); 417 dma_async_issue_pending(espi->dma_tx);
508 418
509 wait_for_completion(&espi->wait); 419 /* signal that we need to wait for completion */
510 420 return 1;
511 ep93xx_spi_dma_finish(espi, DMA_MEM_TO_DEV);
512 ep93xx_spi_dma_finish(espi, DMA_DEV_TO_MEM);
513} 421}
514 422
515/** 423static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
516 * ep93xx_spi_process_transfer() - processes one SPI transfer
517 * @espi: ep93xx SPI controller struct
518 * @msg: current message
519 * @t: transfer to process
520 *
521 * This function processes one SPI transfer given in @t. Function waits until
522 * transfer is complete (may sleep) and updates @msg->status based on whether
523 * transfer was successfully processed or not.
524 */
525static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi,
526 struct spi_message *msg,
527 struct spi_transfer *t)
528{ 424{
529 int err; 425 struct spi_master *master = dev_id;
426 struct ep93xx_spi *espi = spi_master_get_devdata(master);
427 u32 val;
428
429 /*
430 * If we got ROR (receive overrun) interrupt we know that something is
431 * wrong. Just abort the message.
432 */
433 if (readl(espi->mmio + SSPIIR) & SSPIIR_RORIS) {
434 /* clear the overrun interrupt */
435 writel(0, espi->mmio + SSPICR);
436 dev_warn(&master->dev,
437 "receive overrun, aborting the message\n");
438 master->cur_msg->status = -EIO;
439 } else {
440 /*
441 * Interrupt is either RX (RIS) or TX (TIS). For both cases we
442 * simply execute next data transfer.
443 */
444 if (ep93xx_spi_read_write(master)) {
445 /*
446 * In normal case, there still is some processing left
447 * for current transfer. Let's wait for the next
448 * interrupt then.
449 */
450 return IRQ_HANDLED;
451 }
452 }
530 453
531 msg->state = t; 454 /*
455 * Current transfer is finished, either with error or with success. In
456 * any case we disable interrupts and notify the worker to handle
457 * any post-processing of the message.
458 */
459 val = readl(espi->mmio + SSPCR1);
460 val &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
461 writel(val, espi->mmio + SSPCR1);
462
463 spi_finalize_current_transfer(master);
464
465 return IRQ_HANDLED;
466}
532 467
533 err = ep93xx_spi_chip_setup(espi, msg->spi, t); 468static int ep93xx_spi_transfer_one(struct spi_master *master,
534 if (err) { 469 struct spi_device *spi,
535 dev_err(&espi->pdev->dev, 470 struct spi_transfer *xfer)
536 "failed to setup chip for transfer\n"); 471{
537 msg->status = err; 472 struct ep93xx_spi *espi = spi_master_get_devdata(master);
538 return; 473 u32 val;
474 int ret;
475
476 ret = ep93xx_spi_chip_setup(master, spi, xfer);
477 if (ret) {
478 dev_err(&master->dev, "failed to setup chip for transfer\n");
479 return ret;
539 } 480 }
540 481
482 master->cur_msg->state = xfer;
541 espi->rx = 0; 483 espi->rx = 0;
542 espi->tx = 0; 484 espi->tx = 0;
543 485
@@ -546,83 +488,37 @@ static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi,
546 * fit into the FIFO and can be transferred with a single interrupt. 488 * fit into the FIFO and can be transferred with a single interrupt.
547 * So in these cases we will be using PIO and don't bother for DMA. 489 * So in these cases we will be using PIO and don't bother for DMA.
548 */ 490 */
549 if (espi->dma_rx && t->len > SPI_FIFO_SIZE) 491 if (espi->dma_rx && xfer->len > SPI_FIFO_SIZE)
550 ep93xx_spi_dma_transfer(espi); 492 return ep93xx_spi_dma_transfer(master);
551 else
552 ep93xx_spi_pio_transfer(espi);
553 493
554 /* 494 /* Using PIO so prime the TX FIFO and enable interrupts */
555 * In case of error during transmit, we bail out from processing 495 ep93xx_spi_read_write(master);
556 * the message.
557 */
558 if (msg->status)
559 return;
560 496
561 msg->actual_length += t->len; 497 val = readl(espi->mmio + SSPCR1);
498 val |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
499 writel(val, espi->mmio + SSPCR1);
562 500
563 /* 501 /* signal that we need to wait for completion */
564 * After this transfer is finished, perform any possible 502 return 1;
565 * post-transfer actions requested by the protocol driver.
566 */
567 if (t->delay_usecs) {
568 set_current_state(TASK_UNINTERRUPTIBLE);
569 schedule_timeout(usecs_to_jiffies(t->delay_usecs));
570 }
571 if (t->cs_change) {
572 if (!list_is_last(&t->transfer_list, &msg->transfers)) {
573 /*
574 * In case protocol driver is asking us to drop the
575 * chipselect briefly, we let the scheduler to handle
576 * any "delay" here.
577 */
578 ep93xx_spi_cs_control(msg->spi, false);
579 cond_resched();
580 ep93xx_spi_cs_control(msg->spi, true);
581 }
582 }
583} 503}
584 504
585/* 505static int ep93xx_spi_prepare_message(struct spi_master *master,
586 * ep93xx_spi_process_message() - process one SPI message 506 struct spi_message *msg)
587 * @espi: ep93xx SPI controller struct
588 * @msg: message to process
589 *
590 * This function processes a single SPI message. We go through all transfers in
591 * the message and pass them to ep93xx_spi_process_transfer(). Chipselect is
592 * asserted during the whole message (unless per transfer cs_change is set).
593 *
594 * @msg->status contains %0 in case of success or negative error code in case of
595 * failure.
596 */
597static void ep93xx_spi_process_message(struct ep93xx_spi *espi,
598 struct spi_message *msg)
599{ 507{
508 struct ep93xx_spi *espi = spi_master_get_devdata(master);
600 unsigned long timeout; 509 unsigned long timeout;
601 struct spi_transfer *t;
602 int err;
603
604 /*
605 * Enable the SPI controller and its clock.
606 */
607 err = ep93xx_spi_enable(espi);
608 if (err) {
609 dev_err(&espi->pdev->dev, "failed to enable SPI controller\n");
610 msg->status = err;
611 return;
612 }
613 510
614 /* 511 /*
615 * Just to be sure: flush any data from RX FIFO. 512 * Just to be sure: flush any data from RX FIFO.
616 */ 513 */
617 timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT); 514 timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT);
618 while (ep93xx_spi_read_u16(espi, SSPSR) & SSPSR_RNE) { 515 while (readl(espi->mmio + SSPSR) & SSPSR_RNE) {
619 if (time_after(jiffies, timeout)) { 516 if (time_after(jiffies, timeout)) {
620 dev_warn(&espi->pdev->dev, 517 dev_warn(&master->dev,
621 "timeout while flushing RX FIFO\n"); 518 "timeout while flushing RX FIFO\n");
622 msg->status = -ETIMEDOUT; 519 return -ETIMEDOUT;
623 return;
624 } 520 }
625 ep93xx_spi_read_u16(espi, SSPDR); 521 readl(espi->mmio + SSPDR);
626 } 522 }
627 523
628 /* 524 /*
@@ -631,81 +527,38 @@ static void ep93xx_spi_process_message(struct ep93xx_spi *espi,
631 */ 527 */
632 espi->fifo_level = 0; 528 espi->fifo_level = 0;
633 529
634 /* 530 return 0;
635 * Assert the chipselect.
636 */
637 ep93xx_spi_cs_control(msg->spi, true);
638
639 list_for_each_entry(t, &msg->transfers, transfer_list) {
640 ep93xx_spi_process_transfer(espi, msg, t);
641 if (msg->status)
642 break;
643 }
644
645 /*
646 * Now the whole message is transferred (or failed for some reason). We
647 * deselect the device and disable the SPI controller.
648 */
649 ep93xx_spi_cs_control(msg->spi, false);
650 ep93xx_spi_disable(espi);
651} 531}
652 532
653static int ep93xx_spi_transfer_one_message(struct spi_master *master, 533static int ep93xx_spi_prepare_hardware(struct spi_master *master)
654 struct spi_message *msg)
655{ 534{
656 struct ep93xx_spi *espi = spi_master_get_devdata(master); 535 struct ep93xx_spi *espi = spi_master_get_devdata(master);
536 u32 val;
537 int ret;
657 538
658 msg->state = NULL; 539 ret = clk_enable(espi->clk);
659 msg->status = 0; 540 if (ret)
660 msg->actual_length = 0; 541 return ret;
661
662 espi->current_msg = msg;
663 ep93xx_spi_process_message(espi, msg);
664 espi->current_msg = NULL;
665 542
666 spi_finalize_current_message(master); 543 val = readl(espi->mmio + SSPCR1);
544 val |= SSPCR1_SSE;
545 writel(val, espi->mmio + SSPCR1);
667 546
668 return 0; 547 return 0;
669} 548}
670 549
671static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id) 550static int ep93xx_spi_unprepare_hardware(struct spi_master *master)
672{ 551{
673 struct ep93xx_spi *espi = dev_id; 552 struct ep93xx_spi *espi = spi_master_get_devdata(master);
674 u8 irq_status = ep93xx_spi_read_u8(espi, SSPIIR); 553 u32 val;
675 554
676 /* 555 val = readl(espi->mmio + SSPCR1);
677 * If we got ROR (receive overrun) interrupt we know that something is 556 val &= ~SSPCR1_SSE;
678 * wrong. Just abort the message. 557 writel(val, espi->mmio + SSPCR1);
679 */
680 if (unlikely(irq_status & SSPIIR_RORIS)) {
681 /* clear the overrun interrupt */
682 ep93xx_spi_write_u8(espi, SSPICR, 0);
683 dev_warn(&espi->pdev->dev,
684 "receive overrun, aborting the message\n");
685 espi->current_msg->status = -EIO;
686 } else {
687 /*
688 * Interrupt is either RX (RIS) or TX (TIS). For both cases we
689 * simply execute next data transfer.
690 */
691 if (ep93xx_spi_read_write(espi)) {
692 /*
693 * In normal case, there still is some processing left
694 * for current transfer. Let's wait for the next
695 * interrupt then.
696 */
697 return IRQ_HANDLED;
698 }
699 }
700 558
701 /* 559 clk_disable(espi->clk);
702 * Current transfer is finished, either with error or with success. In 560
703 * any case we disable interrupts and notify the worker to handle 561 return 0;
704 * any post-processing of the message.
705 */
706 ep93xx_spi_disable_interrupts(espi);
707 complete(&espi->wait);
708 return IRQ_HANDLED;
709} 562}
710 563
711static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param) 564static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param)
@@ -809,7 +662,10 @@ static int ep93xx_spi_probe(struct platform_device *pdev)
809 if (!master) 662 if (!master)
810 return -ENOMEM; 663 return -ENOMEM;
811 664
812 master->transfer_one_message = ep93xx_spi_transfer_one_message; 665 master->prepare_transfer_hardware = ep93xx_spi_prepare_hardware;
666 master->unprepare_transfer_hardware = ep93xx_spi_unprepare_hardware;
667 master->prepare_message = ep93xx_spi_prepare_message;
668 master->transfer_one = ep93xx_spi_transfer_one;
813 master->bus_num = pdev->id; 669 master->bus_num = pdev->id;
814 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 670 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
815 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 671 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
@@ -850,26 +706,23 @@ static int ep93xx_spi_probe(struct platform_device *pdev)
850 goto fail_release_master; 706 goto fail_release_master;
851 } 707 }
852 708
853 init_completion(&espi->wait);
854
855 /* 709 /*
856 * Calculate maximum and minimum supported clock rates 710 * Calculate maximum and minimum supported clock rates
857 * for the controller. 711 * for the controller.
858 */ 712 */
859 master->max_speed_hz = clk_get_rate(espi->clk) / 2; 713 master->max_speed_hz = clk_get_rate(espi->clk) / 2;
860 master->min_speed_hz = clk_get_rate(espi->clk) / (254 * 256); 714 master->min_speed_hz = clk_get_rate(espi->clk) / (254 * 256);
861 espi->pdev = pdev;
862 715
863 espi->sspdr_phys = res->start + SSPDR; 716 espi->sspdr_phys = res->start + SSPDR;
864 717
865 espi->regs_base = devm_ioremap_resource(&pdev->dev, res); 718 espi->mmio = devm_ioremap_resource(&pdev->dev, res);
866 if (IS_ERR(espi->regs_base)) { 719 if (IS_ERR(espi->mmio)) {
867 error = PTR_ERR(espi->regs_base); 720 error = PTR_ERR(espi->mmio);
868 goto fail_release_master; 721 goto fail_release_master;
869 } 722 }
870 723
871 error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt, 724 error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt,
872 0, "ep93xx-spi", espi); 725 0, "ep93xx-spi", master);
873 if (error) { 726 if (error) {
874 dev_err(&pdev->dev, "failed to request irq\n"); 727 dev_err(&pdev->dev, "failed to request irq\n");
875 goto fail_release_master; 728 goto fail_release_master;
@@ -879,7 +732,7 @@ static int ep93xx_spi_probe(struct platform_device *pdev)
879 dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n"); 732 dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n");
880 733
881 /* make sure that the hardware is disabled */ 734 /* make sure that the hardware is disabled */
882 ep93xx_spi_write_u8(espi, SSPCR1, 0); 735 writel(0, espi->mmio + SSPCR1);
883 736
884 error = devm_spi_register_master(&pdev->dev, master); 737 error = devm_spi_register_master(&pdev->dev, master);
885 if (error) { 738 if (error) {
diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c
index 286b2c81fc6b..f8638e82e5db 100644
--- a/drivers/spi/spi-falcon.c
+++ b/drivers/spi/spi-falcon.c
@@ -395,11 +395,6 @@ static int falcon_sflash_probe(struct platform_device *pdev)
395 struct spi_master *master; 395 struct spi_master *master;
396 int ret; 396 int ret;
397 397
398 if (ltq_boot_select() != BS_SPI) {
399 dev_err(&pdev->dev, "invalid bootstrap options\n");
400 return -ENODEV;
401 }
402
403 master = spi_alloc_master(&pdev->dev, sizeof(*priv)); 398 master = spi_alloc_master(&pdev->dev, sizeof(*priv));
404 if (!master) 399 if (!master)
405 return -ENOMEM; 400 return -ENOMEM;
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index f9698b7aeb3b..babb15f07995 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -56,6 +56,7 @@
56 56
57/* The maximum bytes that a sdma BD can transfer.*/ 57/* The maximum bytes that a sdma BD can transfer.*/
58#define MAX_SDMA_BD_BYTES (1 << 15) 58#define MAX_SDMA_BD_BYTES (1 << 15)
59#define MX51_ECSPI_CTRL_MAX_BURST 512
59 60
60enum spi_imx_devtype { 61enum spi_imx_devtype {
61 IMX1_CSPI, 62 IMX1_CSPI,
@@ -63,7 +64,8 @@ enum spi_imx_devtype {
63 IMX27_CSPI, 64 IMX27_CSPI,
64 IMX31_CSPI, 65 IMX31_CSPI,
65 IMX35_CSPI, /* CSPI on all i.mx except above */ 66 IMX35_CSPI, /* CSPI on all i.mx except above */
66 IMX51_ECSPI, /* ECSPI on i.mx51 and later */ 67 IMX51_ECSPI, /* ECSPI on i.mx51 */
68 IMX53_ECSPI, /* ECSPI on i.mx53 and later */
67}; 69};
68 70
69struct spi_imx_data; 71struct spi_imx_data;
@@ -74,6 +76,9 @@ struct spi_imx_devtype_data {
74 void (*trigger)(struct spi_imx_data *); 76 void (*trigger)(struct spi_imx_data *);
75 int (*rx_available)(struct spi_imx_data *); 77 int (*rx_available)(struct spi_imx_data *);
76 void (*reset)(struct spi_imx_data *); 78 void (*reset)(struct spi_imx_data *);
79 bool has_dmamode;
80 unsigned int fifo_size;
81 bool dynamic_burst;
77 enum spi_imx_devtype devtype; 82 enum spi_imx_devtype devtype;
78}; 83};
79 84
@@ -94,12 +99,14 @@ struct spi_imx_data {
94 unsigned int bits_per_word; 99 unsigned int bits_per_word;
95 unsigned int spi_drctl; 100 unsigned int spi_drctl;
96 101
97 unsigned int count; 102 unsigned int count, remainder;
98 void (*tx)(struct spi_imx_data *); 103 void (*tx)(struct spi_imx_data *);
99 void (*rx)(struct spi_imx_data *); 104 void (*rx)(struct spi_imx_data *);
100 void *rx_buf; 105 void *rx_buf;
101 const void *tx_buf; 106 const void *tx_buf;
102 unsigned int txfifo; /* number of words pushed in tx FIFO */ 107 unsigned int txfifo; /* number of words pushed in tx FIFO */
108 unsigned int dynamic_burst, read_u32;
109 unsigned int word_mask;
103 110
104 /* DMA */ 111 /* DMA */
105 bool usedma; 112 bool usedma;
@@ -125,9 +132,9 @@ static inline int is_imx51_ecspi(struct spi_imx_data *d)
125 return d->devtype_data->devtype == IMX51_ECSPI; 132 return d->devtype_data->devtype == IMX51_ECSPI;
126} 133}
127 134
128static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d) 135static inline int is_imx53_ecspi(struct spi_imx_data *d)
129{ 136{
130 return is_imx51_ecspi(d) ? 64 : 8; 137 return d->devtype_data->devtype == IMX53_ECSPI;
131} 138}
132 139
133#define MXC_SPI_BUF_RX(type) \ 140#define MXC_SPI_BUF_RX(type) \
@@ -219,7 +226,7 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
219 if (bytes_per_word != 1 && bytes_per_word != 2 && bytes_per_word != 4) 226 if (bytes_per_word != 1 && bytes_per_word != 2 && bytes_per_word != 4)
220 return false; 227 return false;
221 228
222 for (i = spi_imx_get_fifosize(spi_imx) / 2; i > 0; i--) { 229 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
223 if (!(transfer->len % (i * bytes_per_word))) 230 if (!(transfer->len % (i * bytes_per_word)))
224 break; 231 break;
225 } 232 }
@@ -228,6 +235,7 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
228 return false; 235 return false;
229 236
230 spi_imx->wml = i; 237 spi_imx->wml = i;
238 spi_imx->dynamic_burst = 0;
231 239
232 return true; 240 return true;
233} 241}
@@ -242,6 +250,7 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
242#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 250#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
243#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) 251#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
244#define MX51_ECSPI_CTRL_BL_OFFSET 20 252#define MX51_ECSPI_CTRL_BL_OFFSET 20
253#define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20)
245 254
246#define MX51_ECSPI_CONFIG 0x0c 255#define MX51_ECSPI_CONFIG 0x0c
247#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) 256#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
@@ -269,6 +278,106 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
269#define MX51_ECSPI_TESTREG 0x20 278#define MX51_ECSPI_TESTREG 0x20
270#define MX51_ECSPI_TESTREG_LBC BIT(31) 279#define MX51_ECSPI_TESTREG_LBC BIT(31)
271 280
281static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
282{
283 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
284#ifdef __LITTLE_ENDIAN
285 unsigned int bytes_per_word;
286#endif
287
288 if (spi_imx->rx_buf) {
289#ifdef __LITTLE_ENDIAN
290 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
291 if (bytes_per_word == 1)
292 val = cpu_to_be32(val);
293 else if (bytes_per_word == 2)
294 val = (val << 16) | (val >> 16);
295#endif
296 val &= spi_imx->word_mask;
297 *(u32 *)spi_imx->rx_buf = val;
298 spi_imx->rx_buf += sizeof(u32);
299 }
300}
301
302static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
303{
304 unsigned int bytes_per_word;
305
306 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
307 if (spi_imx->read_u32) {
308 spi_imx_buf_rx_swap_u32(spi_imx);
309 return;
310 }
311
312 if (bytes_per_word == 1)
313 spi_imx_buf_rx_u8(spi_imx);
314 else if (bytes_per_word == 2)
315 spi_imx_buf_rx_u16(spi_imx);
316}
317
318static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
319{
320 u32 val = 0;
321#ifdef __LITTLE_ENDIAN
322 unsigned int bytes_per_word;
323#endif
324
325 if (spi_imx->tx_buf) {
326 val = *(u32 *)spi_imx->tx_buf;
327 val &= spi_imx->word_mask;
328 spi_imx->tx_buf += sizeof(u32);
329 }
330
331 spi_imx->count -= sizeof(u32);
332#ifdef __LITTLE_ENDIAN
333 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
334
335 if (bytes_per_word == 1)
336 val = cpu_to_be32(val);
337 else if (bytes_per_word == 2)
338 val = (val << 16) | (val >> 16);
339#endif
340 writel(val, spi_imx->base + MXC_CSPITXDATA);
341}
342
343static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
344{
345 u32 ctrl, val;
346 unsigned int bytes_per_word;
347
348 if (spi_imx->count == spi_imx->remainder) {
349 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
350 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
351 if (spi_imx->count > MX51_ECSPI_CTRL_MAX_BURST) {
352 spi_imx->remainder = spi_imx->count %
353 MX51_ECSPI_CTRL_MAX_BURST;
354 val = MX51_ECSPI_CTRL_MAX_BURST * 8 - 1;
355 } else if (spi_imx->count >= sizeof(u32)) {
356 spi_imx->remainder = spi_imx->count % sizeof(u32);
357 val = (spi_imx->count - spi_imx->remainder) * 8 - 1;
358 } else {
359 spi_imx->remainder = 0;
360 val = spi_imx->bits_per_word - 1;
361 spi_imx->read_u32 = 0;
362 }
363
364 ctrl |= (val << MX51_ECSPI_CTRL_BL_OFFSET);
365 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
366 }
367
368 if (spi_imx->count >= sizeof(u32)) {
369 spi_imx_buf_tx_swap_u32(spi_imx);
370 return;
371 }
372
373 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
374
375 if (bytes_per_word == 1)
376 spi_imx_buf_tx_u8(spi_imx);
377 else if (bytes_per_word == 2)
378 spi_imx_buf_tx_u16(spi_imx);
379}
380
272/* MX51 eCSPI */ 381/* MX51 eCSPI */
273static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx, 382static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
274 unsigned int fspi, unsigned int *fres) 383 unsigned int fspi, unsigned int *fres)
@@ -513,8 +622,8 @@ static int mx31_config(struct spi_device *spi)
513 reg |= MX31_CSPICTRL_POL; 622 reg |= MX31_CSPICTRL_POL;
514 if (spi->mode & SPI_CS_HIGH) 623 if (spi->mode & SPI_CS_HIGH)
515 reg |= MX31_CSPICTRL_SSPOL; 624 reg |= MX31_CSPICTRL_SSPOL;
516 if (spi->cs_gpio < 0) 625 if (!gpio_is_valid(spi->cs_gpio))
517 reg |= (spi->cs_gpio + 32) << 626 reg |= (spi->chip_select) <<
518 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : 627 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
519 MX31_CSPICTRL_CS_SHIFT); 628 MX31_CSPICTRL_CS_SHIFT);
520 629
@@ -605,8 +714,8 @@ static int mx21_config(struct spi_device *spi)
605 reg |= MX21_CSPICTRL_POL; 714 reg |= MX21_CSPICTRL_POL;
606 if (spi->mode & SPI_CS_HIGH) 715 if (spi->mode & SPI_CS_HIGH)
607 reg |= MX21_CSPICTRL_SSPOL; 716 reg |= MX21_CSPICTRL_SSPOL;
608 if (spi->cs_gpio < 0) 717 if (!gpio_is_valid(spi->cs_gpio))
609 reg |= (spi->cs_gpio + 32) << MX21_CSPICTRL_CS_SHIFT; 718 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
610 719
611 writel(reg, spi_imx->base + MXC_CSPICTRL); 720 writel(reg, spi_imx->base + MXC_CSPICTRL);
612 721
@@ -693,6 +802,9 @@ static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
693 .trigger = mx1_trigger, 802 .trigger = mx1_trigger,
694 .rx_available = mx1_rx_available, 803 .rx_available = mx1_rx_available,
695 .reset = mx1_reset, 804 .reset = mx1_reset,
805 .fifo_size = 8,
806 .has_dmamode = false,
807 .dynamic_burst = false,
696 .devtype = IMX1_CSPI, 808 .devtype = IMX1_CSPI,
697}; 809};
698 810
@@ -702,6 +814,9 @@ static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
702 .trigger = mx21_trigger, 814 .trigger = mx21_trigger,
703 .rx_available = mx21_rx_available, 815 .rx_available = mx21_rx_available,
704 .reset = mx21_reset, 816 .reset = mx21_reset,
817 .fifo_size = 8,
818 .has_dmamode = false,
819 .dynamic_burst = false,
705 .devtype = IMX21_CSPI, 820 .devtype = IMX21_CSPI,
706}; 821};
707 822
@@ -712,6 +827,9 @@ static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
712 .trigger = mx21_trigger, 827 .trigger = mx21_trigger,
713 .rx_available = mx21_rx_available, 828 .rx_available = mx21_rx_available,
714 .reset = mx21_reset, 829 .reset = mx21_reset,
830 .fifo_size = 8,
831 .has_dmamode = false,
832 .dynamic_burst = false,
715 .devtype = IMX27_CSPI, 833 .devtype = IMX27_CSPI,
716}; 834};
717 835
@@ -721,6 +839,9 @@ static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
721 .trigger = mx31_trigger, 839 .trigger = mx31_trigger,
722 .rx_available = mx31_rx_available, 840 .rx_available = mx31_rx_available,
723 .reset = mx31_reset, 841 .reset = mx31_reset,
842 .fifo_size = 8,
843 .has_dmamode = false,
844 .dynamic_burst = false,
724 .devtype = IMX31_CSPI, 845 .devtype = IMX31_CSPI,
725}; 846};
726 847
@@ -731,6 +852,9 @@ static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
731 .trigger = mx31_trigger, 852 .trigger = mx31_trigger,
732 .rx_available = mx31_rx_available, 853 .rx_available = mx31_rx_available,
733 .reset = mx31_reset, 854 .reset = mx31_reset,
855 .fifo_size = 8,
856 .has_dmamode = true,
857 .dynamic_burst = false,
734 .devtype = IMX35_CSPI, 858 .devtype = IMX35_CSPI,
735}; 859};
736 860
@@ -740,9 +864,23 @@ static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
740 .trigger = mx51_ecspi_trigger, 864 .trigger = mx51_ecspi_trigger,
741 .rx_available = mx51_ecspi_rx_available, 865 .rx_available = mx51_ecspi_rx_available,
742 .reset = mx51_ecspi_reset, 866 .reset = mx51_ecspi_reset,
867 .fifo_size = 64,
868 .has_dmamode = true,
869 .dynamic_burst = true,
743 .devtype = IMX51_ECSPI, 870 .devtype = IMX51_ECSPI,
744}; 871};
745 872
873static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
874 .intctrl = mx51_ecspi_intctrl,
875 .config = mx51_ecspi_config,
876 .trigger = mx51_ecspi_trigger,
877 .rx_available = mx51_ecspi_rx_available,
878 .reset = mx51_ecspi_reset,
879 .fifo_size = 64,
880 .has_dmamode = true,
881 .devtype = IMX53_ECSPI,
882};
883
746static const struct platform_device_id spi_imx_devtype[] = { 884static const struct platform_device_id spi_imx_devtype[] = {
747 { 885 {
748 .name = "imx1-cspi", 886 .name = "imx1-cspi",
@@ -763,6 +901,9 @@ static const struct platform_device_id spi_imx_devtype[] = {
763 .name = "imx51-ecspi", 901 .name = "imx51-ecspi",
764 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data, 902 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
765 }, { 903 }, {
904 .name = "imx53-ecspi",
905 .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data,
906 }, {
766 /* sentinel */ 907 /* sentinel */
767 } 908 }
768}; 909};
@@ -774,6 +915,7 @@ static const struct of_device_id spi_imx_dt_ids[] = {
774 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, 915 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
775 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, 916 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
776 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, 917 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
918 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
777 { /* sentinel */ } 919 { /* sentinel */ }
778}; 920};
779MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); 921MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
@@ -783,6 +925,9 @@ static void spi_imx_chipselect(struct spi_device *spi, int is_active)
783 int active = is_active != BITBANG_CS_INACTIVE; 925 int active = is_active != BITBANG_CS_INACTIVE;
784 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); 926 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
785 927
928 if (spi->mode & SPI_NO_CS)
929 return;
930
786 if (!gpio_is_valid(spi->cs_gpio)) 931 if (!gpio_is_valid(spi->cs_gpio))
787 return; 932 return;
788 933
@@ -791,9 +936,11 @@ static void spi_imx_chipselect(struct spi_device *spi, int is_active)
791 936
792static void spi_imx_push(struct spi_imx_data *spi_imx) 937static void spi_imx_push(struct spi_imx_data *spi_imx)
793{ 938{
794 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) { 939 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
795 if (!spi_imx->count) 940 if (!spi_imx->count)
796 break; 941 break;
942 if (spi_imx->txfifo && (spi_imx->count == spi_imx->remainder))
943 break;
797 spi_imx->tx(spi_imx); 944 spi_imx->tx(spi_imx);
798 spi_imx->txfifo++; 945 spi_imx->txfifo++;
799 } 946 }
@@ -887,15 +1034,37 @@ static int spi_imx_setupxfer(struct spi_device *spi,
887 spi_imx->speed_hz = t->speed_hz; 1034 spi_imx->speed_hz = t->speed_hz;
888 1035
889 /* Initialize the functions for transfer */ 1036 /* Initialize the functions for transfer */
890 if (spi_imx->bits_per_word <= 8) { 1037 if (spi_imx->devtype_data->dynamic_burst) {
891 spi_imx->rx = spi_imx_buf_rx_u8; 1038 u32 mask;
892 spi_imx->tx = spi_imx_buf_tx_u8; 1039
893 } else if (spi_imx->bits_per_word <= 16) { 1040 spi_imx->dynamic_burst = 0;
894 spi_imx->rx = spi_imx_buf_rx_u16; 1041 spi_imx->remainder = 0;
895 spi_imx->tx = spi_imx_buf_tx_u16; 1042 spi_imx->read_u32 = 1;
1043
1044 mask = (1 << spi_imx->bits_per_word) - 1;
1045 spi_imx->rx = spi_imx_buf_rx_swap;
1046 spi_imx->tx = spi_imx_buf_tx_swap;
1047 spi_imx->dynamic_burst = 1;
1048 spi_imx->remainder = t->len;
1049
1050 if (spi_imx->bits_per_word <= 8)
1051 spi_imx->word_mask = mask << 24 | mask << 16
1052 | mask << 8 | mask;
1053 else if (spi_imx->bits_per_word <= 16)
1054 spi_imx->word_mask = mask << 16 | mask;
1055 else
1056 spi_imx->word_mask = mask;
896 } else { 1057 } else {
897 spi_imx->rx = spi_imx_buf_rx_u32; 1058 if (spi_imx->bits_per_word <= 8) {
898 spi_imx->tx = spi_imx_buf_tx_u32; 1059 spi_imx->rx = spi_imx_buf_rx_u8;
1060 spi_imx->tx = spi_imx_buf_tx_u8;
1061 } else if (spi_imx->bits_per_word <= 16) {
1062 spi_imx->rx = spi_imx_buf_rx_u16;
1063 spi_imx->tx = spi_imx_buf_tx_u16;
1064 } else {
1065 spi_imx->rx = spi_imx_buf_rx_u32;
1066 spi_imx->tx = spi_imx_buf_tx_u32;
1067 }
899 } 1068 }
900 1069
901 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t)) 1070 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
@@ -938,7 +1107,7 @@ static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
938 if (of_machine_is_compatible("fsl,imx6dl")) 1107 if (of_machine_is_compatible("fsl,imx6dl"))
939 return 0; 1108 return 0;
940 1109
941 spi_imx->wml = spi_imx_get_fifosize(spi_imx) / 2; 1110 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
942 1111
943 /* Prepare for TX DMA: */ 1112 /* Prepare for TX DMA: */
944 master->dma_tx = dma_request_slave_channel_reason(dev, "tx"); 1113 master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
@@ -1109,6 +1278,9 @@ static int spi_imx_setup(struct spi_device *spi)
1109 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, 1278 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1110 spi->mode, spi->bits_per_word, spi->max_speed_hz); 1279 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1111 1280
1281 if (spi->mode & SPI_NO_CS)
1282 return 0;
1283
1112 if (gpio_is_valid(spi->cs_gpio)) 1284 if (gpio_is_valid(spi->cs_gpio))
1113 gpio_direction_output(spi->cs_gpio, 1285 gpio_direction_output(spi->cs_gpio,
1114 spi->mode & SPI_CS_HIGH ? 0 : 1); 1286 spi->mode & SPI_CS_HIGH ? 0 : 1);
@@ -1208,8 +1380,10 @@ static int spi_imx_probe(struct platform_device *pdev)
1208 spi_imx->bitbang.master->cleanup = spi_imx_cleanup; 1380 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1209 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message; 1381 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1210 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; 1382 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1211 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1383 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
1212 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx)) 1384 | SPI_NO_CS;
1385 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1386 is_imx53_ecspi(spi_imx))
1213 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY; 1387 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
1214 1388
1215 spi_imx->spi_drctl = spi_drctl; 1389 spi_imx->spi_drctl = spi_drctl;
@@ -1262,7 +1436,7 @@ static int spi_imx_probe(struct platform_device *pdev)
1262 * Only validated on i.mx35 and i.mx6 now, can remove the constraint 1436 * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1263 * if validated on other chips. 1437 * if validated on other chips.
1264 */ 1438 */
1265 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx)) { 1439 if (spi_imx->devtype_data->has_dmamode) {
1266 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master); 1440 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1267 if (ret == -EPROBE_DEFER) 1441 if (ret == -EPROBE_DEFER)
1268 goto out_clk_put; 1442 goto out_clk_put;
diff --git a/drivers/spi/spi-loopback-test.c b/drivers/spi/spi-loopback-test.c
index 3459965004f8..bed7403bb6b3 100644
--- a/drivers/spi/spi-loopback-test.c
+++ b/drivers/spi/spi-loopback-test.c
@@ -32,39 +32,50 @@
32#include "spi-test.h" 32#include "spi-test.h"
33 33
34/* flag to only simulate transfers */ 34/* flag to only simulate transfers */
35int simulate_only; 35static int simulate_only;
36module_param(simulate_only, int, 0); 36module_param(simulate_only, int, 0);
37MODULE_PARM_DESC(simulate_only, "if not 0 do not execute the spi message"); 37MODULE_PARM_DESC(simulate_only, "if not 0 do not execute the spi message");
38 38
39/* dump spi messages */ 39/* dump spi messages */
40int dump_messages; 40static int dump_messages;
41module_param(dump_messages, int, 0); 41module_param(dump_messages, int, 0);
42MODULE_PARM_DESC(dump_messages, 42MODULE_PARM_DESC(dump_messages,
43 "=1 dump the basic spi_message_structure, " \ 43 "=1 dump the basic spi_message_structure, " \
44 "=2 dump the spi_message_structure including data, " \ 44 "=2 dump the spi_message_structure including data, " \
45 "=3 dump the spi_message structure before and after execution"); 45 "=3 dump the spi_message structure before and after execution");
46/* the device is jumpered for loopback - enabling some rx_buf tests */ 46/* the device is jumpered for loopback - enabling some rx_buf tests */
47int loopback; 47static int loopback;
48module_param(loopback, int, 0); 48module_param(loopback, int, 0);
49MODULE_PARM_DESC(loopback, 49MODULE_PARM_DESC(loopback,
50 "if set enable loopback mode, where the rx_buf " \ 50 "if set enable loopback mode, where the rx_buf " \
51 "is checked to match tx_buf after the spi_message " \ 51 "is checked to match tx_buf after the spi_message " \
52 "is executed"); 52 "is executed");
53 53
54static int loop_req;
55module_param(loop_req, int, 0);
56MODULE_PARM_DESC(loop_req,
57 "if set controller will be asked to enable test loop mode. " \
58 "If controller supported it, MISO and MOSI will be connected");
59
60static int no_cs;
61module_param(no_cs, int, 0);
62MODULE_PARM_DESC(no_cs,
63 "if set Chip Select (CS) will not be used");
64
54/* run only a specific test */ 65/* run only a specific test */
55int run_only_test = -1; 66static int run_only_test = -1;
56module_param(run_only_test, int, 0); 67module_param(run_only_test, int, 0);
57MODULE_PARM_DESC(run_only_test, 68MODULE_PARM_DESC(run_only_test,
58 "only run the test with this number (0-based !)"); 69 "only run the test with this number (0-based !)");
59 70
60/* use vmalloc'ed buffers */ 71/* use vmalloc'ed buffers */
61int use_vmalloc; 72static int use_vmalloc;
62module_param(use_vmalloc, int, 0644); 73module_param(use_vmalloc, int, 0644);
63MODULE_PARM_DESC(use_vmalloc, 74MODULE_PARM_DESC(use_vmalloc,
64 "use vmalloc'ed buffers instead of kmalloc'ed"); 75 "use vmalloc'ed buffers instead of kmalloc'ed");
65 76
66/* check rx ranges */ 77/* check rx ranges */
67int check_ranges = 1; 78static int check_ranges = 1;
68module_param(check_ranges, int, 0644); 79module_param(check_ranges, int, 0644);
69MODULE_PARM_DESC(check_ranges, 80MODULE_PARM_DESC(check_ranges,
70 "checks rx_buffer pattern are valid"); 81 "checks rx_buffer pattern are valid");
@@ -313,6 +324,17 @@ static int spi_loopback_test_probe(struct spi_device *spi)
313{ 324{
314 int ret; 325 int ret;
315 326
327 if (loop_req || no_cs) {
328 spi->mode |= loop_req ? SPI_LOOP : 0;
329 spi->mode |= no_cs ? SPI_NO_CS : 0;
330 ret = spi_setup(spi);
331 if (ret) {
332 dev_err(&spi->dev, "SPI setup with SPI_LOOP or SPI_NO_CS failed (%d)\n",
333 ret);
334 return ret;
335 }
336 }
337
316 dev_info(&spi->dev, "Executing spi-loopback-tests\n"); 338 dev_info(&spi->dev, "Executing spi-loopback-tests\n");
317 339
318 ret = spi_test_run_tests(spi, spi_tests); 340 ret = spi_test_run_tests(spi, spi_tests);
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index e048268d8ba2..9bf64e6eca9b 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -1338,7 +1338,6 @@ static int omap2_mcspi_probe(struct platform_device *pdev)
1338 struct resource *r; 1338 struct resource *r;
1339 int status = 0, i; 1339 int status = 0, i;
1340 u32 regs_offset = 0; 1340 u32 regs_offset = 0;
1341 static int bus_num = 1;
1342 struct device_node *node = pdev->dev.of_node; 1341 struct device_node *node = pdev->dev.of_node;
1343 const struct of_device_id *match; 1342 const struct of_device_id *match;
1344 1343
@@ -1374,14 +1373,11 @@ static int omap2_mcspi_probe(struct platform_device *pdev)
1374 1373
1375 of_property_read_u32(node, "ti,spi-num-cs", &num_cs); 1374 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1376 master->num_chipselect = num_cs; 1375 master->num_chipselect = num_cs;
1377 master->bus_num = bus_num++;
1378 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL)) 1376 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1379 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; 1377 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1380 } else { 1378 } else {
1381 pdata = dev_get_platdata(&pdev->dev); 1379 pdata = dev_get_platdata(&pdev->dev);
1382 master->num_chipselect = pdata->num_cs; 1380 master->num_chipselect = pdata->num_cs;
1383 if (pdev->id != -1)
1384 master->bus_num = pdev->id;
1385 mcspi->pin_dir = pdata->pin_dir; 1381 mcspi->pin_dir = pdata->pin_dir;
1386 } 1382 }
1387 regs_offset = pdata->regs_offset; 1383 regs_offset = pdata->regs_offset;
diff --git a/drivers/spi/spi-orion.c b/drivers/spi/spi-orion.c
index 28fc9f161b9d..4b6dd73b80da 100644
--- a/drivers/spi/spi-orion.c
+++ b/drivers/spi/spi-orion.c
@@ -669,8 +669,8 @@ static int orion_spi_probe(struct platform_device *pdev)
669 status = of_property_read_u32(np, "reg", &cs); 669 status = of_property_read_u32(np, "reg", &cs);
670 if (status) { 670 if (status) {
671 dev_err(&pdev->dev, 671 dev_err(&pdev->dev,
672 "%s has no valid 'reg' property (%d)\n", 672 "%pOF has no valid 'reg' property (%d)\n",
673 np->full_name, status); 673 np, status);
674 status = 0; 674 status = 0;
675 continue; 675 continue;
676 } 676 }
diff --git a/drivers/spi/spi-pic32.c b/drivers/spi/spi-pic32.c
index fefb688a3432..f8a45af1fa9f 100644
--- a/drivers/spi/spi-pic32.c
+++ b/drivers/spi/spi-pic32.c
@@ -52,14 +52,14 @@ struct pic32_spi_regs {
52 52
53/* Bit fields of SPI Control Register */ 53/* Bit fields of SPI Control Register */
54#define CTRL_RX_INT_SHIFT 0 /* Rx interrupt generation */ 54#define CTRL_RX_INT_SHIFT 0 /* Rx interrupt generation */
55#define RX_FIFO_EMTPY 0 55#define RX_FIFO_EMPTY 0
56#define RX_FIFO_NOT_EMPTY 1 /* not empty */ 56#define RX_FIFO_NOT_EMPTY 1 /* not empty */
57#define RX_FIFO_HALF_FULL 2 /* full by half or more */ 57#define RX_FIFO_HALF_FULL 2 /* full by half or more */
58#define RX_FIFO_FULL 3 /* completely full */ 58#define RX_FIFO_FULL 3 /* completely full */
59 59
60#define CTRL_TX_INT_SHIFT 2 /* TX interrupt generation */ 60#define CTRL_TX_INT_SHIFT 2 /* TX interrupt generation */
61#define TX_FIFO_ALL_EMPTY 0 /* completely empty */ 61#define TX_FIFO_ALL_EMPTY 0 /* completely empty */
62#define TX_FIFO_EMTPY 1 /* empty */ 62#define TX_FIFO_EMPTY 1 /* empty */
63#define TX_FIFO_HALF_EMPTY 2 /* empty by half or more */ 63#define TX_FIFO_HALF_EMPTY 2 /* empty by half or more */
64#define TX_FIFO_NOT_FULL 3 /* atleast one empty */ 64#define TX_FIFO_NOT_FULL 3 /* atleast one empty */
65 65
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
index 2f76e022cc59..4797c57f4263 100644
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -2429,7 +2429,7 @@ static struct vendor_data vendor_lsi = {
2429 .internal_cs_ctrl = true, 2429 .internal_cs_ctrl = true,
2430}; 2430};
2431 2431
2432static struct amba_id pl022_ids[] = { 2432static const struct amba_id pl022_ids[] = {
2433 { 2433 {
2434 /* 2434 /*
2435 * ARM PL022 variant, this has a 16bit wide 2435 * ARM PL022 variant, this has a 16bit wide
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 38d053682892..4cb515a3104c 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -402,8 +402,8 @@ static void cs_assert(struct driver_data *drv_data)
402 return; 402 return;
403 } 403 }
404 404
405 if (gpio_is_valid(chip->gpio_cs)) { 405 if (chip->gpiod_cs) {
406 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted); 406 gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted);
407 return; 407 return;
408 } 408 }
409 409
@@ -424,8 +424,8 @@ static void cs_deassert(struct driver_data *drv_data)
424 return; 424 return;
425 } 425 }
426 426
427 if (gpio_is_valid(chip->gpio_cs)) { 427 if (chip->gpiod_cs) {
428 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted); 428 gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted);
429 return; 429 return;
430 } 430 }
431 431
@@ -1213,17 +1213,16 @@ static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1213 struct pxa2xx_spi_chip *chip_info) 1213 struct pxa2xx_spi_chip *chip_info)
1214{ 1214{
1215 struct driver_data *drv_data = spi_master_get_devdata(spi->master); 1215 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1216 struct gpio_desc *gpiod;
1216 int err = 0; 1217 int err = 0;
1217 1218
1218 if (chip == NULL) 1219 if (chip == NULL)
1219 return 0; 1220 return 0;
1220 1221
1221 if (drv_data->cs_gpiods) { 1222 if (drv_data->cs_gpiods) {
1222 struct gpio_desc *gpiod;
1223
1224 gpiod = drv_data->cs_gpiods[spi->chip_select]; 1223 gpiod = drv_data->cs_gpiods[spi->chip_select];
1225 if (gpiod) { 1224 if (gpiod) {
1226 chip->gpio_cs = desc_to_gpio(gpiod); 1225 chip->gpiod_cs = gpiod;
1227 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 1226 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1228 gpiod_set_value(gpiod, chip->gpio_cs_inverted); 1227 gpiod_set_value(gpiod, chip->gpio_cs_inverted);
1229 } 1228 }
@@ -1237,8 +1236,10 @@ static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1237 /* NOTE: setup() can be called multiple times, possibly with 1236 /* NOTE: setup() can be called multiple times, possibly with
1238 * different chip_info, release previously requested GPIO 1237 * different chip_info, release previously requested GPIO
1239 */ 1238 */
1240 if (gpio_is_valid(chip->gpio_cs)) 1239 if (chip->gpiod_cs) {
1241 gpio_free(chip->gpio_cs); 1240 gpio_free(desc_to_gpio(chip->gpiod_cs));
1241 chip->gpiod_cs = NULL;
1242 }
1242 1243
1243 /* If (*cs_control) is provided, ignore GPIO chip select */ 1244 /* If (*cs_control) is provided, ignore GPIO chip select */
1244 if (chip_info->cs_control) { 1245 if (chip_info->cs_control) {
@@ -1254,11 +1255,11 @@ static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1254 return err; 1255 return err;
1255 } 1256 }
1256 1257
1257 chip->gpio_cs = chip_info->gpio_cs; 1258 gpiod = gpio_to_desc(chip_info->gpio_cs);
1259 chip->gpiod_cs = gpiod;
1258 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 1260 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1259 1261
1260 err = gpio_direction_output(chip->gpio_cs, 1262 err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted);
1261 !chip->gpio_cs_inverted);
1262 } 1263 }
1263 1264
1264 return err; 1265 return err;
@@ -1317,8 +1318,7 @@ static int setup(struct spi_device *spi)
1317 } 1318 }
1318 1319
1319 chip->frm = spi->chip_select; 1320 chip->frm = spi->chip_select;
1320 } else 1321 }
1321 chip->gpio_cs = -1;
1322 chip->enable_dma = drv_data->master_info->enable_dma; 1322 chip->enable_dma = drv_data->master_info->enable_dma;
1323 chip->timeout = TIMOUT_DFLT; 1323 chip->timeout = TIMOUT_DFLT;
1324 } 1324 }
@@ -1416,8 +1416,8 @@ static void cleanup(struct spi_device *spi)
1416 return; 1416 return;
1417 1417
1418 if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods && 1418 if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods &&
1419 gpio_is_valid(chip->gpio_cs)) 1419 chip->gpiod_cs)
1420 gpio_free(chip->gpio_cs); 1420 gpio_free(desc_to_gpio(chip->gpiod_cs));
1421 1421
1422 kfree(chip); 1422 kfree(chip);
1423} 1423}
@@ -1769,8 +1769,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
1769 for (i = 0; i < master->num_chipselect; i++) { 1769 for (i = 0; i < master->num_chipselect; i++) {
1770 struct gpio_desc *gpiod; 1770 struct gpio_desc *gpiod;
1771 1771
1772 gpiod = devm_gpiod_get_index(dev, "cs", i, 1772 gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS);
1773 GPIOD_OUT_HIGH);
1774 if (IS_ERR(gpiod)) { 1773 if (IS_ERR(gpiod)) {
1775 /* Means use native chip select */ 1774 /* Means use native chip select */
1776 if (PTR_ERR(gpiod) == -ENOENT) 1775 if (PTR_ERR(gpiod) == -ENOENT)
diff --git a/drivers/spi/spi-pxa2xx.h b/drivers/spi/spi-pxa2xx.h
index 2823a00a9405..94f7b0713281 100644
--- a/drivers/spi/spi-pxa2xx.h
+++ b/drivers/spi/spi-pxa2xx.h
@@ -83,7 +83,7 @@ struct chip_data {
83 u16 lpss_tx_threshold; 83 u16 lpss_tx_threshold;
84 u8 enable_dma; 84 u8 enable_dma;
85 union { 85 union {
86 int gpio_cs; 86 struct gpio_desc *gpiod_cs;
87 unsigned int frm; 87 unsigned int frm;
88 }; 88 };
89 int gpio_cs_inverted; 89 int gpio_cs_inverted;
diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index 1bfa889b8427..974a8ce58b68 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
@@ -19,6 +19,7 @@
19#include <linux/list.h> 19#include <linux/list.h>
20#include <linux/module.h> 20#include <linux/module.h>
21#include <linux/of.h> 21#include <linux/of.h>
22#include <linux/of_device.h>
22#include <linux/platform_device.h> 23#include <linux/platform_device.h>
23#include <linux/pm_runtime.h> 24#include <linux/pm_runtime.h>
24#include <linux/spi/spi.h> 25#include <linux/spi/spi.h>
@@ -82,6 +83,8 @@
82#define QUP_IO_M_MODE_BAM 3 83#define QUP_IO_M_MODE_BAM 3
83 84
84/* QUP_OPERATIONAL fields */ 85/* QUP_OPERATIONAL fields */
86#define QUP_OP_IN_BLOCK_READ_REQ BIT(13)
87#define QUP_OP_OUT_BLOCK_WRITE_REQ BIT(12)
85#define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11) 88#define QUP_OP_MAX_INPUT_DONE_FLAG BIT(11)
86#define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10) 89#define QUP_OP_MAX_OUTPUT_DONE_FLAG BIT(10)
87#define QUP_OP_IN_SERVICE_FLAG BIT(9) 90#define QUP_OP_IN_SERVICE_FLAG BIT(9)
@@ -118,7 +121,7 @@
118 121
119#define SPI_NUM_CHIPSELECTS 4 122#define SPI_NUM_CHIPSELECTS 4
120 123
121#define SPI_MAX_DMA_XFER (SZ_64K - 64) 124#define SPI_MAX_XFER (SZ_64K - 64)
122 125
123/* high speed mode is when bus rate is greater then 26MHz */ 126/* high speed mode is when bus rate is greater then 26MHz */
124#define SPI_HS_MIN_RATE 26000000 127#define SPI_HS_MIN_RATE 26000000
@@ -147,13 +150,37 @@ struct spi_qup {
147 int n_words; 150 int n_words;
148 int tx_bytes; 151 int tx_bytes;
149 int rx_bytes; 152 int rx_bytes;
153 const u8 *tx_buf;
154 u8 *rx_buf;
150 int qup_v1; 155 int qup_v1;
151 156
152 int use_dma; 157 int mode;
153 struct dma_slave_config rx_conf; 158 struct dma_slave_config rx_conf;
154 struct dma_slave_config tx_conf; 159 struct dma_slave_config tx_conf;
155}; 160};
156 161
162static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer);
163
164static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag)
165{
166 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL);
167
168 return (opflag & flag) != 0;
169}
170
171static inline bool spi_qup_is_dma_xfer(int mode)
172{
173 if (mode == QUP_IO_M_MODE_DMOV || mode == QUP_IO_M_MODE_BAM)
174 return true;
175
176 return false;
177}
178
179/* get's the transaction size length */
180static inline unsigned int spi_qup_len(struct spi_qup *controller)
181{
182 return controller->n_words * controller->w_size;
183}
157 184
158static inline bool spi_qup_is_valid_state(struct spi_qup *controller) 185static inline bool spi_qup_is_valid_state(struct spi_qup *controller)
159{ 186{
@@ -207,29 +234,26 @@ static int spi_qup_set_state(struct spi_qup *controller, u32 state)
207 return 0; 234 return 0;
208} 235}
209 236
210static void spi_qup_fifo_read(struct spi_qup *controller, 237static void spi_qup_read_from_fifo(struct spi_qup *controller, u32 num_words)
211 struct spi_transfer *xfer)
212{ 238{
213 u8 *rx_buf = xfer->rx_buf; 239 u8 *rx_buf = controller->rx_buf;
214 u32 word, state; 240 int i, shift, num_bytes;
215 int idx, shift, w_size; 241 u32 word;
216
217 w_size = controller->w_size;
218 242
219 while (controller->rx_bytes < xfer->len) { 243 for (; num_words; num_words--) {
220
221 state = readl_relaxed(controller->base + QUP_OPERATIONAL);
222 if (0 == (state & QUP_OP_IN_FIFO_NOT_EMPTY))
223 break;
224 244
225 word = readl_relaxed(controller->base + QUP_INPUT_FIFO); 245 word = readl_relaxed(controller->base + QUP_INPUT_FIFO);
226 246
247 num_bytes = min_t(int, spi_qup_len(controller) -
248 controller->rx_bytes,
249 controller->w_size);
250
227 if (!rx_buf) { 251 if (!rx_buf) {
228 controller->rx_bytes += w_size; 252 controller->rx_bytes += num_bytes;
229 continue; 253 continue;
230 } 254 }
231 255
232 for (idx = 0; idx < w_size; idx++, controller->rx_bytes++) { 256 for (i = 0; i < num_bytes; i++, controller->rx_bytes++) {
233 /* 257 /*
234 * The data format depends on bytes per SPI word: 258 * The data format depends on bytes per SPI word:
235 * 4 bytes: 0x12345678 259 * 4 bytes: 0x12345678
@@ -237,38 +261,81 @@ static void spi_qup_fifo_read(struct spi_qup *controller,
237 * 1 byte : 0x00000012 261 * 1 byte : 0x00000012
238 */ 262 */
239 shift = BITS_PER_BYTE; 263 shift = BITS_PER_BYTE;
240 shift *= (w_size - idx - 1); 264 shift *= (controller->w_size - i - 1);
241 rx_buf[controller->rx_bytes] = word >> shift; 265 rx_buf[controller->rx_bytes] = word >> shift;
242 } 266 }
243 } 267 }
244} 268}
245 269
246static void spi_qup_fifo_write(struct spi_qup *controller, 270static void spi_qup_read(struct spi_qup *controller, u32 *opflags)
247 struct spi_transfer *xfer)
248{ 271{
249 const u8 *tx_buf = xfer->tx_buf; 272 u32 remainder, words_per_block, num_words;
250 u32 word, state, data; 273 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
251 int idx, w_size; 274
275 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->rx_bytes,
276 controller->w_size);
277 words_per_block = controller->in_blk_sz >> 2;
278
279 do {
280 /* ACK by clearing service flag */
281 writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
282 controller->base + QUP_OPERATIONAL);
283
284 if (is_block_mode) {
285 num_words = (remainder > words_per_block) ?
286 words_per_block : remainder;
287 } else {
288 if (!spi_qup_is_flag_set(controller,
289 QUP_OP_IN_FIFO_NOT_EMPTY))
290 break;
252 291
253 w_size = controller->w_size; 292 num_words = 1;
293 }
254 294
255 while (controller->tx_bytes < xfer->len) { 295 /* read up to the maximum transfer size available */
296 spi_qup_read_from_fifo(controller, num_words);
256 297
257 state = readl_relaxed(controller->base + QUP_OPERATIONAL); 298 remainder -= num_words;
258 if (state & QUP_OP_OUT_FIFO_FULL) 299
300 /* if block mode, check to see if next block is available */
301 if (is_block_mode && !spi_qup_is_flag_set(controller,
302 QUP_OP_IN_BLOCK_READ_REQ))
259 break; 303 break;
260 304
305 } while (remainder);
306
307 /*
308 * Due to extra stickiness of the QUP_OP_IN_SERVICE_FLAG during block
309 * reads, it has to be cleared again at the very end. However, be sure
310 * to refresh opflags value because MAX_INPUT_DONE_FLAG may now be
311 * present and this is used to determine if transaction is complete
312 */
313 *opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
314 if (is_block_mode && *opflags & QUP_OP_MAX_INPUT_DONE_FLAG)
315 writel_relaxed(QUP_OP_IN_SERVICE_FLAG,
316 controller->base + QUP_OPERATIONAL);
317
318}
319
320static void spi_qup_write_to_fifo(struct spi_qup *controller, u32 num_words)
321{
322 const u8 *tx_buf = controller->tx_buf;
323 int i, num_bytes;
324 u32 word, data;
325
326 for (; num_words; num_words--) {
261 word = 0; 327 word = 0;
262 for (idx = 0; idx < w_size; idx++, controller->tx_bytes++) {
263 328
264 if (!tx_buf) { 329 num_bytes = min_t(int, spi_qup_len(controller) -
265 controller->tx_bytes += w_size; 330 controller->tx_bytes,
266 break; 331 controller->w_size);
332 if (tx_buf)
333 for (i = 0; i < num_bytes; i++) {
334 data = tx_buf[controller->tx_bytes + i];
335 word |= data << (BITS_PER_BYTE * (3 - i));
267 } 336 }
268 337
269 data = tx_buf[controller->tx_bytes]; 338 controller->tx_bytes += num_bytes;
270 word |= data << (BITS_PER_BYTE * (3 - idx));
271 }
272 339
273 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO); 340 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO);
274 } 341 }
@@ -281,31 +348,61 @@ static void spi_qup_dma_done(void *data)
281 complete(&qup->done); 348 complete(&qup->done);
282} 349}
283 350
284static int spi_qup_prep_sg(struct spi_master *master, struct spi_transfer *xfer, 351static void spi_qup_write(struct spi_qup *controller)
285 enum dma_transfer_direction dir, 352{
353 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
354 u32 remainder, words_per_block, num_words;
355
356 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->tx_bytes,
357 controller->w_size);
358 words_per_block = controller->out_blk_sz >> 2;
359
360 do {
361 /* ACK by clearing service flag */
362 writel_relaxed(QUP_OP_OUT_SERVICE_FLAG,
363 controller->base + QUP_OPERATIONAL);
364
365 if (is_block_mode) {
366 num_words = (remainder > words_per_block) ?
367 words_per_block : remainder;
368 } else {
369 if (spi_qup_is_flag_set(controller,
370 QUP_OP_OUT_FIFO_FULL))
371 break;
372
373 num_words = 1;
374 }
375
376 spi_qup_write_to_fifo(controller, num_words);
377
378 remainder -= num_words;
379
380 /* if block mode, check to see if next block is available */
381 if (is_block_mode && !spi_qup_is_flag_set(controller,
382 QUP_OP_OUT_BLOCK_WRITE_REQ))
383 break;
384
385 } while (remainder);
386}
387
388static int spi_qup_prep_sg(struct spi_master *master, struct scatterlist *sgl,
389 unsigned int nents, enum dma_transfer_direction dir,
286 dma_async_tx_callback callback) 390 dma_async_tx_callback callback)
287{ 391{
288 struct spi_qup *qup = spi_master_get_devdata(master); 392 struct spi_qup *qup = spi_master_get_devdata(master);
289 unsigned long flags = DMA_PREP_INTERRUPT | DMA_PREP_FENCE; 393 unsigned long flags = DMA_PREP_INTERRUPT | DMA_PREP_FENCE;
290 struct dma_async_tx_descriptor *desc; 394 struct dma_async_tx_descriptor *desc;
291 struct scatterlist *sgl;
292 struct dma_chan *chan; 395 struct dma_chan *chan;
293 dma_cookie_t cookie; 396 dma_cookie_t cookie;
294 unsigned int nents;
295 397
296 if (dir == DMA_MEM_TO_DEV) { 398 if (dir == DMA_MEM_TO_DEV)
297 chan = master->dma_tx; 399 chan = master->dma_tx;
298 nents = xfer->tx_sg.nents; 400 else
299 sgl = xfer->tx_sg.sgl;
300 } else {
301 chan = master->dma_rx; 401 chan = master->dma_rx;
302 nents = xfer->rx_sg.nents;
303 sgl = xfer->rx_sg.sgl;
304 }
305 402
306 desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags); 403 desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags);
307 if (!desc) 404 if (IS_ERR_OR_NULL(desc))
308 return -EINVAL; 405 return desc ? PTR_ERR(desc) : -EINVAL;
309 406
310 desc->callback = callback; 407 desc->callback = callback;
311 desc->callback_param = qup; 408 desc->callback_param = qup;
@@ -324,9 +421,33 @@ static void spi_qup_dma_terminate(struct spi_master *master,
324 dmaengine_terminate_all(master->dma_rx); 421 dmaengine_terminate_all(master->dma_rx);
325} 422}
326 423
327static int spi_qup_do_dma(struct spi_master *master, struct spi_transfer *xfer) 424static u32 spi_qup_sgl_get_nents_len(struct scatterlist *sgl, u32 max,
425 u32 *nents)
426{
427 struct scatterlist *sg;
428 u32 total = 0;
429
430 for (sg = sgl; sg; sg = sg_next(sg)) {
431 unsigned int len = sg_dma_len(sg);
432
433 /* check for overflow as well as limit */
434 if (((total + len) < total) || ((total + len) > max))
435 break;
436
437 total += len;
438 (*nents)++;
439 }
440
441 return total;
442}
443
444static int spi_qup_do_dma(struct spi_device *spi, struct spi_transfer *xfer,
445 unsigned long timeout)
328{ 446{
329 dma_async_tx_callback rx_done = NULL, tx_done = NULL; 447 dma_async_tx_callback rx_done = NULL, tx_done = NULL;
448 struct spi_master *master = spi->master;
449 struct spi_qup *qup = spi_master_get_devdata(master);
450 struct scatterlist *tx_sgl, *rx_sgl;
330 int ret; 451 int ret;
331 452
332 if (xfer->rx_buf) 453 if (xfer->rx_buf)
@@ -334,43 +455,122 @@ static int spi_qup_do_dma(struct spi_master *master, struct spi_transfer *xfer)
334 else if (xfer->tx_buf) 455 else if (xfer->tx_buf)
335 tx_done = spi_qup_dma_done; 456 tx_done = spi_qup_dma_done;
336 457
337 if (xfer->rx_buf) { 458 rx_sgl = xfer->rx_sg.sgl;
338 ret = spi_qup_prep_sg(master, xfer, DMA_DEV_TO_MEM, rx_done); 459 tx_sgl = xfer->tx_sg.sgl;
339 if (ret)
340 return ret;
341 460
342 dma_async_issue_pending(master->dma_rx); 461 do {
343 } 462 u32 rx_nents = 0, tx_nents = 0;
344 463
345 if (xfer->tx_buf) { 464 if (rx_sgl)
346 ret = spi_qup_prep_sg(master, xfer, DMA_MEM_TO_DEV, tx_done); 465 qup->n_words = spi_qup_sgl_get_nents_len(rx_sgl,
466 SPI_MAX_XFER, &rx_nents) / qup->w_size;
467 if (tx_sgl)
468 qup->n_words = spi_qup_sgl_get_nents_len(tx_sgl,
469 SPI_MAX_XFER, &tx_nents) / qup->w_size;
470 if (!qup->n_words)
471 return -EIO;
472
473 ret = spi_qup_io_config(spi, xfer);
347 if (ret) 474 if (ret)
348 return ret; 475 return ret;
349 476
350 dma_async_issue_pending(master->dma_tx); 477 /* before issuing the descriptors, set the QUP to run */
351 } 478 ret = spi_qup_set_state(qup, QUP_STATE_RUN);
479 if (ret) {
480 dev_warn(qup->dev, "cannot set RUN state\n");
481 return ret;
482 }
483 if (rx_sgl) {
484 ret = spi_qup_prep_sg(master, rx_sgl, rx_nents,
485 DMA_DEV_TO_MEM, rx_done);
486 if (ret)
487 return ret;
488 dma_async_issue_pending(master->dma_rx);
489 }
490
491 if (tx_sgl) {
492 ret = spi_qup_prep_sg(master, tx_sgl, tx_nents,
493 DMA_MEM_TO_DEV, tx_done);
494 if (ret)
495 return ret;
496
497 dma_async_issue_pending(master->dma_tx);
498 }
499
500 if (!wait_for_completion_timeout(&qup->done, timeout))
501 return -ETIMEDOUT;
502
503 for (; rx_sgl && rx_nents--; rx_sgl = sg_next(rx_sgl))
504 ;
505 for (; tx_sgl && tx_nents--; tx_sgl = sg_next(tx_sgl))
506 ;
507
508 } while (rx_sgl || tx_sgl);
352 509
353 return 0; 510 return 0;
354} 511}
355 512
356static int spi_qup_do_pio(struct spi_master *master, struct spi_transfer *xfer) 513static int spi_qup_do_pio(struct spi_device *spi, struct spi_transfer *xfer,
514 unsigned long timeout)
357{ 515{
516 struct spi_master *master = spi->master;
358 struct spi_qup *qup = spi_master_get_devdata(master); 517 struct spi_qup *qup = spi_master_get_devdata(master);
359 int ret; 518 int ret, n_words, iterations, offset = 0;
360 519
361 ret = spi_qup_set_state(qup, QUP_STATE_RUN); 520 n_words = qup->n_words;
362 if (ret) { 521 iterations = n_words / SPI_MAX_XFER; /* round down */
363 dev_warn(qup->dev, "cannot set RUN state\n"); 522 qup->rx_buf = xfer->rx_buf;
364 return ret; 523 qup->tx_buf = xfer->tx_buf;
365 }
366 524
367 ret = spi_qup_set_state(qup, QUP_STATE_PAUSE); 525 do {
368 if (ret) { 526 if (iterations)
369 dev_warn(qup->dev, "cannot set PAUSE state\n"); 527 qup->n_words = SPI_MAX_XFER;
370 return ret; 528 else
371 } 529 qup->n_words = n_words % SPI_MAX_XFER;
530
531 if (qup->tx_buf && offset)
532 qup->tx_buf = xfer->tx_buf + offset * SPI_MAX_XFER;
533
534 if (qup->rx_buf && offset)
535 qup->rx_buf = xfer->rx_buf + offset * SPI_MAX_XFER;
536
537 /*
538 * if the transaction is small enough, we need
539 * to fallback to FIFO mode
540 */
541 if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32)))
542 qup->mode = QUP_IO_M_MODE_FIFO;
372 543
373 spi_qup_fifo_write(qup, xfer); 544 ret = spi_qup_io_config(spi, xfer);
545 if (ret)
546 return ret;
547
548 ret = spi_qup_set_state(qup, QUP_STATE_RUN);
549 if (ret) {
550 dev_warn(qup->dev, "cannot set RUN state\n");
551 return ret;
552 }
553
554 ret = spi_qup_set_state(qup, QUP_STATE_PAUSE);
555 if (ret) {
556 dev_warn(qup->dev, "cannot set PAUSE state\n");
557 return ret;
558 }
559
560 if (qup->mode == QUP_IO_M_MODE_FIFO)
561 spi_qup_write(qup);
562
563 ret = spi_qup_set_state(qup, QUP_STATE_RUN);
564 if (ret) {
565 dev_warn(qup->dev, "cannot set RUN state\n");
566 return ret;
567 }
568
569 if (!wait_for_completion_timeout(&qup->done, timeout))
570 return -ETIMEDOUT;
571
572 offset++;
573 } while (iterations--);
374 574
375 return 0; 575 return 0;
376} 576}
@@ -378,29 +578,15 @@ static int spi_qup_do_pio(struct spi_master *master, struct spi_transfer *xfer)
378static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id) 578static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
379{ 579{
380 struct spi_qup *controller = dev_id; 580 struct spi_qup *controller = dev_id;
381 struct spi_transfer *xfer;
382 u32 opflags, qup_err, spi_err; 581 u32 opflags, qup_err, spi_err;
383 unsigned long flags;
384 int error = 0; 582 int error = 0;
385 583
386 spin_lock_irqsave(&controller->lock, flags);
387 xfer = controller->xfer;
388 controller->xfer = NULL;
389 spin_unlock_irqrestore(&controller->lock, flags);
390
391 qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS); 584 qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS);
392 spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS); 585 spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS);
393 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); 586 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
394 587
395 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS); 588 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS);
396 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS); 589 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS);
397 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
398
399 if (!xfer) {
400 dev_err_ratelimited(controller->dev, "unexpected irq %08x %08x %08x\n",
401 qup_err, spi_err, opflags);
402 return IRQ_HANDLED;
403 }
404 590
405 if (qup_err) { 591 if (qup_err) {
406 if (qup_err & QUP_ERROR_OUTPUT_OVER_RUN) 592 if (qup_err & QUP_ERROR_OUTPUT_OVER_RUN)
@@ -424,54 +610,27 @@ static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
424 error = -EIO; 610 error = -EIO;
425 } 611 }
426 612
427 if (!controller->use_dma) { 613 if (spi_qup_is_dma_xfer(controller->mode)) {
614 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
615 } else {
428 if (opflags & QUP_OP_IN_SERVICE_FLAG) 616 if (opflags & QUP_OP_IN_SERVICE_FLAG)
429 spi_qup_fifo_read(controller, xfer); 617 spi_qup_read(controller, &opflags);
430 618
431 if (opflags & QUP_OP_OUT_SERVICE_FLAG) 619 if (opflags & QUP_OP_OUT_SERVICE_FLAG)
432 spi_qup_fifo_write(controller, xfer); 620 spi_qup_write(controller);
433 } 621 }
434 622
435 spin_lock_irqsave(&controller->lock, flags); 623 if ((opflags & QUP_OP_MAX_INPUT_DONE_FLAG) || error)
436 controller->error = error;
437 controller->xfer = xfer;
438 spin_unlock_irqrestore(&controller->lock, flags);
439
440 if (controller->rx_bytes == xfer->len || error)
441 complete(&controller->done); 624 complete(&controller->done);
442 625
443 return IRQ_HANDLED; 626 return IRQ_HANDLED;
444} 627}
445 628
446static u32 629/* set clock freq ... bits per word, determine mode */
447spi_qup_get_mode(struct spi_master *master, struct spi_transfer *xfer) 630static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer)
448{
449 struct spi_qup *qup = spi_master_get_devdata(master);
450 u32 mode;
451
452 qup->w_size = 4;
453
454 if (xfer->bits_per_word <= 8)
455 qup->w_size = 1;
456 else if (xfer->bits_per_word <= 16)
457 qup->w_size = 2;
458
459 qup->n_words = xfer->len / qup->w_size;
460
461 if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32)))
462 mode = QUP_IO_M_MODE_FIFO;
463 else
464 mode = QUP_IO_M_MODE_BLOCK;
465
466 return mode;
467}
468
469/* set clock freq ... bits per word */
470static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
471{ 631{
472 struct spi_qup *controller = spi_master_get_devdata(spi->master); 632 struct spi_qup *controller = spi_master_get_devdata(spi->master);
473 u32 config, iomode, mode, control; 633 int ret;
474 int ret, n_words;
475 634
476 if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) { 635 if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
477 dev_err(controller->dev, "too big size for loopback %d > %d\n", 636 dev_err(controller->dev, "too big size for loopback %d > %d\n",
@@ -486,30 +645,59 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
486 return -EIO; 645 return -EIO;
487 } 646 }
488 647
648 controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8);
649 controller->n_words = xfer->len / controller->w_size;
650
651 if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32)))
652 controller->mode = QUP_IO_M_MODE_FIFO;
653 else if (spi->master->can_dma &&
654 spi->master->can_dma(spi->master, spi, xfer) &&
655 spi->master->cur_msg_mapped)
656 controller->mode = QUP_IO_M_MODE_BAM;
657 else
658 controller->mode = QUP_IO_M_MODE_BLOCK;
659
660 return 0;
661}
662
663/* prep qup for another spi transaction of specific type */
664static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
665{
666 struct spi_qup *controller = spi_master_get_devdata(spi->master);
667 u32 config, iomode, control;
668 unsigned long flags;
669
670 spin_lock_irqsave(&controller->lock, flags);
671 controller->xfer = xfer;
672 controller->error = 0;
673 controller->rx_bytes = 0;
674 controller->tx_bytes = 0;
675 spin_unlock_irqrestore(&controller->lock, flags);
676
677
489 if (spi_qup_set_state(controller, QUP_STATE_RESET)) { 678 if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
490 dev_err(controller->dev, "cannot set RESET state\n"); 679 dev_err(controller->dev, "cannot set RESET state\n");
491 return -EIO; 680 return -EIO;
492 } 681 }
493 682
494 mode = spi_qup_get_mode(spi->master, xfer); 683 switch (controller->mode) {
495 n_words = controller->n_words; 684 case QUP_IO_M_MODE_FIFO:
496 685 writel_relaxed(controller->n_words,
497 if (mode == QUP_IO_M_MODE_FIFO) { 686 controller->base + QUP_MX_READ_CNT);
498 writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT); 687 writel_relaxed(controller->n_words,
499 writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT); 688 controller->base + QUP_MX_WRITE_CNT);
500 /* must be zero for FIFO */ 689 /* must be zero for FIFO */
501 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT); 690 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
502 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); 691 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
503 } else if (!controller->use_dma) { 692 break;
504 writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT); 693 case QUP_IO_M_MODE_BAM:
505 writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT); 694 writel_relaxed(controller->n_words,
695 controller->base + QUP_MX_INPUT_CNT);
696 writel_relaxed(controller->n_words,
697 controller->base + QUP_MX_OUTPUT_CNT);
506 /* must be zero for BLOCK and BAM */ 698 /* must be zero for BLOCK and BAM */
507 writel_relaxed(0, controller->base + QUP_MX_READ_CNT); 699 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
508 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); 700 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
509 } else {
510 mode = QUP_IO_M_MODE_BAM;
511 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
512 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
513 701
514 if (!controller->qup_v1) { 702 if (!controller->qup_v1) {
515 void __iomem *input_cnt; 703 void __iomem *input_cnt;
@@ -524,23 +712,38 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
524 if (xfer->tx_buf) 712 if (xfer->tx_buf)
525 writel_relaxed(0, input_cnt); 713 writel_relaxed(0, input_cnt);
526 else 714 else
527 writel_relaxed(n_words, input_cnt); 715 writel_relaxed(controller->n_words, input_cnt);
528 716
529 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); 717 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
530 } 718 }
719 break;
720 case QUP_IO_M_MODE_BLOCK:
721 reinit_completion(&controller->done);
722 writel_relaxed(controller->n_words,
723 controller->base + QUP_MX_INPUT_CNT);
724 writel_relaxed(controller->n_words,
725 controller->base + QUP_MX_OUTPUT_CNT);
726 /* must be zero for BLOCK and BAM */
727 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
728 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
729 break;
730 default:
731 dev_err(controller->dev, "unknown mode = %d\n",
732 controller->mode);
733 return -EIO;
531 } 734 }
532 735
533 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES); 736 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
534 /* Set input and output transfer mode */ 737 /* Set input and output transfer mode */
535 iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK); 738 iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
536 739
537 if (!controller->use_dma) 740 if (!spi_qup_is_dma_xfer(controller->mode))
538 iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN); 741 iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
539 else 742 else
540 iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN; 743 iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN;
541 744
542 iomode |= (mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT); 745 iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
543 iomode |= (mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT); 746 iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
544 747
545 writel_relaxed(iomode, controller->base + QUP_IO_M_MODES); 748 writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
546 749
@@ -581,7 +784,7 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
581 config |= xfer->bits_per_word - 1; 784 config |= xfer->bits_per_word - 1;
582 config |= QUP_CONFIG_SPI_MODE; 785 config |= QUP_CONFIG_SPI_MODE;
583 786
584 if (controller->use_dma) { 787 if (spi_qup_is_dma_xfer(controller->mode)) {
585 if (!xfer->tx_buf) 788 if (!xfer->tx_buf)
586 config |= QUP_CONFIG_NO_OUTPUT; 789 config |= QUP_CONFIG_NO_OUTPUT;
587 if (!xfer->rx_buf) 790 if (!xfer->rx_buf)
@@ -599,7 +802,7 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
599 * status change in BAM mode 802 * status change in BAM mode
600 */ 803 */
601 804
602 if (mode == QUP_IO_M_MODE_BAM) 805 if (spi_qup_is_dma_xfer(controller->mode))
603 mask = QUP_OP_IN_SERVICE_FLAG | QUP_OP_OUT_SERVICE_FLAG; 806 mask = QUP_OP_IN_SERVICE_FLAG | QUP_OP_OUT_SERVICE_FLAG;
604 807
605 writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK); 808 writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK);
@@ -616,12 +819,13 @@ static int spi_qup_transfer_one(struct spi_master *master,
616 unsigned long timeout, flags; 819 unsigned long timeout, flags;
617 int ret = -EIO; 820 int ret = -EIO;
618 821
619 ret = spi_qup_io_config(spi, xfer); 822 ret = spi_qup_io_prep(spi, xfer);
620 if (ret) 823 if (ret)
621 return ret; 824 return ret;
622 825
623 timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC); 826 timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC);
624 timeout = DIV_ROUND_UP(xfer->len * 8, timeout); 827 timeout = DIV_ROUND_UP(min_t(unsigned long, SPI_MAX_XFER,
828 xfer->len) * 8, timeout);
625 timeout = 100 * msecs_to_jiffies(timeout); 829 timeout = 100 * msecs_to_jiffies(timeout);
626 830
627 reinit_completion(&controller->done); 831 reinit_completion(&controller->done);
@@ -633,31 +837,22 @@ static int spi_qup_transfer_one(struct spi_master *master,
633 controller->tx_bytes = 0; 837 controller->tx_bytes = 0;
634 spin_unlock_irqrestore(&controller->lock, flags); 838 spin_unlock_irqrestore(&controller->lock, flags);
635 839
636 if (controller->use_dma) 840 if (spi_qup_is_dma_xfer(controller->mode))
637 ret = spi_qup_do_dma(master, xfer); 841 ret = spi_qup_do_dma(spi, xfer, timeout);
638 else 842 else
639 ret = spi_qup_do_pio(master, xfer); 843 ret = spi_qup_do_pio(spi, xfer, timeout);
640 844
641 if (ret) 845 if (ret)
642 goto exit; 846 goto exit;
643 847
644 if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
645 dev_warn(controller->dev, "cannot set EXECUTE state\n");
646 goto exit;
647 }
648
649 if (!wait_for_completion_timeout(&controller->done, timeout))
650 ret = -ETIMEDOUT;
651
652exit: 848exit:
653 spi_qup_set_state(controller, QUP_STATE_RESET); 849 spi_qup_set_state(controller, QUP_STATE_RESET);
654 spin_lock_irqsave(&controller->lock, flags); 850 spin_lock_irqsave(&controller->lock, flags);
655 controller->xfer = NULL;
656 if (!ret) 851 if (!ret)
657 ret = controller->error; 852 ret = controller->error;
658 spin_unlock_irqrestore(&controller->lock, flags); 853 spin_unlock_irqrestore(&controller->lock, flags);
659 854
660 if (ret && controller->use_dma) 855 if (ret && spi_qup_is_dma_xfer(controller->mode))
661 spi_qup_dma_terminate(master, xfer); 856 spi_qup_dma_terminate(master, xfer);
662 857
663 return ret; 858 return ret;
@@ -668,26 +863,28 @@ static bool spi_qup_can_dma(struct spi_master *master, struct spi_device *spi,
668{ 863{
669 struct spi_qup *qup = spi_master_get_devdata(master); 864 struct spi_qup *qup = spi_master_get_devdata(master);
670 size_t dma_align = dma_get_cache_alignment(); 865 size_t dma_align = dma_get_cache_alignment();
671 u32 mode; 866 int n_words;
672
673 qup->use_dma = 0;
674 867
675 if (xfer->rx_buf && (xfer->len % qup->in_blk_sz || 868 if (xfer->rx_buf) {
676 IS_ERR_OR_NULL(master->dma_rx) || 869 if (!IS_ALIGNED((size_t)xfer->rx_buf, dma_align) ||
677 !IS_ALIGNED((size_t)xfer->rx_buf, dma_align))) 870 IS_ERR_OR_NULL(master->dma_rx))
678 return false; 871 return false;
872 if (qup->qup_v1 && (xfer->len % qup->in_blk_sz))
873 return false;
874 }
679 875
680 if (xfer->tx_buf && (xfer->len % qup->out_blk_sz || 876 if (xfer->tx_buf) {
681 IS_ERR_OR_NULL(master->dma_tx) || 877 if (!IS_ALIGNED((size_t)xfer->tx_buf, dma_align) ||
682 !IS_ALIGNED((size_t)xfer->tx_buf, dma_align))) 878 IS_ERR_OR_NULL(master->dma_tx))
683 return false; 879 return false;
880 if (qup->qup_v1 && (xfer->len % qup->out_blk_sz))
881 return false;
882 }
684 883
685 mode = spi_qup_get_mode(master, xfer); 884 n_words = xfer->len / DIV_ROUND_UP(xfer->bits_per_word, 8);
686 if (mode == QUP_IO_M_MODE_FIFO) 885 if (n_words <= (qup->in_fifo_sz / sizeof(u32)))
687 return false; 886 return false;
688 887
689 qup->use_dma = 1;
690
691 return true; 888 return true;
692} 889}
693 890
@@ -750,6 +947,24 @@ err_tx:
750 return ret; 947 return ret;
751} 948}
752 949
950static void spi_qup_set_cs(struct spi_device *spi, bool val)
951{
952 struct spi_qup *controller;
953 u32 spi_ioc;
954 u32 spi_ioc_orig;
955
956 controller = spi_master_get_devdata(spi->master);
957 spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL);
958 spi_ioc_orig = spi_ioc;
959 if (!val)
960 spi_ioc |= SPI_IO_C_FORCE_CS;
961 else
962 spi_ioc &= ~SPI_IO_C_FORCE_CS;
963
964 if (spi_ioc != spi_ioc_orig)
965 writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL);
966}
967
753static int spi_qup_probe(struct platform_device *pdev) 968static int spi_qup_probe(struct platform_device *pdev)
754{ 969{
755 struct spi_master *master; 970 struct spi_master *master;
@@ -824,7 +1039,7 @@ static int spi_qup_probe(struct platform_device *pdev)
824 master->dev.of_node = pdev->dev.of_node; 1039 master->dev.of_node = pdev->dev.of_node;
825 master->auto_runtime_pm = true; 1040 master->auto_runtime_pm = true;
826 master->dma_alignment = dma_get_cache_alignment(); 1041 master->dma_alignment = dma_get_cache_alignment();
827 master->max_dma_len = SPI_MAX_DMA_XFER; 1042 master->max_dma_len = SPI_MAX_XFER;
828 1043
829 platform_set_drvdata(pdev, master); 1044 platform_set_drvdata(pdev, master);
830 1045
@@ -842,9 +1057,10 @@ static int spi_qup_probe(struct platform_device *pdev)
842 else if (!ret) 1057 else if (!ret)
843 master->can_dma = spi_qup_can_dma; 1058 master->can_dma = spi_qup_can_dma;
844 1059
845 /* set v1 flag if device is version 1 */ 1060 controller->qup_v1 = (uintptr_t)of_device_get_match_data(dev);
846 if (of_device_is_compatible(dev->of_node, "qcom,spi-qup-v1.1.1")) 1061
847 controller->qup_v1 = 1; 1062 if (!controller->qup_v1)
1063 master->set_cs = spi_qup_set_cs;
848 1064
849 spin_lock_init(&controller->lock); 1065 spin_lock_init(&controller->lock);
850 init_completion(&controller->done); 1066 init_completion(&controller->done);
@@ -1037,7 +1253,7 @@ static int spi_qup_remove(struct platform_device *pdev)
1037} 1253}
1038 1254
1039static const struct of_device_id spi_qup_dt_match[] = { 1255static const struct of_device_id spi_qup_dt_match[] = {
1040 { .compatible = "qcom,spi-qup-v1.1.1", }, 1256 { .compatible = "qcom,spi-qup-v1.1.1", .data = (void *)1, },
1041 { .compatible = "qcom,spi-qup-v2.1.1", }, 1257 { .compatible = "qcom,spi-qup-v2.1.1", },
1042 { .compatible = "qcom,spi-qup-v2.2.1", }, 1258 { .compatible = "qcom,spi-qup-v2.2.1", },
1043 { } 1259 { }
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 0b4a52b3e1dc..fdcf3076681b 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -568,7 +568,13 @@ static void rockchip_spi_config(struct rockchip_spi *rs)
568 568
569 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); 569 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
570 570
571 writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1); 571 if (rs->n_bytes == 1)
572 writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
573 else if (rs->n_bytes == 2)
574 writel_relaxed((rs->len / 2) - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
575 else
576 writel_relaxed((rs->len * 2) - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
577
572 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR); 578 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR);
573 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); 579 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
574 580
@@ -666,7 +672,7 @@ static bool rockchip_spi_can_dma(struct spi_master *master,
666 672
667static int rockchip_spi_probe(struct platform_device *pdev) 673static int rockchip_spi_probe(struct platform_device *pdev)
668{ 674{
669 int ret = 0; 675 int ret;
670 struct rockchip_spi *rs; 676 struct rockchip_spi *rs;
671 struct spi_master *master; 677 struct spi_master *master;
672 struct resource *mem; 678 struct resource *mem;
@@ -703,13 +709,13 @@ static int rockchip_spi_probe(struct platform_device *pdev)
703 } 709 }
704 710
705 ret = clk_prepare_enable(rs->apb_pclk); 711 ret = clk_prepare_enable(rs->apb_pclk);
706 if (ret) { 712 if (ret < 0) {
707 dev_err(&pdev->dev, "Failed to enable apb_pclk\n"); 713 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
708 goto err_put_master; 714 goto err_put_master;
709 } 715 }
710 716
711 ret = clk_prepare_enable(rs->spiclk); 717 ret = clk_prepare_enable(rs->spiclk);
712 if (ret) { 718 if (ret < 0) {
713 dev_err(&pdev->dev, "Failed to enable spi_clk\n"); 719 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
714 goto err_disable_apbclk; 720 goto err_disable_apbclk;
715 } 721 }
@@ -786,7 +792,7 @@ static int rockchip_spi_probe(struct platform_device *pdev)
786 } 792 }
787 793
788 ret = devm_spi_register_master(&pdev->dev, master); 794 ret = devm_spi_register_master(&pdev->dev, master);
789 if (ret) { 795 if (ret < 0) {
790 dev_err(&pdev->dev, "Failed to register master\n"); 796 dev_err(&pdev->dev, "Failed to register master\n");
791 goto err_free_dma_rx; 797 goto err_free_dma_rx;
792 } 798 }
@@ -816,11 +822,15 @@ static int rockchip_spi_remove(struct platform_device *pdev)
816 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); 822 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
817 struct rockchip_spi *rs = spi_master_get_devdata(master); 823 struct rockchip_spi *rs = spi_master_get_devdata(master);
818 824
819 pm_runtime_disable(&pdev->dev); 825 pm_runtime_get_sync(&pdev->dev);
820 826
821 clk_disable_unprepare(rs->spiclk); 827 clk_disable_unprepare(rs->spiclk);
822 clk_disable_unprepare(rs->apb_pclk); 828 clk_disable_unprepare(rs->apb_pclk);
823 829
830 pm_runtime_put_noidle(&pdev->dev);
831 pm_runtime_disable(&pdev->dev);
832 pm_runtime_set_suspended(&pdev->dev);
833
824 if (rs->dma_tx.ch) 834 if (rs->dma_tx.ch)
825 dma_release_channel(rs->dma_tx.ch); 835 dma_release_channel(rs->dma_tx.ch);
826 if (rs->dma_rx.ch) 836 if (rs->dma_rx.ch)
@@ -834,43 +844,34 @@ static int rockchip_spi_remove(struct platform_device *pdev)
834#ifdef CONFIG_PM_SLEEP 844#ifdef CONFIG_PM_SLEEP
835static int rockchip_spi_suspend(struct device *dev) 845static int rockchip_spi_suspend(struct device *dev)
836{ 846{
837 int ret = 0; 847 int ret;
838 struct spi_master *master = dev_get_drvdata(dev); 848 struct spi_master *master = dev_get_drvdata(dev);
839 struct rockchip_spi *rs = spi_master_get_devdata(master); 849 struct rockchip_spi *rs = spi_master_get_devdata(master);
840 850
841 ret = spi_master_suspend(rs->master); 851 ret = spi_master_suspend(rs->master);
842 if (ret) 852 if (ret < 0)
843 return ret; 853 return ret;
844 854
845 if (!pm_runtime_suspended(dev)) { 855 ret = pm_runtime_force_suspend(dev);
846 clk_disable_unprepare(rs->spiclk); 856 if (ret < 0)
847 clk_disable_unprepare(rs->apb_pclk); 857 return ret;
848 }
849 858
850 pinctrl_pm_select_sleep_state(dev); 859 pinctrl_pm_select_sleep_state(dev);
851 860
852 return ret; 861 return 0;
853} 862}
854 863
855static int rockchip_spi_resume(struct device *dev) 864static int rockchip_spi_resume(struct device *dev)
856{ 865{
857 int ret = 0; 866 int ret;
858 struct spi_master *master = dev_get_drvdata(dev); 867 struct spi_master *master = dev_get_drvdata(dev);
859 struct rockchip_spi *rs = spi_master_get_devdata(master); 868 struct rockchip_spi *rs = spi_master_get_devdata(master);
860 869
861 pinctrl_pm_select_default_state(dev); 870 pinctrl_pm_select_default_state(dev);
862 871
863 if (!pm_runtime_suspended(dev)) { 872 ret = pm_runtime_force_resume(dev);
864 ret = clk_prepare_enable(rs->apb_pclk); 873 if (ret < 0)
865 if (ret < 0) 874 return ret;
866 return ret;
867
868 ret = clk_prepare_enable(rs->spiclk);
869 if (ret < 0) {
870 clk_disable_unprepare(rs->apb_pclk);
871 return ret;
872 }
873 }
874 875
875 ret = spi_master_resume(rs->master); 876 ret = spi_master_resume(rs->master);
876 if (ret < 0) { 877 if (ret < 0) {
@@ -878,7 +879,7 @@ static int rockchip_spi_resume(struct device *dev)
878 clk_disable_unprepare(rs->apb_pclk); 879 clk_disable_unprepare(rs->apb_pclk);
879 } 880 }
880 881
881 return ret; 882 return 0;
882} 883}
883#endif /* CONFIG_PM_SLEEP */ 884#endif /* CONFIG_PM_SLEEP */
884 885
@@ -901,14 +902,14 @@ static int rockchip_spi_runtime_resume(struct device *dev)
901 struct rockchip_spi *rs = spi_master_get_devdata(master); 902 struct rockchip_spi *rs = spi_master_get_devdata(master);
902 903
903 ret = clk_prepare_enable(rs->apb_pclk); 904 ret = clk_prepare_enable(rs->apb_pclk);
904 if (ret) 905 if (ret < 0)
905 return ret; 906 return ret;
906 907
907 ret = clk_prepare_enable(rs->spiclk); 908 ret = clk_prepare_enable(rs->spiclk);
908 if (ret) 909 if (ret < 0)
909 clk_disable_unprepare(rs->apb_pclk); 910 clk_disable_unprepare(rs->apb_pclk);
910 911
911 return ret; 912 return 0;
912} 913}
913#endif /* CONFIG_PM */ 914#endif /* CONFIG_PM */
914 915
@@ -919,6 +920,7 @@ static const struct dev_pm_ops rockchip_spi_pm = {
919}; 920};
920 921
921static const struct of_device_id rockchip_spi_dt_match[] = { 922static const struct of_device_id rockchip_spi_dt_match[] = {
923 { .compatible = "rockchip,rv1108-spi", },
922 { .compatible = "rockchip,rk3036-spi", }, 924 { .compatible = "rockchip,rk3036-spi", },
923 { .compatible = "rockchip,rk3066-spi", }, 925 { .compatible = "rockchip,rk3066-spi", },
924 { .compatible = "rockchip,rk3188-spi", }, 926 { .compatible = "rockchip,rk3188-spi", },
diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index c304c7167866..0eb1e9583485 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -38,6 +38,7 @@ struct sh_msiof_chipdata {
38 u16 tx_fifo_size; 38 u16 tx_fifo_size;
39 u16 rx_fifo_size; 39 u16 rx_fifo_size;
40 u16 master_flags; 40 u16 master_flags;
41 u16 min_div;
41}; 42};
42 43
43struct sh_msiof_spi_priv { 44struct sh_msiof_spi_priv {
@@ -49,6 +50,7 @@ struct sh_msiof_spi_priv {
49 struct completion done; 50 struct completion done;
50 unsigned int tx_fifo_size; 51 unsigned int tx_fifo_size;
51 unsigned int rx_fifo_size; 52 unsigned int rx_fifo_size;
53 unsigned int min_div;
52 void *tx_dma_page; 54 void *tx_dma_page;
53 void *rx_dma_page; 55 void *rx_dma_page;
54 dma_addr_t tx_dma_addr; 56 dma_addr_t tx_dma_addr;
@@ -261,6 +263,8 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
261 if (!WARN_ON(!spi_hz || !parent_rate)) 263 if (!WARN_ON(!spi_hz || !parent_rate))
262 div = DIV_ROUND_UP(parent_rate, spi_hz); 264 div = DIV_ROUND_UP(parent_rate, spi_hz);
263 265
266 div = max_t(unsigned long, div, p->min_div);
267
264 for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_div_table); k++) { 268 for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_div_table); k++) {
265 brps = DIV_ROUND_UP(div, sh_msiof_spi_div_table[k].div); 269 brps = DIV_ROUND_UP(div, sh_msiof_spi_div_table[k].div);
266 /* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */ 270 /* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
@@ -998,24 +1002,33 @@ static const struct sh_msiof_chipdata sh_data = {
998 .tx_fifo_size = 64, 1002 .tx_fifo_size = 64,
999 .rx_fifo_size = 64, 1003 .rx_fifo_size = 64,
1000 .master_flags = 0, 1004 .master_flags = 0,
1005 .min_div = 1,
1006};
1007
1008static const struct sh_msiof_chipdata rcar_gen2_data = {
1009 .tx_fifo_size = 64,
1010 .rx_fifo_size = 64,
1011 .master_flags = SPI_MASTER_MUST_TX,
1012 .min_div = 1,
1001}; 1013};
1002 1014
1003static const struct sh_msiof_chipdata r8a779x_data = { 1015static const struct sh_msiof_chipdata rcar_gen3_data = {
1004 .tx_fifo_size = 64, 1016 .tx_fifo_size = 64,
1005 .rx_fifo_size = 64, 1017 .rx_fifo_size = 64,
1006 .master_flags = SPI_MASTER_MUST_TX, 1018 .master_flags = SPI_MASTER_MUST_TX,
1019 .min_div = 2,
1007}; 1020};
1008 1021
1009static const struct of_device_id sh_msiof_match[] = { 1022static const struct of_device_id sh_msiof_match[] = {
1010 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data }, 1023 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
1011 { .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data }, 1024 { .compatible = "renesas,msiof-r8a7790", .data = &rcar_gen2_data },
1012 { .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data }, 1025 { .compatible = "renesas,msiof-r8a7791", .data = &rcar_gen2_data },
1013 { .compatible = "renesas,msiof-r8a7792", .data = &r8a779x_data }, 1026 { .compatible = "renesas,msiof-r8a7792", .data = &rcar_gen2_data },
1014 { .compatible = "renesas,msiof-r8a7793", .data = &r8a779x_data }, 1027 { .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data },
1015 { .compatible = "renesas,msiof-r8a7794", .data = &r8a779x_data }, 1028 { .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data },
1016 { .compatible = "renesas,rcar-gen2-msiof", .data = &r8a779x_data }, 1029 { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },
1017 { .compatible = "renesas,msiof-r8a7796", .data = &r8a779x_data }, 1030 { .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data },
1018 { .compatible = "renesas,rcar-gen3-msiof", .data = &r8a779x_data }, 1031 { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },
1019 { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */ 1032 { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */
1020 {}, 1033 {},
1021}; 1034};
@@ -1230,6 +1243,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
1230 platform_set_drvdata(pdev, p); 1243 platform_set_drvdata(pdev, p);
1231 p->master = master; 1244 p->master = master;
1232 p->info = info; 1245 p->info = info;
1246 p->min_div = chipdata->min_div;
1233 1247
1234 init_completion(&p->done); 1248 init_completion(&p->done);
1235 1249
diff --git a/drivers/spi/spi-sh.c b/drivers/spi/spi-sh.c
index 2bf53f0e27d9..50e0ea9acf8b 100644
--- a/drivers/spi/spi-sh.c
+++ b/drivers/spi/spi-sh.c
@@ -446,8 +446,8 @@ static int spi_sh_probe(struct platform_device *pdev)
446 446
447 irq = platform_get_irq(pdev, 0); 447 irq = platform_get_irq(pdev, 0);
448 if (irq < 0) { 448 if (irq < 0) {
449 dev_err(&pdev->dev, "platform_get_irq error\n"); 449 dev_err(&pdev->dev, "platform_get_irq error: %d\n", irq);
450 return -ENODEV; 450 return irq;
451 } 451 }
452 452
453 master = spi_alloc_master(&pdev->dev, sizeof(struct spi_sh_data)); 453 master = spi_alloc_master(&pdev->dev, sizeof(struct spi_sh_data));
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 75644bcd938b..680cdf549506 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1132,7 +1132,7 @@ static int stm32_spi_probe(struct platform_device *pdev)
1132 goto err_master_put; 1132 goto err_master_put;
1133 } 1133 }
1134 1134
1135 spi->rst = devm_reset_control_get(&pdev->dev, NULL); 1135 spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1136 if (!IS_ERR(spi->rst)) { 1136 if (!IS_ERR(spi->rst)) {
1137 reset_control_assert(spi->rst); 1137 reset_control_assert(spi->rst);
1138 udelay(2); 1138 udelay(2);
diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c
index 03a773a9531a..fb38234249a8 100644
--- a/drivers/spi/spi-sun6i.c
+++ b/drivers/spi/spi-sun6i.c
@@ -502,7 +502,7 @@ static int sun6i_spi_probe(struct platform_device *pdev)
502 502
503 init_completion(&sspi->done); 503 init_completion(&sspi->done);
504 504
505 sspi->rstc = devm_reset_control_get(&pdev->dev, NULL); 505 sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
506 if (IS_ERR(sspi->rstc)) { 506 if (IS_ERR(sspi->rstc)) {
507 dev_err(&pdev->dev, "Couldn't get reset controller\n"); 507 dev_err(&pdev->dev, "Couldn't get reset controller\n");
508 ret = PTR_ERR(sspi->rstc); 508 ret = PTR_ERR(sspi->rstc);
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index 08012ae5aa66..44550182a4a3 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -1083,7 +1083,7 @@ static int tegra_spi_probe(struct platform_device *pdev)
1083 goto exit_free_irq; 1083 goto exit_free_irq;
1084 } 1084 }
1085 1085
1086 tspi->rst = devm_reset_control_get(&pdev->dev, "spi"); 1086 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
1087 if (IS_ERR(tspi->rst)) { 1087 if (IS_ERR(tspi->rst)) {
1088 dev_err(&pdev->dev, "can not get reset\n"); 1088 dev_err(&pdev->dev, "can not get reset\n");
1089 ret = PTR_ERR(tspi->rst); 1089 ret = PTR_ERR(tspi->rst);
diff --git a/drivers/spi/spi-tegra20-sflash.c b/drivers/spi/spi-tegra20-sflash.c
index 2c797ee2664d..22893a7e0aa0 100644
--- a/drivers/spi/spi-tegra20-sflash.c
+++ b/drivers/spi/spi-tegra20-sflash.c
@@ -485,7 +485,7 @@ static int tegra_sflash_probe(struct platform_device *pdev)
485 goto exit_free_irq; 485 goto exit_free_irq;
486 } 486 }
487 487
488 tsd->rst = devm_reset_control_get(&pdev->dev, "spi"); 488 tsd->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
489 if (IS_ERR(tsd->rst)) { 489 if (IS_ERR(tsd->rst)) {
490 dev_err(&pdev->dev, "can not get reset\n"); 490 dev_err(&pdev->dev, "can not get reset\n");
491 ret = PTR_ERR(tsd->rst); 491 ret = PTR_ERR(tsd->rst);
diff --git a/drivers/spi/spi-tegra20-slink.c b/drivers/spi/spi-tegra20-slink.c
index 0c06ce424210..3e12d5f87ee4 100644
--- a/drivers/spi/spi-tegra20-slink.c
+++ b/drivers/spi/spi-tegra20-slink.c
@@ -1081,7 +1081,7 @@ static int tegra_slink_probe(struct platform_device *pdev)
1081 goto exit_free_irq; 1081 goto exit_free_irq;
1082 } 1082 }
1083 1083
1084 tspi->rst = devm_reset_control_get(&pdev->dev, "spi"); 1084 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
1085 if (IS_ERR(tspi->rst)) { 1085 if (IS_ERR(tspi->rst)) {
1086 dev_err(&pdev->dev, "can not get reset\n"); 1086 dev_err(&pdev->dev, "can not get reset\n");
1087 ret = PTR_ERR(tspi->rst); 1087 ret = PTR_ERR(tspi->rst);
diff --git a/drivers/spi/spi-xlp.c b/drivers/spi/spi-xlp.c
index 80cb4d6af892..74a01b09a8a5 100644
--- a/drivers/spi/spi-xlp.c
+++ b/drivers/spi/spi-xlp.c
@@ -393,8 +393,8 @@ static int xlp_spi_probe(struct platform_device *pdev)
393 393
394 irq = platform_get_irq(pdev, 0); 394 irq = platform_get_irq(pdev, 0);
395 if (irq < 0) { 395 if (irq < 0) {
396 dev_err(&pdev->dev, "no IRQ resource found\n"); 396 dev_err(&pdev->dev, "no IRQ resource found: %d\n", irq);
397 return -EINVAL; 397 return irq;
398 } 398 }
399 err = devm_request_irq(&pdev->dev, irq, xlp_spi_interrupt, 0, 399 err = devm_request_irq(&pdev->dev, irq, xlp_spi_interrupt, 0,
400 pdev->name, xspi); 400 pdev->name, xspi);
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 4fcbb0aa71d3..cf8ee5e48f73 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -40,9 +40,13 @@
40#include <linux/ioport.h> 40#include <linux/ioport.h>
41#include <linux/acpi.h> 41#include <linux/acpi.h>
42#include <linux/highmem.h> 42#include <linux/highmem.h>
43#include <linux/idr.h>
43 44
44#define CREATE_TRACE_POINTS 45#define CREATE_TRACE_POINTS
45#include <trace/events/spi.h> 46#include <trace/events/spi.h>
47#define SPI_DYN_FIRST_BUS_NUM 0
48
49static DEFINE_IDR(spi_master_idr);
46 50
47static void spidev_release(struct device *dev) 51static void spidev_release(struct device *dev)
48{ 52{
@@ -321,8 +325,7 @@ static int spi_uevent(struct device *dev, struct kobj_uevent_env *env)
321 if (rc != -ENODEV) 325 if (rc != -ENODEV)
322 return rc; 326 return rc;
323 327
324 add_uevent_var(env, "MODALIAS=%s%s", SPI_MODULE_PREFIX, spi->modalias); 328 return add_uevent_var(env, "MODALIAS=%s%s", SPI_MODULE_PREFIX, spi->modalias);
325 return 0;
326} 329}
327 330
328struct bus_type spi_bus_type = { 331struct bus_type spi_bus_type = {
@@ -421,6 +424,7 @@ static LIST_HEAD(spi_controller_list);
421/* 424/*
422 * Used to protect add/del opertion for board_info list and 425 * Used to protect add/del opertion for board_info list and
423 * spi_controller list, and their matching process 426 * spi_controller list, and their matching process
427 * also used to protect object of type struct idr
424 */ 428 */
425static DEFINE_MUTEX(board_lock); 429static DEFINE_MUTEX(board_lock);
426 430
@@ -1533,15 +1537,15 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
1533 int rc; 1537 int rc;
1534 1538
1535 /* Mode (clock phase/polarity/etc.) */ 1539 /* Mode (clock phase/polarity/etc.) */
1536 if (of_find_property(nc, "spi-cpha", NULL)) 1540 if (of_property_read_bool(nc, "spi-cpha"))
1537 spi->mode |= SPI_CPHA; 1541 spi->mode |= SPI_CPHA;
1538 if (of_find_property(nc, "spi-cpol", NULL)) 1542 if (of_property_read_bool(nc, "spi-cpol"))
1539 spi->mode |= SPI_CPOL; 1543 spi->mode |= SPI_CPOL;
1540 if (of_find_property(nc, "spi-cs-high", NULL)) 1544 if (of_property_read_bool(nc, "spi-cs-high"))
1541 spi->mode |= SPI_CS_HIGH; 1545 spi->mode |= SPI_CS_HIGH;
1542 if (of_find_property(nc, "spi-3wire", NULL)) 1546 if (of_property_read_bool(nc, "spi-3wire"))
1543 spi->mode |= SPI_3WIRE; 1547 spi->mode |= SPI_3WIRE;
1544 if (of_find_property(nc, "spi-lsb-first", NULL)) 1548 if (of_property_read_bool(nc, "spi-lsb-first"))
1545 spi->mode |= SPI_LSB_FIRST; 1549 spi->mode |= SPI_LSB_FIRST;
1546 1550
1547 /* Device DUAL/QUAD mode */ 1551 /* Device DUAL/QUAD mode */
@@ -1583,8 +1587,8 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
1583 1587
1584 if (spi_controller_is_slave(ctlr)) { 1588 if (spi_controller_is_slave(ctlr)) {
1585 if (strcmp(nc->name, "slave")) { 1589 if (strcmp(nc->name, "slave")) {
1586 dev_err(&ctlr->dev, "%s is not called 'slave'\n", 1590 dev_err(&ctlr->dev, "%pOF is not called 'slave'\n",
1587 nc->full_name); 1591 nc);
1588 return -EINVAL; 1592 return -EINVAL;
1589 } 1593 }
1590 return 0; 1594 return 0;
@@ -1593,8 +1597,8 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
1593 /* Device address */ 1597 /* Device address */
1594 rc = of_property_read_u32(nc, "reg", &value); 1598 rc = of_property_read_u32(nc, "reg", &value);
1595 if (rc) { 1599 if (rc) {
1596 dev_err(&ctlr->dev, "%s has no valid 'reg' property (%d)\n", 1600 dev_err(&ctlr->dev, "%pOF has no valid 'reg' property (%d)\n",
1597 nc->full_name, rc); 1601 nc, rc);
1598 return rc; 1602 return rc;
1599 } 1603 }
1600 spi->chip_select = value; 1604 spi->chip_select = value;
@@ -1603,8 +1607,7 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
1603 rc = of_property_read_u32(nc, "spi-max-frequency", &value); 1607 rc = of_property_read_u32(nc, "spi-max-frequency", &value);
1604 if (rc) { 1608 if (rc) {
1605 dev_err(&ctlr->dev, 1609 dev_err(&ctlr->dev,
1606 "%s has no valid 'spi-max-frequency' property (%d)\n", 1610 "%pOF has no valid 'spi-max-frequency' property (%d)\n", nc, rc);
1607 nc->full_name, rc);
1608 return rc; 1611 return rc;
1609 } 1612 }
1610 spi->max_speed_hz = value; 1613 spi->max_speed_hz = value;
@@ -1621,8 +1624,7 @@ of_register_spi_device(struct spi_controller *ctlr, struct device_node *nc)
1621 /* Alloc an spi_device */ 1624 /* Alloc an spi_device */
1622 spi = spi_alloc_device(ctlr); 1625 spi = spi_alloc_device(ctlr);
1623 if (!spi) { 1626 if (!spi) {
1624 dev_err(&ctlr->dev, "spi_device alloc error for %s\n", 1627 dev_err(&ctlr->dev, "spi_device alloc error for %pOF\n", nc);
1625 nc->full_name);
1626 rc = -ENOMEM; 1628 rc = -ENOMEM;
1627 goto err_out; 1629 goto err_out;
1628 } 1630 }
@@ -1631,8 +1633,7 @@ of_register_spi_device(struct spi_controller *ctlr, struct device_node *nc)
1631 rc = of_modalias_node(nc, spi->modalias, 1633 rc = of_modalias_node(nc, spi->modalias,
1632 sizeof(spi->modalias)); 1634 sizeof(spi->modalias));
1633 if (rc < 0) { 1635 if (rc < 0) {
1634 dev_err(&ctlr->dev, "cannot find modalias for %s\n", 1636 dev_err(&ctlr->dev, "cannot find modalias for %pOF\n", nc);
1635 nc->full_name);
1636 goto err_out; 1637 goto err_out;
1637 } 1638 }
1638 1639
@@ -1647,8 +1648,7 @@ of_register_spi_device(struct spi_controller *ctlr, struct device_node *nc)
1647 /* Register the new device */ 1648 /* Register the new device */
1648 rc = spi_add_device(spi); 1649 rc = spi_add_device(spi);
1649 if (rc) { 1650 if (rc) {
1650 dev_err(&ctlr->dev, "spi_device register error %s\n", 1651 dev_err(&ctlr->dev, "spi_device register error %pOF\n", nc);
1651 nc->full_name);
1652 goto err_of_node_put; 1652 goto err_of_node_put;
1653 } 1653 }
1654 1654
@@ -1682,8 +1682,7 @@ static void of_register_spi_devices(struct spi_controller *ctlr)
1682 spi = of_register_spi_device(ctlr, nc); 1682 spi = of_register_spi_device(ctlr, nc);
1683 if (IS_ERR(spi)) { 1683 if (IS_ERR(spi)) {
1684 dev_warn(&ctlr->dev, 1684 dev_warn(&ctlr->dev,
1685 "Failed to create SPI device for %s\n", 1685 "Failed to create SPI device for %pOF\n", nc);
1686 nc->full_name);
1687 of_node_clear_flag(nc, OF_POPULATED); 1686 of_node_clear_flag(nc, OF_POPULATED);
1688 } 1687 }
1689 } 1688 }
@@ -2052,11 +2051,10 @@ static int of_spi_register_master(struct spi_controller *ctlr)
2052 */ 2051 */
2053int spi_register_controller(struct spi_controller *ctlr) 2052int spi_register_controller(struct spi_controller *ctlr)
2054{ 2053{
2055 static atomic_t dyn_bus_id = ATOMIC_INIT((1<<15) - 1);
2056 struct device *dev = ctlr->dev.parent; 2054 struct device *dev = ctlr->dev.parent;
2057 struct boardinfo *bi; 2055 struct boardinfo *bi;
2058 int status = -ENODEV; 2056 int status = -ENODEV;
2059 int dynamic = 0; 2057 int id;
2060 2058
2061 if (!dev) 2059 if (!dev)
2062 return -ENODEV; 2060 return -ENODEV;
@@ -2072,19 +2070,28 @@ int spi_register_controller(struct spi_controller *ctlr)
2072 */ 2070 */
2073 if (ctlr->num_chipselect == 0) 2071 if (ctlr->num_chipselect == 0)
2074 return -EINVAL; 2072 return -EINVAL;
2075 2073 /* allocate dynamic bus number using Linux idr */
2076 if ((ctlr->bus_num < 0) && ctlr->dev.of_node) 2074 if ((ctlr->bus_num < 0) && ctlr->dev.of_node) {
2077 ctlr->bus_num = of_alias_get_id(ctlr->dev.of_node, "spi"); 2075 id = of_alias_get_id(ctlr->dev.of_node, "spi");
2078 2076 if (id >= 0) {
2079 /* convention: dynamically assigned bus IDs count down from the max */ 2077 ctlr->bus_num = id;
2078 mutex_lock(&board_lock);
2079 id = idr_alloc(&spi_master_idr, ctlr, ctlr->bus_num,
2080 ctlr->bus_num + 1, GFP_KERNEL);
2081 mutex_unlock(&board_lock);
2082 if (WARN(id < 0, "couldn't get idr"))
2083 return id == -ENOSPC ? -EBUSY : id;
2084 }
2085 }
2080 if (ctlr->bus_num < 0) { 2086 if (ctlr->bus_num < 0) {
2081 /* FIXME switch to an IDR based scheme, something like 2087 mutex_lock(&board_lock);
2082 * I2C now uses, so we can't run out of "dynamic" IDs 2088 id = idr_alloc(&spi_master_idr, ctlr, SPI_DYN_FIRST_BUS_NUM, 0,
2083 */ 2089 GFP_KERNEL);
2084 ctlr->bus_num = atomic_dec_return(&dyn_bus_id); 2090 mutex_unlock(&board_lock);
2085 dynamic = 1; 2091 if (WARN(id < 0, "couldn't get idr"))
2092 return id;
2093 ctlr->bus_num = id;
2086 } 2094 }
2087
2088 INIT_LIST_HEAD(&ctlr->queue); 2095 INIT_LIST_HEAD(&ctlr->queue);
2089 spin_lock_init(&ctlr->queue_lock); 2096 spin_lock_init(&ctlr->queue_lock);
2090 spin_lock_init(&ctlr->bus_lock_spinlock); 2097 spin_lock_init(&ctlr->bus_lock_spinlock);
@@ -2100,11 +2107,16 @@ int spi_register_controller(struct spi_controller *ctlr)
2100 */ 2107 */
2101 dev_set_name(&ctlr->dev, "spi%u", ctlr->bus_num); 2108 dev_set_name(&ctlr->dev, "spi%u", ctlr->bus_num);
2102 status = device_add(&ctlr->dev); 2109 status = device_add(&ctlr->dev);
2103 if (status < 0) 2110 if (status < 0) {
2111 /* free bus id */
2112 mutex_lock(&board_lock);
2113 idr_remove(&spi_master_idr, ctlr->bus_num);
2114 mutex_unlock(&board_lock);
2104 goto done; 2115 goto done;
2105 dev_dbg(dev, "registered %s %s%s\n", 2116 }
2117 dev_dbg(dev, "registered %s %s\n",
2106 spi_controller_is_slave(ctlr) ? "slave" : "master", 2118 spi_controller_is_slave(ctlr) ? "slave" : "master",
2107 dev_name(&ctlr->dev), dynamic ? " (dynamic)" : ""); 2119 dev_name(&ctlr->dev));
2108 2120
2109 /* If we're using a queued driver, start the queue */ 2121 /* If we're using a queued driver, start the queue */
2110 if (ctlr->transfer) 2122 if (ctlr->transfer)
@@ -2113,6 +2125,10 @@ int spi_register_controller(struct spi_controller *ctlr)
2113 status = spi_controller_initialize_queue(ctlr); 2125 status = spi_controller_initialize_queue(ctlr);
2114 if (status) { 2126 if (status) {
2115 device_del(&ctlr->dev); 2127 device_del(&ctlr->dev);
2128 /* free bus id */
2129 mutex_lock(&board_lock);
2130 idr_remove(&spi_master_idr, ctlr->bus_num);
2131 mutex_unlock(&board_lock);
2116 goto done; 2132 goto done;
2117 } 2133 }
2118 } 2134 }
@@ -2191,19 +2207,33 @@ static int __unregister(struct device *dev, void *null)
2191 */ 2207 */
2192void spi_unregister_controller(struct spi_controller *ctlr) 2208void spi_unregister_controller(struct spi_controller *ctlr)
2193{ 2209{
2210 struct spi_controller *found;
2194 int dummy; 2211 int dummy;
2195 2212
2213 /* First make sure that this controller was ever added */
2214 mutex_lock(&board_lock);
2215 found = idr_find(&spi_master_idr, ctlr->bus_num);
2216 mutex_unlock(&board_lock);
2217 if (found != ctlr) {
2218 dev_dbg(&ctlr->dev,
2219 "attempting to delete unregistered controller [%s]\n",
2220 dev_name(&ctlr->dev));
2221 return;
2222 }
2196 if (ctlr->queued) { 2223 if (ctlr->queued) {
2197 if (spi_destroy_queue(ctlr)) 2224 if (spi_destroy_queue(ctlr))
2198 dev_err(&ctlr->dev, "queue remove failed\n"); 2225 dev_err(&ctlr->dev, "queue remove failed\n");
2199 } 2226 }
2200
2201 mutex_lock(&board_lock); 2227 mutex_lock(&board_lock);
2202 list_del(&ctlr->list); 2228 list_del(&ctlr->list);
2203 mutex_unlock(&board_lock); 2229 mutex_unlock(&board_lock);
2204 2230
2205 dummy = device_for_each_child(&ctlr->dev, NULL, __unregister); 2231 dummy = device_for_each_child(&ctlr->dev, NULL, __unregister);
2206 device_unregister(&ctlr->dev); 2232 device_unregister(&ctlr->dev);
2233 /* free bus id */
2234 mutex_lock(&board_lock);
2235 idr_remove(&spi_master_idr, ctlr->bus_num);
2236 mutex_unlock(&board_lock);
2207} 2237}
2208EXPORT_SYMBOL_GPL(spi_unregister_controller); 2238EXPORT_SYMBOL_GPL(spi_unregister_controller);
2209 2239
@@ -3311,8 +3341,8 @@ static int of_spi_notify(struct notifier_block *nb, unsigned long action,
3311 put_device(&ctlr->dev); 3341 put_device(&ctlr->dev);
3312 3342
3313 if (IS_ERR(spi)) { 3343 if (IS_ERR(spi)) {
3314 pr_err("%s: failed to create for '%s'\n", 3344 pr_err("%s: failed to create for '%pOF'\n",
3315 __func__, rd->dn->full_name); 3345 __func__, rd->dn);
3316 of_node_clear_flag(rd->dn, OF_POPULATED); 3346 of_node_clear_flag(rd->dn, OF_POPULATED);
3317 return notifier_from_errno(PTR_ERR(spi)); 3347 return notifier_from_errno(PTR_ERR(spi));
3318 } 3348 }
diff --git a/tools/Makefile b/tools/Makefile
index 658f8adcf896..9dfede37c8ff 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -90,7 +90,7 @@ kvm_stat: FORCE
90 $(call descend,kvm/$@) 90 $(call descend,kvm/$@)
91 91
92all: acpi cgroup cpupower gpio hv firewire liblockdep \ 92all: acpi cgroup cpupower gpio hv firewire liblockdep \
93 perf selftests turbostat usb \ 93 perf selftests spi turbostat usb \
94 virtio vm net x86_energy_perf_policy \ 94 virtio vm net x86_energy_perf_policy \
95 tmon freefall iio objtool kvm_stat 95 tmon freefall iio objtool kvm_stat
96 96
@@ -100,7 +100,7 @@ acpi_install:
100cpupower_install: 100cpupower_install:
101 $(call descend,power/$(@:_install=),install) 101 $(call descend,power/$(@:_install=),install)
102 102
103cgroup_install firewire_install gpio_install hv_install iio_install perf_install usb_install virtio_install vm_install net_install objtool_install: 103cgroup_install firewire_install gpio_install hv_install iio_install perf_install spi_install usb_install virtio_install vm_install net_install objtool_install:
104 $(call descend,$(@:_install=),install) 104 $(call descend,$(@:_install=),install)
105 105
106liblockdep_install: 106liblockdep_install:
diff --git a/tools/spi/Build b/tools/spi/Build
new file mode 100644
index 000000000000..8e8466033d99
--- /dev/null
+++ b/tools/spi/Build
@@ -0,0 +1,2 @@
1spidev_test-y += spidev_test.o
2spidev_fdx-y += spidev_fdx.o
diff --git a/tools/spi/Makefile b/tools/spi/Makefile
index 3815b18ba070..90615e10c79a 100644
--- a/tools/spi/Makefile
+++ b/tools/spi/Makefile
@@ -1,6 +1,66 @@
1include ../scripts/Makefile.include
2
3bindir ?= /usr/bin
4
5ifeq ($(srctree),)
6srctree := $(patsubst %/,%,$(dir $(CURDIR)))
7srctree := $(patsubst %/,%,$(dir $(srctree)))
8endif
9
10# Do not use make's built-in rules
11# (this improves performance and avoids hard-to-debug behaviour);
12MAKEFLAGS += -r
13
1CC = $(CROSS_COMPILE)gcc 14CC = $(CROSS_COMPILE)gcc
15LD = $(CROSS_COMPILE)ld
16CFLAGS += -O2 -Wall -g -D_GNU_SOURCE -I$(OUTPUT)include
17
18ALL_TARGETS := spidev_test spidev_fdx
19ALL_PROGRAMS := $(patsubst %,$(OUTPUT)%,$(ALL_TARGETS))
20
21all: $(ALL_PROGRAMS)
22
23export srctree OUTPUT CC LD CFLAGS
24include $(srctree)/tools/build/Makefile.include
2 25
3all: spidev_test spidev_fdx 26#
27# We need the following to be outside of kernel tree
28#
29$(OUTPUT)include/linux/spi/spidev.h: ../../include/uapi/linux/spi/spidev.h
30 mkdir -p $(OUTPUT)include/linux/spi 2>&1 || true
31 ln -sf $(CURDIR)/../../include/uapi/linux/spi/spidev.h $@
32
33prepare: $(OUTPUT)include/linux/spi/spidev.h
34
35#
36# spidev_test
37#
38SPIDEV_TEST_IN := $(OUTPUT)spidev_test-in.o
39$(SPIDEV_TEST_IN): prepare FORCE
40 $(Q)$(MAKE) $(build)=spidev_test
41$(OUTPUT)spidev_test: $(SPIDEV_TEST_IN)
42 $(QUIET_LINK)$(CC) $(CFLAGS) $(LDFLAGS) $< -o $@
43
44#
45# spidev_fdx
46#
47SPIDEV_FDX_IN := $(OUTPUT)spidev_fdx-in.o
48$(SPIDEV_FDX_IN): prepare FORCE
49 $(Q)$(MAKE) $(build)=spidev_fdx
50$(OUTPUT)spidev_fdx: $(SPIDEV_FDX_IN)
51 $(QUIET_LINK)$(CC) $(CFLAGS) $(LDFLAGS) $< -o $@
4 52
5clean: 53clean:
6 $(RM) spidev_test spidev_fdx 54 rm -f $(ALL_PROGRAMS)
55 rm -f $(OUTPUT)include/linux/spi/spidev.h
56 find $(if $(OUTPUT),$(OUTPUT),.) -name '*.o' -delete -o -name '\.*.d' -delete
57
58install: $(ALL_PROGRAMS)
59 install -d -m 755 $(DESTDIR)$(bindir); \
60 for program in $(ALL_PROGRAMS); do \
61 install $$program $(DESTDIR)$(bindir); \
62 done
63
64FORCE:
65
66.PHONY: all install clean FORCE prepare
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-28 05:26:50 -0500